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mmc: omap_hsmmc: Enable DDR mode support

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In order to enable DDR mode, Dual Data Rate mode bit has to be set in
MMCHS_CON register. Set it here.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This commit is contained in:
Kishon Vijay Abraham I 2018-01-30 16:01:34 +01:00 committed by Jaehoon Chung
parent 8fc238bfad
commit 9b3fc21837
2 changed files with 6 additions and 0 deletions
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1
arch/arm/include/asm/omap_mmc.h
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@ -89,6 +89,7 @@ struct omap_hsmmc_plat {
#define WPP_ACTIVEHIGH (0x0 << 8)
#define RESERVED_MASK (0x3 << 9)
#define CTPL_MMC_SD (0x0 << 11)
#define DDR (0x1 << 19)
#define DMA_MASTER (0x1 << 20)
#define BLEN_512BYTESLEN (0x200 << 0)
#define NBLK_STPCNT (0x0 << 16)

5
drivers/mmc/omap_hsmmc.c
View file

@ -271,6 +271,11 @@ static void omap_hsmmc_set_timing(struct mmc *mmc)
val &= ~AC12_UHSMC_MASK;
priv->mode = mmc->selected_mode;
if (mmc_is_mode_ddr(priv->mode))
writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
else
writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
switch (priv->mode) {
case MMC_HS_200:
case UHS_SDR104: