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Convert CONFIG_DM9000_BYTE_SWAPPED et al to Kconfig

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This converts the following to Kconfig:
   CONFIG_DM9000_BYTE_SWAPPED
   CONFIG_DM9000_NO_SROM
   CONFIG_DM9000_USE_16BIT
   CONFIG_DM9000_DEBUG
   CONFIG_MXC_GPT_HCLK
   CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-12-02 16:42:18 -05:00
parent 6bd2372094
commit 9b0240f8c6
18 changed files with 32 additions and 40 deletions
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2
arch/arm/Kconfig
View file

@ -915,6 +915,7 @@ config ARCH_MX7
select CPU_V7A select CPU_V7A
select GPIO_EXTRA_HEADER select GPIO_EXTRA_HEADER
select MACH_IMX select MACH_IMX
select MXC_GPT_HCLK
select SYS_FSL_HAS_SEC select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE select SYS_FSL_SEC_LE
@ -928,6 +929,7 @@ config ARCH_MX6
select CPU_V7A select CPU_V7A
select GPIO_EXTRA_HEADER select GPIO_EXTRA_HEADER
select MACH_IMX select MACH_IMX
select MXC_GPT_HCLK
select SYS_FSL_HAS_SEC select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE select SYS_FSL_SEC_LE

3
arch/arm/mach-imx/Kconfig
View file

@ -18,6 +18,9 @@ config SYSCOUNTER_TIMER
config GPT_TIMER config GPT_TIMER
bool bool
config MXC_GPT_HCLK
bool
config IMX_RDC config IMX_RDC
bool "i.MX Resource domain controller driver" bool "i.MX Resource domain controller driver"
depends on ARCH_MX6 || ARCH_MX7 depends on ARCH_MX6 || ARCH_MX7

3
board/davinci/da8xxevm/Kconfig
View file

@ -37,6 +37,9 @@ config SYS_VENDOR
config SYS_CONFIG_NAME config SYS_CONFIG_NAME
default "omapl138_lcdk" default "omapl138_lcdk"
config NAND_6BYTES_OOB_FREE_10BYTES_ECC
def_bool y
endif endif
source "board/ti/common/Kconfig" source "board/ti/common/Kconfig"

7
board/timll/devkit8000/devkit8000.c
View file

@ -76,10 +76,11 @@ int board_init(void)
} }
/* Configure GPMC registers for DM9000 */ /* Configure GPMC registers for DM9000 */
#define DM9000_BASE 0x2c000000
static void gpmc_dm9000_config(void) static void gpmc_dm9000_config(void)
{ {
enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6], enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
CONFIG_DM9000_BASE, GPMC_SIZE_16M); DM9000_BASE, GPMC_SIZE_16M);
} }
/* /*
@ -100,9 +101,7 @@ int misc_init_r(void)
#endif #endif
#ifdef CONFIG_DRIVER_DM9000 #ifdef CONFIG_DRIVER_DM9000
/* Configure GPMC registers for DM9000 */ gpmc_dm9000_config();
enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
CONFIG_DM9000_BASE, GPMC_SIZE_16M);
/* Use OMAP DIE_ID as MAC address */ /* Use OMAP DIE_ID as MAC address */
if (!eth_env_get_enetaddr("ethaddr", enetaddr)) { if (!eth_env_get_enetaddr("ethaddr", enetaddr)) {

1
configs/M5253DEMO_defconfig
View file

@ -44,4 +44,5 @@ CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_MAX_FLASH_SECT=2048 CONFIG_SYS_MAX_FLASH_SECT=2048
CONFIG_USE_SYS_MAX_FLASH_BANKS=y CONFIG_USE_SYS_MAX_FLASH_BANKS=y
CONFIG_DRIVER_DM9000=y CONFIG_DRIVER_DM9000=y
CONFIG_DM9000_BYTE_SWAPPED=y
CONFIG_MCFUART=y CONFIG_MCFUART=y

2
configs/at91sam9261ek_dataflash_cs0_defconfig
View file

@ -54,6 +54,8 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_DATAFLASH=y CONFIG_SPI_FLASH_DATAFLASH=y
CONFIG_DRIVER_DM9000=y CONFIG_DRIVER_DM9000=y
CONFIG_DM9000_NO_SROM=y
CONFIG_DM9000_USE_16BIT=y
CONFIG_PINCTRL=y CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y CONFIG_DM_SERIAL=y

2
configs/at91sam9261ek_dataflash_cs3_defconfig
View file

@ -54,6 +54,8 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_DATAFLASH=y CONFIG_SPI_FLASH_DATAFLASH=y
CONFIG_DRIVER_DM9000=y CONFIG_DRIVER_DM9000=y
CONFIG_DM9000_NO_SROM=y
CONFIG_DM9000_USE_16BIT=y
CONFIG_PINCTRL=y CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y CONFIG_DM_SERIAL=y

2
configs/at91sam9261ek_nandflash_defconfig
View file

@ -52,6 +52,8 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_DATAFLASH=y CONFIG_SPI_FLASH_DATAFLASH=y
CONFIG_DRIVER_DM9000=y CONFIG_DRIVER_DM9000=y
CONFIG_DM9000_NO_SROM=y
CONFIG_DM9000_USE_16BIT=y
CONFIG_PINCTRL=y CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y CONFIG_DM_SERIAL=y

2
configs/devkit8000_defconfig
View file

@ -84,4 +84,6 @@ CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_DRIVER_DM9000=y CONFIG_DRIVER_DM9000=y
CONFIG_DM9000_NO_SROM=y
CONFIG_DM9000_USE_16BIT=y
CONFIG_JFFS2_NAND=y CONFIG_JFFS2_NAND=y

12
drivers/net/Kconfig
View file

@ -198,6 +198,18 @@ config DRIVER_DM9000
help help
The Davicom DM9000 parallel bus external ethernet interface chip. The Davicom DM9000 parallel bus external ethernet interface chip.
config DM9000_BYTE_SWAPPED
bool "Byte swapped access for DM9000"
depends on DRIVER_DM9000
config DM9000_NO_SROM
bool "No SROM on DM9000"
depends on DRIVER_DM9000
config DM9000_USE_16BIT
bool "Use 16bit access in DM9000"
depends on DRIVER_DM9000
config DWC_ETH_QOS config DWC_ETH_QOS
bool "Synopsys DWC Ethernet QOS device support" bool "Synopsys DWC Ethernet QOS device support"
select PHYLIB select PHYLIB

6
include/configs/M5253DEMO.h
View file

@ -20,12 +20,6 @@
env/embedded.o(.text*); env/embedded.o(.text*);
#ifdef CONFIG_DRIVER_DM9000 #ifdef CONFIG_DRIVER_DM9000
# define CONFIG_DM9000_BASE (CFG_SYS_CS1_BASE | 0x300)
# define DM9000_IO CONFIG_DM9000_BASE
# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
# undef CONFIG_DM9000_DEBUG
# define CONFIG_DM9000_BYTE_SWAPPED
# define CONFIG_OVERWRITE_ETHADDR_ONCE # define CONFIG_OVERWRITE_ETHADDR_ONCE
# define CONFIG_EXTRA_ENV_SETTINGS \ # define CONFIG_EXTRA_ENV_SETTINGS \

7
include/configs/at91sam9261ek.h
View file

@ -34,13 +34,6 @@
#endif #endif
/* Ethernet */
#define CONFIG_DM9000_BASE 0x30000000
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
#define CONFIG_DM9000_USE_16BIT
#define CONFIG_DM9000_NO_SROM
/* USB */ /* USB */
#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ #define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */

2
include/configs/brppt2.h
View file

@ -16,8 +16,6 @@
#define CFG_SYS_PL310_BASE L2_PL310_BASE #define CFG_SYS_PL310_BASE L2_PL310_BASE
#endif /* !CONFIG_SYS_L2CACHE_OFF */ #endif /* !CONFIG_SYS_L2CACHE_OFF */
#define CONFIG_MXC_GPT_HCLK
/* MMC */ /* MMC */
/* Boot */ /* Boot */

7
include/configs/ci20.h
View file

@ -17,11 +17,4 @@
/* NS16550-ish UARTs */ /* NS16550-ish UARTs */
#define CFG_SYS_NS16550_CLK 48000000 #define CFG_SYS_NS16550_CLK 48000000
/* Ethernet: davicom DM9000 */
#define CONFIG_DM9000_BASE 0xb6000000
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
/* Miscellaneous configuration options */
#endif /* __CONFIG_CI20_H__ */ #endif /* __CONFIG_CI20_H__ */

11
include/configs/devkit8000.h
View file

@ -16,17 +16,6 @@
#include <configs/ti_omap3_common.h> #include <configs/ti_omap3_common.h>
/* Hardware drivers */
/* DM9000 */
#define CONFIG_DM9000_BASE 0x2c000000
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
#define CONFIG_DM9000_USE_16BIT 1
#define CONFIG_DM9000_NO_SROM 1
#undef CONFIG_DM9000_DEBUG
/* TWL4030 */
/* BOOTP/DHCP options */ /* BOOTP/DHCP options */
#define MEM_LAYOUT_ENV_SETTINGS \ #define MEM_LAYOUT_ENV_SETTINGS \

1
include/configs/mx6_common.h
View file

@ -16,7 +16,6 @@
#endif #endif
#endif #endif
#define CONFIG_MXC_GPT_HCLK
#include <linux/sizes.h> #include <linux/sizes.h>
#include <asm/arch/imx-regs.h> #include <asm/arch/imx-regs.h>

1
include/configs/mx7_common.h
View file

@ -14,7 +14,6 @@
#include <asm/mach-imx/gpio.h> #include <asm/mach-imx/gpio.h>
/* Timer settings */ /* Timer settings */
#define CONFIG_MXC_GPT_HCLK
#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
/* Miscellaneous configurable options */ /* Miscellaneous configurable options */

1
include/configs/omapl138_lcdk.h
View file

@ -109,7 +109,6 @@
#define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE #define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CFG_SYS_NAND_MASK_CLE 0x10 #define CFG_SYS_NAND_MASK_CLE 0x10
#define CFG_SYS_NAND_MASK_ALE 0x8 #define CFG_SYS_NAND_MASK_ALE 0x8
#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
#define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K #define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K
#define CFG_SYS_NAND_U_BOOT_DST 0xc1080000 #define CFG_SYS_NAND_U_BOOT_DST 0xc1080000
#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST #define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST