ppc4xx: Add basic support for AMCC 460EX/460GT (3/5)

This patch adds basic support for the AMCC 460EX/460GT PPC's.

Signed-off-by: Stefan Roese <sr@denx.de>

include/405_mal.h

@@ -94,6 +94,7 @@
       /* Mal IER		      */
 #if defined(CONFIG_440SPE) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
     defined(CONFIG_405EX)
 #define MAL_IER_PT	  0x00000080
 #define MAL_IER_PRE	  0x00000040

include/4xx_i2c.h

@@ -41,7 +41,8 @@
 #endif /* CONFIG_I2C_MULTI_BUS */
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #define I2C_BASE_ADDR	(CFG_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS)
 #elif defined(CONFIG_440) || defined(CONFIG_405EX)
 /* all remaining 440 variants */

include/asm-ppc/4xx_pcie.h

@@ -29,6 +29,18 @@
 #define PCIE2_SDR		0x370
 #endif
 
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define CFG_PCIE_NR_PORTS	2
+
+#define CFG_PCIE_ADDR_HIGH	0x0000000d
+
+#define DCRN_PCIE0_BASE		0x100
+#define DCRN_PCIE1_BASE		0x120
+
+#define PCIE0_SDR		0x300
+#define PCIE1_SDR		0x340
+#endif
+
 #if defined(CONFIG_405EX)
 #define CFG_PCIE_NR_PORTS	2
 
@@ -68,7 +80,7 @@
 #define PESDR0_PLLLCT2		0x03a1
 #define PESDR0_PLLLCT3		0x03a2
 
-/* common regs, at least for 405EX and 440SPe */
+/* common regs, at for all 4xx with PCIe core */
 #define SDRN_PESDR_UTLSET1(n)		(sdr_base(n) + 0x00)
 #define SDRN_PESDR_UTLSET2(n)		(sdr_base(n) + 0x01)
 #define SDRN_PESDR_DLPSET(n)		(sdr_base(n) + 0x02)
@@ -198,8 +210,73 @@
 #define PESDR1_LPB		0x044B
 #define PESDR1_PHYSTA		0x044C
 
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+
+#define PESDR0_L0BIST		0x0308	/* PE0 L0 built in self test */
+#define PESDR0_L0BISTSTS	0x0309	/* PE0 L0 built in self test status */
+#define PESDR0_L0CDRCTL		0x030A	/* PE0 L0 CDR control */
+#define PESDR0_L0DRV		0x030B	/* PE0 L0 drive */
+#define PESDR0_L0REC		0x030C	/* PE0 L0 receiver */
+#define PESDR0_L0LPB		0x030D	/* PE0 L0 loopback */
+#define PESDR0_L0CLK		0x030E	/* PE0 L0 clocking */
+#define PESDR0_PHY_CTL_RST	0x030F	/* PE0 PHY control reset */
+#define PESDR0_RSTSTA		0x0310	/* PE0 reset status */
+#define PESDR0_OBS		0x0311	/* PE0 observation register */
+#define PESDR0_L0ERRC		0x0320	/* PE0 L0 error counter */
+
+#define PESDR1_L0BIST		0x0348	/* PE1 L0 built in self test */
+#define PESDR1_L1BIST		0x0349	/* PE1 L1 built in self test */
+#define PESDR1_L2BIST		0x034A	/* PE1 L2 built in self test */
+#define PESDR1_L3BIST		0x034B	/* PE1 L3 built in self test */
+#define PESDR1_L0BISTSTS	0x034C	/* PE1 L0 built in self test status */
+#define PESDR1_L1BISTSTS	0x034D	/* PE1 L1 built in self test status */
+#define PESDR1_L2BISTSTS	0x034E	/* PE1 L2 built in self test status */
+#define PESDR1_L3BISTSTS	0x034F	/* PE1 L3 built in self test status */
+#define PESDR1_L0CDRCTL		0x0350	/* PE1 L0 CDR control */
+#define PESDR1_L1CDRCTL		0x0351	/* PE1 L1 CDR control */
+#define PESDR1_L2CDRCTL		0x0352	/* PE1 L2 CDR control */
+#define PESDR1_L3CDRCTL		0x0353	/* PE1 L3 CDR control */
+#define PESDR1_L0DRV		0x0354	/* PE1 L0 drive */
+#define PESDR1_L1DRV		0x0355	/* PE1 L1 drive */
+#define PESDR1_L2DRV		0x0356	/* PE1 L2 drive */
+#define PESDR1_L3DRV		0x0357	/* PE1 L3 drive */
+#define PESDR1_L0REC		0x0358	/* PE1 L0 receiver */
+#define PESDR1_L1REC		0x0359	/* PE1 L1 receiver */
+#define PESDR1_L2REC		0x035A	/* PE1 L2 receiver */
+#define PESDR1_L3REC		0x035B	/* PE1 L3 receiver */
+#define PESDR1_L0LPB		0x035C	/* PE1 L0 loopback */
+#define PESDR1_L1LPB		0x035D	/* PE1 L1 loopback */
+#define PESDR1_L2LPB		0x035E	/* PE1 L2 loopback */
+#define PESDR1_L3LPB		0x035F	/* PE1 L3 loopback */
+#define PESDR1_L0CLK		0x0360	/* PE1 L0 clocking */
+#define PESDR1_L1CLK		0x0361	/* PE1 L1 clocking */
+#define PESDR1_L2CLK		0x0362	/* PE1 L2 clocking */
+#define PESDR1_L3CLK		0x0363	/* PE1 L3 clocking */
+#define PESDR1_PHY_CTL_RST	0x0364	/* PE1 PHY control reset */
+#define PESDR1_RSTSTA		0x0365	/* PE1 reset status */
+#define PESDR1_OBS		0x0366	/* PE1 observation register */
+#define PESDR1_L0ERRC		0x0368	/* PE1 L0 error counter */
+#define PESDR1_L1ERRC		0x0369	/* PE1 L1 error counter */
+#define PESDR1_L2ERRC		0x036A	/* PE1 L2 error counter */
+#define PESDR1_L3ERRC		0x036B	/* PE1 L3 error counter */
+#define PESDR0_IHS1		0x036C	/* PE interrupt handler interfact setting 1 */
+#define PESDR0_IHS2		0x036D	/* PE interrupt handler interfact setting 2 */
+
 #endif
 
+/* SDR Bit Mappings */
+#define PESDRx_RCSSET_HLDPLB	0x10000000
+#define PESDRx_RCSSET_RSTGU	0x01000000
+#define PESDRx_RCSSET_RDY       0x00100000
+#define PESDRx_RCSSET_RSTDL     0x00010000
+#define PESDRx_RCSSET_RSTPYN    0x00001000
+
+#define PESDRx_RCSSTS_PLBIDL	0x10000000
+#define PESDRx_RCSSTS_HRSTRQ	0x01000000
+#define PESDRx_RCSSTS_PGRST	0x00100000
+#define PESDRx_RCSSTS_VC0ACT	0x00010000
+#define PESDRx_RCSSTS_BMEN	0x00000100
+
 /*
  * UTL register offsets
  */

include/asm-ppc/ppc4xx-intvec.h

@@ -117,6 +117,73 @@
 #define VECNUM_MCTR0        (64 +  8)  /* MAl intp coalescence TR0      */
 #define VECNUM_MCTR1        (64 +  9)  /* MAl intp coalescence TR1      */
 
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+
+/* UIC 0 */
+#define VECNUM_U1	1		/* UART1			*/
+#define VECNUM_IIC0	2		/* IIC0				*/
+#define VECNUM_IIC1	3		/* IIC1				*/
+#define VECNUM_PIM	4		/* PCI inbound message		*/
+#define VECNUM_PCRW	5		/* PCI command reg write	*/
+#define VECNUM_PPM	6		/* PCI power management		*/
+#define VECNUM_MSI0	8		/* PCI MSI level 0		*/
+#define VECNUM_EIR0	9		/* External interrupt 0		*/
+#define VECNUM_UIC2NC	10		/* UIC2 non-critical interrupt	*/
+#define VECNUM_UIC2C	11		/* UIC2 critical interrupt	*/
+#define VECNUM_D0	12		/* DMA channel 0		*/
+#define VECNUM_D1	13		/* DMA channel 1		*/
+#define VECNUM_D2	14		/* DMA channel 2		*/
+#define VECNUM_D3	15		/* DMA channel 3		*/
+#define VECNUM_UIC3NC	16		/* UIC3 non-critical interrupt	*/
+#define VECNUM_UIC3C	17		/* UIC3 critical interrupt	*/
+#define VECNUM_EIR1	9		/* External interrupt 1		*/
+#define VECNUM_UIC1NC	30		/* UIC1 non-critical interrupt	*/
+#define VECNUM_UIC1C	31		/* UIC1 critical interrupt	*/
+
+/* UIC 1 */
+#define VECNUM_EIR2	(32 + 0)	/* External interrupt 0		*/
+#define VECNUM_U0	(32 + 1)	/* UART0			*/
+#define VECNUM_EIR3	(32 + 20)	/* External interrupt 3		*/
+#define VECNUM_EIR4	(32 + 21)	/* External interrupt 4		*/
+#define VECNUM_EIR5	(32 + 26)	/* External interrupt 5		*/
+#define VECNUM_EIR6	(32 + 27)	/* External interrupt 6		*/
+#define VECNUM_U2	(32 + 28)	/* UART2			*/
+#define VECNUM_U3	(32 + 29)	/* UART3			*/
+#define VECNUM_EIR7	(32 + 30)	/* External interrupt 7		*/
+#define VECNUM_EIR8	(32 + 31)	/* External interrupt 8		*/
+
+/* UIC 2 */
+#define VECNUM_EIR9	(64 + 2)	/* External interrupt 9		*/
+#define VECNUM_MS	(64 + 3)	/* MAL SERR			*/
+#define	VECNUM_TXDE	(64 + 4)	/* MAL TXDE			*/
+#define	VECNUM_RXDE	(64 + 5)	/* MAL RXDE			*/
+#define VECNUM_MTE	(64 + 6)	/* MAL TXEOB			*/
+#define	VECNUM_MRE	(64 + 7)	/* MAL RXEOB			*/
+#define	VECNUM_ETH0	(64 + 16)	/* Ethernet 0			*/
+#define	VECNUM_ETH1	(64 + 17)	/* Ethernet 1			*/
+#define	VECNUM_ETH2	(64 + 18)	/* Ethernet 2			*/
+#define	VECNUM_ETH3	(64 + 19)	/* Ethernet 3			*/
+#define VECNUM_EWU0	(64 + 20)	/* Emac 0 wakeup		*/
+#define VECNUM_EWU1	(64 + 21)	/* Emac 1 wakeup		*/
+#define VECNUM_EWU2	(64 + 22)	/* Emac 2 wakeup		*/
+#define VECNUM_EWU3	(64 + 23)	/* Emac 3 wakeup		*/
+#define VECNUM_EIR10	(64 + 24)	/* External interrupt 10	*/
+#define VECNUM_EIR11	(64 + 25)	/* External interrupt 11	*/
+
+/* UIC 3 */
+#define VECNUM_EIR12	(96 + 20)	/* External interrupt 20	*/
+#define VECNUM_EIR13	(96 + 21)	/* External interrupt 21	*/
+#define VECNUM_EIR14	(96 + 22)	/* External interrupt 22	*/
+#define VECNUM_EIR15	(96 + 23)	/* External interrupt 23	*/
+#define VECNUM_PCIEMSI0	(96 + 24)	/* PCI Express MSI level 0	*/
+#define VECNUM_PCIEMSI1	(96 + 25)	/* PCI Express MSI level 1	*/
+#define VECNUM_PCIEMSI2	(96 + 26)	/* PCI Express MSI level 2	*/
+#define VECNUM_PCIEMSI3	(96 + 27)	/* PCI Express MSI level 3	*/
+#define VECNUM_PCIEMSI4	(96 + 28)	/* PCI Express MSI level 4	*/
+#define VECNUM_PCIEMSI5	(96 + 29)	/* PCI Express MSI level 5	*/
+#define VECNUM_PCIEMSI6	(96 + 30)	/* PCI Express MSI level 6	*/
+#define VECNUM_PCIEMSI7	(96 + 31)	/* PCI Express MSI level 7	*/
+
 #elif defined(CONFIG_440SPE)
 
 /* UIC 0 */
@@ -130,10 +197,14 @@
 #define VECNUM_MSI0         7           /* PCI MSI level 0              */
 #define VECNUM_MSI1         8           /* PCI MSI level 0              */
 #define VECNUM_MSI2         9           /* PCI MSI level 0              */
+#define VECNUM_UIC2NC       10          /* UIC2 non-critical interrupt  */
+#define VECNUM_UIC2C        11          /* UIC2 critical interrupt      */
 #define VECNUM_D0           12          /* DMA channel 0                */
 #define VECNUM_D1           13          /* DMA channel 1                */
 #define VECNUM_D2           14          /* DMA channel 2                */
 #define VECNUM_D3           15          /* DMA channel 3                */
+#define VECNUM_UIC3NC       16          /* UIC3 non-critical interrupt  */
+#define VECNUM_UIC3C        17          /* UIC3 critical interrupt      */
 #define VECNUM_UIC1NC       30          /* UIC1 non-critical interrupt  */
 #define VECNUM_UIC1C        31          /* UIC1 critical interrupt      */
 

include/asm-ppc/processor.h

@@ -802,6 +802,10 @@
 #define PVR_440SPe_RA	0x53521890 /* 440SPe rev A without RAID 6 support	*/
 #define PVR_440SPe_6_RB	0x53421891 /* 440SPe rev B with RAID 6 support enabled	*/
 #define PVR_440SPe_RB	0x53521891 /* 440SPe rev B without RAID 6 support	*/
+#define PVR_460EX_SE_RA	0x130218A2 /* 460EX rev A with Security Engine    */
+#define PVR_460EX_RA	0x130218A3 /* 460EX rev A without Security Engine */
+#define PVR_460GT_SE_RA	0x130218A0 /* 460GT rev A with Security Engine    */
+#define PVR_460GT_RA	0x130218A1 /* 460GT rev A without Security Engine */
 #define PVR_601		0x00010000
 #define PVR_602		0x00050000
 #define PVR_603		0x00030000

include/asm-ppc/u-boot.h

@@ -115,7 +115,8 @@ typedef struct bd_info {
 #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
     defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
     defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	unsigned int	bi_opbfreq;		/* OPB clock in Hz */
 	int		bi_iic_fast[2];		/* Use fast i2c mode */
 #endif
@@ -123,7 +124,8 @@ typedef struct bd_info {
 	unsigned char	bi_sernum[8];
 #endif
 #if defined(CONFIG_4xx)
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	int 		bi_phynum[4];           /* Determines phy mapping */
 	int 		bi_phymode[4];          /* Determines phy mode */
 #elif defined(CONFIG_405EP) || defined(CONFIG_440)