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board: atmel: add SAMA5D2 PTC Engineering board
The board supports following features: - Boot media support: NAND Flash/SPI Flash - Support ethernet - Support USB mass storage Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
This commit is contained in:
Wenyou Yang
Andreas Bießmann
parent
cc434ad5c1
commit
9989c1567d
8 changed files with 500 additions and 0 deletions
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@ -71,6 +71,11 @@ config TARGET_AT91SAM9X5EK
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select CPU_ARM926EJS
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select SUPPORT_SPL
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config TARGET_SAMA5D2_PTC
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bool "SAMA5D2 PTC board"
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select CPU_V7
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select SUPPORT_SPL
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config TARGET_SAMA5D2_XPLAINED
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bool "SAMA5D2 Xplained board"
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select CPU_V7
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@ -138,6 +143,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig"
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source "board/atmel/at91sam9n12ek/Kconfig"
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source "board/atmel/at91sam9rlek/Kconfig"
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source "board/atmel/at91sam9x5ek/Kconfig"
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source "board/atmel/sama5d2_ptc/Kconfig"
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source "board/atmel/sama5d2_xplained/Kconfig"
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source "board/atmel/sama5d3_xplained/Kconfig"
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source "board/atmel/sama5d3xek/Kconfig"
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15
board/atmel/sama5d2_ptc/Kconfig
Normal file
15
board/atmel/sama5d2_ptc/Kconfig
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@ -0,0 +1,15 @@
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if TARGET_SAMA5D2_PTC
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config SYS_BOARD
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default "sama5d2_ptc"
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config SYS_VENDOR
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default "atmel"
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config SYS_SOC
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default "at91"
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config SYS_CONFIG_NAME
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default "sama5d2_ptc"
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endif
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7
board/atmel/sama5d2_ptc/MAINTAINERS
Normal file
7
board/atmel/sama5d2_ptc/MAINTAINERS
Normal file
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@ -0,0 +1,7 @@
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SAMA5D2 PTC Engineering BOARD
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M: Wenyou Yang <wenyou.yang@atmel.com>
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S: Maintained
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F: board/atmel/sama5d2_ptc/
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F: include/configs/sama5d2_ptc.h
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F: configs/sama5d2_ptc_spiflash_defconfig
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F: configs/sama5d2_ptc_nandflash_defconfig
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8
board/atmel/sama5d2_ptc/Makefile
Normal file
8
board/atmel/sama5d2_ptc/Makefile
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@ -0,0 +1,8 @@
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#
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# Copyright (C) 2016 Atmel
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# Wenyou Yang <wenyou.yang@atmel.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += sama5d2_ptc.o
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285
board/atmel/sama5d2_ptc/sama5d2_ptc.c
Normal file
285
board/atmel/sama5d2_ptc/sama5d2_ptc.c
Normal file
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@ -0,0 +1,285 @@
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/*
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* Copyright (C) 2016 Atmel
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* Wenyou.Yang <wenyou.yang@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <atmel_hlcdc.h>
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#include <lcd.h>
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#include <mmc.h>
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#include <net.h>
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#include <netdev.h>
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#include <spi.h>
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#include <version.h>
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#include <asm/io.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/atmel_pio4.h>
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#include <asm/arch/atmel_mpddrc.h>
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#include <asm/arch/atmel_usba_udc.h>
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#include <asm/arch/atmel_sdhci.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/sama5_sfr.h>
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#include <asm/arch/sama5d2.h>
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#include <asm/arch/sama5d3_smc.h>
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DECLARE_GLOBAL_DATA_PTR;
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && cs == 0;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
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}
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static void board_spi0_hw_init(void)
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{
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0);
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0);
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atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
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at91_periph_clk_enable(ATMEL_ID_SPI0);
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}
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static void board_nand_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
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at91_periph_clk_enable(ATMEL_ID_HSMC);
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writel(AT91_SFR_EBICFG_DRIVE0_HIGH |
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AT91_SFR_EBICFG_PULL0_NONE |
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AT91_SFR_EBICFG_DRIVE1_HIGH |
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AT91_SFR_EBICFG_PULL1_NONE, &sfr->ebicfg);
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/* Configure SMC CS3 for NAND */
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
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AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
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AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3) |
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AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_DBW_8 |
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AT91_SMC_MODE_TDF_CYCLE(3),
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&smc->cs[3].mode);
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atmel_pio4_set_f_periph(AT91_PIO_PORTA, 0, 0); /* D0 */
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atmel_pio4_set_f_periph(AT91_PIO_PORTA, 1, 0); /* D1 */
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atmel_pio4_set_f_periph(AT91_PIO_PORTA, 2, 0); /* D2 */
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atmel_pio4_set_f_periph(AT91_PIO_PORTA, 3, 0); /* D3 */
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atmel_pio4_set_f_periph(AT91_PIO_PORTA, 4, 0); /* D4 */
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atmel_pio4_set_f_periph(AT91_PIO_PORTA, 5, 0); /* D5 */
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atmel_pio4_set_f_periph(AT91_PIO_PORTA, 6, 0); /* D6 */
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atmel_pio4_set_f_periph(AT91_PIO_PORTA, 7, 0); /* D7 */
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atmel_pio4_set_f_periph(AT91_PIO_PORTA, 12, 0); /* RE */
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atmel_pio4_set_f_periph(AT91_PIO_PORTA, 8, 0); /* WE */
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atmel_pio4_set_f_periph(AT91_PIO_PORTA, 9, 1); /* NCS */
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atmel_pio4_set_f_periph(AT91_PIO_PORTA, 21, 1); /* RDY */
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atmel_pio4_set_f_periph(AT91_PIO_PORTA, 10, 1); /* ALE */
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atmel_pio4_set_f_periph(AT91_PIO_PORTA, 11, 1); /* CLE */
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}
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static void board_usb_hw_init(void)
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{
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atmel_pio4_set_pio_output(AT91_PIO_PORTA, 28, 1);
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}
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static void board_gmac_hw_init(void)
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{
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atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */
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atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */
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atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */
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atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */
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atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */
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atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */
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atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */
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atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */
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atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */
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atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */
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at91_periph_clk_enable(ATMEL_ID_GMAC);
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}
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static void board_uart0_hw_init(void)
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{
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atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1); /* URXD0 */
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atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
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at91_periph_clk_enable(CONFIG_USART_ID);
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}
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int board_early_init_f(void)
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{
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at91_periph_clk_enable(ATMEL_ID_PIOA);
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at91_periph_clk_enable(ATMEL_ID_PIOB);
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at91_periph_clk_enable(ATMEL_ID_PIOC);
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at91_periph_clk_enable(ATMEL_ID_PIOD);
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board_uart0_hw_init();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_ATMEL_SPI
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board_spi0_hw_init();
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#endif
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#ifdef CONFIG_NAND_ATMEL
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board_nand_hw_init();
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#endif
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#ifdef CONFIG_MACB
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board_gmac_hw_init();
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#endif
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#ifdef CONFIG_CMD_USB
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board_usb_hw_init();
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#endif
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#ifdef CONFIG_USB_GADGET_ATMEL_USBA
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at91_udp_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
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if (rc)
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printf("GMAC register failed\n");
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#endif
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#ifdef CONFIG_USB_GADGET_ATMEL_USBA
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usba_udc_probe(&pdata);
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#ifdef CONFIG_USB_ETH_RNDIS
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usb_eth_initialize(bis);
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#endif
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#endif
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return rc;
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}
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/* SPL */
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#ifdef CONFIG_SPL_BUILD
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void spl_board_init(void)
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{
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#ifdef CONFIG_SYS_USE_SERIALFLASH
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board_spi0_hw_init();
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#endif
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#ifdef CONFIG_SYS_USE_NANDFLASH
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board_nand_hw_init();
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#endif
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}
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static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
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{
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ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
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ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
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ATMEL_MPDDRC_CR_NR_ROW_14 |
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ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
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ATMEL_MPDDRC_CR_DIC_DS |
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ATMEL_MPDDRC_CR_DIS_DLL |
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ATMEL_MPDDRC_CR_NB_8BANKS |
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ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
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ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
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ddrc->rtr = 0x511;
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ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
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(3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
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(4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
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(9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
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(3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
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(4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
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(4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
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(4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
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ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
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(29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
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(0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
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(3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
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ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
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(0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
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(0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
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(4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
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(7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
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}
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void mem_init(void)
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{
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struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
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struct atmel_mpddrc_config ddrc_config;
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u32 reg;
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ddrc_conf(&ddrc_config);
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at91_periph_clk_enable(ATMEL_ID_MPDDRC);
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at91_system_clk_enable(AT91_PMC_DDR);
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reg = readl(&mpddrc->io_calibr);
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reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
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reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
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reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
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reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
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writel(reg, &mpddrc->io_calibr);
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writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
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&mpddrc->rd_data_path);
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ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
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writel(0x3, &mpddrc->cal_mr4);
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writel(64, &mpddrc->tim_cal);
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}
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void at91_pmc_init(void)
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{
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at91_plla_init(AT91_PMC_PLLAR_29 |
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AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
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AT91_PMC_PLLXR_MUL(82) |
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AT91_PMC_PLLXR_DIV(1));
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at91_pllicpr_init(0);
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at91_mck_init(AT91_PMC_MCKR_H32MXDIV |
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AT91_PMC_MCKR_PLLADIV_2 |
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AT91_PMC_MCKR_MDIV_3 |
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AT91_PMC_MCKR_CSS_PLLA);
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}
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#endif
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12
configs/sama5d2_ptc_nandflash_defconfig
Normal file
12
configs/sama5d2_ptc_nandflash_defconfig
Normal file
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@ -0,0 +1,12 @@
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CONFIG_ARM=y
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CONFIG_ARCH_AT91=y
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CONFIG_TARGET_SAMA5D2_PTC=y
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CONFIG_SPL=y
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CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH"
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# CONFIG_CMD_IMI is not set
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_LOADS is not set
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_SF=y
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# CONFIG_CMD_FPGA is not set
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CONFIG_SPI_FLASH=y
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12
configs/sama5d2_ptc_spiflash_defconfig
Normal file
12
configs/sama5d2_ptc_spiflash_defconfig
Normal file
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@ -0,0 +1,12 @@
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CONFIG_ARM=y
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CONFIG_ARCH_AT91=y
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CONFIG_TARGET_SAMA5D2_PTC=y
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CONFIG_SPL=y
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CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
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# CONFIG_CMD_IMI is not set
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_LOADS is not set
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_SF=y
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# CONFIG_CMD_FPGA is not set
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CONFIG_SPI_FLASH=y
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155
include/configs/sama5d2_ptc.h
Normal file
155
include/configs/sama5d2_ptc.h
Normal file
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/*
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* Configuration settings for the SAMA5D2 PTC Engineering board.
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*
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* Copyright (C) 2016 Atmel
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* Wenyou Yang <wenyou.yang@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* No NOR flash, this definition should put before common header */
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#define CONFIG_SYS_NO_FLASH
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#include "at91-sama5_common.h"
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/* serial console */
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART_BASE ATMEL_BASE_UART0
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#define CONFIG_USART_ID ATMEL_ID_UART0
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
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#define CONFIG_SYS_SDRAM_SIZE 0x20000000
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_INIT_SP_ADDR 0x210000
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#else
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
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#endif
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#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
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#undef CONFIG_AT91_GPIO
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#define CONFIG_ATMEL_PIO4
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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|
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/* SerialFlash */
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#ifdef CONFIG_CMD_SF
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#define CONFIG_ATMEL_SPI
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#define CONFIG_SPI_FLASH_ATMEL
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#define CONFIG_SF_DEFAULT_BUS 0
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#define CONFIG_SF_DEFAULT_CS 0
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#define CONFIG_SF_DEFAULT_SPEED 30000000
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#endif
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|
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/* NAND flash */
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#define CONFIG_CMD_NAND
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|
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#ifdef CONFIG_CMD_NAND
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||||
#define CONFIG_NAND_ATMEL
|
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
|
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/* our ALE is AD21 */
|
||||
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
|
||||
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
/* PMECC & PMERRLOC */
|
||||
#define CONFIG_ATMEL_NAND_HWECC
|
||||
#define CONFIG_ATMEL_NAND_HW_PMECC
|
||||
#define CONFIG_CMD_NAND_TRIMFFS
|
||||
#endif
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_CMD_USB
|
||||
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_ATMEL
|
||||
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
|
||||
#define CONFIG_USB_STORAGE
|
||||
#endif
|
||||
|
||||
/* USB device */
|
||||
#define CONFIG_USB_GADGET
|
||||
#define CONFIG_USB_GADGET_DUALSPEED
|
||||
#define CONFIG_USB_GADGET_ATMEL_USBA
|
||||
#define CONFIG_USB_ETHER
|
||||
#define CONFIG_USB_ETH_RNDIS
|
||||
#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D2_PTC"
|
||||
|
||||
#if defined(CONFIG_CMD_USB)
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif
|
||||
|
||||
/* Ethernet Hardware */
|
||||
#define CONFIG_MACB
|
||||
#define CONFIG_RMII
|
||||
#define CONFIG_NET_RETRY_COUNT 20
|
||||
#define CONFIG_MACB_SEARCH_PHY
|
||||
|
||||
#ifdef CONFIG_SYS_USE_NANDFLASH
|
||||
#undef CONFIG_ENV_OFFSET
|
||||
#undef CONFIG_ENV_OFFSET_REDUND
|
||||
#undef CONFIG_BOOTCOMMAND
|
||||
/* u-boot env in nand flash */
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#define CONFIG_ENV_OFFSET 0x200000
|
||||
#define CONFIG_ENV_OFFSET_REDUND 0x400000
|
||||
#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0xb80000 0x80000;" \
|
||||
"nand read 0x22000000 0x600000 0x600000;" \
|
||||
"bootz 0x22000000 - 0x21000000"
|
||||
#endif
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
#define CONFIG_BOOTARGS \
|
||||
"console=ttyS0,57600 earlyprintk " \
|
||||
"mtdparts=atmel_nand:6M(bootstrap)ro, 6M(kernel)ro,-(rootfs) " \
|
||||
"rootfstype=ubifs ubi.mtd=2 root=ubi0:rootfs"
|
||||
|
||||
/* SPL */
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_TEXT_BASE 0x200000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x10000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
|
||||
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_GPIO_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
|
||||
#define CONFIG_SPL_BOARD_INIT
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
|
||||
|
||||
#ifdef CONFIG_SYS_USE_SERIALFLASH
|
||||
#define CONFIG_SPL_SPI_SUPPORT
|
||||
#define CONFIG_SPL_SPI_FLASH_SUPPORT
|
||||
#define CONFIG_SPL_SPI_LOAD
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
|
||||
|
||||
#elif CONFIG_SYS_USE_NANDFLASH
|
||||
#define CONFIG_SPL_NAND_SUPPORT
|
||||
#define CONFIG_SPL_NAND_DRIVERS
|
||||
#define CONFIG_SPL_NAND_BASE
|
||||
#define CONFIG_PMECC_CAP 8
|
||||
#define CONFIG_PMECC_SECTOR_SIZE 512
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_OOBSIZE 224
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
|
||||
#endif
|
||||
|
||||
#endif
|
||||
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