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spi: kirkwood_spi.c: Add driver model support
This patch adds driver model support to the kirkwood SPI driver. Which is also used on the MVEBU SoC's, now being converted to DM. Non-DM support is still available for the "older" platforms using this driver, like kirkwood. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Valentin Longchamp <valentin.longchamp@keymile.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org>
This commit is contained in:
Stefan Roese
parent
18dd3b2221
commit
9985bdb1ce
1 changed files with 171 additions and 75 deletions
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@ -9,6 +9,7 @@
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*/
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#include <common.h>
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#include <dm.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/io.h>
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@ -18,6 +19,83 @@
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#endif
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#include <asm/arch-mvebu/spi.h>
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static void _spi_cs_activate(struct kwspi_registers *reg)
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{
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setbits_le32(®->ctrl, KWSPI_CSN_ACT);
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}
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static void _spi_cs_deactivate(struct kwspi_registers *reg)
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{
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clrbits_le32(®->ctrl, KWSPI_CSN_ACT);
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}
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static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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unsigned int tmpdout, tmpdin;
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int tm, isread = 0;
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debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen);
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if (flags & SPI_XFER_BEGIN)
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_spi_cs_activate(reg);
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/*
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* handle data in 8-bit chunks
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* TBD: 2byte xfer mode to be enabled
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*/
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clrsetbits_le32(®->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
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while (bitlen > 4) {
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debug("loopstart bitlen %d\n", bitlen);
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tmpdout = 0;
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/* Shift data so it's msb-justified */
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if (dout)
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tmpdout = *(u32 *)dout & 0xff;
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clrbits_le32(®->irq_cause, KWSPI_SMEMRDIRQ);
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writel(tmpdout, ®->dout); /* Write the data out */
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debug("*** spi_xfer: ... %08x written, bitlen %d\n",
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tmpdout, bitlen);
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/*
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* Wait for SPI transmit to get out
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* or time out (1 second = 1000 ms)
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* The NE event must be read and cleared first
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*/
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for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
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if (readl(®->irq_cause) & KWSPI_SMEMRDIRQ) {
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isread = 1;
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tmpdin = readl(®->din);
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debug("spi_xfer: din %p..%08x read\n",
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din, tmpdin);
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if (din) {
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*((u8 *)din) = (u8)tmpdin;
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din += 1;
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}
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if (dout)
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dout += 1;
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bitlen -= 8;
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}
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if (isread)
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break;
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}
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if (tm >= KWSPI_TIMEOUT)
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printf("*** spi_xfer: Time out during SPI transfer\n");
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debug("loopend bitlen %d\n", bitlen);
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}
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if (flags & SPI_XFER_END)
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_spi_cs_deactivate(reg);
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return 0;
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}
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#ifndef CONFIG_DM_SPI
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static struct kwspi_registers *spireg =
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(struct kwspi_registers *)MVEBU_SPI_BASE;
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@ -145,16 +223,6 @@ void spi_init(void)
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{
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}
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static void _spi_cs_activate(struct kwspi_registers *reg)
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{
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setbits_le32(®->ctrl, KWSPI_CSN_ACT);
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}
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static void _spi_cs_deactivate(struct kwspi_registers *reg)
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{
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clrbits_le32(®->ctrl, KWSPI_CSN_ACT);
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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_spi_cs_activate(spireg);
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@ -165,73 +233,101 @@ void spi_cs_deactivate(struct spi_slave *slave)
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_spi_cs_deactivate(spireg);
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}
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static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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unsigned int tmpdout, tmpdin;
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int tm, isread = 0;
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debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen);
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if (flags & SPI_XFER_BEGIN)
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_spi_cs_activate(reg);
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/*
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* handle data in 8-bit chunks
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* TBD: 2byte xfer mode to be enabled
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*/
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clrsetbits_le32(®->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
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while (bitlen > 4) {
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debug("loopstart bitlen %d\n", bitlen);
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tmpdout = 0;
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/* Shift data so it's msb-justified */
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if (dout)
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tmpdout = *(u32 *)dout & 0xff;
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clrbits_le32(®->irq_cause, KWSPI_SMEMRDIRQ);
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writel(tmpdout, ®->dout); /* Write the data out */
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debug("*** spi_xfer: ... %08x written, bitlen %d\n",
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tmpdout, bitlen);
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/*
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* Wait for SPI transmit to get out
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* or time out (1 second = 1000 ms)
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* The NE event must be read and cleared first
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*/
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for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
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if (readl(®->irq_cause) & KWSPI_SMEMRDIRQ) {
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isread = 1;
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tmpdin = readl(®->din);
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debug("spi_xfer: din %p..%08x read\n",
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din, tmpdin);
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if (din) {
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*((u8 *)din) = (u8)tmpdin;
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din += 1;
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}
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if (dout)
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dout += 1;
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bitlen -= 8;
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}
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if (isread)
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break;
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}
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if (tm >= KWSPI_TIMEOUT)
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printf("*** spi_xfer: Time out during SPI transfer\n");
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debug("loopend bitlen %d\n", bitlen);
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}
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if (flags & SPI_XFER_END)
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_spi_cs_deactivate(reg);
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return 0;
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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return _spi_xfer(spireg, bitlen, dout, din, flags);
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}
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#else
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/* Here now the DM part */
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struct mvebu_spi_platdata {
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struct kwspi_registers *spireg;
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};
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struct mvebu_spi_priv {
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struct kwspi_registers *spireg;
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};
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static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
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{
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struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
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struct kwspi_registers *reg = plat->spireg;
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u32 data;
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/* calculate spi clock prescaller using max_hz */
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data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10;
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data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
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data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
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/* program spi clock prescaler using max_hz */
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writel(KWSPI_ADRLEN_3BYTE | data, ®->cfg);
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debug("data = 0x%08x\n", data);
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return 0;
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}
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static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
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{
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return 0;
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}
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static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
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return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
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}
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static int mvebu_spi_probe(struct udevice *bus)
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{
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struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
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struct kwspi_registers *reg = plat->spireg;
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writel(KWSPI_SMEMRDY, ®->ctrl);
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writel(KWSPI_SMEMRDIRQ, ®->irq_cause);
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writel(KWSPI_IRQMASK, ®->irq_mask);
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return 0;
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}
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static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
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{
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struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
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plat->spireg = (struct kwspi_registers *)dev_get_addr(bus);
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return 0;
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}
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static const struct dm_spi_ops mvebu_spi_ops = {
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.xfer = mvebu_spi_xfer,
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.set_speed = mvebu_spi_set_speed,
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.set_mode = mvebu_spi_set_mode,
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/*
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* cs_info is not needed, since we require all chip selects to be
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* in the device tree explicitly
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*/
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};
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static const struct udevice_id mvebu_spi_ids[] = {
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{ .compatible = "marvell,armada-380-spi" },
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{ .compatible = "marvell,armada-xp-spi" },
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{ }
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};
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U_BOOT_DRIVER(mvebu_spi) = {
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.name = "mvebu_spi",
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.id = UCLASS_SPI,
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.of_match = mvebu_spi_ids,
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.ops = &mvebu_spi_ops,
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.ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
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.priv_auto_alloc_size = sizeof(struct mvebu_spi_priv),
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.probe = mvebu_spi_probe,
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};
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#endif
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