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Merge branch 'master' of git://git.denx.de/u-boot-arm

Browse source 
Conflicts:

	board/davinci/da830evm/da830evm.c
	board/edb93xx/sdram_cfg.c
	board/esd/otc570/otc570.c
	board/netstar/eeprom.c
	board/netstar/eeprom_start.S
	cpu/arm920t/ep93xx/timer.c
	include/configs/netstar.h
	include/configs/otc570.h

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Minkyu Kang 2010-03-15 10:51:36 +09:00
commit 995a4b1d83
262 changed files with 14844 additions and 4179 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

45
MAINTAINERS
View file

@ -134,8 +134,6 @@ Wolfgang Denk <wd@denx.de>
PCIPPC2 MPC750
PCIPPC6 MPC750
EXBITGEN PPC405GP
Jon Diekema <jon.diekema@smiths-aerospace.com>
sbc8260 MPC8260
@ -152,6 +150,10 @@ Dave Ellis <DGE@sixnetio.com>
SXNI855T MPC8xx
Fred Fan <fanyefeng@gmail.com>
mx51evk i.MX51
Thomas Frieden <ThomasF@hyperion-entertainment.com>
AmigaOneG3SE MPC7xx
@ -411,9 +413,9 @@ Heiko Schocher <hs@denx.de>
muas3001 MPC8270
municse MPC5200
sc3 PPC405GP
suen3 ARM926EJS (Kirkwood SoC)
uc101 MPC5200
Peter De Schrijver <p2@mind.be>
ML2 PPC4xx
@ -616,6 +618,10 @@ Simon Kagstrom <simon.kagstrom@netinsight.net>
openrd_base ARM926EJS (Kirkwood SoC)
Minkyu Kang <mk7.kang@samsung.com>
SMDKC100 ARM CORTEX-A8 (S5PC100 SoC)
Nishant Kamat <nskamat@ti.com>
omap1610h2 ARM926EJS
@ -630,17 +636,17 @@ Sergey Kubushyn <ksi@koi8.net>
SONATA ARM926EJS
SCHMOOGIE ARM926EJS
Sandeep Paulraj <s-paulraj@ti.com>
davinci_dm355evm ARM926EJS
davinci_dm355leopard ARM926EJS
davinci_dm365evm ARM926EJS
davinci_dm6467evm ARM926EJS
Prakash Kumar <prakash@embedx.com>
cerf250 xscale
Vipin Kumar <vipin.kumar@st.com>
spear300 ARM926EJS (spear300 Soc)
spear310 ARM926EJS (spear310 Soc)
spear320 ARM926EJS (spear320 Soc)
spear600 ARM926EJS (spear600 Soc)
Sergey Lapin <slapin@ossfans.org>
afeb9260 ARM926EJS (AT91SAM9260 SoC)
@ -673,6 +679,13 @@ Kyungmin Park <kyungmin.park@samsung.com>
apollon ARM1136EJS
Sandeep Paulraj <s-paulraj@ti.com>
davinci_dm355evm ARM926EJS
davinci_dm355leopard ARM926EJS
davinci_dm365evm ARM926EJS
davinci_dm6467evm ARM926EJS
Peter Pearse <peter.pearse@arm.com>
integratorcp All current ARM supplied & supported core modules
-see http://www.arm.com/products/DevTools/Hardware_Platforms.html
@ -699,6 +712,10 @@ Tom Rix <Tom.Rix@windriver.com>
omap3_zoom2 ARM CORTEX-A8 (OMAP3xx SoC)
John Rigby <jcrigby@gmail.com>
tx25 i.MX25
Stefan Roese <sr@denx.de>
ixdpg425 xscale
@ -714,6 +731,10 @@ Steve Sakoman <sakoman@gmail.com>
omap3_overo ARM CORTEX-A8 (OMAP3xx SoC)
Jens Scharsig <esw@bus-elektronik.de>
eb_cpux9k2 ARM920T (AT91RM9200 SoC)
Robert Schwebel <r.schwebel@pengutronix.de>
csb226 xscale
@ -765,10 +786,6 @@ Alex Z
lart SA1100
dnp1110 SA1110
Minkyu Kang <mk7.kang@samsung.com>
SMDKC100 ARM CORTEX-A8 (S5PC100 SoC)
-------------------------------------------------------------------------
Unknown / orphaned boards:

6
MAKEALL
View file

@ -213,7 +213,6 @@ LIST_4xx=" \
DU440 \
ebony \
ERIC \
EXBITGEN \
fx12mm \
G2000 \
gdppc440etx \
@ -404,6 +403,7 @@ LIST_85xx=" \
MPC8568MDS \
MPC8569MDS \
MPC8569MDS_ATM \
MPC8569MDS_NAND \
MPC8572DS \
MPC8572DS_36BIT \
P2020DS \
@ -587,6 +587,7 @@ LIST_ARM9=" \
spear310 \
spear320 \
spear600 \
suen3 \
trab \
VCMA9 \
versatile \
@ -599,6 +600,7 @@ LIST_ARM9=" \
davinci_sonata \
davinci_dm355evm \
davinci_dm355leopard \
davinci_dm365evm \
davinci_dm6467evm \
"
@ -632,6 +634,7 @@ LIST_ARM11=" \
#########################################################################
LIST_ARM_CORTEX_A8=" \
devkit8000 \
mx51evk \
omap3_beagle \
omap3_overo \
omap3_evm \
@ -663,6 +666,7 @@ LIST_at91=" \
CPU9260 \
CPU9G20 \
csb637 \
eb_cpux9k2 \
kb9202 \
meesc \
mp2usb \

21
Makefile
View file

@ -1336,9 +1336,6 @@ ebony_config: unconfig
ERIC_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx eric
EXBITGEN_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx exbitgen
fx12mm_flash_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
@mkdir -p $(obj)include $(obj)board/avnet/fx12mm
@ -2275,9 +2272,6 @@ MPC8313ERDB_NAND_66_config: unconfig
MPC8315ERDB_NAND_config \
MPC8315ERDB_config: unconfig
@if [ "$(findstring _NAND_,$@)" ] ; then \
ln -sf mpc8313erdb nand_spl/board/freescale/mpc8315erdb ; \
fi ;
@$(MKCONFIG) -t $(@:_config=) MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
MPC8323ERDB_config: unconfig
@ -2500,6 +2494,7 @@ MPC8568MDS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale
MPC8569MDS_ATM_config \
MPC8569MDS_NAND_config \
MPC8569MDS_config: unconfig
@$(MKCONFIG) -t $(@:_config=) MPC8569MDS ppc mpc85xx mpc8569mds freescale
@ -2716,6 +2711,9 @@ CPUAT91_config : unconfig
csb637_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t csb637 NULL at91rm9200
eb_cpux9k2_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t eb_cpux9k2 BuS at91
kb9202_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t kb9202 NULL at91rm9200
@ -3062,6 +3060,9 @@ spear320_config : unconfig
spear600_config : unconfig
@$(MKCONFIG) -n $@ -t $(@:_config=) spear6xx arm arm926ejs $(@:_config=) spear spear
suen3_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs km_arm keymile kirkwood
SX1_stdout_serial_config \
SX1_config: unconfig
@mkdir -p $(obj)include
@ -3102,6 +3103,10 @@ trab_old_config: unconfig
}
@$(MKCONFIG) -a $(call xtract_trab,$@) arm arm920t trab NULL s3c24x0
tx25_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs tx25 karo mx25
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
VCMA9_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t vcma9 mpl s3c24x0
@ -3302,6 +3307,9 @@ mx31pdk_nand_config : unconfig
fi
@$(MKCONFIG) -a mx31pdk arm arm1136 mx31pdk freescale mx31
mx51evk_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51evk freescale mx51
omap2420h4_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 ti omap24xx
@ -3773,6 +3781,7 @@ clobber: clean
$(obj)cscope.* $(obj)*.*~
@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
@rm -f $(obj)u-boot.kwb
@rm -f $(obj)u-boot.imx
@rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes}
@rm -f $(obj)cpu/mpc824x/bedbug_603e.c
@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm

10
README
View file

@ -822,6 +822,16 @@ The following options need to be configured:
- NETWORK Support (other):
CONFIG_DRIVER_AT91EMAC
Support for AT91RM9200 EMAC.
CONFIG_RMII
Define this to use reduced MII inteface
CONFIG_DRIVER_AT91EMAC_QUIET
If this defined, the driver is quiet.
The driver doen't show link status messages.
CONFIG_DRIVER_LAN91C96
Support for SMSC's LAN91C96 chips.

50
board/BuS/eb_cpux9k2/Makefile Normal file
View file

@ -0,0 +1,50 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := cpux9k2.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

1
board/BuS/eb_cpux9k2/config.mk Normal file
View file

@ -0,0 +1 @@
TEXT_BASE = 0x23f00000

387
board/BuS/eb_cpux9k2/cpux9k2.c Normal file
View file

@ -0,0 +1,387 @@
/*
* (C) Copyright 2008-2009
* BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
* Jens Scharsig <esw@bus-elektronik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <exports.h>
#include <net.h>
#include <netdev.h>
#include <nand.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_mc.h>
#ifdef CONFIG_STATUS_LED
#include <status_led.h>
#endif
#ifdef CONFIG_VIDEO
#include <bus_vcxk.h>
extern unsigned long display_width;
extern unsigned long display_height;
#endif
#ifdef CONFIG_CMD_NAND
void cpux9k2_nand_hw_init(void);
#endif
DECLARE_GLOBAL_DATA_PTR;
/*
* Miscelaneous platform dependent initialisations
*/
int board_init(void)
{
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
/* Enable Ctrlc */
console_init_f();
/* Correct IRDA resistor problem / Set PA23_TXD in Output */
writel(AT91_PMX_AA_TXD2, &pio->pioa.oer);
gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_STATUS_LED
status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
#endif
#ifdef CONFIG_CMD_NAND
cpux9k2_nand_hw_init();
#endif
return 0;
}
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
uchar mac[8];
uchar tm;
uchar midx;
uchar macn6, macn7;
#ifdef CONFIG_NET_MULTI
if (getenv("ethaddr") == NULL) {
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x00,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
(uchar *) &mac, sizeof(mac)) != 0) {
puts("Error reading MAC from EEPROM\n");
} else {
tm = 0;
macn6 = 0;
macn7 = 0xFF;
for (midx = 0; midx < 6; midx++) {
if ((mac[midx] != 0) && (mac[midx] != 0xFF))
tm++;
macn6 += mac[midx];
macn7 ^= mac[midx];
}
if ((macn6 != mac[6]) || (macn7 != mac[7]))
tm = 0;
if (tm)
eth_setenv_enetaddr("ethaddr", mac);
else
puts("Error: invalid MAC at EEPROM\n");
}
}
#endif
gd->jt[XF_do_reset] = (void *) do_reset;
#ifdef CONFIG_STATUS_LED
status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
#endif
return 0;
}
#endif
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
udelay(10000);
eth_init(gd->bd);
}
#endif
/*
* DRAM initialisations
*/
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size =
get_ram_size((volatile long *) PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
}
/*
* Ethernet initialisations
*/
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
int rc = 0;
rc = at91emac_register(bis, (u32) AT91_EMAC_BASE);
return rc;
}
#endif
/*
* Disk On Chip (NAND) Millenium initialization.
* The NAND lives in the CS2* space
*/
#if defined(CONFIG_CMD_NAND)
#define MASK_ALE (1 << 22) /* our ALE is AD22 */
#define MASK_CLE (1 << 21) /* our CLE is AD21 */
void cpux9k2_nand_hw_init(void)
{
unsigned long csr;
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_mc_t *mc = (at91_mc_t *) AT91_MC_BASE;
/* Setup Smart Media, fitst enable the address range of CS3 */
writel(readl(&mc->ebi.csa) | AT91_EBI_CSA_CS3A, &mc->ebi.csa);
/* RWH = 1 | RWS = 0 | TDF = 1 | NWS = 3 */
csr = AT91_SMC_CSR_RWHOLD(1) | AT91_SMC_CSR_TDF(1) |
AT91_SMC_CSR_NWS(3) |
AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_8 |
AT91_SMC_CSR_WSEN;
writel(csr, &mc->smc.csr[3]);
writel(AT91_PMX_CA_SMOE | AT91_PMX_CA_SMWE, &pio->pioc.asr);
writel(AT91_PMX_CA_BFCK | AT91_PMX_CA_SMOE | AT91_PMX_CA_SMWE,
&pio->pioc.pdr);
/* Configure PC2 as input (signal Nand READY ) */
writel(AT91_PMX_CA_BFAVD, &pio->pioc.per);
writel(AT91_PMX_CA_BFAVD, &pio->pioc.odr); /* disable output */
writel(AT91_PMX_CA_BFCK, &pio->pioc.codr);
/* PIOC clock enabling */
writel(1 << AT91_ID_PIOC, &pmc->pcer);
}
static void board_nand_hwcontrol(struct mtd_info *mtd,
int cmd, unsigned int ctrl)
{
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
if (ctrl & NAND_CTRL_CHANGE) {
IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
if (ctrl & NAND_CLE)
IO_ADDR_W |= MASK_CLE;
if (ctrl & NAND_ALE)
IO_ADDR_W |= MASK_ALE;
if ((ctrl & NAND_NCE))
writel(1, &pio->pioc.codr);
else
writel(1, &pio->pioc.sodr);
this->IO_ADDR_W = (void *) IO_ADDR_W;
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
static int board_nand_dev_ready(struct mtd_info *mtd)
{
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
return ((readl(&pio->pioc.pdsr) & (1 << 2)) != 0);
}
int board_nand_init(struct nand_chip *nand)
{
cpux9k2_nand_hw_init();
nand->ecc.mode = NAND_ECC_SOFT;
nand->cmd_ctrl = board_nand_hwcontrol;
nand->dev_ready = board_nand_dev_ready;
nand->chip_delay = 20;
return 0;
}
#endif
#if defined(CONFIG_VIDEO)
/*
* drv_video_init
* FUNCTION: initialize VCxK device
*/
int drv_video_init(void)
{
#ifdef CONFIG_SPLASH_SCREEN
unsigned long splash;
#endif
char *s;
unsigned long csr;
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_mc_t *mc = (at91_mc_t *) AT91_MC_BASE;
printf("Init Video as ");
s = getenv("displaywidth");
if (s != NULL)
display_width = simple_strtoul(s, NULL, 10);
else
display_width = 256;
s = getenv("displayheight");
if (s != NULL)
display_height = simple_strtoul(s, NULL, 10);
else
display_height = 256;
printf("%ld x %ld pixel matrix\n", display_width, display_height);
/* RWH = 7 | RWS =7 | TDF = 15 | NWS = 0x7F */
csr = AT91_SMC_CSR_RWHOLD(7) | AT91_SMC_CSR_RWSETUP(7) |
AT91_SMC_CSR_TDF(15) | AT91_SMC_CSR_NWS(127) |
AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 |
AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN;
writel(csr, &mc->smc.csr[2]);
writel(1 << AT91_ID_PIOB, &pmc->pcer);
vcxk_init(display_width, display_height);
#ifdef CONFIG_SPLASH_SCREEN
s = getenv("splashimage");
if (s != NULL) {
splash = simple_strtoul(s, NULL, 16);
printf("use splashimage: %lx\n", splash);
video_display_bitmap(splash, 0, 0);
}
#endif
return 0;
}
#endif
#ifdef CONFIG_SOFT_I2C
void i2c_init_board(void)
{
u32 pin;
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
writel(1 << AT91_ID_PIOA, &pmc->pcer);
pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
writel(pin, &pio->pioa.idr);
writel(pin, &pio->pioa.pudr);
writel(pin, &pio->pioa.per);
writel(pin, &pio->pioa.oer);
writel(pin, &pio->pioa.sodr);
}
#endif
/*--------------------------------------------------------------------------*/
#ifdef CONFIG_STATUS_LED
void __led_toggle(led_id_t mask)
{
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
if (readl(&pio->piod.odsr) & mask)
writel(mask, &pio->piod.codr);
else
writel(mask, &pio->piod.codr);
}
void __led_init(led_id_t mask, int state)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
writel(1 << AT91_ID_PIOD, &pmc->pcer); /* Enable PIOB clock */
/* Disable peripherals on LEDs */
writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.per);
/* Enable pins as outputs */
writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.oer);
/* Turn all LEDs OFF */
writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.sodr);
__led_set(mask, state);
}
void __led_set(led_id_t mask, int state)
{
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
if (state == STATUS_LED_ON)
writel(mask, &pio->piod.codr);
else
writel(mask, &pio->piod.sodr);
}
#endif
/*---------------------------------------------------------------------------*/
int do_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int rcode = 0;
ulong side;
ulong bright;
switch (argc) {
case 3:
side = simple_strtoul(argv[1], NULL, 10);
bright = simple_strtoul(argv[2], NULL, 10);
if ((side >= 0) && (side <= 3) &&
(bright >= 0) && (bright <= 1000)) {
vcxk_setbrightness(side, bright);
rcode = 0;
} else {
printf("parameters out of range\n");
printf("Usage:\n%s\n", cmdtp->usage);
rcode = 1;
}
break;
default:
printf("Usage:\n%s\n", cmdtp->usage);
rcode = 1;
break;
}
return rcode;
}
/*---------------------------------------------------------------------------*/
U_BOOT_CMD(
bright, 3, 0, do_brightness,
"bright - sets the display brightness\n",
" <side> <0..1000>\n side: 0/3=both; 1=first; 2=second\n"
);
/* EOF cpu9k2.c */

2
board/atmel/at91cap9adk/at91cap9adk.c
View file

@ -282,7 +282,7 @@ void lcd_show_board_info(void)
lcd_printf ("(C) 2008 ATMEL Corp\n");
lcd_printf ("at91support@atmel.com\n");
lcd_printf ("%s CPU at %s MHz\n",
AT91_CPU_NAME,
CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate()));
dram_size = 0;

15
board/atmel/at91rm9200dk/at91rm9200dk.c
View file

@ -23,9 +23,15 @@
*/
#include <common.h>
#include <exports.h>
#include <netdev.h>
#include <asm/arch/AT91RM9200.h>
#include <asm/io.h>
#if defined(CONFIG_DRIVER_ETHER)
#include <at91rm9200_net.h>
#include <dm9161.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -95,6 +101,15 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
#endif
#endif /* CONFIG_DRIVER_ETHER */
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
int rc = 0;
rc = at91emac_register(bis, 0);
return rc;
}
#endif
/*
* Disk On Chip (NAND) Millenium initialization.
* The NAND lives in the CS2* space

14
board/atmel/at91rm9200ek/at91rm9200ek.c
View file

@ -23,9 +23,14 @@
*/
#include <common.h>
#include <exports.h>
#include <netdev.h>
#include <asm/arch/AT91RM9200.h>
#include <asm/io.h>
#if defined(CONFIG_DRIVER_ETHER)
#include <at91rm9200_net.h>
#include <dm9161.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -84,3 +89,12 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
}
#endif
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
int rc = 0;
rc = at91emac_register(bis, 0);
return rc;
}
#endif

2
board/atmel/at91sam9261ek/at91sam9261ek.c
View file

@ -217,7 +217,7 @@ void lcd_show_board_info(void)
lcd_printf ("(C) 2008 ATMEL Corp\n");
lcd_printf ("at91support@atmel.com\n");
lcd_printf ("%s CPU at %s MHz\n",
AT91_CPU_NAME,
CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate()));
dram_size = 0;

155
board/atmel/at91sam9263ek/at91sam9263ek.c
View file

@ -25,13 +25,13 @@
#include <common.h>
#include <asm/sizes.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91sam9263_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <asm/arch/hardware.h>
#include <lcd.h>
@ -52,49 +52,57 @@ DECLARE_GLOBAL_DATA_PTR;
static void at91sam9263ek_nand_hw_init(void)
{
unsigned long csa;
at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE;
at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
/* Enable CS3 */
csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
writel(csa, &matrix->csa[0]);
/* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
at91_sys_write(AT91_MATRIX_EBI0CSA,
csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
AT91_SMC_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
AT91_SMC_DBW_8 |
#endif
AT91_SMC_TDF_(2));
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
&smc->cs[3].setup);
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
1 << AT91SAM9263_ID_PIOCDE);
writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
&smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
AT91_SMC_MODE_DBW_8 |
#endif
AT91_SMC_MODE_TDF_CYCLE(2),
&smc->cs[3].mode);
writel(1 << AT91SAM9263_ID_PIOA | 1 << AT91SAM9263_ID_PIOCDE,
&pmc->pcer);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
#ifdef CONFIG_MACB
static void at91sam9263ek_macb_hw_init(void)
{
unsigned long rstc;
unsigned long erstl;
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE;
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
/*
* Disable pull-up on:
@ -104,35 +112,27 @@ static void at91sam9263ek_macb_hw_init(void)
*
* PHY has internal pull-down
*/
writel(pin_to_mask(AT91_PIN_PC25),
pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
writel(pin_to_mask(AT91_PIN_PE25) |
pin_to_mask(AT91_PIN_PE26),
pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
writel(1 << 25, &pio->pioc.pudr);
writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(AT91_RSTC_ERSTL & (0x0D << 8)) |
AT91_RSTC_URSTEN);
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
AT91_RSTC_MR_URSTEN, &rstc->mr);
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
/* Wait for end hardware reset */
while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
;
/* Restore NRST value */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(rstc) |
AT91_RSTC_URSTEN);
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
/* Re-enable pull-up */
writel(pin_to_mask(AT91_PIN_PC25),
pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
writel(pin_to_mask(AT91_PIN_PE25) |
pin_to_mask(AT91_PIN_PE26),
pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
writel(1 << 25, &pio->pioc.puer);
writel((1 << 25) | (1 <<26), &pio->pioe.puer);
at91_macb_hw_init();
}
@ -158,41 +158,42 @@ vidinfo_t panel_info = {
void lcd_enable(void)
{
at91_set_gpio_value(AT91_PIN_PA30, 1); /* power up */
at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power up */
}
void lcd_disable(void)
{
at91_set_gpio_value(AT91_PIN_PA30, 0); /* power down */
at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power down */
}
static void at91sam9263ek_lcd_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer);
gd->fb_base = AT91SAM9263_SRAM0_BASE;
}
@ -217,7 +218,7 @@ void lcd_show_board_info(void)
lcd_printf ("(C) 2008 ATMEL Corp\n");
lcd_printf ("at91support@atmel.com\n");
lcd_printf ("%s CPU at %s MHz\n",
AT91_CPU_NAME,
CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate()));
dram_size = 0;
@ -258,7 +259,7 @@ int board_init(void)
at91sam9263ek_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
at91_set_gpio_output(AT91_PIN_PE20, 1); /* select spi0 clock */
at91_set_pio_output(AT91_PIO_PORTE, 20, 1); /* select spi0 clock */
at91_spi0_hw_init(1 << 0);
#endif
#ifdef CONFIG_MACB
@ -297,7 +298,7 @@ int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
rc = macb_eth_initialize(0, (void *) AT91_EMAC_BASE, 0x00);
#endif
return rc;
}

21
board/atmel/at91sam9263ek/led.c
View file

@ -23,22 +23,25 @@
*/
#include <common.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
void coloured_LED_init(void)
{
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB |
1 << AT91SAM9263_ID_PIOCDE);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_gpio_output(CONFIG_RED_LED, 1);
at91_set_gpio_output(CONFIG_GREEN_LED, 1);
at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
writel(1 << AT91SAM9263_ID_PIOB | 1 << AT91SAM9263_ID_PIOCDE,
&pmc->pcer);
at91_set_gpio_value(CONFIG_RED_LED, 0);
at91_set_gpio_value(CONFIG_GREEN_LED, 1);
at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
at91_set_pio_output(CONFIG_RED_LED, 1);
at91_set_pio_output(CONFIG_GREEN_LED, 1);
at91_set_pio_output(CONFIG_YELLOW_LED, 1);
at91_set_pio_value(CONFIG_RED_LED, 0);
at91_set_pio_value(CONFIG_GREEN_LED, 1);
at91_set_pio_value(CONFIG_YELLOW_LED, 1);
}

2
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
View file

@ -217,7 +217,7 @@ void lcd_show_board_info(void)
lcd_printf ("(C) 2008 ATMEL Corp\n");
lcd_printf ("at91support@atmel.com\n");
lcd_printf ("%s CPU at %s MHz\n",
AT91_CPU_NAME,
CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate()));
dram_size = 0;

2
board/atmel/at91sam9rlek/at91sam9rlek.c
View file

@ -157,7 +157,7 @@ void lcd_show_board_info(void)
lcd_printf ("(C) 2008 ATMEL Corp\n");
lcd_printf ("at91support@atmel.com\n");
lcd_printf ("%s CPU at %s MHz\n",
AT91_CPU_NAME,
CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate()));
dram_size = 0;

13
board/cmc_pu2/cmc_pu2.c
View file

@ -30,8 +30,12 @@
#include <common.h>
#include <asm/mach-types.h>
#include <asm/arch/AT91RM9200.h>
#include <asm/io.h>
#include <netdev.h>
#if defined(CONFIG_DRIVER_ETHER)
#include <at91rm9200_net.h>
#include <dm9161.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -177,3 +181,12 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
#endif
#endif /* CONFIG_DRIVER_ETHER */
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
int rc = 0;
rc = at91emac_register(bis, 0);
return rc;
}
#endif

13
board/csb637/csb637.c
View file

@ -23,8 +23,12 @@
#include <common.h>
#include <asm/arch/AT91RM9200.h>
#include <netdev.h>
#include <asm/io.h>
#if defined(CONFIG_DRIVER_ETHER)
#include <at91rm9200_net.h>
#include <bcm5221.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -79,3 +83,12 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
#endif
#endif /* CONFIG_DRIVER_ETHER */
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
int rc = 0;
rc = at91emac_register(bis, 0);
return rc;
}
#endif

102
board/davinci/da830evm/da830evm.c
View file

@ -34,7 +34,11 @@
#include <common.h>
#include <i2c.h>
#include <net.h>
#include <netdev.h>
#include <asm/arch/hardware.h>
#include <asm/arch/emif_defs.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
#include "../common/misc.h"
@ -51,6 +55,37 @@ static const struct pinmux_config spi0_pins[] = {
{ pinmux[7], 1, 7 }
};
/* EMIF-A bus pins for 8-bit NAND support on CS3 */
static const struct pinmux_config emifa_nand_pins[] = {
{ pinmux[13], 1, 6 },
{ pinmux[13], 1, 7 },
{ pinmux[14], 1, 0 },
{ pinmux[14], 1, 1 },
{ pinmux[14], 1, 2 },
{ pinmux[14], 1, 3 },
{ pinmux[14], 1, 4 },
{ pinmux[14], 1, 5 },
{ pinmux[15], 1, 7 },
{ pinmux[16], 1, 0 },
{ pinmux[18], 1, 1 },
{ pinmux[18], 1, 4 },
{ pinmux[18], 1, 5 },
};
/* EMAC PHY interface pins */
static const struct pinmux_config emac_pins[] = {
{ pinmux[9], 0, 5 },
{ pinmux[10], 2, 1 },
{ pinmux[10], 2, 2 },
{ pinmux[10], 2, 3 },
{ pinmux[10], 2, 4 },
{ pinmux[10], 2, 5 },
{ pinmux[10], 2, 6 },
{ pinmux[10], 2, 7 },
{ pinmux[11], 2, 0 },
{ pinmux[11], 2, 1 },
};
/* UART pin muxer settings */
static const struct pinmux_config uart_pins[] = {
{ pinmux[8], 2, 7 },
@ -59,8 +94,8 @@ static const struct pinmux_config uart_pins[] = {
/* I2C pin muxer settings */
static const struct pinmux_config i2c_pins[] = {
{ pinmux[9], 2, 3 },
{ pinmux[9], 2, 4 }
{ pinmux[8], 2, 3 },
{ pinmux[8], 2, 4 }
};
/* USB0_DRVVBUS pin muxer settings */
@ -77,6 +112,12 @@ static const struct pinmux_resource pinmuxes[] = {
#ifdef CONFIG_USB_DA8XX
PINMUX_ITEM(usb_pins),
#endif
#ifdef CONFIG_USE_NAND
PINMUX_ITEM(emifa_nand_pins),
#endif
#if defined(CONFIG_DRIVER_TI_EMAC)
PINMUX_ITEM(emac_pins),
#endif
};
int board_init(void)
@ -96,6 +137,22 @@ int board_init(void)
writel(0xffffffff, &davinci_aintc_regs->ecr3);
#endif
#ifdef CONFIG_NAND_DAVINCI
/* EMIFA 100MHz clock select */
writel(readl(&davinci_syscfg_regs->cfgchip3) & ~2,
&davinci_syscfg_regs->cfgchip3);
/* NAND CS setup */
writel((DAVINCI_ABCR_WSETUP(0) |
DAVINCI_ABCR_WSTROBE(2) |
DAVINCI_ABCR_WHOLD(0) |
DAVINCI_ABCR_RSETUP(0) |
DAVINCI_ABCR_RSTROBE(2) |
DAVINCI_ABCR_RHOLD(0) |
DAVINCI_ABCR_TA(2) |
DAVINCI_ABCR_ASIZE_8BIT),
&davinci_emif_regs->AB2CR);
#endif
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM;
@ -132,3 +189,44 @@ int board_init(void)
return(0);
}
#if defined(CONFIG_DRIVER_TI_EMAC)
#define PHY_SW_I2C_ADDR 0x5f /* Address of PHY on i2c bus */
/*
* Initializes on-board ethernet controllers.
*/
int board_eth_init(bd_t *bis)
{
u_int8_t mac_addr[6];
u_int8_t switch_start_cmd[2] = { 0x01, 0x23 };
/* Read Ethernet MAC address from EEPROM */
if (dvevm_read_mac_address(mac_addr))
/* set address env if not already set */
dv_configure_mac_address(mac_addr);
/* read the address back from env */
if (!eth_getenv_enetaddr("ethaddr", mac_addr))
return -1;
/* provide the resulting addr to the driver */
davinci_eth_set_mac_addr(mac_addr);
/* enable the Ethernet switch in the 3 port PHY */
if (i2c_write(PHY_SW_I2C_ADDR, 0, 0,
switch_start_cmd, sizeof(switch_start_cmd))) {
printf("Ethernet switch start failed!\n");
return -1;
}
/* finally, initialise the driver */
if (!davinci_emac_initialize()) {
printf("Error: Ethernet init failed!\n");
return -1;
}
return 0;
}
#endif /* CONFIG_DRIVER_TI_EMAC */

39
board/edb93xx/sdram_cfg.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
* Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
*
* Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
*
@ -30,9 +30,9 @@
(SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL))
#define PRECHARGE_BANK(bank) (*(volatile uint32_t *) \
(SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank))
(SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank)) = 0
static void force_precharge(void);
static void precharge_all_banks(void);
static void setup_refresh_timer(void);
static void program_mode_registers(void);
@ -47,7 +47,7 @@ void sdram_cfg(void)
early_udelay(200);
force_precharge();
precharge_all_banks();
setup_refresh_timer();
@ -57,19 +57,37 @@ void sdram_cfg(void)
writel(GLCONFIG_CKE, &sdram->glconfig);
}
static void force_precharge(void)
static void precharge_all_banks(void)
{
struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
/* Issue PRECHARGE ALL commands */
writel(GLCONFIG_INIT | GLCONFIG_CKE, &sdram->glconfig);
/*
* Errata most EP93xx revisions say that PRECHARGE ALL isn't always
* issued.
* Errata of most EP93xx revisions say that PRECHARGE ALL isn't always
* issued
*
* Do a read from each bank to make sure they're precharged
* Cirrus proposes a workaround which consists in performing a read from
* each bank to force the precharge. This causes some boards to hang.
* Writing to the SDRAM banks instead of reading has the same
* side-effect (the SDRAM controller issues the necessary precharges),
* but is known to work on all supported boards
*/
PRECHARGE_BANK(0);
#if (CONFIG_NR_DRAM_BANKS >= 2)
PRECHARGE_BANK(1);
#endif
#if (CONFIG_NR_DRAM_BANKS >= 3)
PRECHARGE_BANK(2);
#endif
#if (CONFIG_NR_DRAM_BANKS == 4)
PRECHARGE_BANK(3);
#endif
}
static void setup_refresh_timer(void)
@ -101,6 +119,11 @@ static void setup_refresh_timer(void)
static void program_mode_registers(void)
{
struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
/* Select mode register update mode */
writel(GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
/*
* The mode registers are programmed by performing a read from each
* SDRAM bank. The value of the address that is read defines the value

178
board/esd/otc570/otc570.c
View file

@ -28,13 +28,13 @@
#include <common.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91sam9_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hardware.h>
#include <asm/arch/io.h>
#include <atmel_lcdc.h>
@ -58,10 +58,10 @@ int get_hw_rev(void)
if (hw_rev >= 0)
return hw_rev;
hw_rev = at91_get_gpio_value(AT91_PIN_PB19);
hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1;
hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2;
hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3;
hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
if (hw_rev == 15)
hw_rev = 0;
@ -73,40 +73,44 @@ int get_hw_rev(void)
static void otc570_nand_hw_init(void)
{
unsigned long csa;
at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE;
at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
/* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
at91_sys_write(AT91_MATRIX_EBI0CSA,
csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
writel(csa, &matrix->csa[0]);
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_DBW_8 |
AT91_SMC_TDF_(2));
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
&smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
&smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
AT91_SMC_MODE_DBW_8 |
AT91_SMC_MODE_TDF_CYCLE(2),
&smc->cs[3].mode);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif /* CONFIG_CMD_NAND */
#ifdef CONFIG_MACB
static void otc570_macb_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
at91_macb_hw_init();
}
#endif
@ -119,26 +123,27 @@ static void otc570_macb_hw_init(void)
*/
static void otc570_ethercat_hw_init(void)
{
at91_smc_t *smc1 = (at91_smc_t *) AT91_SMC1_BASE;
/* Configure SMC EBI1_CS0 for EtherCAT */
at91_sys_write(AT91_SMC1_SETUP(0),
AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC1_PULSE(0),
AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) |
AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(9));
at91_sys_write(AT91_SMC1_CYCLE(0),
AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(6));
writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
&smc1->cs[0].setup);
writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
&smc1->cs[0].pulse);
writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
&smc1->cs[0].cycle);
/*
* Configure behavior at external wait signal, byte-select mode, 16 bit
* data bus width, none data float wait states and TDF optimization
*/
at91_sys_write(AT91_SMC1_MODE(0),
AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY |
AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) |
AT91_SMC_TDFMODE);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
/* Configure RDY/BSY */
at91_set_B_periph(AT91_PIN_PE20, 0); /* EBI1_NWAIT */
at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
}
#ifdef CONFIG_LCD
@ -164,43 +169,44 @@ vidinfo_t panel_info = {
void lcd_enable(void)
{
at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */
at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power up */
}
void lcd_disable(void)
{
at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */
at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power down */
}
static void otc570_lcd_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDVSYNC */
at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
at91_set_gpio_output(AT91_PIN_PA30, 1); /* PCI */
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
at91_set_pio_output(AT91_PIO_PORTA, 30, 1); /* PCI */
writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer);
gd->fb_base = CONFIG_OTC570_LCD_BASE;
}
@ -219,7 +225,7 @@ void lcd_show_board_info(void)
nand_size += nand_info[i].size;
lcd_printf("\n%s\n", U_BOOT_VERSION);
lcd_printf("%s CPU at %s MHz\n", AT91_CPU_NAME,
lcd_printf("%s CPU at %s MHz\n", CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate()));
lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20,
@ -242,7 +248,7 @@ int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00);
#endif
return rc;
}
@ -290,32 +296,33 @@ u32 get_board_rev(void)
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
char str[64];
char str[64];
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_gpio_output(AT91_PIN_PA29, 1);
at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0);
at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */
at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */
writel(1 << AT91SAM9263_ID_US0, &pmc->pcer);
/* Set USART_MODE = 1 (RS485) */
at91_sys_write((0xFFF8C004 - AT91_BASE_SYS), 1);
writel(1, 0xFFF8C004);
printf("USART0: ");
if (getenv_r("usart0", str, sizeof(str)) == -1) {
printf("No entry - assuming 1-wire\n");
/* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */
at91_set_gpio_output(AT91_PIN_PA29, 0);
at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
} else {
if (strcmp(str, "1-wire") == 0) {
printf("%s\n", str);
at91_set_gpio_output(AT91_PIN_PA29, 0);
at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
} else if (strcmp(str, "rs485") == 0) {
printf("%s\n", str);
at91_set_gpio_output(AT91_PIN_PA29, 1);
at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
} else {
printf("Wrong entry - assuming 1-wire ");
printf("(valid values are '1-wire' or 'rs485')\n");
at91_set_gpio_output(AT91_PIN_PA29, 0);
at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
}
}
printf("Display memory address: 0x%08lX\n", gd->fb_base);
@ -326,14 +333,17 @@ int misc_init_r(void)
int board_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
/* Peripheral Clock Enable Register */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
1 << AT91SAM9263_ID_PIOB |
1 << AT91SAM9263_ID_PIOCDE |
1 << AT91SAM9263_ID_TWI |
1 << AT91SAM9263_ID_SPI0 |
1 << AT91SAM9263_ID_LCDC |
1 << AT91SAM9263_ID_UHP);
writel( 1 << AT91SAM9263_ID_PIOA |
1 << AT91SAM9263_ID_PIOB |
1 << AT91SAM9263_ID_PIOCDE |
1 << AT91SAM9263_ID_TWI |
1 << AT91SAM9263_ID_SPI0 |
1 << AT91SAM9263_ID_LCDC |
1 << AT91SAM9263_ID_UHP,
&pmc->pcer);
/* arch number of OTC570-Board */
gd->bd->bi_arch_number = MACH_TYPE_OTC570;

28
board/esd/plu405/plu405.c
View file

@ -46,6 +46,34 @@ const unsigned char fpgadata[] =
*/
#include "../common/fpga.c"
/*
* generate a short spike on the CAN tx line
* to bring the couplers in sync
*/
void init_coupler(u32 addr)
{
struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
/* reset */
out_8(&ctrl->cr, CR_RR);
/* dominant */
out_8(&ctrl->btr0, 0x00); /* btr setup is required */
out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
out_8(&ctrl->cr, 0x00);
/* delay */
in_8(&ctrl->cr);
in_8(&ctrl->cr);
in_8(&ctrl->cr);
in_8(&ctrl->cr);
/* reset */
out_8(&ctrl->cr, CR_RR);
}
int board_early_init_f(void)
{
/*

14
board/eukrea/cpuat91/cpuat91.c
View file

@ -26,9 +26,14 @@
*/
#include <common.h>
#include <netdev.h>
#include <asm/arch/AT91RM9200.h>
#include <asm/io.h>
#if defined(CONFIG_DRIVER_ETHER)
#include <at91rm9200_net.h>
#include <ks8721.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -79,3 +84,12 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
#endif /* CONFIG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
int rc = 0;
rc = at91emac_register(bis, 0);
return rc;
}
#endif

126
board/exbitgen/exbitgen.c
View file

@ -1,126 +0,0 @@
#include <common.h>
#include <asm/u-boot.h>
#include <asm/processor.h>
#include "exbitgen.h"
void sdram_init(void);
/* ************************************************************************ */
int board_early_init_f (void)
/* ------------------------------------------------------------------------ --
* Purpose :
* Remarks :
* Restrictions:
* See also :
* Example :
* ************************************************************************ */
{
unsigned long i;
/*-------------------------------------------------------------------------+
| Interrupt controller setup for the Walnut board.
| Note: IRQ 0-15 405GP internally generated; active high; level sensitive
| IRQ 16 405GP internally generated; active low; level sensitive
| IRQ 17-24 RESERVED
| IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
| IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
| IRQ 27 (EXT IRQ 2) Not Used
| IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
| IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
| IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
| IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
| Note for Walnut board:
| An interrupt taken for the FPGA (IRQ 25) indicates that either
| the Mouse, Keyboard, IRDA, or External Expansion caused the
| interrupt. The FPGA must be read to determine which device
| caused the interrupt. The default setting of the FPGA clears
|
+-------------------------------------------------------------------------*/
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF90); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
/* Perform reset of PHY connected to PPC via register in CPLD */
out8 (PHY_CTRL_ADDR, 0x2e); /* activate nRESET,FDX,F100,ANEN, enable output */
for (i = 0; i < 10000000; i++) {
;
}
out8 (PHY_CTRL_ADDR, 0x2f); /* deactivate nRESET */
return 0;
}
/* ************************************************************************ */
int checkboard (void)
/* ------------------------------------------------------------------------ --
* Purpose :
* Remarks :
* Restrictions:
* See also :
* Example :
* ************************************************************************ */
{
printf ("Exbit H/W id: %d\n", in8 (HW_ID_ADDR));
return (0);
}
/* ************************************************************************ */
phys_size_t initdram (int board_type)
/* ------------------------------------------------------------------------ --
* Purpose : Determines size of mounted DRAM.
* Remarks : Size is determined by reading SDRAM configuration registers as
* set up by sdram_init.
* Restrictions:
* See also :
* Example :
* ************************************************************************ */
{
ulong tot_size;
ulong bank_size;
ulong tmp;
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
* in cpu/ppc4xx
*/
sdram_init();
tot_size = 0;
mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
return tot_size;
}

597
board/exbitgen/flash.c
View file

@ -1,597 +0,0 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Modified 4/5/2001
* Wait for completion of each sector erase command issued
* 4/5/2001
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
*/
#include <common.h>
#include <asm/u-boot.h>
#include <asm/processor.h>
#include <ppc4xx.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
#ifdef MEIGSBOARD_ONBOARD_FLASH /* onboard = 2MB */
# ifdef CONFIG_EXBITGEN
# define FLASH_WORD_SIZE unsigned long
# endif
#else /* Meigsboard socket flash = 512KB */
# ifdef CONFIG_EXBITGEN
# define FLASH_WORD_SIZE unsigned char
# endif
#endif
#ifdef CONFIG_EXBITGEN
#define ADDR0 0x5555
#define ADDR1 0x2aaa
#define FLASH_WORD_SIZE unsigned char
#endif
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long bank_size;
unsigned long tot_size;
unsigned long bank_addr;
int i;
/* Init: no FLASHes known */
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].size = 0;
}
tot_size = 0;
/* Detect Boot Flash */
bank_addr = CONFIG_SYS_FLASH0_BASE;
bank_size = flash_get_size((vu_long *)bank_addr, &flash_info[0]);
if (bank_size > 0) {
(void)flash_protect(FLAG_PROTECT_CLEAR,
bank_addr,
bank_addr + bank_size - 1,
&flash_info[0]);
}
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Boot Flash Bank\n");
}
flash_info[0].size = bank_size;
tot_size += bank_size;
/* Detect Application Flash */
bank_addr = CONFIG_SYS_FLASH1_BASE;
for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
bank_size = flash_get_size((vu_long *)bank_addr, &flash_info[i]);
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
break;
}
if (bank_size > 0) {
(void)flash_protect(FLAG_PROTECT_CLEAR,
bank_addr,
bank_addr + bank_size - 1,
&flash_info[i]);
}
flash_info[i].size = bank_size;
tot_size += bank_size;
bank_addr += bank_size;
}
if (flash_info[1].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Application Flash Bank\n");
}
/* Protect monitor and environment sectors */
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[0]);
#if 0xfffffffc >= CONFIG_SYS_FLASH0_BASE
#if 0xfffffffc <= CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_FLASH0_SIZE - 1
flash_protect(FLAG_PROTECT_SET,
0xfffffffc, 0xffffffff,
&flash_info[0]);
#endif
#endif
#endif
#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
&flash_info[0]);
#endif
return tot_size;
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
case FLASH_MAN_SST: printf ("SST "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
break;
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
break;
case FLASH_AMDLV033C: printf ("AM29LV033C (32 Mbit, uniform sector size)\n");
break;
case FLASH_AMDLV065D: printf ("AM29LV065D (64 Mbit, uniform sector size)\n");
break;
case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
break;
case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
break;
case FLASH_SST040: printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
printf ("\n");
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
FLASH_WORD_SIZE value;
ulong base = (ulong)addr;
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
/* Write auto select command: read Manufacturer ID */
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
value = addr2[0];
switch (value) {
case (FLASH_WORD_SIZE)AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case (FLASH_WORD_SIZE)FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
case (FLASH_WORD_SIZE)SST_MANUFACT:
info->flash_id = FLASH_MAN_SST;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
value = addr2[1]; /* device ID */
switch (value) {
case (FLASH_WORD_SIZE)AMD_ID_F040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x0080000; /* => 512 ko */
break;
case (FLASH_WORD_SIZE)AMD_ID_LV400T:
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 0.5 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV400B:
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 0.5 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV033C:
info->flash_id += FLASH_AMDLV033C;
info->sector_count = 64;
info->size = 0x00400000;
break; /* => 4 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV065D:
info->flash_id += FLASH_AMDLV065D;
info->sector_count = 128;
info->size = 0x00800000;
break; /* => 8 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV320T:
info->flash_id += FLASH_AM320T;
info->sector_count = 67;
info->size = 0x00400000;
break; /* => 4 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV320B:
info->flash_id += FLASH_AM320B;
info->sector_count = 67;
info->size = 0x00400000;
break; /* => 4 MB */
case (FLASH_WORD_SIZE)SST_ID_xF800A:
info->flash_id += FLASH_SST800A;
info->sector_count = 16;
info->size = 0x00100000;
break; /* => 1 MB */
case (FLASH_WORD_SIZE)SST_ID_xF160A:
info->flash_id += FLASH_SST160A;
info->sector_count = 32;
info->size = 0x00200000;
break; /* => 2 MB */
case (FLASH_WORD_SIZE)SST_ID_xF040:
info->flash_id += FLASH_SST040;
info->sector_count = 128;
info->size = 0x00080000;
break; /* => 512KB */
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
(info->flash_id == FLASH_AM040) ||
(info->flash_id == FLASH_AMDLV033C) ||
(info->flash_id == FLASH_AMDLV065D)) {
ulong sectsize = info->size / info->sector_count;
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * sectsize);
} else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
info->protect[i] = 0;
else
info->protect[i] = addr2[2] & 1;
}
/* switch to the read mode */
if (info->flash_id != FLASH_UNKNOWN) {
addr2 = (FLASH_WORD_SIZE *)info->start[0];
*addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
}
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
volatile FLASH_WORD_SIZE *addr2;
int flag, prot, sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if (info->flash_id == FLASH_UNKNOWN) {
printf ("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
start = get_timer (0);
last = start;
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr2[0] = (FLASH_WORD_SIZE)0x00300030;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
while ((addr2[0] & 0x00800080) !=
(FLASH_WORD_SIZE) 0x00800080) {
if ((now=get_timer(start)) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
addr[0] = (FLASH_WORD_SIZE)0x00F000F0;
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
addr[0] = (FLASH_WORD_SIZE)0x00F000F0;
}
}
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
ulong start;
int flag;
int i;
/* Check if Flash is (sufficiently) erased */
if ((*((volatile ulong *)dest) & data) != data) {
printf("dest = %08lx, *dest = %08lx, data = %08lx\n",
dest, *(volatile ulong *)dest, data);
return 2;
}
for (i=0; i < 4/sizeof(FLASH_WORD_SIZE); i++) {
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
dest2[i] = data2[i];
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
while ((dest2[i] & 0x00800080) != (data2[i] & 0x00800080)) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
addr2[0] = (FLASH_WORD_SIZE)0x00F000F0;
return (1);
}
}
}
addr2[0] = (FLASH_WORD_SIZE)0x00F000F0;
return (0);
}
/*-----------------------------------------------------------------------
*/

1011
board/exbitgen/init.S
View file

File diff suppressed because it is too large Load diff

3
board/freescale/mpc8360emds/mpc8360emds.c
View file

@ -159,7 +159,8 @@ int board_eth_init(bd_t *bd)
int i;
for (i = 0; i < ARRAY_SIZE(uec_info); i++)
uec_info[i].enet_interface = ENET_1000_RGMII_RXID;
uec_info[i].enet_interface_type = RGMII_RXID;
uec_info[i].speed = 1000;
}
return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
}

9
board/freescale/mpc8569mds/config.mk
View file

@ -23,4 +23,13 @@
#
# mpc8569mds board
#
ifndef NAND_SPL
ifeq ($(CONFIG_MK_NAND), y)
TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds
endif
endif
ifndef TEXT_BASE
TEXT_BASE = 0xfff80000
endif

11
board/freescale/mpc8569mds/tlb.c
View file

@ -90,6 +90,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_64M, 1),
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
/* *I*G - L2SRAM */
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

48
board/freescale/mx51evk/Makefile Normal file
View file

@ -0,0 +1,48 @@
#
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
#
# (C) Copyright 2009 Freescale Semiconductor, Inc.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := mx51evk.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

16
board/exbitgen/config.mk → board/freescale/mx51evk/config.mk
View file

@ -1,6 +1,5 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
#
# See file CREDITS for list of people who contributed to this
# project.
@ -21,13 +20,6 @@
# MA 02111-1307 USA
#
#
# ExbitGen board
#
LDFLAGS += $(LINKER_UNDEFS)
TEXT_BASE := 0xFFF80000
#TEXT_BASE := 0x00100000
PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS)
LDSCRIPT = cpu/$(CPU)/$(SOC)/u-boot.lds
TEXT_BASE = 0x97800000
IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg

119
board/freescale/mx51evk/imximage.cfg Normal file
View file

@ -0,0 +1,119 @@
#
# (C Copyright 2009
# Stefano Babic DENX Software Engineering sbabic@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
# MA 02110-1301 USA
#
# Refer docs/README.imxmage for more details about how-to configure
# and create imximage boot image
#
# The syntax is taken as close as possible with the kwbimage
# Boot Device : one of
# spi_flash, nand, onenand, sd_card
BOOT_FROM spi
# Device Configuration Data (DCD)
#
# Each entry must have the format:
# Addr-type Address Value
#
# where:
# Addr-type register length (1,2 or 4 bytes)
# Address absolute address of the register
# value value to be stored in the register
# Setting IOMUXC
DATA 4 0x73FA88a0 0x200
DATA 4 0x73FA850c 0x20c5
DATA 4 0x73FA8510 0x20c5
DATA 4 0x73FA883c 0x2
DATA 4 0x73FA8848 0x2
DATA 4 0x73FA84b8 0xe7
DATA 4 0x73FA84bc 0x45
DATA 4 0x73FA84c0 0x45
DATA 4 0x73FA84c4 0x45
DATA 4 0x73FA84c8 0x45
DATA 4 0x73FA8820 0x0
DATA 4 0x73FA84a4 0x3
DATA 4 0x73FA84a8 0x3
DATA 4 0x73FA84ac 0xe3
DATA 4 0x73FA84b0 0xe3
DATA 4 0x73FA84b4 0xe3
DATA 4 0x73FA84cc 0xe3
DATA 4 0x73FA84d0 0xe2
DATA 4 0x73FA882c 0x6
DATA 4 0x73FA88a4 0x6
DATA 4 0x73FA88ac 0x6
DATA 4 0x73FA88b8 0x6
# Setting DDR for micron
# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
# CAS=3 BL=4
# ESDCTL_ESDCTL0
DATA 4 0x83FD9000 0x82a20000
# ESDCTL_ESDCTL1
DATA 4 0x83FD9008 0x82a20000
# ESDCTL_ESDMISC
DATA 4 0x83FD9010 0x000ad0d0
# ESDCTL_ESDCFG0
DATA 4 0x83FD9004 0x333574aa
# ESDCTL_ESDCFG1
DATA 4 0x83FD900C 0x333574aa
# Init DRAM on CS0
# ESDCTL_ESDSCR
DATA 4 0x83FD9014 0x04008008
DATA 4 0x83FD9014 0x0000801a
DATA 4 0x83FD9014 0x0000801b
DATA 4 0x83FD9014 0x00448019
DATA 4 0x83FD9014 0x07328018
DATA 4 0x83FD9014 0x04008008
DATA 4 0x83FD9014 0x00008010
DATA 4 0x83FD9014 0x00008010
DATA 4 0x83FD9014 0x06328018
DATA 4 0x83FD9014 0x03808019
DATA 4 0x83FD9014 0x00408019
DATA 4 0x83FD9014 0x00008000
# Init DRAM on CS1
DATA 4 0x83FD9014 0x0400800c
DATA 4 0x83FD9014 0x0000801e
DATA 4 0x83FD9014 0x0000801f
DATA 4 0x83FD9014 0x0000801d
DATA 4 0x83FD9014 0x0732801c
DATA 4 0x83FD9014 0x0400800c
DATA 4 0x83FD9014 0x00008014
DATA 4 0x83FD9014 0x00008014
DATA 4 0x83FD9014 0x0632801c
DATA 4 0x83FD9014 0x0380801d
DATA 4 0x83FD9014 0x0040801d
DATA 4 0x83FD9014 0x00008004
# Write to CTL0
DATA 4 0x83FD9000 0xb2a20000
# Write to CTL1
DATA 4 0x83FD9008 0xb2a20000
# ESDMISC
DATA 4 0x83FD9010 0x000ad6d0
#ESDCTL_ESDCDLYGD
DATA 4 0x83FD9034 0x90000000
DATA 4 0x83FD9014 0x00000000

397
board/freescale/mx51evk/mx51evk.c Normal file
View file

@ -0,0 +1,397 @@
/*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx51_pins.h>
#include <asm/arch/iomux.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include "mx51evk.h"
DECLARE_GLOBAL_DATA_PTR;
static u32 system_rev;
struct io_board_ctrl *mx51_io_board;
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR, 1, 1},
{MMC_SDHC2_BASE_ADDR, 1, 1},
};
#endif
u32 get_board_rev(void)
{
return system_rev;
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
return 0;
}
static void setup_iomux_uart(void)
{
unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
}
static void setup_expio(void)
{
u32 reg;
struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
struct clkctl *pclkctl = (struct clkctl *)CCM_BASE_ADDR;
/* CS5 setup */
mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0);
writel(0x00410089, &pweim[5].csgcr1);
writel(0x00000002, &pweim[5].csgcr2);
/* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
writel(0x32260000, &pweim[5].csrcr1);
/* APR = 0 */
writel(0x00000000, &pweim[5].csrcr2);
/*
* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0,
* WCSA=0, WCSN=0
*/
writel(0x72080F00, &pweim[5].cswcr1);
mx51_io_board = (struct io_board_ctrl *)(CS5_BASE_ADDR +
IO_BOARD_OFFSET);
if ((readw(&mx51_io_board->id1) == 0xAAAA) &&
(readw(&mx51_io_board->id2) == 0x5555)) {
if (is_soc_rev(CHIP_REV_2_0) < 0) {
reg = readl(&pclkctl->cbcdr);
reg = (reg & (~0x70000)) | 0x30000;
writel(reg, &pclkctl->cbcdr);
/* make sure divider effective */
while (readl(&pclkctl->cdhipr) != 0)
;
writel(0x0, &pclkctl->ccdr);
}
} else {
/* CS1 */
writel(0x00410089, &pweim[1].csgcr1);
writel(0x00000002, &pweim[1].csgcr2);
/* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
writel(0x32260000, &pweim[1].csrcr1);
/* APR=0 */
writel(0x00000000, &pweim[1].csrcr2);
/*
* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
* WEN=0, WCSA=0, WCSN=0
*/
writel(0x72080F00, &pweim[1].cswcr1);
mx51_io_board = (struct io_board_ctrl *)(CS1_BASE_ADDR +
IO_BOARD_OFFSET);
}
/* Reset interrupt status reg */
writew(0x1F, &(mx51_io_board->int_rest));
writew(0x00, &(mx51_io_board->int_rest));
writew(0xFFFF, &(mx51_io_board->int_mask));
/* Reset the XUART and Ethernet controllers */
reg = readw(&(mx51_io_board->sw_reset));
reg |= 0x9;
writew(reg, &(mx51_io_board->sw_reset));
reg &= ~0x9;
writew(reg, &(mx51_io_board->sw_reset));
}
static void setup_iomux_fec(void)
{
/*FEC_MDIO*/
mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
/*FEC_MDC*/
mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
/* FEC RDATA[3] */
mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
/* FEC RDATA[2] */
mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
/* FEC RDATA[1] */
mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
/* FEC RDATA[0] */
mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
/* FEC TDATA[3] */
mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
/* FEC TDATA[2] */
mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
/* FEC TDATA[1] */
mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
/* FEC TDATA[0] */
mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
/* FEC TX_EN */
mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
/* FEC TX_ER */
mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
/* FEC TX_CLK */
mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
/* FEC TX_COL */
mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
/* FEC RX_CLK */
mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
/* FEC RX_CRS */
mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
/* FEC RX_ER */
mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
/* FEC RX_DV */
mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
}
#ifdef CONFIG_FSL_ESDHC
int board_mmc_getcd(u8 *cd, struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
*cd = readl(GPIO1_BASE_ADDR) & 0x01;
else
*cd = readl(GPIO1_BASE_ADDR) & 0x40;
return 0;
}
int board_mmc_init(bd_t *bis)
{
u32 index;
s32 status = 0;
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
index++) {
switch (index) {
case 0:
mxc_request_iomux(MX51_PIN_SD1_CMD,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_request_iomux(MX51_PIN_SD1_CLK,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_request_iomux(MX51_PIN_SD1_DATA0,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_request_iomux(MX51_PIN_SD1_DATA1,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_request_iomux(MX51_PIN_SD1_DATA2,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_request_iomux(MX51_PIN_SD1_DATA3,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
PAD_CTL_PUE_PULL |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
PAD_CTL_PUE_PULL |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
PAD_CTL_PUE_PULL |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
PAD_CTL_PUE_PULL |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
PAD_CTL_PUE_PULL |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
PAD_CTL_PUE_PULL |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_GPIO1_0,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
PAD_CTL_HYS_ENABLE);
mxc_request_iomux(MX51_PIN_GPIO1_1,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
PAD_CTL_HYS_ENABLE);
break;
case 1:
mxc_request_iomux(MX51_PIN_SD2_CMD,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_request_iomux(MX51_PIN_SD2_CLK,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_request_iomux(MX51_PIN_SD2_DATA0,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX51_PIN_SD2_DATA1,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX51_PIN_SD2_DATA2,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX51_PIN_SD2_DATA3,
IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_SD2_CMD,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_request_iomux(MX51_PIN_GPIO1_6,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
PAD_CTL_HYS_ENABLE);
mxc_request_iomux(MX51_PIN_GPIO1_5,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
PAD_CTL_HYS_ENABLE);
break;
default:
printf("Warning: you configured more ESDHC controller"
"(%d) as supported by the board(2)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
return status;
}
status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
}
return status;
}
#endif
int board_init(void)
{
system_rev = get_cpu_rev();
gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE;
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
setup_iomux_uart();
setup_expio();
setup_iomux_fec();
return 0;
}
int checkboard(void)
{
puts("Board: MX51EVK ");
switch (system_rev & 0xff) {
case CHIP_REV_3_0:
puts("3.0 [");
break;
case CHIP_REV_2_5:
puts("2.5 [");
break;
case CHIP_REV_2_0:
puts("2.0 [");
break;
case CHIP_REV_1_1:
puts("1.1 [");
break;
case CHIP_REV_1_0:
default:
puts("1.0 [");
break;
}
switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {
case 0x0001:
puts("POR");
break;
case 0x0009:
puts("RST");
break;
case 0x0010:
case 0x0011:
puts("WDOG");
break;
default:
puts("unknown");
}
puts("]\n");
return 0;
}

51
board/freescale/mx51evk/mx51evk.h Normal file
View file

@ -0,0 +1,51 @@
/*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __BOARD_FREESCALE_MX51_EVK_H__
#define __BOARD_FREESCALE_MX51_EVK_H__
#ifndef __ASSEMBLY__
struct io_board_ctrl {
u16 led_ctrl; /* 0x00 */
u16 resv1[0x03];
u16 sb_stat; /* 0x08 */
u16 resv2[0x03];
u16 int_stat; /* 0x10 */
u16 resv3[0x07];
u16 int_rest; /* 0x20 */
u16 resv4[0x0B];
u16 int_mask; /* 0x38 */
u16 resv5[0x03];
u16 id1; /* 0x40 */
u16 resv6[0x03];
u16 id2; /* 0x48 */
u16 resv7[0x03];
u16 version; /* 0x50 */
u16 resv8[0x03];
u16 id3; /* 0x58 */
u16 resv9[0x03];
u16 sw_reset; /* 0x60 */
};
#endif
#define IO_BOARD_OFFSET (0x20000)
#endif

15
board/exbitgen/Makefile → board/karo/tx25/Makefile
View file

@ -1,6 +1,6 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# (C) Copyright 2009 DENX Software Engineering
# Author: John Rigby <jcrigby@gmail.com>
#
# See file CREDITS for list of people who contributed to this
# project.
@ -25,16 +25,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o
SOBJS = init.o
COBJS := tx25.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $^
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
@ -44,9 +43,9 @@ distclean: clean
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

5
board/karo/tx25/config.mk Normal file
View file

@ -0,0 +1,5 @@
ifdef CONFIG_NAND_SPL
TEXT_BASE = 0x81ec0000
else
TEXT_BASE = 0x81f00000
endif

131
board/karo/tx25/lowlevel_init.S Normal file
View file

@ -0,0 +1,131 @@
/*
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
*
* Based on U-Boot and RedBoot sources for several different i.mx
* platforms.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm/macro.h>
.macro init_aips
write32 0x43f00000, 0x77777777
write32 0x43f00004, 0x77777777
write32 0x43f00000, 0x77777777
write32 0x53f00004, 0x77777777
.endm
.macro init_max
write32 0x43f04000, 0x43210
write32 0x43f04100, 0x43210
write32 0x43f04200, 0x43210
write32 0x43f04300, 0x43210
write32 0x43f04400, 0x43210
write32 0x43f04010, 0x10
write32 0x43f04110, 0x10
write32 0x43f04210, 0x10
write32 0x43f04310, 0x10
write32 0x43f04410, 0x10
write32 0x43f04800, 0x0
write32 0x43f04900, 0x0
write32 0x43f04a00, 0x0
write32 0x43f04b00, 0x0
write32 0x43f04c00, 0x0
.endm
.macro init_m3if
write32 0xb8003000, 0x1
.endm
.macro init_clocks
/*
* clocks
*
* first enable CLKO debug output
* 0x40000000 enables the debug CLKO signal
* 0x05000000 sets CLKO divider to 6
* 0x00600000 makes CLKO parent clk the USB clk
*/
write32 0x53f80064, 0x45600000
write32 0x53f80008, 0x20034000
/*
* enable all implemented clocks in all three
* clock control registers
*/
write32 0x53f8000c, 0x1fffffff
write32 0x53f80010, 0xffffffff
write32 0x53f80014, 0xfdfff
.endm
.macro init_ddrtype
/*
* ddr_type is 3.3v SDRAM
*/
write32 0x43fac454, 0x800
.endm
/*
* sdram controller init
*/
.macro init_sdram_bank bankaddr, ctl, cfg
ldr r0, =0xb8001000
ldr r2, =\bankaddr
/*
* reset SDRAM controller
* then wait for initialization to complete
*/
ldr r1, =(1 << 1)
str r1, [r0, #0x10]
1: ldr r3, [r0, #0x10]
tst r3, #(1 << 31)
beq 1b
ldr r1, =0x95728
str r1, [r0, #\cfg] /* config */
ldr r1, =0x92116480 /* control | precharge */
str r1, [r0, #\ctl] /* write command to controller */
str r1, [r2, #0x400] /* command encoded in address */
ldr r1, =0xa2116480 /* auto refresh */
str r1, [r0, #\ctl]
ldrb r3, [r2] /* read dram twice to auto refresh */
ldrb r3, [r2]
ldr r1, =0xb2116480 /* control | load mode */
str r1, [r0, #\ctl] /* write command to controller */
strb r1, [r2, #0x33] /* command encoded in address */
ldr r1, =0x82116480 /* control | normal (0)*/
str r1, [r0, #\ctl] /* write command to controller */
.endm
.globl lowlevel_init
lowlevel_init:
init_aips
init_max
init_m3if
init_clocks
init_sdram_bank 0x80000000, 0x0, 0x4
init_sdram_bank 0x90000000, 0x8, 0xc
mov pc, lr

176
board/karo/tx25/tx25.c Normal file
View file

@ -0,0 +1,176 @@
/*
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
*
* Based on imx27lite.c:
* Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
* Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
* And:
* RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/imx25-pinmux.h>
static void mdelay(int n)
{
while (n-- > 0)
udelay(1000);
}
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FEC_MXC
void tx25_fec_init(void)
{
struct iomuxc_mux_ctl *muxctl;
struct iomuxc_pad_ctl *padctl;
u32 val;
u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
struct gpio_regs *gpio4 = (struct gpio_regs *)IMX_GPIO4_BASE;
struct gpio_regs *gpio3 = (struct gpio_regs *)IMX_GPIO3_BASE;
u32 saved_rdata0_mode, saved_rdata1_mode, saved_rx_dv_mode;
debug("tx25_fec_init\n");
/*
* fec pin init is generic
*/
mx25_fec_init_pins();
/*
* Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.
*
* FEC_RESET_B: gpio4[7] is ALT 5 mode of pin D13
* FEC_ENABLE_B: gpio4[9] is ALT 5 mode of pin D11
*/
muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
writel(gpio_mux_mode, &muxctl->pad_d13);
writel(gpio_mux_mode, &muxctl->pad_d11);
writel(0x0, &padctl->pad_d13);
writel(0x0, &padctl->pad_d11);
/* drop PHY power and assert reset (low) */
val = readl(&gpio4->dr) & ~((1 << 7) | (1 << 9));
writel(val, &gpio4->dr);
val = readl(&gpio4->dir) | (1 << 7) | (1 << 9);
writel(val, &gpio4->dir);
mdelay(5);
debug("resetting phy\n");
/* turn on PHY power leaving reset asserted */
val = readl(&gpio4->dr) | 1 << 9;
writel(val, &gpio4->dr);
mdelay(10);
/*
* Setup some strapping pins that are latched by the PHY
* as reset goes high.
*
* Set PHY mode to 111
* mode0 comes from FEC_RDATA0 which is GPIO 3_10 in mux mode 5
* mode1 comes from FEC_RDATA1 which is GPIO 3_11 in mux mode 5
* mode2 is tied high so nothing to do
*
* Turn on RMII mode
* RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode
*/
/*
* save three current mux modes and set each to gpio mode
*/
saved_rdata0_mode = readl(&muxctl->pad_fec_rdata0);
saved_rdata1_mode = readl(&muxctl->pad_fec_rdata1);
saved_rx_dv_mode = readl(&muxctl->pad_fec_rx_dv);
writel(gpio_mux_mode, &muxctl->pad_fec_rdata0);
writel(gpio_mux_mode, &muxctl->pad_fec_rdata1);
writel(gpio_mux_mode, &muxctl->pad_fec_rx_dv);
/*
* set each to 1 and make each an output
*/
val = readl(&gpio3->dr) | (1 << 10) | (1 << 11) | (1 << 12);
writel(val, &gpio3->dr);
val = readl(&gpio3->dir) | (1 << 10) | (1 << 11) | (1 << 12);
writel(val, &gpio3->dir);
mdelay(22); /* this value came from RedBoot */
/*
* deassert PHY reset
*/
val = readl(&gpio4->dr) | 1 << 7;
writel(val, &gpio4->dr);
writel(val, &gpio4->dr);
mdelay(5);
/*
* set FEC pins back
*/
writel(saved_rdata0_mode, &muxctl->pad_fec_rdata0);
writel(saved_rdata1_mode, &muxctl->pad_fec_rdata1);
writel(saved_rx_dv_mode, &muxctl->pad_fec_rx_dv);
}
#else
#define tx25_fec_init()
#endif
int board_init()
{
#ifdef CONFIG_MXC_UART
extern void mx25_uart_init_pins(void);
mx25_uart_init_pins();
#endif
return 0;
}
int board_late_init(void)
{
tx25_fec_init();
return 0;
}
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
#if CONFIG_NR_DRAM_BANKS > 1
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2,
PHYS_SDRAM_2_SIZE);
#endif
return 0;
}
int checkboard(void)
{
printf("KARO TX25\n");
return 0;
}

13
board/kb9202/kb9202.c
View file

@ -28,8 +28,12 @@
#include <common.h>
#include <asm/arch/AT91RM9200.h>
#include <asm/io.h>
#include <netdev.h>
#if defined(CONFIG_DRIVER_ETHER)
#include <at91rm9200_net.h>
#include <lxt971a.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -92,3 +96,12 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
#endif
#endif /* CONFIG_DRIVER_ETHER */
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
int rc = 0;
rc = at91emac_register(bis, 0);
return rc;
}
#endif

6
board/keymile/common/common.c
View file

@ -35,6 +35,7 @@
#include <libfdt.h>
#endif
#include "../common/common.h"
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
#include <i2c.h>
@ -421,7 +422,6 @@ static int get_scl (void)
return ((val & SCL_BIT) == SCL_BIT);
}
#endif
#if !defined(CONFIG_KMETER1)
@ -500,7 +500,7 @@ void i2c_init_board(void)
out_8 (&dev->cr, (I2C_CR_MEN));
#else
#if defined(CONFIG_HARD_I2C)
#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_MACH_SUEN3)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
@ -578,10 +578,12 @@ int fdt_get_node_and_value (void *blob,
}
#endif
#if !defined(CONFIG_MACH_SUEN3)
int ethernet_present (void)
{
return (in_8((u8 *)CONFIG_SYS_PIGGY_BASE + CONFIG_SYS_SLOT_ID_OFF) & 0x80);
}
#endif
int board_eth_init (bd_t *bis)
{

54
board/keymile/km_arm/Makefile Normal file
View file

@ -0,0 +1,54 @@
#
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Prafulla Wadaskar <prafulla@marvell.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
endif
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o ../common/common.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

28
board/keymile/km_arm/config.mk Normal file
View file

@ -0,0 +1,28 @@
#
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Prafulla Wadaskar <prafulla@marvell.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
TEXT_BASE = 0x004000000
# Kirkwood Boot Image configuration file
KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg

324
board/keymile/km_arm/km_arm.c Normal file
View file

@ -0,0 +1,324 @@
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Prafulla Wadaskar <prafulla@marvell.com>
*
* (C) Copyright 2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2010
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
#include <i2c.h>
#include <nand.h>
#include <netdev.h>
#include <miiphy.h>
#include <asm/io.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
#include "../common/common.h"
DECLARE_GLOBAL_DATA_PTR;
static int io_dev;
extern I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf);
/* Multi-Purpose Pins Functionality configuration */
u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MPP3_NF_IO5,
MPP4_NF_IO6,
MPP5_NF_IO7,
MPP6_SYSRST_OUTn,
MPP7_PEX_RST_OUTn,
#if defined(CONFIG_SOFT_I2C)
MPP8_GPIO, /* SDA */
MPP9_GPIO, /* SCL */
#endif
#if defined(CONFIG_HARD_I2C)
MPP8_TW_SDA,
MPP9_TW_SCK,
#endif
MPP10_UART0_TXD,
MPP11_UART0_RXD,
MPP12_GPO, /* Reserved */
MPP13_UART1_TXD,
MPP14_UART1_RXD,
MPP15_GPIO, /* Not used */
MPP16_GPIO, /* Not used */
MPP17_GPIO, /* Reserved */
MPP18_NF_IO0,
MPP19_NF_IO1,
MPP20_GPIO,
MPP21_GPIO,
MPP22_GPIO,
MPP23_GPIO,
MPP24_GPIO,
MPP25_GPIO,
MPP26_GPIO,
MPP27_GPIO,
MPP28_GPIO,
MPP29_GPIO,
MPP30_GPIO,
MPP31_GPIO,
MPP32_GPIO,
MPP33_GPIO,
MPP34_GPIO, /* CDL1 (input) */
MPP35_GPIO, /* CDL2 (input) */
MPP36_GPIO, /* MAIN_IRQ (input) */
MPP37_GPIO, /* BOARD_LED */
MPP38_GPIO, /* Piggy3 LED[1] */
MPP39_GPIO, /* Piggy3 LED[2] */
MPP40_GPIO, /* Piggy3 LED[3] */
MPP41_GPIO, /* Piggy3 LED[4] */
MPP42_GPIO, /* Piggy3 LED[5] */
MPP43_GPIO, /* Piggy3 LED[6] */
MPP44_GPIO, /* Piggy3 LED[7] */
MPP45_GPIO, /* Piggy3 LED[8] */
MPP46_GPIO, /* Reserved */
MPP47_GPIO, /* Reserved */
MPP48_GPIO, /* Reserved */
MPP49_GPIO, /* SW_INTOUTn */
0
};
int ethernet_present(void)
{
uchar buf;
int ret = 0;
if (i2c_read(0x10, 2, 1, &buf, 1) != 0) {
printf ("%s: Error reading Boco\n", __FUNCTION__);
return -1;
}
if ((buf & 0x40) == 0x40) {
ret = 1;
}
return ret;
}
int misc_init_r(void)
{
I2C_MUX_DEVICE *i2cdev;
char *str;
int mach_type;
/* add I2C Bus for I/O Expander */
i2cdev = i2c_mux_ident_muxstring((uchar *)"pca9554a:70:a");
io_dev = i2cdev->busid;
puts("Piggy:");
if (ethernet_present() == 0)
puts (" not");
puts(" present\n");
str = getenv("mach_type");
if (str != NULL) {
mach_type = simple_strtoul(str, NULL, 10);
printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
gd->bd->bi_arch_number = mach_type;
}
return 0;
}
int board_init(void)
{
u32 tmp;
kirkwood_mpp_conf(kwmpp_config);
/*
* The FLASH_GPIO_PIN switches between using a
* NAND or a SPI FLASH. Set this pin on start
* to NAND mode.
*/
tmp = readl(KW_GPIO0_BASE);
writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
tmp = readl(KW_GPIO0_BASE + 4);
writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
printf("KM: setting NAND mode\n");
/*
* arch number of board
*/
gd->bd->bi_arch_number = MACH_TYPE_SUEN3;
/* address of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
#if defined(CONFIG_SOFT_I2C)
/* init the GPIO for I2C Bitbang driver */
kw_gpio_set_valid(SUEN3_SDA_PIN, 1);
kw_gpio_set_valid(SUEN3_SCL_PIN, 1);
kw_gpio_direction_output(SUEN3_SDA_PIN, 0);
kw_gpio_direction_output(SUEN3_SCL_PIN, 0);
#endif
#if defined(CONFIG_SYS_EEPROM_WREN)
kw_gpio_set_valid(SUEN3_ENV_WP, 38);
kw_gpio_direction_output(SUEN3_ENV_WP, 1);
#endif
return 0;
}
#if defined(CONFIG_CMD_SF)
int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
u32 tmp;
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
if ((strcmp(argv[1], "off") == 0)) {
printf("SPI FLASH disabled, NAND enabled\n");
/* Multi-Purpose Pins Functionality configuration */
kwmpp_config[0] = MPP0_NF_IO2;
kwmpp_config[1] = MPP1_NF_IO3;
kwmpp_config[2] = MPP2_NF_IO4;
kwmpp_config[3] = MPP3_NF_IO5;
kirkwood_mpp_conf(kwmpp_config);
tmp = readl(KW_GPIO0_BASE);
writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
} else if ((strcmp(argv[1], "on") == 0)) {
printf("SPI FLASH enabled, NAND disabled\n");
/* Multi-Purpose Pins Functionality configuration */
kwmpp_config[0] = MPP0_SPI_SCn;
kwmpp_config[1] = MPP1_SPI_MOSI;
kwmpp_config[2] = MPP2_SPI_SCK;
kwmpp_config[3] = MPP3_SPI_MISO;
kirkwood_mpp_conf(kwmpp_config);
tmp = readl(KW_GPIO0_BASE);
writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
} else {
cmd_usage(cmdtp);
return 1;
}
return 0;
}
U_BOOT_CMD(
spitoggle, 2, 0, do_spi_toggle,
"En-/disable SPI FLASH access",
"<on|off> - Enable (on) or disable (off) SPI FLASH access\n"
);
#endif
int dram_init(void)
{
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = kw_sdram_bar(i);
gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
kw_sdram_bs(i));
}
return 0;
}
/* Configure and enable MV88E1118 PHY */
void reset_phy(void)
{
char *name = "egiga0";
if (miiphy_set_current_dev(name))
return;
/* reset the phy */
miiphy_reset(name, CONFIG_PHY_BASE_ADR);
}
#if defined(CONFIG_HUSH_INIT_VAR)
int hush_init_var (void)
{
ivm_read_eeprom ();
return 0;
}
#endif
#if defined(CONFIG_BOOTCOUNT_LIMIT)
void bootcount_store (ulong a)
{
volatile ulong *save_addr;
volatile ulong size = 0;
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
size += gd->bd->bi_dram[i].size;
}
save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
writel(a, save_addr);
writel(BOOTCOUNT_MAGIC, &save_addr[1]);
}
ulong bootcount_load (void)
{
volatile ulong *save_addr;
volatile ulong size = 0;
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
size += gd->bd->bi_dram[i].size;
}
save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC)
return 0;
else
return readl(save_addr);
}
#endif
#if defined(CONFIG_SOFT_I2C)
void set_sda (int state)
{
I2C_ACTIVE;
I2C_SDA(state);
}
void set_scl (int state)
{
I2C_SCL(state);
}
int get_sda (void)
{
I2C_TRISTATE;
return I2C_READ;
}
int get_scl (void)
{
return (kw_gpio_get_value(SUEN3_SCL_PIN) ? 1 : 0);
}
#endif
#if defined(CONFIG_SYS_EEPROM_WREN)
int eeprom_write_enable (unsigned dev_addr, int state)
{
kw_gpio_set_value(SUEN3_ENV_WP, !state);
return !kw_gpio_get_value(SUEN3_ENV_WP);
}
#endif

175
board/keymile/km_arm/kwbimage.cfg Normal file
View file

@ -0,0 +1,175 @@
#
# (C) Copyright 2010
# Heiko Schocher, DENX Software Engineering, hs@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
# Refer docs/README.kwimage for more details about how-to configure
# and create kirkwood boot image
#
# Boot Media configurations
BOOT_FROM spi # Boot from SPI flash
DATA 0xFFD10000 0x01111111 # MPP Control 0 Register
# bit 3-0: MPPSel0 1, NF_IO[2]
# bit 7-4: MPPSel1 1, NF_IO[3]
# bit 12-8: MPPSel2 1, NF_IO[4]
# bit 15-12: MPPSel3 1, NF_IO[5]
# bit 19-16: MPPSel4 1, NF_IO[6]
# bit 23-20: MPPSel5 1, NF_IO[7]
# bit 27-24: MPPSel6 1, SYSRST_O
# bit 31-28: MPPSel7 0, GPO[7]
DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
# bit 3-0: MPPSel16 0, GPIO[16]
# bit 7-4: MPPSel17 0, GPIO[17]
# bit 12-8: MPPSel18 1, NF_IO[0]
# bit 15-12: MPPSel19 1, NF_IO[1]
# bit 19-16: MPPSel20 0, GPIO[20]
# bit 23-20: MPPSel21 0, GPIO[21]
# bit 27-24: MPPSel22 0, GPIO[22]
# bit 31-28: MPPSel23 0, GPIO[23]
DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
DATA 0xFFD20134 0xBBBBBBBB # L2 RAM Timing 0 Register
DATA 0xFFD20138 0x00BBBBBB # L2 RAM Timing 1 Register
DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register
DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register
DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register
#Dram initalization
DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register
# bit13-0: 0x400 (DDR2 clks refresh rate)
# bit23-14: zero
# bit24: 1= enable exit self refresh mode on DDR access
# bit25: 1 required
# bit29-26: zero
# bit31-30: 01
DATA 0xFFD01404 0x36343000 # DDR Controller Control Low
# bit 3-0: 0 reserved
# bit 4: 0=addr/cmd in smame cycle
# bit 5: 0=clk is driven during self refresh, we don't care for APX
# bit 6: 0=use recommended falling edge of clk for addr/cmd
# bit14: 0=input buffer always powered up
# bit18: 1=cpu lock transaction enabled
# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
# bit30-28: 3 required
# bit31: 0=no additional STARTBURST delay
DATA 0xFFD01408 0x2302544B # DDR Timing (Low) (active cycles value +1)
# bit3-0: TRAS lsbs
# bit7-4: TRCD
# bit11- 8: TRP
# bit15-12: TWR
# bit19-16: TWTR
# bit20: TRAS msb
# bit23-21: 0x0
# bit27-24: TRRD
# bit31-28: TRTP
DATA 0xFFD0140C 0x00000032 # DDR Timing (High)
# bit6-0: TRFC
# bit8-7: TR2R
# bit10-9: TR2W
# bit12-11: TW2W
# bit31-13: zero required
DATA 0xFFD01410 0x0000000D # DDR Address Control
# bit1-0: 01, Cs0width=x16
# bit3-2: 11, Cs0size=1Gb
# bit5-4: 00, Cs2width=nonexistent
# bit7-6: 00, Cs1size =nonexistent
# bit9-8: 00, Cs2width=nonexistent
# bit11-10: 00, Cs2size =nonexistent
# bit13-12: 00, Cs3width=nonexistent
# bit15-14: 00, Cs3size =nonexistent
# bit16: 0, Cs0AddrSel
# bit17: 0, Cs1AddrSel
# bit18: 0, Cs2AddrSel
# bit19: 0, Cs3AddrSel
# bit31-20: 0 required
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
# bit0: 0, OpenPage enabled
# bit31-1: 0 required
DATA 0xFFD01418 0x00000000 # DDR Operation
# bit3-0: 0x0, DDR cmd
# bit31-4: 0 required
DATA 0xFFD0141C 0x00000642 # DDR Mode
DATA 0xFFD01420 0x00000040 # DDR Extended Mode
# bit0: 0, DDR DLL enabled
# bit1: 0, DDR drive strenght normal
# bit2: 1, DDR ODT control lsd disabled
# bit5-3: 000, required
# bit6: 1, DDR ODT control msb, enabled
# bit9-7: 000, required
# bit10: 0, differential DQS enabled
# bit11: 0, required
# bit12: 0, DDR output buffer enabled
# bit31-13: 0 required
DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
# bit2-0: 111, required
# bit3 : 1 , MBUS Burst Chop disabled
# bit6-4: 111, required
# bit7 : 0
# bit8 : 0 , no sample stage
# bit9 : 0 , no half clock cycle addition to dataout
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
# bit15-12: 1111 required
# bit31-16: 0 required
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
# bit0: 1, Window enabled
# bit1: 0, Write Protect disabled
# bit3-2: 00, CS0 hit selected
# bit23-4: ones, required
# bit31-24: 0x07, Size (i.e. 128MB)
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
DATA 0xFFD01494 0x00000000 # DDR ODT Control (Low)
# bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
# bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
# bit3-2: 00, ODT1 controlled by register
# bit31-4: zero, required
DATA 0xFFD0149C 0x0000E90F # CPU ODT Control
# bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
# bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
# bit9-8: 1, ODTEn, never active
# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
# bit0=1, enable DDR init upon this register write
# End of Header extension
DATA 0x0 0x0

14
board/m501sk/m501sk.c
View file

@ -24,8 +24,13 @@
*/
#include <common.h>
#include <asm/io.h>
#include <netdev.h>
#if defined(CONFIG_DRIVER_ETHER)
#include <at91rm9200_net.h>
#include <dm9161.h>
#endif
#include "m501sk.h"
#include "net.h"
@ -186,4 +191,13 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
}
#endif /* CONFIG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
int rc = 0;
rc = at91emac_register(bis, 0);
return rc;
}
#endif
#endif /* CONFIG_M501SK */

13
board/mp2usb/mp2usb.c
View file

@ -27,8 +27,12 @@
#include <common.h>
#include <asm/arch/AT91RM9200.h>
#include <netdev.h>
#include <asm/io.h>
#if defined(CONFIG_DRIVER_ETHER)
#include <at91rm9200_net.h>
#include <dm9161.h>
#endif
#include <asm/mach-types.h>
DECLARE_GLOBAL_DATA_PTR;
@ -83,3 +87,12 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
#endif
#endif /* CONFIG_DRIVER_ETHER */
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
int rc = 0;
rc = at91emac_register(bis, 0);
return rc;
}
#endif

56
board/netstar/Makefile
View file

@ -29,20 +29,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := netstar.o
SOBJS := setup.o crcek.o
SOBJS := setup.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) eeprom.c \
eeprom_start.S
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
LOAD_ADDR = 0x10400000
LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds
lnk = $(if $(obj),$(obj),.)
HOSTCFLAGS = -Wall -pedantic -I$(TOPDIR)/include
#########################################################################
all: $(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin \
$(obj)crcek.srec $(obj)crcek.bin $(obj)crcit
@ -50,41 +45,42 @@ all: $(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin \
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $^
$(obj)eeprom.srec: $(obj)eeprom.o $(obj)eeprom_start.o $(obj)u-boot.lds
cd $(lnk) && $(LD) -T $(obj)u-boot.lds -g -Ttext $(LOAD_ADDR) \
-o $(<:.o=) -e eeprom eeprom.o eeprom_start.o \
-L$(obj)../../examples/standalone -lstubs \
-L$(obj)../../lib_generic -lgeneric \
-L$(gcclibdir) -lgcc
$(OBJCOPY) -O srec $(<:.o=) $@
$(obj)eeprom_start.o:
echo "b eeprom" | $(CC) $(AFLAGS) -c -x assembler -o $@ -
$(obj)eeprom.bin: $(obj)eeprom.srec
$(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
$(obj)eeprom: $(obj)eeprom_start.o $(obj)eeprom.o
$(LD) -Ttext $(LOAD_ADDR) -e eeprom -o $@ $^ \
-L$(obj)../../examples/standalone -lstubs \
$(PLATFORM_LIBS)
$(obj)eeprom.srec: $(obj)eeprom
$(OBJCOPY) -S -O srec $(<:.o=) $@
$(obj)eeprom.bin: $(obj)eeprom
$(OBJCOPY) -S -O binary $< $@
$(obj)crcek.srec: $(obj)crcek.o
$(LD) -g -Ttext 0x00000000 \
-o $(<:.o=) -e crcek $^
$(OBJCOPY) -O srec $(<:.o=) $@
$(LD) -g -Ttext 0x00000000 -e crcek -o $(<:.o=) $^
$(OBJCOPY) -S -O srec $(<:.o=) $@
$(obj)crcek.bin: $(obj)crcek.srec
$(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
$(OBJCOPY) -I srec -O binary $< $@
$(obj)crcit: $(obj)crcit.o $(obj)crc32.o
$(HOSTCC) $(HOSTCFLAGS) -o $@ $^
$(obj)crcit.o: crcit.c
$(obj)crcit.o: crcit.c
$(HOSTCC) $(HOSTCFLAGS) -o $@ -c $<
$(obj)crc32.o: $(SRCTREE)/lib_generic/crc32.c
$(HOSTCC) $(HOSTCFLAGS) -DUSE_HOSTCC -o $@ -c $<
$(obj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
$(obj)crc32.o: $(SRCTREE)/lib_generic/crc32.c
$(HOSTCC) $(HOSTCFLAGS) -DUSE_HOSTCC -I$(TOPDIR)/include \
-o $@ -c $<
clean:
rm -f $(SOBJS) $(OBJS) $(obj)eeprom $(obj)eeprom.srec \
$(obj)eeprom.bin $(obj)crcek $(obj)crcek.srec \
$(obj)crcek.bin $(obj)u-boot.lds
rm -f $(SOBJS) $(OBJS) \
$(obj)eeprom_start.o $(obj)eeprom.o \
$(obj)eeprom $(obj)eeprom.srec $(obj)eeprom.bin \
$(obj)crcek.o $(obj)crcek $(obj)crcek.srec $(obj)crcek.bin
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend

95
board/netstar/eeprom.c
View file

@ -28,67 +28,76 @@
#include <net.h>
#include "../drivers/net/smc91111.h"
static u16 read_eeprom_reg(struct eth_device *dev, u16 reg)
static struct eth_device dev = {
.iobase = CONFIG_SMC91111_BASE
};
static u16 read_eeprom_reg(u16 reg)
{
int timeout;
SMC_SELECT_BANK(dev, 2);
SMC_outw(dev, reg, PTR_REG);
SMC_SELECT_BANK(&dev, 2);
SMC_outw(&dev, reg, PTR_REG);
SMC_SELECT_BANK(&dev, 1);
SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT |
CTL_RELOAD, CTL_REG);
SMC_SELECT_BANK(dev, 1);
SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
CTL_REG);
timeout = 100;
while((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout)
while ((SMC_inw(&dev, CTL_REG) & CTL_RELOAD) && --timeout)
udelay(100);
if (timeout == 0) {
printf("Timeout Reading EEPROM register %02x\n", reg);
printf("Timeout reading register %02x\n", reg);
return 0;
}
return SMC_inw (dev, GP_REG);
return SMC_inw(&dev, GP_REG);
}
static int write_eeprom_reg(struct eth_device *dev, u16 value, u16 reg)
static int write_eeprom_reg(u16 value, u16 reg)
{
int timeout;
SMC_SELECT_BANK(dev, 2);
SMC_outw(dev, reg, PTR_REG);
SMC_SELECT_BANK(&dev, 2);
SMC_outw(&dev, reg, PTR_REG);
SMC_SELECT_BANK(&dev, 1);
SMC_outw(&dev, value, GP_REG);
SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT |
CTL_STORE, CTL_REG);
SMC_SELECT_BANK(dev, 1);
SMC_outw(dev, value, GP_REG);
SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
timeout = 100;
while ((SMC_inw(dev, CTL_REG) & CTL_STORE) && --timeout)
udelay (100);
while ((SMC_inw(&dev, CTL_REG) & CTL_STORE) && --timeout)
udelay(100);
if (timeout == 0) {
printf("Timeout Writing EEPROM register %02x\n", reg);
printf("Timeout writing register %02x\n", reg);
return 0;
}
return 1;
}
static int write_data(struct eth_device *dev, u16 *buf, int len)
static int write_data(u16 *buf, int len)
{
u16 reg = 0x23;
while (len--)
write_eeprom_reg(dev, *buf++, reg++);
write_eeprom_reg(*buf++, reg++);
return 0;
}
static int verify_macaddr(struct eth_device *dev, char *s)
static int verify_macaddr(char *s)
{
u16 reg;
int i, err = 0;
printf("MAC Address: ");
err = i = 0;
puts("HWaddr: ");
for (i = 0; i < 3; i++) {
reg = read_eeprom_reg(dev, 0x20 + i);
reg = read_eeprom_reg(0x20 + i);
printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n');
if (s)
err |= reg != ((u16 *)s)[i];
@ -97,7 +106,7 @@ static int verify_macaddr(struct eth_device *dev, char *s)
return err ? 0 : 1;
}
static int set_mac(struct eth_device *dev, char *s)
static int set_mac(char *s)
{
int i;
char *e, eaddr[6];
@ -109,7 +118,7 @@ static int set_mac(struct eth_device *dev, char *s)
}
for (i = 0; i < 3; i++)
write_eeprom_reg(dev, *(((u16 *)eaddr) + i), 0x20 + i);
write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i);
return 0;
}
@ -145,34 +154,30 @@ int eeprom(int argc, char *argv[])
int i, len, ret;
unsigned char buf[58], *p;
struct eth_device dev = {
.iobase = CONFIG_SMC91111_BASE
};
app_startup(argv);
if (get_version() != XF_VERSION) {
printf("Wrong XF_VERSION.\n");
printf("Application expects ABI version %d\n", XF_VERSION);
printf("Actual U-Boot ABI version %d\n", (int)get_version());
i = get_version();
if (i != XF_VERSION) {
printf("Using ABI version %d, but U-Boot provides %d\n",
XF_VERSION, i);
return 1;
}
if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
printf("SMSC91111 not found.\n");
if ((SMC_inw(&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
puts("SMSC91111 not found\n");
return 2;
}
/* Called without parameters - print MAC address */
if (argc < 2) {
verify_macaddr(&dev, NULL);
verify_macaddr(NULL);
return 0;
}
/* Print help message */
if (argv[1][1] == 'h') {
printf("NetStar EEPROM writer\n");
printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n");
puts("NetStar EEPROM writer\n"
"Built: " U_BOOT_DATE " at " U_BOOT_TIME "\n"
"Usage:\n\t<mac_address> [<element_1>] [<...>]\n");
return 0;
}
@ -189,7 +194,7 @@ int eeprom(int argc, char *argv[])
printf("Element %d: odd character count\n", i - 1);
return 3;
case -3:
printf("Out of EEPROM memory\n");
puts("Out of EEPROM memory\n");
return 3;
default:
p += ret;
@ -198,16 +203,16 @@ int eeprom(int argc, char *argv[])
}
/* First argument (MAC) is mandatory */
set_mac(&dev, argv[1]);
if (verify_macaddr(&dev, argv[1])) {
printf("*** MAC address does not match! ***\n");
set_mac(argv[1]);
if (verify_macaddr(argv[1])) {
puts("*** HWaddr does not match! ***\n");
return 4;
}
while (len--)
*p++ = 0;
write_data(&dev, (u16 *)buf, sizeof(buf) >> 1);
write_data((u16 *)buf, sizeof(buf) >> 1);
return 0;
}

13
board/netstar/eeprom_start.S
View file

@ -1,13 +0,0 @@
/*
* Copyright (c) 2005 2N Telekomunikace
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
*/
.globl _start
_start: b eeprom
.end

2
board/ronetix/pm9261/pm9261.c
View file

@ -189,7 +189,7 @@ void lcd_show_board_info(void)
lcd_printf ("(C) 2009 Ronetix GmbH\n");
lcd_printf ("support@ronetix.at\n");
lcd_printf ("%s CPU at %s MHz",
AT91_CPU_NAME,
CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate()));
dram_size = 0;

2
board/ronetix/pm9263/pm9263.c
View file

@ -304,7 +304,7 @@ void lcd_show_board_info(void)
lcd_printf ("(C) 2009 Ronetix GmbH\n");
lcd_printf ("support@ronetix.at\n");
lcd_printf ("%s CPU at %s MHz",
AT91_CPU_NAME,
CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate()));
dram_size = 0;

2
board/spear/spear310/spear310.c
View file

@ -32,7 +32,7 @@
int board_init(void)
{
return spear_board_init(MACH_TYPE_SPEAR300);
return spear_board_init(MACH_TYPE_SPEAR310);
}
/*

2
board/spear/spear320/spear320.c
View file

@ -32,7 +32,7 @@
int board_init(void)
{
return spear_board_init(MACH_TYPE_SPEAR300);
return spear_board_init(MACH_TYPE_SPEAR320);
}
/*

33
board/voiceblue/Makefile
View file

@ -29,40 +29,37 @@ LIB = $(obj)lib$(BOARD).a
COBJS := voiceblue.o
SOBJS := setup.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) eeprom.c eeprom_start.S
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
LOAD_ADDR = 0x10400000
LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds
lnk = $(if $(obj),$(obj),.)
#########################################################################
all: $(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $^
$(obj)eeprom.srec: $(obj)eeprom.o $(obj)eeprom_start.o $(obj)u-boot.lds
cd $(lnk) && $(LD) -T $(obj)u-boot.lds -g -Ttext $(LOAD_ADDR) \
-o $(<:.o=) -e eeprom eeprom.o eeprom_start.o \
$(obj)eeprom_start.o:
echo "b eeprom" | $(CC) $(AFLAGS) -c -x assembler -o $@ -
$(obj)eeprom: $(obj)eeprom_start.o $(obj)eeprom.o
$(LD) -Ttext $(LOAD_ADDR) -e eeprom -o $@ $^ \
-L$(obj)../../examples/standalone -lstubs \
-L$(obj)../../lib_generic -lgeneric \
-L$(gcclibdir) -lgcc
$(OBJCOPY) -O srec $(<:.o=) $@
$(PLATFORM_LIBS)
$(obj)eeprom.bin: $(obj)eeprom.srec
$(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
$(obj)eeprom.srec: $(obj)eeprom
$(OBJCOPY) -S -O srec $(<:.o=) $@
$(obj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
$(obj)eeprom.bin: $(obj)eeprom
$(OBJCOPY) -S -O binary $< $@
clean:
rm -f $(SOBJS) $(OBJS) $(obj)eeprom \
$(obj)eeprom.srec $(obj)eeprom.bin \
$(obj)eeprom.o $(obj)eeprom_start.o \
$(obj)u-boot.lds
$(obj)eeprom.o $(obj)eeprom_start.o
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend

97
board/voiceblue/eeprom.c
View file

@ -22,75 +22,82 @@
* Some code shamelessly stolen back from Robin Getz.
*/
#define DEBUG
#include <common.h>
#include <exports.h>
#include <timestamp.h>
#include <net.h>
#include "../drivers/net/smc91111.h"
static u16 read_eeprom_reg(struct eth_device *dev, u16 reg)
static struct eth_device dev = {
.iobase = CONFIG_SMC91111_BASE
};
static u16 read_eeprom_reg(u16 reg)
{
int timeout;
SMC_SELECT_BANK(dev, 2);
SMC_outw(dev, reg, PTR_REG);
SMC_SELECT_BANK(&dev, 2);
SMC_outw(&dev, reg, PTR_REG);
SMC_SELECT_BANK(&dev, 1);
SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT |
CTL_RELOAD, CTL_REG);
SMC_SELECT_BANK(dev, 1);
SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
CTL_REG);
timeout = 100;
while((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout)
while ((SMC_inw(&dev, CTL_REG) & CTL_RELOAD) && --timeout)
udelay(100);
if (timeout == 0) {
printf("Timeout Reading EEPROM register %02x\n", reg);
printf("Timeout reading register %02x\n", reg);
return 0;
}
return SMC_inw (dev, GP_REG);
return SMC_inw(&dev, GP_REG);
}
static int write_eeprom_reg(struct eth_device *dev, u16 value, u16 reg)
static int write_eeprom_reg(u16 value, u16 reg)
{
int timeout;
SMC_SELECT_BANK(dev, 2);
SMC_outw(dev, reg, PTR_REG);
SMC_SELECT_BANK(&dev, 2);
SMC_outw(&dev, reg, PTR_REG);
SMC_SELECT_BANK(&dev, 1);
SMC_outw(&dev, value, GP_REG);
SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT |
CTL_STORE, CTL_REG);
SMC_SELECT_BANK(dev, 1);
SMC_outw(dev, value, GP_REG);
SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
timeout = 100;
while ((SMC_inw(dev, CTL_REG) & CTL_STORE) && --timeout)
udelay (100);
while ((SMC_inw(&dev, CTL_REG) & CTL_STORE) && --timeout)
udelay(100);
if (timeout == 0) {
printf("Timeout Writing EEPROM register %02x\n", reg);
printf("Timeout writing register %02x\n", reg);
return 0;
}
return 1;
}
static int write_data(struct eth_device *dev, u16 *buf, int len)
static int write_data(u16 *buf, int len)
{
u16 reg = 0x23;
while (len--)
write_eeprom_reg(dev, *buf++, reg++);
write_eeprom_reg(*buf++, reg++);
return 0;
}
static int verify_macaddr(struct eth_device *dev, char *s)
static int verify_macaddr(char *s)
{
u16 reg;
int i, err = 0;
printf("MAC Address: ");
err = i = 0;
puts("HWaddr: ");
for (i = 0; i < 3; i++) {
reg = read_eeprom_reg(dev, 0x20 + i);
reg = read_eeprom_reg(0x20 + i);
printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n');
if (s)
err |= reg != ((u16 *)s)[i];
@ -99,7 +106,7 @@ static int verify_macaddr(struct eth_device *dev, char *s)
return err ? 0 : 1;
}
static int set_mac(struct eth_device *dev, char *s)
static int set_mac(char *s)
{
int i;
char *e, eaddr[6];
@ -111,7 +118,7 @@ static int set_mac(struct eth_device *dev, char *s)
}
for (i = 0; i < 3; i++)
write_eeprom_reg(dev, *(((u16 *)eaddr) + i), 0x20 + i);
write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i);
return 0;
}
@ -147,34 +154,30 @@ int eeprom(int argc, char *argv[])
int i, len, ret;
unsigned char buf[58], *p;
struct eth_device dev = {
.iobase = CONFIG_SMC91111_BASE
};
app_startup(argv);
if (get_version() != XF_VERSION) {
printf("Wrong XF_VERSION.\n");
printf("Application expects ABI version %d\n", XF_VERSION);
printf("Actual U-Boot ABI version %d\n", (int)get_version());
i = get_version();
if (i != XF_VERSION) {
printf("Using ABI version %d, but U-Boot provides %d\n",
XF_VERSION, i);
return 1;
}
if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
printf("SMSC91111 not found.\n");
if ((SMC_inw(&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
puts("SMSC91111 not found\n");
return 2;
}
/* Called without parameters - print MAC address */
if (argc < 2) {
verify_macaddr(&dev, NULL);
verify_macaddr(NULL);
return 0;
}
/* Print help message */
if (argv[1][1] == 'h') {
printf("VoiceBlue EEPROM writer\n");
printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n");
puts("VoiceBlue EEPROM writer\n"
"Built: " U_BOOT_DATE " at " U_BOOT_TIME "\n"
"Usage:\n\t<mac_address> [<element_1>] [<...>]\n");
return 0;
}
@ -191,7 +194,7 @@ int eeprom(int argc, char *argv[])
printf("Element %d: odd character count\n", i - 1);
return 3;
case -3:
printf("Out of EEPROM memory\n");
puts("Out of EEPROM memory\n");
return 3;
default:
p += ret;
@ -200,16 +203,16 @@ int eeprom(int argc, char *argv[])
}
/* First argument (MAC) is mandatory */
set_mac(&dev, argv[1]);
if (verify_macaddr(&dev, argv[1])) {
printf("*** MAC address does not match! ***\n");
set_mac(argv[1]);
if (verify_macaddr(argv[1])) {
puts("*** HWaddr does not match! ***\n");
return 4;
}
while (len--)
*p++ = 0;
write_data(&dev, (u16 *)buf, sizeof(buf) >> 1);
write_data((u16 *)buf, sizeof(buf) >> 1);
return 0;
}

11
board/voiceblue/eeprom_start.S
View file

@ -1,11 +0,0 @@
/*
* Copyright (c) 2005 2N Telekomunikace
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
*/
.globl _start
_start: b eeprom

9
common/cmd_itest.c
View file

@ -66,12 +66,17 @@ op_tbl_t op_table [] = {
static long evalexp(char *s, int w)
{
long l, *p;
long l = 0;
long *p;
/* if the parameter starts with a * then assume is a pointer to the value we want */
if (s[0] == '*') {
p = (long *)simple_strtoul(&s[1], NULL, 16);
l = *p;
switch (w) {
case 1: return((long)(*(unsigned char *)p));
case 2: return((long)(*(unsigned short *)p));
case 4: return(*p);
}
} else {
l = simple_strtoul(s, NULL, 16);
}

33
common/cmd_ximg.c
View file

@ -225,20 +225,25 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
break;
#if defined(CONFIG_BZIP2)
case IH_COMP_BZIP2:
printf (" Uncompressing part %d ... ", part);
/*
* If we've got less than 4 MB of malloc() space,
* use slower decompression algorithm which requires
* at most 2300 KB of memory.
*/
i = BZ2_bzBuffToBuffDecompress
((char*)ntohl(hdr->ih_load),
&unc_len, (char *)data, len,
CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0);
if (i != BZ_OK) {
printf ("BUNZIP2 ERROR %d - "
"image not loaded\n", i);
return 1;
{
int i;
printf (" Uncompressing part %d ... ", part);
/*
* If we've got less than 4 MB of malloc()
* space, use slower decompression algorithm
* which requires at most 2300 KB of memory.
*/
i = BZ2_bzBuffToBuffDecompress(
(char*)ntohl(hdr->ih_load),
&unc_len, (char *)data, len,
CONFIG_SYS_MALLOC_LEN < (4096 * 1024),
0);
if (i != BZ_OK) {
printf ("BUNZIP2 ERROR %d - "
"image not loaded\n", i);
return 1;
}
}
break;
#endif /* CONFIG_BZIP2 */

7
common/env_nand.c
View file

@ -298,6 +298,13 @@ void env_relocate_spec (void)
tmp_env1 = (env_t *) malloc(CONFIG_ENV_SIZE);
tmp_env2 = (env_t *) malloc(CONFIG_ENV_SIZE);
if ((tmp_env1 == NULL) || (tmp_env2 == NULL)) {
puts("Can't allocate buffers for environment\n");
free (tmp_env1);
free (tmp_env2);
return use_default();
}
if (readenv(CONFIG_ENV_OFFSET, (u_char *) tmp_env1))
puts("No Valid Environment Area Found\n");
if (readenv(CONFIG_ENV_OFFSET_REDUND, (u_char *) tmp_env2))

8
common/lcd.c
View file

@ -456,22 +456,14 @@ ulong lcd_setmem (ulong addr)
static void lcd_setfgcolor (int color)
{
#ifdef CONFIG_ATMEL_LCD
lcd_color_fg = color;
#else
lcd_color_fg = color & 0x0F;
#endif
}
/*----------------------------------------------------------------------*/
static void lcd_setbgcolor (int color)
{
#ifdef CONFIG_ATMEL_LCD
lcd_color_bg = color;
#else
lcd_color_bg = color & 0x0F;
#endif
}
/*----------------------------------------------------------------------*/

12
common/miiphyutil.c
View file

@ -293,7 +293,7 @@ int miiphy_info (char *devname, unsigned char addr, unsigned int *oui,
int miiphy_reset (char *devname, unsigned char addr)
{
unsigned short reg;
int loop_cnt;
int timeout = 500;
if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) {
debug ("PHY status read failed\n");
@ -311,13 +311,13 @@ int miiphy_reset (char *devname, unsigned char addr)
* auto-clearing). This should happen within 0.5 seconds per the
* IEEE spec.
*/
loop_cnt = 0;
reg = 0x8000;
while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) {
if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) {
debug ("PHY status read failed\n");
return (-1);
while (((reg & 0x8000) != 0) && timeout--) {
if (miiphy_read(devname, addr, PHY_BMCR, &reg) != 0) {
debug("PHY status read failed\n");
return -1;
}
udelay(1000);
}
if ((reg & 0x8000) == 0) {
return (0);

19
common/usb.c
View file

@ -197,16 +197,21 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe,
if (timeout == 0)
return (int)size;
if (dev->status != 0) {
/*
* Let's wait a while for the timeout to elapse.
* It has no real use, but it keeps the interface happy.
*/
wait_ms(timeout);
return -1;
/*
* Wait for status to update until timeout expires, USB driver
* interrupt handler may set the status when the USB operation has
* been completed.
*/
while (timeout--) {
if (!((volatile unsigned long)dev->status & USB_ST_NOT_PROC))
break;
wait_ms(1);
}
if (dev->status)
return -1;
return dev->act_len;
}
/*-------------------------------------------------------------------

1
cpu/74xx_7xx/traps.c
View file

@ -34,6 +34,7 @@
#include <common.h>
#include <command.h>
#include <kgdb.h>
#include <asm/processor.h>
#ifdef CONFIG_AMIGAONEG3SE

47
cpu/arm920t/at91/Makefile Normal file
View file

@ -0,0 +1,47 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
SOBJS += lowlevel_init.o
COBJS += reset.o
COBJS += timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

164
cpu/arm920t/at91/lowlevel_init.S Normal file
View file

@ -0,0 +1,164 @@
/*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
*
* Modified for the at91rm9200dk board by
* (C) Copyright 2004
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#include <asm/arch/hardware.h>
#include <asm/arch/at91_mc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_pio.h>
#define ARM920T_CONTROL 0xC0000000 /* @ set bit 31 (iA) and 30 (nF) */
_MTEXT_BASE:
#undef START_FROM_MEM
#ifdef START_FROM_MEM
.word TEXT_BASE-PHYS_FLASH_1
#else
.word TEXT_BASE
#endif
.globl lowlevel_init
lowlevel_init:
ldr r1, =AT91_ASM_PMC_MOR
/* Main oscillator Enable register */
#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
ldr r0, =0x0000FF01 /* Enable main oscillator */
#else
ldr r0, =0x0000FF00 /* Disable main oscillator */
#endif
str r0, [r1] /*AT91C_CKGR_MOR] */
/* Add loop to compensate Main Oscillator startup time */
ldr r0, =0x00000010
LoopOsc:
subs r0, r0, #1
bhi LoopOsc
/* memory control configuration */
/* this isn't very elegant, but what the heck */
ldr r0, =SMRDATA
ldr r1, _MTEXT_BASE
sub r0, r0, r1
add r2, r0, #80
pllloop:
/* the address */
ldr r1, [r0], #4
/* the value */
ldr r3, [r0], #4
str r3, [r1]
cmp r2, r0
bne pllloop
/* delay - this is all done by guess */
ldr r0, =0x00010000
/* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
lock:
subs r0, r0, #1
bhi lock
ldr r0, =SMRDATA1
ldr r1, _MTEXT_BASE
sub r0, r0, r1
add r2, r0, #176
sdinit:
/* the address */
ldr r1, [r0], #4
/* the value */
ldr r3, [r0], #4
str r3, [r1]
cmp r2, r0
bne sdinit
/* switch from FastBus to Asynchronous clock mode */
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #ARM920T_CONTROL
mcr p15, 0, r0, c1, c0, 0
/* everything is fine now */
mov pc, lr
.ltorg
SMRDATA:
.word AT91_ASM_MC_EBI_CFG
.word CONFIG_SYS_EBI_CFGR_VAL
.word AT91_ASM_MC_SMC_CSR0
.word CONFIG_SYS_SMC_CSR0_VAL
.word AT91_ASM_PMC_PLLAR
.word CONFIG_SYS_PLLAR_VAL
.word AT91_ASM_PMC_PLLBR
.word CONFIG_SYS_PLLBR_VAL
.word AT91_ASM_PMC_MCKR
.word CONFIG_SYS_MCKR_VAL
/* here there's a delay */
SMRDATA1:
.word AT91_ASM_PIOC_ASR
.word CONFIG_SYS_PIOC_ASR_VAL
.word AT91_ASM_PIOC_BSR
.word CONFIG_SYS_PIOC_BSR_VAL
.word AT91_ASM_PIOC_PDR
.word CONFIG_SYS_PIOC_PDR_VAL
.word AT91_ASM_MC_EBI_CSA
.word CONFIG_SYS_EBI_CSA_VAL
.word AT91_ASM_MC_SDRAMC_CR
.word CONFIG_SYS_SDRC_CR_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL1
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL2
.word CONFIG_SYS_SDRAM1
.word CONFIG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL3
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
/* SMRDATA1 is 176 bytes long */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

59
cpu/arm920t/at91/reset.c Normal file
View file

@ -0,0 +1,59 @@
/*
* (C) Copyright 2002
* Lineo, Inc. <www.lineo.com>
* Bernhard Kuhn <bkuhn@lineo.com>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_st.h>
void board_reset(void) __attribute__((__weak__));
void reset_cpu(ulong ignored)
{
at91_st_t *st = (at91_st_t *) AT91_ST_BASE;
#if defined(CONFIG_AT91RM9200_USART)
/*shutdown the console to avoid strange chars during reset */
serial_exit();
#endif
if (board_reset)
board_reset();
/* Reset the cpu by setting up the watchdog timer */
writel(AT91_ST_WDMR_RSTEN | AT91_ST_WDMR_EXTEN | AT91_ST_WDMR_WDV(2),
&st->wdmr);
writel(AT91_ST_CR_WDRST, &st->cr);
/* and let it timeout */
while (1)
;
/* Never reached */
}

163
cpu/arm920t/at91/timer.c Normal file
View file

@ -0,0 +1,163 @@
/*
* (C) Copyright 2002
* Lineo, Inc. <www.lineo.com>
* Bernhard Kuhn <bkuhn@lineo.com>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/hardware.h>
#include <asm/arch/at91_tc.h>
#include <asm/arch/at91_pmc.h>
/* the number of clocks per CONFIG_SYS_HZ */
#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
static u32 timestamp;
static u32 lastinc;
int timer_init(void)
{
at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
/* enables TC1.0 clock */
writel(1 << AT91_ID_TC0, &pmc->pcer); /* enable clock */
writel(0, &tc->bcr);
writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr);
writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr);
/* set to MCLK/2 and restart the timer
when the value in TC_RC is reached */
writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interupts */
writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
lastinc = 0;
timestamp = 0;
return 0;
}
/*
* timer without interrupts
*/
void reset_timer(void)
{
reset_timer_masked();
}
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
void set_timer(ulong t)
{
timestamp = t;
}
void __udelay(unsigned long usec)
{
udelay_masked(usec);
}
void reset_timer_masked(void)
{
/* reset time */
at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
lastinc = readl(&tc->tc[0].cv) & 0x0000ffff;
timestamp = 0;
}
ulong get_timer_raw(void)
{
at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
u32 now;
now = readl(&tc->tc[0].cv) & 0x0000ffff;
if (now >= lastinc) {
/* normal mode */
timestamp += now - lastinc;
} else {
/* we have an overflow ... */
timestamp += now + TIMER_LOAD_VAL - lastinc;
}
lastinc = now;
return timestamp;
}
ulong get_timer_masked(void)
{
return get_timer_raw()/TIMER_LOAD_VAL;
}
void udelay_masked(unsigned long usec)
{
u32 tmo;
u32 endtime;
signed long diff;
tmo = CONFIG_SYS_HZ_CLOCK / 1000;
tmo *= usec;
tmo /= 1000;
endtime = get_timer_raw() + tmo;
do {
u32 now = get_timer_raw();
diff = endtime - now;
} while (diff >= 0);
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}

4
cpu/arm920t/at91rm9200/bcm5221.c
View file

@ -28,10 +28,10 @@
#include <at91rm9200_net.h>
#include <net.h>
#include <bcm5221.h>
#ifdef CONFIG_DRIVER_ETHER
#include <bcm5221.h>
#if defined(CONFIG_CMD_NET)
/*

3
cpu/arm920t/at91rm9200/dm9161.c
View file

@ -23,9 +23,8 @@
#include <at91rm9200_net.h>
#include <net.h>
#include <dm9161.h>
#ifdef CONFIG_DRIVER_ETHER
#include <dm9161.h>
#if defined(CONFIG_CMD_NET)

4
cpu/arm920t/cpu.c
View file

@ -33,6 +33,10 @@
#include <command.h>
#include <asm/system.h>
#ifdef CONFIG_AT91_LEGACY
#warning Your board is using legacy AT91RM9200 SoC access. Please update!
#endif
static void cache_flush(void);
int cleanup_before_linux (void)

111
cpu/arm920t/ep93xx/timer.c
View file

@ -1,8 +1,7 @@
/*
* Cirrus Logic EP93xx timer support.
*
* Copyright (C) 2009, 2010
* Matthias Kaehlcke <matthias@kaehlcke.net>
* Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
*
* Copyright (C) 2004, 2005
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
@ -31,70 +30,60 @@
#include <linux/types.h>
#include <asm/arch/ep93xx.h>
#include <asm/io.h>
#include <div64.h>
#define TIMER_CLKSEL (1 << 3)
#define TIMER_MODE (1 << 6)
#define TIMER_ENABLE (1 << 7)
#define TIMER_FREQ 508469
#define TIMER_LOAD_VAL (TIMER_FREQ / CONFIG_SYS_HZ)
#define TIMER_FREQ 508469 /* ticks / second */
#define TIMER_MAX_VAL 0xFFFFFFFF
static ulong timestamp;
static ulong lastdec;
static inline unsigned long clk_to_systicks(unsigned long clk_ticks)
static struct ep93xx_timer
{
unsigned long sys_ticks = (clk_ticks * CONFIG_SYS_HZ) / TIMER_FREQ;
unsigned long long ticks;
unsigned long last_read;
} timer;
return sys_ticks;
}
static inline unsigned long usecs_to_ticks(unsigned long usecs)
static inline unsigned long long usecs_to_ticks(unsigned long usecs)
{
unsigned long ticks;
if (usecs >= 1000) {
ticks = usecs / 1000;
ticks *= (TIMER_LOAD_VAL * CONFIG_SYS_HZ);
ticks /= 1000;
} else {
ticks = usecs * TIMER_LOAD_VAL * CONFIG_SYS_HZ;
ticks /= (1000 * 1000);
}
unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ;
do_div(ticks, 1000 * 1000);
return ticks;
}
static inline unsigned long read_timer(void)
static inline void read_timer(void)
{
struct timer_regs *timer = (struct timer_regs *)TIMER_BASE;
struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value);
return readl(&timer->timer3.value);
if (now >= timer.last_read)
timer.ticks += now - timer.last_read;
else
/* an overflow occurred */
timer.ticks += TIMER_MAX_VAL - timer.last_read + now;
timer.last_read = now;
}
/*
* timer without interrupts
* Get the number of ticks (in CONFIG_SYS_HZ resolution)
*/
unsigned long long get_ticks(void)
{
const unsigned long now = read_timer();
unsigned long long sys_ticks;
if (lastdec >= now) {
/* normal mode */
timestamp += lastdec - now;
} else {
/* we have an overflow ... */
timestamp += lastdec + TIMER_LOAD_VAL - now;
}
read_timer();
lastdec = now;
sys_ticks = timer.ticks * CONFIG_SYS_HZ;
do_div(sys_ticks, TIMER_FREQ);
return timestamp;
return sys_ticks;
}
unsigned long get_timer_masked(void)
{
return clk_to_systicks(get_ticks());
return get_ticks();
}
unsigned long get_timer(unsigned long base)
@ -104,8 +93,8 @@ unsigned long get_timer(unsigned long base)
void reset_timer_masked(void)
{
lastdec = read_timer();
timestamp = 0;
read_timer();
timer.ticks = 0;
}
void reset_timer(void)
@ -113,45 +102,31 @@ void reset_timer(void)
reset_timer_masked();
}
void set_timer(unsigned long t)
{
timestamp = t;
}
void __udelay(unsigned long usec)
{
const unsigned long ticks = usecs_to_ticks(usec);
const unsigned long target = clk_to_systicks(ticks) + get_timer(0);
unsigned long long target;
while (get_timer_masked() < target)
/* noop */;
}
read_timer();
void udelay_masked(unsigned long usec)
{
const unsigned long ticks = usecs_to_ticks(usec);
const unsigned long target = clk_to_systicks(ticks) + get_timer(0);
target = timer.ticks + usecs_to_ticks(usec);
reset_timer_masked();
while (get_timer_masked() < target)
/* noop */;
while (timer.ticks < target)
read_timer();
}
int timer_init(void)
{
struct timer_regs *timer = (struct timer_regs *)TIMER_BASE;
struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
/* use timer 3 with 508KHz and free running */
writel(TIMER_CLKSEL, &timer->timer3.control);
/* use timer 3 with 508KHz and free running, not enabled now */
writel(TIMER_CLKSEL, &timer_regs->timer3.control);
/* auto load, manual update of Timer 3 */
lastdec = TIMER_LOAD_VAL;
writel(TIMER_LOAD_VAL, &timer->timer3.load);
/* set initial timer value */
writel(TIMER_MAX_VAL, &timer_regs->timer3.load);
/* Enable the timer and periodic mode */
writel(TIMER_ENABLE | TIMER_MODE | TIMER_CLKSEL,
&timer->timer3.control);
/* Enable the timer */
writel(TIMER_ENABLE | TIMER_CLKSEL,
&timer_regs->timer3.control);
reset_timer_masked();

128
cpu/arm926ejs/at91/at91cap9_devices.c
View file

@ -34,30 +34,38 @@
void at91_serial0_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US0);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* TXD0 */
at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* RXD0 */
writel(1 << AT91CAP9_ID_US0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US1);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* RXD1 */
writel(1 << AT91CAP9_ID_US1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US2);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* RXD2 */
writel(1 << AT91CAP9_ID_US2, &pmc->pcer);
}
void at91_serial3_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */
writel(1 << AT91_ID_SYS, &pmc->pcer);
}
void at91_serial_hw_init(void)
@ -82,71 +90,75 @@ void at91_serial_hw_init(void)
#ifdef CONFIG_HAS_DATAFLASH
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */
at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */
at91_set_b_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0);
writel(1 << AT91CAP9_ID_SPI0, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_B_periph(AT91_PIN_PA5, 1);
at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
}
if (cs_mask & (1 << 1)) {
at91_set_B_periph(AT91_PIN_PA3, 1);
at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 2)) {
at91_set_B_periph(AT91_PIN_PD0, 1);
at91_set_b_periph(AT91_PIO_PORTD, 0, 1);
}
if (cs_mask & (1 << 3)) {
at91_set_B_periph(AT91_PIN_PD1, 1);
at91_set_b_periph(AT91_PIO_PORTD, 1, 1);
}
if (cs_mask & (1 << 4)) {
at91_set_gpio_output(AT91_PIN_PA5, 1);
at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
}
if (cs_mask & (1 << 5)) {
at91_set_gpio_output(AT91_PIN_PA3, 1);
at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 6)) {
at91_set_gpio_output(AT91_PIN_PD0, 1);
at91_set_pio_output(AT91_PIO_PORTD, 0, 1);
}
if (cs_mask & (1 << 7)) {
at91_set_gpio_output(AT91_PIN_PD1, 1);
at91_set_pio_output(AT91_PIO_PORTD, 1, 1);
}
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* SPI1_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* SPI1_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI1);
writel(1 << AT91CAP9_ID_SPI1, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_A_periph(AT91_PIN_PB15, 1);
at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
}
if (cs_mask & (1 << 1)) {
at91_set_A_periph(AT91_PIN_PB16, 1);
at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
}
if (cs_mask & (1 << 2)) {
at91_set_A_periph(AT91_PIN_PB17, 1);
at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
}
if (cs_mask & (1 << 3)) {
at91_set_A_periph(AT91_PIN_PB18, 1);
at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
}
if (cs_mask & (1 << 4)) {
at91_set_gpio_output(AT91_PIN_PB15, 1);
at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
}
if (cs_mask & (1 << 5)) {
at91_set_gpio_output(AT91_PIN_PB16, 1);
at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
}
if (cs_mask & (1 << 6)) {
at91_set_gpio_output(AT91_PIN_PB17, 1);
at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
}
if (cs_mask & (1 << 7)) {
at91_set_gpio_output(AT91_PIN_PB18, 1);
at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
}
}
@ -155,26 +167,26 @@ void at91_spi1_hw_init(unsigned long cs_mask)
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */
at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */
at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */
at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */
at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */
at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */
at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */
at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */
at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */
at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */
at91_set_a_periph(AT91_PIO_PORTB, 21, 0); /* ETXCK_EREFCK */
at91_set_a_periph(AT91_PIO_PORTB, 22, 0); /* ERXDV */
at91_set_a_periph(AT91_PIO_PORTB, 25, 0); /* ERX0 */
at91_set_a_periph(AT91_PIO_PORTB, 26, 0); /* ERX1 */
at91_set_a_periph(AT91_PIO_PORTB, 27, 0); /* ERXER */
at91_set_a_periph(AT91_PIO_PORTB, 28, 0); /* ETXEN */
at91_set_a_periph(AT91_PIO_PORTB, 23, 0); /* ETX0 */
at91_set_a_periph(AT91_PIO_PORTB, 24, 0); /* ETX1 */
at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* EMDIO */
at91_set_a_periph(AT91_PIO_PORTB, 29, 0); /* EMDC */
#ifndef CONFIG_RMII
at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */
at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
at91_set_b_periph(AT91_PIO_PORTC, 25, 0); /* ECRS */
at91_set_b_periph(AT91_PIO_PORTC, 26, 0); /* ECOL */
at91_set_b_periph(AT91_PIO_PORTC, 22, 0); /* ERX2 */
at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* ERX3 */
at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ERXCK */
at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ETX2 */
at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ETX3 */
at91_set_b_periph(AT91_PIO_PORTC, 24, 0); /* ETXER */
#endif
}
#endif
@ -182,10 +194,12 @@ void at91_macb_hw_init(void)
#ifdef CONFIG_AT91_CAN
void at91_can_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PA12, 0); /* CAN_TX */
at91_set_A_periph(AT91_PIN_PA13, 1); /* CAN_RX */
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* CAN_TX */
at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* CAN_RX */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_CAN);
writel(1 << AT91CAP9_ID_CAN, &pmc->pcer);
}
#endif

124
cpu/arm926ejs/at91/at91sam9260_devices.c
View file

@ -30,30 +30,38 @@
void at91_serial0_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */
at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* RXD0 */
writel(1 << AT91SAM9260_ID_US0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* RXD1 */
writel(1 << AT91SAM9260_ID_US1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* RXD2 */
writel(1 << AT91SAM9260_ID_US2, &pmc->pcer);
}
void at91_serial3_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */
writel(1 << AT91_ID_SYS, &pmc->pcer);
}
void at91_serial_hw_init(void)
@ -78,71 +86,75 @@ void at91_serial_hw_init(void)
#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0);
writel(1 << AT91SAM9260_ID_SPI0, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_A_periph(AT91_PIN_PA3, 1);
at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 1)) {
at91_set_B_periph(AT91_PIN_PC11, 1);
at91_set_b_periph(AT91_PIO_PORTC, 11, 1);
}
if (cs_mask & (1 << 2)) {
at91_set_B_periph(AT91_PIN_PC16, 1);
at91_set_b_periph(AT91_PIO_PORTC, 16, 1);
}
if (cs_mask & (1 << 3)) {
at91_set_B_periph(AT91_PIN_PC17, 1);
at91_set_b_periph(AT91_PIO_PORTC, 17, 1);
}
if (cs_mask & (1 << 4)) {
at91_set_gpio_output(AT91_PIN_PA3, 1);
at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 5)) {
at91_set_gpio_output(AT91_PIN_PC11, 1);
at91_set_pio_output(AT91_PIO_PORTC, 11, 1);
}
if (cs_mask & (1 << 6)) {
at91_set_gpio_output(AT91_PIN_PC16, 1);
at91_set_pio_output(AT91_PIO_PORTC, 16, 1);
}
if (cs_mask & (1 << 7)) {
at91_set_gpio_output(AT91_PIN_PC17, 1);
at91_set_pio_output(AT91_PIO_PORTC, 17, 1);
}
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */
at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */
at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* SPI1_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* SPI1_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* SPI1_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI1);
writel(1 << AT91SAM9260_ID_SPI1, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_A_periph(AT91_PIN_PB3, 1);
at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
}
if (cs_mask & (1 << 1)) {
at91_set_B_periph(AT91_PIN_PC5, 1);
at91_set_b_periph(AT91_PIO_PORTC, 5, 1);
}
if (cs_mask & (1 << 2)) {
at91_set_B_periph(AT91_PIN_PC4, 1);
at91_set_b_periph(AT91_PIO_PORTC, 4, 1);
}
if (cs_mask & (1 << 3)) {
at91_set_gpio_output(AT91_PIN_PC3, 1);
at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
}
if (cs_mask & (1 << 4)) {
at91_set_gpio_output(AT91_PIN_PB3, 1);
at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
}
if (cs_mask & (1 << 5)) {
at91_set_gpio_output(AT91_PIN_PC5, 1);
at91_set_pio_output(AT91_PIO_PORTC, 5, 1);
}
if (cs_mask & (1 << 6)) {
at91_set_gpio_output(AT91_PIN_PC4, 1);
at91_set_pio_output(AT91_PIO_PORTC, 4, 1);
}
if (cs_mask & (1 << 7)) {
at91_set_gpio_output(AT91_PIN_PC3, 1);
at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
}
}
#endif
@ -150,35 +162,35 @@ void at91_spi1_hw_init(unsigned long cs_mask)
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* ETXCK_EREFCK */
at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ERXDV */
at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ERX0 */
at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERX1 */
at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* ERXER */
at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ETXEN */
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ETX0 */
at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ETX1 */
at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* EMDIO */
at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* EMDC */
#ifndef CONFIG_RMII
at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ECRS */
at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECOL */
at91_set_b_periph(AT91_PIO_PORTA, 25, 0); /* ERX2 */
at91_set_b_periph(AT91_PIO_PORTA, 26, 0); /* ERX3 */
at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ERXCK */
#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260)
/*
* use PA10, PA11 for ETX2, ETX3.
* PA23 and PA24 are for TWI EEPROM
*/
at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */
at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */
at91_set_b_periph(AT91_PIO_PORTA, 10, 0); /* ETX2 */
at91_set_b_periph(AT91_PIO_PORTA, 11, 0); /* ETX3 */
#else
at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* ETX2 */
at91_set_b_periph(AT91_PIO_PORTA, 24, 0); /* ETX3 */
#endif
at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* ETXER */
#endif
}
#endif

84
cpu/arm926ejs/at91/at91sam9261_devices.c
View file

@ -30,30 +30,38 @@
void at91_serial0_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTC, 8, 1); /* TXD0 */
at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* RXD0 */
writel(1 << AT91SAM9261_ID_US0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */
writel(1 << AT91SAM9261_ID_US1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */
writel(1 << AT91SAM9261_ID_US2, &pmc->pcer);
}
void at91_serial3_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
writel(1 << AT91_ID_SYS, &pmc->pcer);
}
void at91_serial_hw_init(void)
@ -78,71 +86,75 @@ void at91_serial_hw_init(void)
#ifdef CONFIG_HAS_DATAFLASH
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0);
writel(1 << AT91SAM9261_ID_SPI0, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_A_periph(AT91_PIN_PA3, 1);
at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 1)) {
at91_set_A_periph(AT91_PIN_PA4, 1);
at91_set_a_periph(AT91_PIO_PORTA, 4, 1);
}
if (cs_mask & (1 << 2)) {
at91_set_A_periph(AT91_PIN_PA5, 1);
at91_set_a_periph(AT91_PIO_PORTA, 5, 1);
}
if (cs_mask & (1 << 3)) {
at91_set_A_periph(AT91_PIN_PA6, 1);
at91_set_a_periph(AT91_PIO_PORTA, 6, 1);
}
if (cs_mask & (1 << 4)) {
at91_set_gpio_output(AT91_PIN_PA3, 1);
at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 5)) {
at91_set_gpio_output(AT91_PIN_PA4, 1);
at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
}
if (cs_mask & (1 << 6)) {
at91_set_gpio_output(AT91_PIN_PA5, 1);
at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
}
if (cs_mask & (1 << 7)) {
at91_set_gpio_output(AT91_PIN_PA6, 1);
at91_set_pio_output(AT91_PIO_PORTA, 6, 1);
}
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */
at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */
at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* SPI1_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 31, 0); /* SPI1_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 29, 0); /* SPI1_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI1);
writel(1 << AT91SAM9261_ID_SPI1, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_A_periph(AT91_PIN_PB28, 1);
at91_set_a_periph(AT91_PIO_PORTB, 28, 1);
}
if (cs_mask & (1 << 1)) {
at91_set_B_periph(AT91_PIN_PA24, 1);
at91_set_b_periph(AT91_PIO_PORTA, 24, 1);
}
if (cs_mask & (1 << 2)) {
at91_set_B_periph(AT91_PIN_PA25, 1);
at91_set_b_periph(AT91_PIO_PORTA, 25, 1);
}
if (cs_mask & (1 << 3)) {
at91_set_A_periph(AT91_PIN_PA26, 1);
at91_set_a_periph(AT91_PIO_PORTA, 26, 1);
}
if (cs_mask & (1 << 4)) {
at91_set_gpio_output(AT91_PIN_PB28, 1);
at91_set_pio_output(AT91_PIO_PORTB, 28, 1);
}
if (cs_mask & (1 << 5)) {
at91_set_gpio_output(AT91_PIN_PA24, 1);
at91_set_pio_output(AT91_PIO_PORTA, 24, 1);
}
if (cs_mask & (1 << 6)) {
at91_set_gpio_output(AT91_PIN_PA25, 1);
at91_set_pio_output(AT91_PIO_PORTA, 25, 1);
}
if (cs_mask & (1 << 7)) {
at91_set_gpio_output(AT91_PIN_PA26, 1);
at91_set_pio_output(AT91_PIO_PORTA, 26, 1);
}
}
#endif

137
cpu/arm926ejs/at91/at91sam9263_devices.c
View file

@ -27,37 +27,46 @@
*/
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <asm/arch/at91_pio.h>
void at91_serial0_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */
at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */
writel(1 << AT91SAM9263_ID_US0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US1);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* RXD1 */
writel(1 << AT91SAM9263_ID_US1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US2);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* RXD2 */
writel(1 << AT91SAM9263_ID_US2, &pmc->pcer);
}
void at91_serial3_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */
writel(1 << AT91_ID_SYS, &pmc->pcer);
}
void at91_serial_hw_init(void)
@ -82,71 +91,75 @@ void at91_serial_hw_init(void)
#ifdef CONFIG_HAS_DATAFLASH
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */
at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */
at91_set_b_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0);
writel(1 << AT91SAM9263_ID_SPI0, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_B_periph(AT91_PIN_PA5, 1);
at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
}
if (cs_mask & (1 << 1)) {
at91_set_B_periph(AT91_PIN_PA3, 1);
at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 2)) {
at91_set_B_periph(AT91_PIN_PA4, 1);
at91_set_b_periph(AT91_PIO_PORTA, 4, 1);
}
if (cs_mask & (1 << 3)) {
at91_set_B_periph(AT91_PIN_PB11, 1);
at91_set_b_periph(AT91_PIO_PORTB, 11, 1);
}
if (cs_mask & (1 << 4)) {
at91_set_gpio_output(AT91_PIN_PA5, 1);
at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
}
if (cs_mask & (1 << 5)) {
at91_set_gpio_output(AT91_PIN_PA3, 1);
at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 6)) {
at91_set_gpio_output(AT91_PIN_PA4, 1);
at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
}
if (cs_mask & (1 << 7)) {
at91_set_gpio_output(AT91_PIN_PB11, 1);
at91_set_pio_output(AT91_PIO_PORTB, 11, 1);
}
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* SPI1_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* SPI1_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI1);
writel(1 << AT91SAM9263_ID_SPI1, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_A_periph(AT91_PIN_PB15, 1);
at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
}
if (cs_mask & (1 << 1)) {
at91_set_A_periph(AT91_PIN_PB16, 1);
at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
}
if (cs_mask & (1 << 2)) {
at91_set_A_periph(AT91_PIN_PB17, 1);
at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
}
if (cs_mask & (1 << 3)) {
at91_set_A_periph(AT91_PIN_PB18, 1);
at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
}
if (cs_mask & (1 << 4)) {
at91_set_gpio_output(AT91_PIN_PB15, 1);
at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
}
if (cs_mask & (1 << 5)) {
at91_set_gpio_output(AT91_PIN_PB16, 1);
at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
}
if (cs_mask & (1 << 6)) {
at91_set_gpio_output(AT91_PIN_PB17, 1);
at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
}
if (cs_mask & (1 << 7)) {
at91_set_gpio_output(AT91_PIN_PB18, 1);
at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
}
}
#endif
@ -154,26 +167,26 @@ void at91_spi1_hw_init(unsigned long cs_mask)
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
at91_set_a_periph(AT91_PIO_PORTE, 21, 0); /* ETXCK_EREFCK */
at91_set_b_periph(AT91_PIO_PORTC, 25, 0); /* ERXDV */
at91_set_a_periph(AT91_PIO_PORTE, 25, 0); /* ERX0 */
at91_set_a_periph(AT91_PIO_PORTE, 26, 0); /* ERX1 */
at91_set_a_periph(AT91_PIO_PORTE, 27, 0); /* ERXER */
at91_set_a_periph(AT91_PIO_PORTE, 28, 0); /* ETXEN */
at91_set_a_periph(AT91_PIO_PORTE, 23, 0); /* ETX0 */
at91_set_a_periph(AT91_PIO_PORTE, 24, 0); /* ETX1 */
at91_set_a_periph(AT91_PIO_PORTE, 30, 0); /* EMDIO */
at91_set_a_periph(AT91_PIO_PORTE, 29, 0); /* EMDC */
#ifndef CONFIG_RMII
at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
at91_set_a_periph(AT91_PIO_PORTE, 22, 0); /* ECRS */
at91_set_b_periph(AT91_PIO_PORTC, 26, 0); /* ECOL */
at91_set_b_periph(AT91_PIO_PORTC, 22, 0); /* ERX2 */
at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* ERX3 */
at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ERXCK */
at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ETX2 */
at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ETX3 */
at91_set_b_periph(AT91_PIO_PORTC, 24, 0); /* ETXER */
#endif
}
#endif
@ -182,18 +195,20 @@ void at91_macb_hw_init(void)
void at91_uhp_hw_init(void)
{
/* Enable VBus on UHP ports */
at91_set_gpio_output(AT91_PIN_PA21, 0);
at91_set_gpio_output(AT91_PIN_PA24, 0);
at91_set_pio_output(AT91_PIO_PORTA, 21, 0);
at91_set_pio_output(AT91_PIO_PORTA, 24, 0);
}
#endif
#ifdef CONFIG_AT91_CAN
void at91_can_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PA13, 0); /* CAN_TX */
at91_set_A_periph(AT91_PIN_PA14, 1); /* CAN_RX */
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CAN_TX */
at91_set_a_periph(AT91_PIO_PORTA, 14, 1); /* CAN_RX */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_CAN);
writel(1 << AT91SAM9263_ID_CAN, &pmc->pcer);
}
#endif

120
cpu/arm926ejs/at91/at91sam9m10g45_devices.c
View file

@ -30,30 +30,38 @@
void at91_serial0_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US0);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */
at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* RXD0 */
writel(1 << AT91SAM9G45_ID_US0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US1);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* RXD1 */
writel(1 << AT91SAM9G45_ID_US1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PD6, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PD7, 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US2);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* RXD2 */
writel(1 << AT91SAM9G45_ID_US2, &pmc->pcer);
}
void at91_serial3_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);;
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */
writel(1 << AT91_ID_SYS, &pmc->pcer);
}
void at91_serial_hw_init(void)
@ -78,71 +86,75 @@ void at91_serial_hw_init(void)
#ifdef CONFIG_ATMEL_SPI
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI0);
writel(1 << AT91SAM9G45_ID_SPI0, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_A_periph(AT91_PIN_PB3, 0);
at91_set_a_periph(AT91_PIO_PORTB, 3, 0);
}
if (cs_mask & (1 << 1)) {
at91_set_B_periph(AT91_PIN_PB18, 0);
at91_set_b_periph(AT91_PIO_PORTB, 18, 0);
}
if (cs_mask & (1 << 2)) {
at91_set_B_periph(AT91_PIN_PB19, 0);
at91_set_b_periph(AT91_PIO_PORTB, 19, 0);
}
if (cs_mask & (1 << 3)) {
at91_set_B_periph(AT91_PIN_PD27, 0);
at91_set_b_periph(AT91_PIO_PORTD, 27, 0);
}
if (cs_mask & (1 << 4)) {
at91_set_gpio_output(AT91_PIN_PB3, 0);
at91_set_pio_output(AT91_PIO_PORTB, 3, 0);
}
if (cs_mask & (1 << 5)) {
at91_set_gpio_output(AT91_PIN_PB18, 0);
at91_set_pio_output(AT91_PIO_PORTB, 18, 0);
}
if (cs_mask & (1 << 6)) {
at91_set_gpio_output(AT91_PIN_PB19, 0);
at91_set_pio_output(AT91_PIO_PORTB, 19, 0);
}
if (cs_mask & (1 << 7)) {
at91_set_gpio_output(AT91_PIN_PD27, 0);
at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
}
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* SPI1_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* SPI1_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI1);
writel(1 << AT91SAM9G45_ID_SPI1, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_A_periph(AT91_PIN_PB17, 0);
at91_set_a_periph(AT91_PIO_PORTB, 17, 0);
}
if (cs_mask & (1 << 1)) {
at91_set_B_periph(AT91_PIN_PD28, 0);
at91_set_b_periph(AT91_PIO_PORTD, 28, 0);
}
if (cs_mask & (1 << 2)) {
at91_set_A_periph(AT91_PIN_PD18, 0);
at91_set_a_periph(AT91_PIO_PORTD, 18, 0);
}
if (cs_mask & (1 << 3)) {
at91_set_A_periph(AT91_PIN_PD19, 0);
at91_set_a_periph(AT91_PIO_PORTD, 19, 0);
}
if (cs_mask & (1 << 4)) {
at91_set_gpio_output(AT91_PIN_PB17, 0);
at91_set_pio_output(AT91_PIO_PORTB, 17, 0);
}
if (cs_mask & (1 << 5)) {
at91_set_gpio_output(AT91_PIN_PD28, 0);
at91_set_pio_output(AT91_PIO_PORTD, 28, 0);
}
if (cs_mask & (1 << 6)) {
at91_set_gpio_output(AT91_PIN_PD18, 0);
at91_set_pio_output(AT91_PIO_PORTD, 18, 0);
}
if (cs_mask & (1 << 7)) {
at91_set_gpio_output(AT91_PIN_PD19, 0);
at91_set_pio_output(AT91_PIO_PORTD, 19, 0);
}
}
@ -151,25 +163,25 @@ void at91_spi1_hw_init(unsigned long cs_mask)
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ETXCK_EREFCK */
at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERXDV */
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ERX0 */
at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ERX1 */
at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ERXER */
at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ETXEN */
at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* ETX0 */
at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* ETX1 */
at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* EMDIO */
at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* EMDC */
#ifndef CONFIG_RMII
at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECRS */
at91_set_b_periph(AT91_PIO_PORTA, 30, 0); /* ECOL */
at91_set_b_periph(AT91_PIO_PORTA, 8, 0); /* ERX2 */
at91_set_b_periph(AT91_PIO_PORTA, 9, 0); /* ERX3 */
at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ERXCK */
at91_set_b_periph(AT91_PIO_PORTA, 6, 0); /* ETX2 */
at91_set_b_periph(AT91_PIO_PORTA, 7, 0); /* ETX3 */
at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ETXER */
#endif
}
#endif

58
cpu/arm926ejs/at91/at91sam9rl_devices.c
View file

@ -30,30 +30,38 @@
void at91_serial0_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US0);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* TXD0 */
at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* RXD0 */
writel(1 << AT91SAM9RL_ID_US0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US1);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* RXD1 */
writel(1 << AT91SAM9RL_ID_US1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US2);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* RXD2 */
writel(1 << AT91SAM9RL_ID_US2, &pmc->pcer);
}
void at91_serial3_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */
writel(1 << AT91_ID_SYS, &pmc->pcer);
}
void at91_serial_hw_init(void)
@ -78,36 +86,38 @@ void at91_serial_hw_init(void)
#ifdef CONFIG_HAS_DATAFLASH
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_set_A_periph(AT91_PIN_PA25, 0); /* SPI0_MISO */
at91_set_A_periph(AT91_PIN_PA26, 0); /* SPI0_MOSI */
at91_set_A_periph(AT91_PIN_PA27, 0); /* SPI0_SPCK */
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI);
writel(1 << AT91SAM9RL_ID_SPI, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_A_periph(AT91_PIN_PA28, 1);
at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
}
if (cs_mask & (1 << 1)) {
at91_set_B_periph(AT91_PIN_PB7, 1);
at91_set_b_periph(AT91_PIO_PORTB, 7, 1);
}
if (cs_mask & (1 << 2)) {
at91_set_A_periph(AT91_PIN_PD8, 1);
at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
}
if (cs_mask & (1 << 3)) {
at91_set_B_periph(AT91_PIN_PD9, 1);
at91_set_b_periph(AT91_PIO_PORTD, 9, 1);
}
if (cs_mask & (1 << 4)) {
at91_set_gpio_output(AT91_PIN_PA28, 1);
at91_set_pio_output(AT91_PIO_PORTA, 28, 1);
}
if (cs_mask & (1 << 5)) {
at91_set_gpio_output(AT91_PIN_PB7, 1);
at91_set_pio_output(AT91_PIO_PORTB, 7, 1);
}
if (cs_mask & (1 << 6)) {
at91_set_gpio_output(AT91_PIN_PD8, 1);
at91_set_pio_output(AT91_PIO_PORTD, 8, 1);
}
if (cs_mask & (1 << 7)) {
at91_set_gpio_output(AT91_PIN_PD9, 1);
at91_set_pio_output(AT91_PIO_PORTD, 9, 1);
}
}
#endif

60
cpu/arm926ejs/at91/clock.c
View file

@ -13,9 +13,9 @@
#include <config.h>
#include <asm/arch/hardware.h>
#include <asm/arch/io.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>
#include <asm/arch/io.h>
static unsigned long cpu_clk_rate_hz;
static unsigned long main_clk_rate_hz;
@ -57,14 +57,14 @@ u32 get_pllb_init(void)
static unsigned long at91_css_to_rate(unsigned long css)
{
switch (css) {
case AT91_PMC_CSS_SLOW:
return AT91_SLOW_CLOCK;
case AT91_PMC_CSS_MAIN:
return main_clk_rate_hz;
case AT91_PMC_CSS_PLLA:
return plla_rate_hz;
case AT91_PMC_CSS_PLLB:
return pllb_rate_hz;
case AT91_PMC_MCKR_CSS_SLOW:
return AT91_SLOW_CLOCK;
case AT91_PMC_MCKR_CSS_MAIN:
return main_clk_rate_hz;
case AT91_PMC_MCKR_CSS_PLLA:
return plla_rate_hz;
case AT91_PMC_MCKR_CSS_PLLB:
return pllb_rate_hz;
}
return 0;
@ -146,7 +146,8 @@ static u32 at91_pll_rate(u32 freq, u32 reg)
int at91_clock_init(unsigned long main_clock)
{
unsigned freq, mckr;
#ifndef AT91_MAIN_CLOCK
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
unsigned tmp;
/*
* When the bootloader initialized the main oscillator correctly,
@ -156,15 +157,16 @@ int at91_clock_init(unsigned long main_clock)
*/
if (!main_clock) {
do {
tmp = at91_sys_read(AT91_CKGR_MCFR);
} while (!(tmp & AT91_PMC_MAINRDY));
main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
tmp = readl(&pmc->mcfr);
} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
tmp &= AT91_PMC_MCFR_MAINF_MASK;
main_clock = tmp * (AT91_SLOW_CLOCK / 16);
}
#endif
main_clk_rate_hz = main_clock;
/* report if PLLA is more than mildly overclocked */
plla_rate_hz = at91_pll_rate(main_clock, at91_sys_read(AT91_CKGR_PLLAR));
plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
#ifdef CONFIG_USB_ATMEL
/*
@ -174,7 +176,7 @@ int at91_clock_init(unsigned long main_clock)
* REVISIT: assumes MCK doesn't derive from PLLB!
*/
at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
AT91_PMC_USB96M;
AT91_PMC_PLLBR_USBDIV_2;
pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init);
#endif
@ -182,28 +184,32 @@ int at91_clock_init(unsigned long main_clock)
* MCK and CPU derive from one of those primary clocks.
* For now, assume this parentage won't change.
*/
mckr = at91_sys_read(AT91_PMC_MCKR);
mckr = readl(&pmc->mckr);
#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
/* plla divisor by 2 */
plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
#endif
freq = mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_CSS);
mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
freq = mck_rate_hz;
freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
#if defined(CONFIG_AT91RM9200)
mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
/* mdiv */
mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#elif defined(CONFIG_AT91SAM9G20)
mck_rate_hz = (mckr & AT91_PMC_MDIV) ?
freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
if (mckr & AT91_PMC_PDIV)
freq /= 2; /* processor clock division */
/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
if (mckr & AT91_PMC_MCKR_MDIV_MASK)
freq /= 2; /* processor clock division */
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
mck_rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == AT91SAM9_PMC_MDIV_3
? freq / 3
: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#else
mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#endif
cpu_clk_rate_hz = freq;
return 0;
return 0;
}

46
cpu/arm926ejs/at91/cpu.c
View file

@ -22,18 +22,29 @@
*/
#include <common.h>
#ifdef CONFIG_AT91_LEGACY
#warning Your board is using legacy SoC access. Please update!
#endif
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>
#include <asm/arch/io.h>
#ifndef AT91_MAIN_CLOCK
#define AT91_MAIN_CLOCK 0
#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
#define CONFIG_SYS_AT91_MAIN_CLOCK 0
#endif
/*
* The at91sam9260 has 4 GPBR (0-3), we'll use the last one, nr 3,
* to keep track of the bootcount.
*/
#define AT91_GPBR_BOOTCOUNT_REGISTER 3
#define AT91_BOOTCOUNT_ADDRESS (AT91_GPBR + 4*AT91_GPBR_BOOTCOUNT_REGISTER)
int arch_cpu_init(void)
{
return at91_clock_init(AT91_MAIN_CLOCK);
return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
}
#if defined(CONFIG_DISPLAY_CPUINFO)
@ -41,7 +52,7 @@ int print_cpuinfo(void)
{
char buf[32];
printf("CPU: %s\n", AT91_CPU_NAME);
printf("CPU: %s\n", CONFIG_SYS_AT91_CPU_NAME);
printf("Crystal frequency: %8s MHz\n",
strmhz(buf, get_main_clk_rate()));
printf("CPU clock : %8s MHz\n",
@ -52,3 +63,30 @@ int print_cpuinfo(void)
return 0;
}
#endif
#ifdef CONFIG_BOOTCOUNT_LIMIT
/*
* Just as the mpc5xxx, we combine the BOOTCOUNT_MAGIC and boocount
* in one 32-bit register. This is done, as the AT91SAM9260 only has
* 4 GPBR.
*/
void bootcount_store (ulong a)
{
volatile ulong *save_addr =
(volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS);
*save_addr = (BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff);
}
ulong bootcount_load (void)
{
volatile ulong *save_addr =
(volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS);
if ((*save_addr & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
return 0;
else
return (*save_addr & 0x0000ffff);
}
#endif /* CONFIG_BOOTCOUNT_LIMIT */

1
cpu/arm926ejs/at91/led.c
View file

@ -24,6 +24,7 @@
#include <common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>

95
cpu/arm926ejs/at91/lowlevel_init.S
View file

@ -27,15 +27,20 @@
*/
#include <config.h>
#include <version.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_wdt.h>
#include <asm/arch/at91sam9_matrix.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/at91sam9_sdramc.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_rstc.h>
#ifdef CONFIG_AT91_LEGACY
#include <asm/arch/at91sam9_matrix.h>
#endif
#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
#endif
_TEXT_BASE:
.word TEXT_BASE
@ -75,7 +80,7 @@ POS1:
* - Check if the PLL is already initialized
* ----------------------------------------------------------------------------
*/
ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
ldr r1, =(AT91_ASM_PMC_MCKR)
ldr r0, [r1]
and r0, r0, #3
cmp r0, #0
@ -85,18 +90,18 @@ POS1:
* - Enable the Main Oscillator
* ---------------------------------------------------------------------------
*/
ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR)
ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR)
ldr r1, =(AT91_ASM_PMC_MOR)
ldr r2, =(AT91_ASM_PMC_SR)
/* Main oscillator Enable register PMC_MOR: */
ldr r0, =CONFIG_SYS_MOR_VAL
str r0, [r1]
/* Reading the PMC Status to detect when the Main Oscillator is enabled */
mov r4, #AT91_PMC_MOSCS
mov r4, #AT91_PMC_IXR_MOSCS
MOSCS_Loop:
ldr r3, [r2]
and r3, r4, r3
cmp r3, #AT91_PMC_MOSCS
cmp r3, #AT91_PMC_IXR_MOSCS
bne MOSCS_Loop
/* ----------------------------------------------------------------------------
@ -105,16 +110,16 @@ MOSCS_Loop:
* Setup PLLA
* ----------------------------------------------------------------------------
*/
ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR)
ldr r1, =(AT91_ASM_PMC_PLLAR)
ldr r0, =CONFIG_SYS_PLLAR_VAL
str r0, [r1]
/* Reading the PMC Status register to detect when the PLLA is locked */
mov r4, #AT91_PMC_LOCKA
mov r4, #AT91_PMC_IXR_LOCKA
MOSCS_Loop1:
ldr r3, [r2]
and r3, r4, r3
cmp r3, #AT91_PMC_LOCKA
cmp r3, #AT91_PMC_IXR_LOCKA
bne MOSCS_Loop1
/* ----------------------------------------------------------------------------
@ -123,38 +128,37 @@ MOSCS_Loop1:
* - Switch on the Main Oscillator
* ----------------------------------------------------------------------------
*/
ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
ldr r1, =(AT91_ASM_PMC_MCKR)
/* -Master Clock Controller register PMC_MCKR */
ldr r0, =CONFIG_SYS_MCKR1_VAL
str r0, [r1]
/* Reading the PMC Status to detect when the Master clock is ready */
mov r4, #AT91_PMC_MCKRDY
mov r4, #AT91_PMC_IXR_MCKRDY
MCKRDY_Loop:
ldr r3, [r2]
and r3, r4, r3
cmp r3, #AT91_PMC_MCKRDY
cmp r3, #AT91_PMC_IXR_MCKRDY
bne MCKRDY_Loop
ldr r0, =CONFIG_SYS_MCKR2_VAL
str r0, [r1]
/* Reading the PMC Status to detect when the Master clock is ready */
mov r4, #AT91_PMC_MCKRDY
mov r4, #AT91_PMC_IXR_MCKRDY
MCKRDY_Loop1:
ldr r3, [r2]
and r3, r4, r3
cmp r3, #AT91_PMC_MCKRDY
cmp r3, #AT91_PMC_IXR_MCKRDY
bne MCKRDY_Loop1
PLL_setup_end:
/* ----------------------------------------------------------------------------
* - memory control configuration 2
* ----------------------------------------------------------------------------
*/
ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR)
ldr r0, =(AT91_ASM_SDRAMC_TR)
ldr r1, [r0]
cmp r1, #0
bne SDRAM_setup_end
@ -166,7 +170,6 @@ PLL_setup_end:
sub r2, r2, r1
add r0, r0, r5
add r2, r2, r5
2:
/* the address */
ldr r1, [r0], #4
@ -183,60 +186,53 @@ SDRAM_setup_end:
.ltorg
SMRDATA:
.word (AT91_BASE_SYS + AT91_WDT_MR)
.word AT91_ASM_WDT_MR
.word CONFIG_SYS_WDTC_WDMR_VAL
/* configure PIOx as EBI0 D[16-31] */
#if defined(CONFIG_AT91SAM9263)
.word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR)
.word AT91_ASM_PIOD_PDR
.word CONFIG_SYS_PIOD_PDR_VAL1
.word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR)
.word AT91_ASM_PIOD_PUDR
.word CONFIG_SYS_PIOD_PPUDR_VAL
.word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR)
.word AT91_ASM_PIOD_ASR
.word CONFIG_SYS_PIOD_PPUDR_VAL
#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
|| defined(CONFIG_AT91SAM9G20)
.word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR)
.word AT91_ASM_PIOC_PDR
.word CONFIG_SYS_PIOC_PDR_VAL1
.word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR)
.word AT91_ASM_PIOC_PUDR
.word CONFIG_SYS_PIOC_PPUDR_VAL
#endif
#if defined(AT91_MATRIX_EBI0CSA)
.word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA)
.word CONFIG_SYS_MATRIX_EBI0CSA_VAL
#else /* AT91_MATRIX_EBICSA */
.word (AT91_BASE_SYS + AT91_MATRIX_EBICSA)
.word AT91_ASM_MATRIX_CSA0
.word CONFIG_SYS_MATRIX_EBICSA_VAL
#endif
/* flash */
.word (AT91_BASE_SYS + AT91_SMC_MODE(0))
.word AT91_ASM_SMC_MODE0
.word CONFIG_SYS_SMC0_MODE0_VAL
.word (AT91_BASE_SYS + AT91_SMC_CYCLE(0))
.word AT91_ASM_SMC_CYCLE0
.word CONFIG_SYS_SMC0_CYCLE0_VAL
.word (AT91_BASE_SYS + AT91_SMC_PULSE(0))
.word AT91_ASM_SMC_PULSE0
.word CONFIG_SYS_SMC0_PULSE0_VAL
.word (AT91_BASE_SYS + AT91_SMC_SETUP(0))
.word AT91_ASM_SMC_SETUP0
.word CONFIG_SYS_SMC0_SETUP0_VAL
SMRDATA1:
.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL1
.word (AT91_BASE_SYS + AT91_SDRAMC_TR)
.word AT91_ASM_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL1
.word (AT91_BASE_SYS + AT91_SDRAMC_CR)
.word AT91_ASM_SDRAMC_CR
.word CONFIG_SYS_SDRC_CR_VAL
.word (AT91_BASE_SYS + AT91_SDRAMC_MDR)
.word AT91_ASM_SDRAMC_MDR
.word CONFIG_SYS_SDRC_MDR_VAL
.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL2
.word AT91_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL1
.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL3
.word AT91_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL2
@ -254,26 +250,25 @@ SMRDATA1:
.word CONFIG_SYS_SDRAM_VAL8
.word AT91_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL9
.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL4
.word AT91_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL10
.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL5
.word AT91_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL11
.word (AT91_BASE_SYS + AT91_SDRAMC_TR)
.word AT91_ASM_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL2
.word AT91_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL12
/* User reset enable*/
.word (AT91_BASE_SYS + AT91_RSTC_MR)
.word AT91_ASM_RSTC_MR
.word CONFIG_SYS_RSTC_RMR_VAL
#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
/* MATRIX_MCFG - REMAP all masters */
.word (AT91_BASE_SYS + AT91_MATRIX_MCFG0)
.word AT91_ASM_MATRIX_MCFG
.word 0x1FF
#endif
SMRDATA2:
.word 0

8
cpu/arm926ejs/at91/reset.c
View file

@ -32,10 +32,12 @@
*/
void reset_cpu(ulong ignored)
{
at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE;
/* this is the way Linux does it */
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY |
AT91_RSTC_PROCRST |
AT91_RSTC_PERRST);
writel(AT91_RSTC_KEY | AT91_RSTC_CR_PROCRST | AT91_RSTC_CR_PERRST,
&rstc->cr);
while (1);
/* Never reached */

17
cpu/arm926ejs/at91/timer.c
View file

@ -35,8 +35,6 @@
* setting the 20 bit counter period to its maximum (0xfffff).
*/
#define TIMER_LOAD_VAL 0xfffff
#define READ_RESET_TIMER at91_sys_read(AT91_PIT_PIVR)
#define READ_TIMER at91_sys_read(AT91_PIT_PIIR)
static ulong timestamp;
static ulong lastinc;
@ -61,14 +59,16 @@ static inline unsigned long long usec_to_tick(unsigned long long usec)
/* nothing really to do with interrupts, just starts up a counter. */
int timer_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
/*
* Enable PITC Clock
* The clock is already enabled for system controller in boot
*/
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
writel(1 << AT91_ID_SYS, &pmc->pcer);
/* Enable PITC */
at91_sys_write(AT91_PIT_MR, TIMER_LOAD_VAL | AT91_PIT_PITEN);
writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
reset_timer_masked();
@ -82,7 +82,9 @@ int timer_init(void)
*/
unsigned long long get_ticks(void)
{
ulong now = READ_TIMER;
at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
ulong now = readl(&pit->piir);
if (now >= lastinc) /* normal mode (non roll) */
/* move stamp forward with absolut diff ticks */
@ -96,7 +98,10 @@ unsigned long long get_ticks(void)
void reset_timer_masked(void)
{
/* reset time */
lastinc = READ_TIMER; /* capture current incrementer value time */
at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
/* capture current incrementer value time */
lastinc = readl(&pit->piir);
timestamp = 0; /* start "advancing" time stamp from 0 */
}

46
cpu/arm926ejs/mx25/Makefile Normal file
View file

@ -0,0 +1,46 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
COBJS = generic.o timer.o
MX27OBJS = reset.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
SRCS += $(addprefix $(SRCTREE)/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(MX27OBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

263
cpu/arm926ejs/mx25/generic.c Normal file
View file

@ -0,0 +1,263 @@
/*
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
*
* Based on mx27/generic.c:
* Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
* Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <div64.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/imx25-pinmux.h>
#ifdef CONFIG_MXC_MMC
#include <asm/arch/mxcmmc.h>
#endif
/*
* get the system pll clock in Hz
*
* mfi + mfn / (mfd +1)
* f = 2 * f_ref * --------------------
* pd + 1
*/
static unsigned int imx_decode_pll (unsigned int pll, unsigned int f_ref)
{
unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
& CCM_PLL_MFI_MASK;
unsigned int mfn = (pll >> CCM_PLL_MFN_SHIFT)
& CCM_PLL_MFN_MASK;
unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
& CCM_PLL_MFD_MASK;
unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
& CCM_PLL_PD_MASK;
mfi = mfi <= 5 ? 5 : mfi;
return lldiv (2 * (u64) f_ref * (mfi * (mfd + 1) + mfn),
(mfd + 1) * (pd + 1));
}
static ulong imx_get_mpllclk (void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong fref = 24000000;
return imx_decode_pll (readl (&ccm->mpctl), fref);
}
ulong imx_get_armclk (void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong cctl = readl (&ccm->cctl);
ulong fref = imx_get_mpllclk ();
ulong div;
if (cctl & CCM_CCTL_ARM_SRC)
fref = lldiv ((fref * 3), 4);
div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
& CCM_CCTL_ARM_DIV_MASK) + 1;
return lldiv (fref, div);
}
ulong imx_get_ahbclk (void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong cctl = readl (&ccm->cctl);
ulong fref = imx_get_armclk ();
ulong div;
div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
& CCM_CCTL_AHB_DIV_MASK) + 1;
return lldiv (fref, div);
}
ulong imx_get_perclk (int clk)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong fref = imx_get_ahbclk ();
ulong div;
div = readl (&ccm->pcdr[CCM_PERCLK_REG (clk)]);
div = ((div >> CCM_PERCLK_SHIFT (clk)) & CCM_PERCLK_MASK) + 1;
return lldiv (fref, div);
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo (void)
{
char buf[32];
printf ("CPU: Freescale i.MX25 at %s MHz\n\n",
strmhz (buf, imx_get_mpllclk ()));
return 0;
}
#endif
int cpu_eth_init (bd_t * bis)
{
#if defined(CONFIG_FEC_MXC)
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong val;
val = readl (&ccm->cgr0);
val |= (1 << 23);
writel (val, &ccm->cgr0);
return fecmxc_initialize (bis);
#else
return 0;
#endif
}
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init (bd_t * bis)
{
#ifdef CONFIG_MXC_MMC
return mxc_mmc_init (bis);
#else
return 0;
#endif
}
#ifdef CONFIG_MXC_UART
void mx25_uart_init_pins (void)
{
struct iomuxc_mux_ctl *muxctl;
struct iomuxc_pad_ctl *padctl;
u32 inpadctl;
u32 outpadctl;
u32 muxmode0;
muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
muxmode0 = MX25_PIN_MUX_MODE (0);
/*
* set up input pins with hysteresis and 100K pull-ups
*/
inpadctl = MX25_PIN_PAD_CTL_HYS
| MX25_PIN_PAD_CTL_PKE
| MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU;
/*
* set up output pins with 100K pull-downs
* FIXME: need to revisit this
* PUE is ignored if PKE is not set
* so the right value here is likely
* 0x0 for no pull up/down
* or
* 0xc0 for 100k pull down
*/
outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
/* UART1 */
/* rxd */
writel (muxmode0, &muxctl->pad_uart1_rxd);
writel (inpadctl, &padctl->pad_uart1_rxd);
/* txd */
writel (muxmode0, &muxctl->pad_uart1_txd);
writel (outpadctl, &padctl->pad_uart1_txd);
/* rts */
writel (muxmode0, &muxctl->pad_uart1_rts);
writel (outpadctl, &padctl->pad_uart1_rts);
/* cts */
writel (muxmode0, &muxctl->pad_uart1_cts);
writel (inpadctl, &padctl->pad_uart1_cts);
}
#endif /* CONFIG_MXC_UART */
#ifdef CONFIG_FEC_MXC
void mx25_fec_init_pins (void)
{
struct iomuxc_mux_ctl *muxctl;
struct iomuxc_pad_ctl *padctl;
u32 inpadctl_100kpd;
u32 inpadctl_22kpu;
u32 outpadctl;
u32 muxmode0;
muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
muxmode0 = MX25_PIN_MUX_MODE (0);
inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS
| MX25_PIN_PAD_CTL_PKE
| MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS
| MX25_PIN_PAD_CTL_PKE
| MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU;
/*
* set up output pins with 100K pull-downs
* FIXME: need to revisit this
* PUE is ignored if PKE is not set
* so the right value here is likely
* 0x0 for no pull
* or
* 0xc0 for 100k pull down
*/
outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
/* FEC_TX_CLK */
writel (muxmode0, &muxctl->pad_fec_tx_clk);
writel (inpadctl_100kpd, &padctl->pad_fec_tx_clk);
/* FEC_RX_DV */
writel (muxmode0, &muxctl->pad_fec_rx_dv);
writel (inpadctl_100kpd, &padctl->pad_fec_rx_dv);
/* FEC_RDATA0 */
writel (muxmode0, &muxctl->pad_fec_rdata0);
writel (inpadctl_100kpd, &padctl->pad_fec_rdata0);
/* FEC_TDATA0 */
writel (muxmode0, &muxctl->pad_fec_tdata0);
writel (outpadctl, &padctl->pad_fec_tdata0);
/* FEC_TX_EN */
writel (muxmode0, &muxctl->pad_fec_tx_en);
writel (outpadctl, &padctl->pad_fec_tx_en);
/* FEC_MDC */
writel (muxmode0, &muxctl->pad_fec_mdc);
writel (outpadctl, &padctl->pad_fec_mdc);
/* FEC_MDIO */
writel (muxmode0, &muxctl->pad_fec_mdio);
writel (inpadctl_22kpu, &padctl->pad_fec_mdio);
/* FEC_RDATA1 */
writel (muxmode0, &muxctl->pad_fec_rdata1);
writel (inpadctl_100kpd, &padctl->pad_fec_rdata1);
/* FEC_TDATA1 */
writel (muxmode0, &muxctl->pad_fec_tdata1);
writel (outpadctl, &padctl->pad_fec_tdata1);
}
#endif /* CONFIG_FEC_MXC */

56
cpu/arm926ejs/mx25/reset.c Normal file
View file

@ -0,0 +1,56 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
/*
* Reset the cpu by setting up the watchdog timer and let it time out
*/
void reset_cpu (ulong ignored)
{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */
writel (0x00000000, &regs->wcr);
/* Write Service Sequence */
writel (0x00005555, &regs->wsr);
writel (0x0000AAAA, &regs->wsr);
/* Enable watchdog */
writel (WCR_WDE, &regs->wcr);
while (1) ;
}

187
cpu/arm926ejs/mx25/timer.c Normal file
View file

@ -0,0 +1,187 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
*
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
* Add support for MX25
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <div64.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
static ulong timestamp;
static ulong lastinc;
/*
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
* "tick" is internal timer period
*/
#ifdef CONFIG_MX25_TIMER_HIGH_PRECISION
/* ~0.4% error - measured with stop-watch on 100s boot-delay */
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, CONFIG_MX25_CLK32);
return tick;
}
static inline unsigned long long time_to_tick(unsigned long long time)
{
time *= CONFIG_MX25_CLK32;
do_div(time, CONFIG_SYS_HZ);
return time;
}
static inline unsigned long long us_to_tick(unsigned long long us)
{
us = us * CONFIG_MX25_CLK32 + 999999;
do_div(us, 1000000);
return us;
}
#else
/* ~2% error */
#define TICK_PER_TIME ((CONFIG_MX25_CLK32 + CONFIG_SYS_HZ / 2) / \
CONFIG_SYS_HZ)
#define US_PER_TICK (1000000 / CONFIG_MX25_CLK32)
static inline unsigned long long tick_to_time(unsigned long long tick)
{
do_div(tick, TICK_PER_TIME);
return tick;
}
static inline unsigned long long time_to_tick(unsigned long long time)
{
return time * TICK_PER_TIME;
}
static inline unsigned long long us_to_tick(unsigned long long us)
{
us += US_PER_TICK - 1;
do_div(us, US_PER_TICK);
return us;
}
#endif
/* nothing really to do with interrupts, just starts up a counter. */
/* The 32KHz 32-bit timer overruns in 134217 seconds */
int timer_init(void)
{
int i;
struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
/* setup GP Timer 1 */
writel(GPT_CTRL_SWR, &gpt->ctrl);
writel(readl(&ccm->cgr1) | CCM_CGR1_GPT1, &ccm->cgr1);
for (i = 0; i < 100; i++)
writel(0, &gpt->ctrl); /* We have no udelay by now */
writel(0, &gpt->pre); /* prescaler = 1 */
/* Freerun Mode, 32KHz input */
writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR,
&gpt->ctrl);
writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl);
return 0;
}
void reset_timer_masked(void)
{
struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
/* reset time */
/* capture current incrementer value time */
lastinc = readl(&gpt->counter);
timestamp = 0; /* start "advancing" time stamp from 0 */
}
void reset_timer(void)
{
reset_timer_masked();
}
unsigned long long get_ticks (void)
{
struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
ulong now = readl(&gpt->counter); /* current tick value */
if (now >= lastinc) {
/*
* normal mode (non roll)
* move stamp forward with absolut diff ticks
*/
timestamp += (now - lastinc);
} else {
/* we have rollover of incrementer */
timestamp += (0xFFFFFFFF - lastinc) + now;
}
lastinc = now;
return timestamp;
}
ulong get_timer_masked (void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
* 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
return tick_to_time(get_ticks());
}
ulong get_timer (ulong base)
{
return get_timer_masked () - base;
}
void set_timer (ulong t)
{
timestamp = time_to_tick(t);
}
/* delay x useconds AND preserve advance timstamp value */
void __udelay (unsigned long usec)
{
unsigned long long tmp;
ulong tmo;
tmo = us_to_tick(usec);
tmp = get_ticks() + tmo; /* get current timestamp */
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
}

5
cpu/arm926ejs/mx27/generic.c
View file

@ -166,6 +166,11 @@ int print_cpuinfo (void)
int cpu_eth_init(bd_t *bis)
{
#if defined(CONFIG_FEC_MXC)
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
/* enable FEC clock */
writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
return fecmxc_initialize(bis);
#else
return 0;

42
cpu/arm926ejs/start.S
View file

@ -53,6 +53,27 @@
.globl _start
_start:
b reset
#ifdef CONFIG_PRELOADER
/* No exception handlers in preloader */
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
_hang:
.word do_hang
/* pad to 64 byte boundary */
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
#else
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
@ -76,6 +97,7 @@ _irq:
_fiq:
.word fiq
#endif /* CONFIG_PRELOADER */
.balignl 16,0xdeadbeef
@ -150,7 +172,6 @@ relocate: /* relocate U-Boot to RAM */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
@ -166,11 +187,14 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub sp, r0, #128 /* leave 32 words for abort-stack */
#ifndef CONFIG_PRELOADER
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
#endif /* CONFIG_PRELOADER */
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, r0, #7 /* 8-byte align stack for ABI compliance */
@ -179,6 +203,7 @@ clear_bss:
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
#ifndef CONFIG_PRELOADER
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
@ -186,11 +211,16 @@ clbss_l:str r2, [r0] /* clear loop... */
bl coloured_LED_init
bl red_LED_on
#endif /* CONFIG_PRELOADER */
ldr pc, _start_armboot
_start_armboot:
#ifdef CONFIG_NAND_SPL
.word nand_boot
#else
.word start_armboot
#endif /* CONFIG_NAND_SPL */
/*
@ -231,6 +261,7 @@ cpu_init_crit:
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#ifndef CONFIG_PRELOADER
/*
*************************************************************************
*
@ -332,10 +363,18 @@ cpu_init_crit:
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
#endif /* CONFIG_PRELOADER */
/*
* exception handlers
*/
#ifdef CONFIG_PRELOADER
.align 5
do_hang:
ldr sp, _TEXT_BASE /* switch to abort stack */
1:
bl 1b /* hang and never return */
#else /* !CONFIG_PRELOADER */
.align 5
undefined_instruction:
get_bad_stack
@ -398,3 +437,4 @@ fiq:
bl do_fiq
#endif
#endif /* CONFIG_PRELOADER */

48
cpu/arm_cortexa8/mx51/Makefile Normal file
View file

@ -0,0 +1,48 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2009 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
COBJS = soc.o clock.o iomux.o timer.o speed.o
SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

294
cpu/arm_cortexa8/mx51/clock.c Normal file
View file

@ -0,0 +1,294 @@
/*
* (C) Copyright 2007
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
enum pll_clocks {
PLL1_CLOCK = 0,
PLL2_CLOCK,
PLL3_CLOCK,
PLL_CLOCKS,
};
struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
[PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
[PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
[PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
};
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
/*
* Calculate the frequency of this pll.
*/
static u32 decode_pll(struct mxc_pll_reg *pll, u32 infreq)
{
u32 mfi, mfn, mfd, pd;
mfn = __raw_readl(&pll->mfn);
mfd = __raw_readl(&pll->mfd) + 1;
mfi = __raw_readl(&pll->op);
pd = (mfi & 0xF) + 1;
mfi = (mfi >> 4) & 0xF;
mfi = (mfi >= 5) ? mfi : 5;
return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
}
/*
* Get mcu main rate
*/
u32 get_mcu_main_clk(void)
{
u32 reg, freq;
reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
MXC_CCM_CACRR_ARM_PODF_OFFSET;
freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
return freq / (reg + 1);
}
/*
* Get the rate of peripheral's root clock.
*/
static u32 get_periph_clk(void)
{
u32 reg;
reg = __raw_readl(&mxc_ccm->cbcdr);
if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
reg = __raw_readl(&mxc_ccm->cbcmr);
switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
case 0:
return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
case 1:
return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
default:
return 0;
}
/* NOTREACHED */
}
/*
* Get the rate of ipg clock.
*/
static u32 get_ipg_clk(void)
{
u32 ahb_podf, ipg_podf;
ahb_podf = __raw_readl(&mxc_ccm->cbcdr);
ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
MXC_CCM_CBCDR_IPG_PODF_OFFSET;
ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
MXC_CCM_CBCDR_AHB_PODF_OFFSET;
return get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
}
/*
* Get the rate of ipg_per clock.
*/
static u32 get_ipg_per_clk(void)
{
u32 pred1, pred2, podf;
if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
return get_ipg_clk();
/* Fixme: not handle what about lpm*/
podf = __raw_readl(&mxc_ccm->cbcdr);
pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
}
/*
* Get the rate of uart clk.
*/
static u32 get_uart_clk(void)
{
unsigned int freq, reg, pred, podf;
reg = __raw_readl(&mxc_ccm->cscmr1);
switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
case 0x0:
freq = decode_pll(mxc_plls[PLL1_CLOCK],
CONFIG_MX51_HCLK_FREQ);
break;
case 0x1:
freq = decode_pll(mxc_plls[PLL2_CLOCK],
CONFIG_MX51_HCLK_FREQ);
break;
case 0x2:
freq = decode_pll(mxc_plls[PLL3_CLOCK],
CONFIG_MX51_HCLK_FREQ);
break;
default:
return 66500000;
}
reg = __raw_readl(&mxc_ccm->cscdr1);
pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
freq /= (pred + 1) * (podf + 1);
return freq;
}
/*
* This function returns the low power audio clock.
*/
u32 get_lp_apm(void)
{
u32 ret_val = 0;
u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
if (((ccsr >> 9) & 1) == 0)
ret_val = CONFIG_MX51_HCLK_FREQ;
else
ret_val = ((32768 * 1024));
return ret_val;
}
/*
* get cspi clock rate.
*/
u32 imx_get_cspiclk(void)
{
u32 ret_val = 0, pdf, pre_pdf, clk_sel;
u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
>> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
>> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
>> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
switch (clk_sel) {
case 0:
ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
CONFIG_MX51_HCLK_FREQ) /
((pre_pdf + 1) * (pdf + 1));
break;
case 1:
ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
CONFIG_MX51_HCLK_FREQ) /
((pre_pdf + 1) * (pdf + 1));
break;
case 2:
ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
CONFIG_MX51_HCLK_FREQ) /
((pre_pdf + 1) * (pdf + 1));
break;
default:
ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
break;
}
return ret_val;
}
/*
* The API of get mxc clockes.
*/
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
case MXC_ARM_CLK:
return get_mcu_main_clk();
case MXC_AHB_CLK:
break;
case MXC_IPG_CLK:
return get_ipg_clk();
case MXC_IPG_PERCLK:
return get_ipg_per_clk();
case MXC_UART_CLK:
return get_uart_clk();
case MXC_CSPI_CLK:
return imx_get_cspiclk();
case MXC_FEC_CLK:
return decode_pll(mxc_plls[PLL1_CLOCK],
CONFIG_MX51_HCLK_FREQ);
default:
break;
}
return -1;
}
u32 imx_get_uartclk(void)
{
return get_uart_clk();
}
u32 imx_get_fecclk(void)
{
return mxc_get_clock(MXC_IPG_CLK);
}
/*
* Dump some core clockes.
*/
int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
u32 freq;
freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
printf("mx51 pll1: %dMHz\n", freq / 1000000);
freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
printf("mx51 pll2: %dMHz\n", freq / 1000000);
freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
printf("mx51 pll3: %dMHz\n", freq / 1000000);
printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
return 0;
}
/***************************************************/
U_BOOT_CMD(
clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx51_showclocks,
"display mx51 clocks\n",
""
);

166
cpu/arm_cortexa8/mx51/iomux.c Normal file
View file

@ -0,0 +1,166 @@
/*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx51_pins.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
/* IOMUX register (base) addresses */
enum iomux_reg_addr {
IOMUXGPR0 = IOMUXC_BASE_ADDR,
IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR,
};
#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
/* Get the iomux register address of this pin */
static inline u32 get_mux_reg(iomux_pin_name_t pin)
{
u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
if (is_soc_rev(CHIP_REV_2_0) < 0) {
/*
* Fixup register address:
* i.MX51 TO1 has offset with the register
* which is define as TO2.
*/
if ((pin == MX51_PIN_NANDF_RB5) ||
(pin == MX51_PIN_NANDF_RB6) ||
(pin == MX51_PIN_NANDF_RB7))
; /* Do nothing */
else if (mux_reg >= 0x2FC)
mux_reg += 8;
else if (mux_reg >= 0x130)
mux_reg += 0xC;
}
mux_reg += IOMUXSW_MUX_CTL;
return mux_reg;
}
/* Get the pad register address of this pin */
static inline u32 get_pad_reg(iomux_pin_name_t pin)
{
u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
if (is_soc_rev(CHIP_REV_2_0) < 0) {
/*
* Fixup register address:
* i.MX51 TO1 has offset with the register
* which is define as TO2.
*/
if ((pin == MX51_PIN_NANDF_RB5) ||
(pin == MX51_PIN_NANDF_RB6) ||
(pin == MX51_PIN_NANDF_RB7))
; /* Do nothing */
else if (pad_reg == 0x4D0 - PAD_I_START)
pad_reg += 0x4C;
else if (pad_reg == 0x860 - PAD_I_START)
pad_reg += 0x9C;
else if (pad_reg >= 0x804 - PAD_I_START)
pad_reg += 0xB0;
else if (pad_reg >= 0x7FC - PAD_I_START)
pad_reg += 0xB4;
else if (pad_reg >= 0x4E4 - PAD_I_START)
pad_reg += 0xCC;
else
pad_reg += 8;
}
pad_reg += IOMUXSW_PAD_CTL;
return pad_reg;
}
/* Get the last iomux register address */
static inline u32 get_mux_end(void)
{
if (is_soc_rev(CHIP_REV_2_0) < 0)
return IOMUXC_BASE_ADDR + (0x3F8 - 4);
else
return IOMUXC_BASE_ADDR + (0x3F0 - 4);
}
/*
* This function is used to configure a pin through the IOMUX module.
* @param pin a pin number as defined in iomux_pin_name_t
* @param cfg an output function as defined in iomux_pin_cfg_t
*
* @return 0 if successful; Non-zero otherwise
*/
static void iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
{
u32 mux_reg = get_mux_reg(pin);
if ((mux_reg > get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
return ;
if (cfg == IOMUX_CONFIG_GPIO)
writel(PIN_TO_ALT_GPIO(pin), mux_reg);
else
writel(cfg, mux_reg);
}
/*
* Request ownership for an IO pin. This function has to be the first one
* being called before that pin is used. The caller has to check the
* return value to make sure it returns 0.
*
* @param pin a name defined by iomux_pin_name_t
* @param cfg an input function as defined in iomux_pin_cfg_t
*
*/
void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
{
iomux_config_mux(pin, cfg);
}
/*
* Release ownership for an IO pin
*
* @param pin a name defined by iomux_pin_name_t
* @param cfg an input function as defined in iomux_pin_cfg_t
*/
void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
{
}
/*
* This function configures the pad value for a IOMUX pin.
*
* @param pin a pin number as defined in iomux_pin_name_t
* @param config the ORed value of elements defined in iomux_pad_config_t
*/
void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
{
u32 pad_reg = get_pad_reg(pin);
writel(config, pad_reg);
}
unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
{
u32 pad_reg = get_pad_reg(pin);
return readl(pad_reg);
}

288
cpu/arm_cortexa8/mx51/lowlevel_init.S Normal file
View file

@ -0,0 +1,288 @@
/*
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/asm-offsets.h>
/*
* L2CC Cache setup/invalidation/disable
*/
.macro init_l2cc
/* explicitly disable L2 cache */
mrc 15, 0, r0, c1, c0, 1
bic r0, r0, #0x2
mcr 15, 0, r0, c1, c0, 1
/* reconfigure L2 cache aux control reg */
mov r0, #0xC0 /* tag RAM */
add r0, r0, #0x4 /* data RAM */
orr r0, r0, #(1 << 24) /* disable write allocate delay */
orr r0, r0, #(1 << 23) /* disable write allocate combine */
orr r0, r0, #(1 << 22) /* disable write allocate */
cmp r3, #0x10 /* r3 contains the silicon rev */
/* disable write combine for TO 2 and lower revs */
orrls r0, r0, #(1 << 25)
mcr 15, 1, r0, c9, c0, 2
.endm /* init_l2cc */
/* AIPS setup - Only setup MPROTx registers.
* The PACR default values are good.*/
.macro init_aips
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
ldr r0, =AIPS1_BASE_ADDR
ldr r1, =0x77777777
str r1, [r0, #0x0]
str r1, [r0, #0x4]
ldr r0, =AIPS2_BASE_ADDR
str r1, [r0, #0x0]
str r1, [r0, #0x4]
/*
* Clear the on and off peripheral modules Supervisor Protect bit
* for SDMA to access them. Did not change the AIPS control registers
* (offset 0x20) access type
*/
.endm /* init_aips */
/* M4IF setup */
.macro init_m4if
/* VPU and IPU given higher priority (0x4)
* IPU accesses with ID=0x1 given highest priority (=0xA)
*/
ldr r0, =M4IF_BASE_ADDR
ldr r1, =0x00000203
str r1, [r0, #0x40]
ldr r1, =0x0
str r1, [r0, #0x44]
ldr r1, =0x00120125
str r1, [r0, #0x9C]
ldr r1, =0x001901A3
str r1, [r0, #0x48]
.endm /* init_m4if */
.macro setup_pll pll, freq
ldr r2, =\pll
ldr r1, =0x00001232
str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
mov r1, #0x2
str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
str r3, [r2, #PLL_DP_OP]
str r3, [r2, #PLL_DP_HFS_OP]
str r4, [r2, #PLL_DP_MFD]
str r4, [r2, #PLL_DP_HFS_MFD]
str r5, [r2, #PLL_DP_MFN]
str r5, [r2, #PLL_DP_HFS_MFN]
ldr r1, =0x00001232
str r1, [r2, #PLL_DP_CTL]
1: ldr r1, [r2, #PLL_DP_CTL]
ands r1, r1, #0x1
beq 1b
.endm
.macro init_clock
ldr r0, =CCM_BASE_ADDR
/* Gate of clocks to the peripherals first */
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
ldr r1, =0x0
str r1, [r0, #CLKCTL_CCGR1]
str r1, [r0, #CLKCTL_CCGR2]
str r1, [r0, #CLKCTL_CCGR3]
ldr r1, =0x00030000
str r1, [r0, #CLKCTL_CCGR4]
ldr r1, =0x00FFF030
str r1, [r0, #CLKCTL_CCGR5]
ldr r1, =0x00000300
str r1, [r0, #CLKCTL_CCGR6]
/* Disable IPU and HSC dividers */
mov r1, #0x60000
str r1, [r0, #CLKCTL_CCDR]
/* Make sure to switch the DDR away from PLL 1 */
ldr r1, =0x19239145
str r1, [r0, #CLKCTL_CBCDR]
/* make sure divider effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
/* Switch ARM to step clock */
mov r1, #0x4
str r1, [r0, #CLKCTL_CCSR]
mov r3, #DP_OP_800
mov r4, #DP_MFD_800
mov r5, #DP_MFN_800
setup_pll PLL1_BASE_ADDR
mov r3, #DP_OP_665
mov r4, #DP_MFD_665
mov r5, #DP_MFN_665
setup_pll PLL3_BASE_ADDR
/* Switch peripheral to PLL 3 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x000010C0
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x13239145
str r1, [r0, #CLKCTL_CBCDR]
mov r3, #DP_OP_665
mov r4, #DP_MFD_665
mov r5, #DP_MFN_665
setup_pll PLL2_BASE_ADDR
/* Switch peripheral to PLL2 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x19239145
str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x000020C0
str r1, [r0, #CLKCTL_CBCMR]
mov r3, #DP_OP_216
mov r4, #DP_MFD_216
mov r5, #DP_MFN_216
setup_pll PLL3_BASE_ADDR
/* Set the platform clock dividers */
ldr r0, =ARM_BASE_ADDR
ldr r1, =0x00000725
str r1, [r0, #0x14]
ldr r0, =CCM_BASE_ADDR
/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
ldr r1, =0x0
ldr r3, [r1, #ROM_SI_REV]
cmp r3, #0x10
movls r1, #0x1
movhi r1, #0
str r1, [r0, #CLKCTL_CACRR]
/* Switch ARM back to PLL 1 */
mov r1, #0
str r1, [r0, #CLKCTL_CCSR]
/* setup the rest */
/* Use lp_apm (24MHz) source for perclk */
ldr r1, =0x000020C2
str r1, [r0, #CLKCTL_CBCMR]
/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
ldr r1, =0x59E35100
str r1, [r0, #CLKCTL_CBCDR]
/* Restore the default values in the Gate registers */
ldr r1, =0xFFFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
str r1, [r0, #CLKCTL_CCGR1]
str r1, [r0, #CLKCTL_CCGR2]
str r1, [r0, #CLKCTL_CCGR3]
str r1, [r0, #CLKCTL_CCGR4]
str r1, [r0, #CLKCTL_CCGR5]
str r1, [r0, #CLKCTL_CCGR6]
/* Use PLL 2 for UART's, get 66.5MHz from it */
ldr r1, =0xA5A2A020
str r1, [r0, #CLKCTL_CSCMR1]
ldr r1, =0x00C30321
str r1, [r0, #CLKCTL_CSCDR1]
/* make sure divider effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
mov r1, #0x0
str r1, [r0, #CLKCTL_CCDR]
/* for cko - for ARM div by 8 */
mov r1, #0x000A0000
add r1, r1, #0x00000F0
str r1, [r0, #CLKCTL_CCOSR]
.endm
.macro setup_wdog
ldr r0, =WDOG1_BASE_ADDR
mov r1, #0x30
strh r1, [r0]
.endm
.section ".text.init", "x"
.globl lowlevel_init
lowlevel_init:
ldr r0, =GPIO1_BASE_ADDR
ldr r1, [r0, #0x0]
orr r1, r1, #(1 << 23)
str r1, [r0, #0x0]
ldr r1, [r0, #0x4]
orr r1, r1, #(1 << 23)
str r1, [r0, #0x4]
#ifdef ENABLE_IMPRECISE_ABORT
mrs r1, spsr /* save old spsr */
mrs r0, cpsr /* read out the cpsr */
bic r0, r0, #0x100 /* clear the A bit */
msr spsr, r0 /* update spsr */
add lr, pc, #0x8 /* update lr */
movs pc, lr /* update cpsr */
nop
nop
nop
nop
msr spsr, r1 /* restore old spsr */
#endif
init_l2cc
init_aips
init_m4if
init_clock
/* r12 saved upper lr*/
mov pc,lr
/* Board level setting value */
DDR_PERCHARGE_CMD: .word 0x04008008
DDR_REFRESH_CMD: .word 0x00008010
DDR_LMR1_W: .word 0x00338018
DDR_LMR_CMD: .word 0xB2220000
DDR_TIMING_W: .word 0xB02567A9
DDR_MISC_W: .word 0x000A0104

114
cpu/arm_cortexa8/mx51/soc.c Normal file
View file

@ -0,0 +1,114 @@
/*
* (C) Copyright 2007
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/errno.h>
#include <asm/io.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
u32 get_cpu_rev(void)
{
int reg;
int system_rev;
reg = __raw_readl(ROM_SI_REV);
switch (reg) {
case 0x02:
system_rev = 0x51000 | CHIP_REV_1_1;
break;
case 0x10:
if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
system_rev = 0x51000 | CHIP_REV_2_5;
else
system_rev = 0x51000 | CHIP_REV_2_0;
break;
case 0x20:
system_rev = 0x51000 | CHIP_REV_3_0;
break;
return system_rev;
default:
system_rev = 0x51000 | CHIP_REV_1_0;
break;
}
return system_rev;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
u32 cpurev;
cpurev = get_cpu_rev();
printf("CPU: Freescale i.MX51 family %d.%dV at %d MHz\n",
(cpurev & 0xF0) >> 4,
(cpurev & 0x0F) >> 4,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
return 0;
}
#endif
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
#if defined(CONFIG_FEC_MXC)
extern int fecmxc_initialize(bd_t *bis);
#endif
int cpu_eth_init(bd_t *bis)
{
int rc = -ENODEV;
#if defined(CONFIG_FEC_MXC)
rc = fecmxc_initialize(bis);
#endif
return rc;
}
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(bd_t *bis)
{
#ifdef CONFIG_FSL_ESDHC
return fsl_esdhc_mmc_init(bis);
#else
return 0;
#endif
}
void reset_cpu(ulong addr)
{
__raw_writew(4, WDOG1_BASE_ADDR);
}

41
board/exbitgen/exbitgen.h → cpu/arm_cortexa8/mx51/speed.c
View file

@ -1,7 +1,10 @@
/*
* (C) Copyright 2003
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -21,32 +24,16 @@
* MA 02111-1307 USA
*/
#define GPIO_CPU_LED GPIO_3
#include <common.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
int get_clocks(void)
{
DECLARE_GLOBAL_DATA_PTR;
#define CPLD_BASE 0x10000000 /* t.b.m. */
#define DEBUG_LEDS_ADDR CPLD_BASE + 0x01
#define HW_ID_ADDR CPLD_BASE + 0x02
#define DIP_SWITCH_ADDR CPLD_BASE + 0x04
#define PHY_CTRL_ADDR CPLD_BASE + 0x05
#define SPI_OUT_ADDR CPLD_BASE + 0x07
#define SPI_IN_ADDR CPLD_BASE + 0x08
#define MDIO_OUT_ADDR CPLD_BASE + 0x09
#define MDIO_IN_ADDR CPLD_BASE + 0x0A
#define MISC_OUT_ADDR CPLD_BASE + 0x0B
/* Addresses used on I2C bus */
#define LM75_CHIP_ADDR 0x9C
#define LM75_CPU_ADDR 0x9E
#define SDRAM_SPD_ADDR 0xA0
#define SDRAM_SPD_WRITE_ADDRESS (SDRAM_SPD_ADDR)
#define SDRAM_SPD_READ_ADDRESS (SDRAM_SPD_ADDR+1)
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE 1
#ifdef CONFIG_FSL_ESDHC
gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
#endif
return 0;
}

119
cpu/arm_cortexa8/mx51/timer.c Normal file
View file

@ -0,0 +1,119 @@
/*
* (C) Copyright 2007
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
/* General purpose timers registers */
struct mxc_gpt {
unsigned int control;
unsigned int prescaler;
unsigned int status;
unsigned int nouse[6];
unsigned int counter;
};
static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
/* General purpose timers bitfields */
#define GPTCR_SWR (1<<15) /* Software reset */
#define GPTCR_FRR (1<<9) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
#define GPTCR_TEN (1) /* Timer enable */
static ulong timestamp;
static ulong lastinc;
int timer_init(void)
{
int i;
/* setup GP Timer 1 */
__raw_writel(GPTCR_SWR, &cur_gpt->control);
/* We have no udelay by now */
for (i = 0; i < 100; i++)
__raw_writel(0, &cur_gpt->control);
__raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
/* Freerun Mode, PERCLK1 input */
i = __raw_readl(&cur_gpt->control);
__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
reset_timer_masked();
return 0;
}
void reset_timer(void)
{
reset_timer_masked();
}
void reset_timer_masked(void)
{
ulong val = __raw_readl(&cur_gpt->counter);
lastinc = val / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
timestamp = 0;
}
ulong get_timer_masked(void)
{
ulong val = __raw_readl(&cur_gpt->counter);
val /= (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
if (val >= lastinc)
timestamp += (val - lastinc);
else
timestamp += ((0xFFFFFFFF / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ))
- lastinc) + val;
lastinc = val;
return val;
}
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
void set_timer(ulong t)
{
timestamp = t;
}
/* delay x useconds AND perserve advance timstamp value */
void __udelay(unsigned long usec)
{
unsigned long now, start, tmo;
tmo = usec * (CONFIG_MX51_CLK32 / 1000) / 1000;
if (!tmo)
tmo = 1;
now = start = readl(&cur_gpt->counter);
while ((now - start) < tmo)
now = readl(&cur_gpt->counter);
}

26
board/netstar/eeprom.lds → cpu/arm_cortexa8/mx51/u-boot.lds
View file

@ -1,8 +1,11 @@
/*
* January 2004 - Changed to support H4 device
* Copyright (c) 2004 Texas Instruments
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
* (C) Copyright 2005
* Ladislav Michl, 2N Telekomunikace, <michl@2n.cz>
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -14,7 +17,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -28,15 +31,17 @@ OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
.text :
{
eeprom_start.o (.text)
cpu/arm_cortexa8/start.o
*(.text)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
@ -44,8 +49,13 @@ SECTIONS
. = ALIGN(4);
.got : { *(.got) }
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
.bss : { *(.bss) }
_end = .;
}

6
cpu/arm_cortexa8/omap3/board.c
View file

@ -146,6 +146,12 @@ void setup_auxcr()
__asm__ __volatile__("orr r0, r0, #1 << 5");
/* SMI instruction to call ROM Code API */
__asm__ __volatile__(".word 0xE1600070");
/* Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround) */
__asm__ __volatile__("mov r12, #0x2");
__asm__ __volatile__("mrc p15, 1, r0, c9, c0, 2");
__asm__ __volatile__("orr r0, r0, #1 << 27");
/* SMI instruction to call ROM Code API */
__asm__ __volatile__(".word 0xE1600070");
__asm__ __volatile__("mov r0, %0":"=r"(i));
__asm__ __volatile__("mov r12, %0":"=r"(j));
}

20
cpu/arm_cortexa8/omap3/clock.c
View file

@ -40,7 +40,7 @@
*****************************************************************************/
u32 get_osc_clk_speed(void)
{
u32 start, cstart, cend, cdiff, val;
u32 start, cstart, cend, cdiff, cdiv, val;
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
struct prm *prm_base = (struct prm *)PRM_BASE;
struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
@ -48,9 +48,15 @@ u32 get_osc_clk_speed(void)
val = readl(&prm_base->clksrc_ctrl);
/* If SYS_CLK is being divided by 2, remove for now */
val = (val & (~SYSCLKDIV_2)) | SYSCLKDIV_1;
writel(val, &prm_base->clksrc_ctrl);
if (val & SYSCLKDIV_2)
cdiv = 2;
else if (val & SYSCLKDIV_1)
cdiv = 1;
else
/*
* Should never reach here! (Assume divider as 1)
*/
cdiv = 1;
/* enable timer2 */
val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
@ -61,6 +67,7 @@ u32 get_osc_clk_speed(void)
/* Enable I and F Clocks for GPT1 */
val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
writel(val, &prcm_base->iclken_wkup);
val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
writel(val, &prcm_base->fclken_wkup);
@ -83,6 +90,11 @@ u32 get_osc_clk_speed(void)
cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
cdiff = cend - cstart; /* get elapsed ticks */
if (cdiv == 2)
{
cdiff *= 2;
}
/* based on number of ticks assign speed */
if (cdiff > 19000)
return S38_4M;

6
cpu/mcf52x2/cpu.c
View file

@ -33,6 +33,7 @@
#include <command.h>
#include <asm/immap.h>
#include <netdev.h>
#include "cpu.h"
DECLARE_GLOBAL_DATA_PTR;
@ -143,6 +144,11 @@ int checkcpu(void)
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
/* Call the board specific reset actions first. */
if(board_reset) {
board_reset();
}
mbar_writeByte(MCF_RCM_RCR,
MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
return 0;

33
cpu/mcf52x2/cpu.h Normal file
View file

@ -0,0 +1,33 @@
/*
* cpu.h
*
* Copyright (c) 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _CPU_H_
#define _CPU_H_
#include <command.h>
/* Use this to create board specific reset functions */
void board_reset(void) __attribute__((__weak__));
#endif /* _CPU_H_ */

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