Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-28 23:51:33 +00:00
Code Issues Projects Releases Packages Wiki Activity

Merge with /home/wd/git/u-boot/custodian/u-boot-testing

Browse source
This commit is contained in:
Wolfgang Denk 2007-07-03 15:07:56 +02:00
commit 98c440bee6
39 changed files with 1294 additions and 179 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
MAKEALL
View file

@ -150,6 +150,14 @@ LIST_85xx=" \
TQM8560 \ TQM8560 \
" "
#########################################################################
## MPC86xx Systems
#########################################################################
LIST_86xx=" \
MPC8641HPCN \
"
######################################################################### #########################################################################
## 74xx/7xx Systems ## 74xx/7xx Systems
######################################################################### #########################################################################
@ -170,6 +178,7 @@ LIST_ppc="${LIST_5xx} ${LIST_5xxx} \
${LIST_8220} ${LIST_824x} ${LIST_8260} \ ${LIST_8220} ${LIST_824x} ${LIST_8260} \
${LIST_83xx} \ ${LIST_83xx} \
${LIST_85xx} \ ${LIST_85xx} \
${LIST_86xx} \
${LIST_4xx} \ ${LIST_4xx} \
${LIST_74xx} ${LIST_7xx}" ${LIST_74xx} ${LIST_7xx}"
@ -356,7 +365,7 @@ do
microblaze| \ microblaze| \
mips|mips_el| \ mips|mips_el| \
nios|nios2| \ nios|nios2| \
ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \ ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \
x86|I486) x86|I486)
for target in `eval echo '$LIST_'${arg}` for target in `eval echo '$LIST_'${arg}`
do do

10
board/cds/mpc8548cds/mpc8548cds.c
View file

@ -345,23 +345,23 @@ int last_stage_init(void)
/* This is needed to get the RGMII working for the 1.3+ /* This is needed to get the RGMII working for the 1.3+
* CDS cards */ * CDS cards */
if (get_board_version() == 0x13) { if (get_board_version() == 0x13) {
miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, miiphy_write(CONFIG_TSEC1_NAME,
TSEC1_PHY_ADDR, 29, 18); TSEC1_PHY_ADDR, 29, 18);
miiphy_read(CONFIG_MPC85XX_TSEC1_NAME, miiphy_read(CONFIG_TSEC1_NAME,
TSEC1_PHY_ADDR, 30, &temp); TSEC1_PHY_ADDR, 30, &temp);
temp = (temp & 0xf03f); temp = (temp & 0xf03f);
temp |= 2 << 9; /* 36 ohm */ temp |= 2 << 9; /* 36 ohm */
temp |= 2 << 6; /* 39 ohm */ temp |= 2 << 6; /* 39 ohm */
miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, miiphy_write(CONFIG_TSEC1_NAME,
TSEC1_PHY_ADDR, 30, temp); TSEC1_PHY_ADDR, 30, temp);
miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, miiphy_write(CONFIG_TSEC1_NAME,
TSEC1_PHY_ADDR, 29, 3); TSEC1_PHY_ADDR, 29, 3);
miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, miiphy_write(CONFIG_TSEC1_NAME,
TSEC1_PHY_ADDR, 30, 0x8000); TSEC1_PHY_ADDR, 30, 0x8000);
} }

4
common/Makefile
View file

@ -38,8 +38,8 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \
cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \ cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
cmd_nand.o cmd_net.o cmd_nvedit.o \ cmd_nand.o cmd_net.o cmd_nvedit.o \
cmd_pci.o cmd_pcmcia.o cmd_portio.o \ cmd_pci.o cmd_pcmcia.o cmd_portio.o \
cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o \ cmd_reginfo.o cmd_reiser.o cmd_sata.o cmd_scsi.o cmd_spi.o \
cmd_usb.o cmd_vfd.o \ cmd_universe.o cmd_usb.o cmd_vfd.o \
command.o console.o cyclon2.o devices.o dlmalloc.o docecc.o \ command.o console.o cyclon2.o devices.o dlmalloc.o docecc.o \
environment.o env_common.o \ environment.o env_common.o \
env_nand.o env_dataflash.o env_flash.o env_eeprom.o \ env_nand.o env_dataflash.o env_flash.o env_eeprom.o \

712
common/cmd_sata.c Normal file
View file

@ -0,0 +1,712 @@
/*
* Copyright (C) Procsys. All rights reserved.
* Author: Mushtaq Khan <mushtaq_k@procsys.com>
* <mushtaqk_921@yahoo.co.in>
*
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* with the reference to libata in kernel 2.4.32
*
*/
/*
* File contains SATA read-write and other utility functions.
*/
#include <common.h>
#include <asm/io.h>
#include <pci.h>
#include <command.h>
#include <config.h>
#include <ide.h>
#include <ata.h>
#ifdef CFG_SATA_SUPPORTED
/*For debug prints set macro DEBUG_SATA to 1 */
#define DEBUG_SATA 0
/*Macro for SATA library specific declarations */
#define SATA_DECL
#include <sata.h>
#undef SATA_DECL
static u8 __inline__
sata_inb (unsigned long ioaddr)
{
return inb (ioaddr);
}
static void __inline__
sata_outb (unsigned char val, unsigned long ioaddr)
{
outb (val, ioaddr);
}
static void
output_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
{
outsw (ioaddr->data_addr, sect_buf, words << 1);
}
static int
input_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
{
insw (ioaddr->data_addr, sect_buf, words << 1);
return 0;
}
static void
sata_cpy (unsigned char *dst, unsigned char *src, unsigned int len)
{
unsigned char *end, *last;
last = dst;
end = src + len - 1;
/* reserve space for '\0' */
if (len < 2)
goto OUT;
/* skip leading white space */
while ((*src) && (src < end) && (*src == ' '))
++src;
/* copy string, omitting trailing white space */
while ((*src) && (src < end)) {
*dst++ = *src;
if (*src++ != ' ')
last = dst;
}
OUT:
*last = '\0';
}
int
sata_bus_softreset (int num)
{
u8 dev = 0, status = 0, i;
port[num].dev_mask = 0;
for (i = 0; i < CFG_SATA_DEVS_PER_BUS; i++) {
if (!(sata_devchk (&port[num].ioaddr, i))) {
PRINTF ("dev_chk failed for dev#%d\n", i);
} else {
port[num].dev_mask |= (1 << i);
PRINTF ("dev_chk passed for dev#%d\n", i);
}
}
if (!(port[num].dev_mask)) {
printf ("no devices on port%d\n", num);
return 1;
}
dev_select (&port[num].ioaddr, dev);
port[num].ctl_reg = 0x08; /*Default value of control reg */
sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
udelay (10);
sata_outb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
udelay (10);
sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
/* spec mandates ">= 2ms" before checking status.
* We wait 150ms, because that was the magic delay used for
* ATAPI devices in Hale Landis's ATADRVR, for the period of time
* between when the ATA command register is written, and then
* status is checked. Because waiting for "a while" before
* checking status is fine, post SRST, we perform this magic
* delay here as well.
*/
msleep (150);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300);
while ((status & ATA_BUSY)) {
msleep (100);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3);
}
if (status & ATA_BUSY)
printf ("ata%u is slow to respond,plz be patient\n", port);
while ((status & ATA_BUSY)) {
msleep (100);
status = sata_chk_status (&port[num].ioaddr);
}
if (status & ATA_BUSY) {
printf ("ata%u failed to respond : ", port);
printf ("bus reset failed\n");
return 1;
}
return 0;
}
void
sata_identify (int num, int dev)
{
u8 cmd = 0, status = 0, devno = num * CFG_SATA_DEVS_PER_BUS + dev;
u16 iobuf[ATA_SECT_SIZE];
u64 n_sectors = 0;
u8 mask = 0;
memset (iobuf, 0, sizeof (iobuf));
hd_driveid_t *iop = (hd_driveid_t *) iobuf;
if (dev == 0)
mask = 0x01;
else
mask = 0x02;
if (!(port[num].dev_mask & mask)) {
printf ("dev%d is not present on port#%d\n", dev, num);
return;
}
printf ("port=%d dev=%d\n", num, dev);
dev_select (&port[num].ioaddr, dev);
status = 0;
cmd = ATA_CMD_IDENT; /*Device Identify Command */
sata_outb (cmd, port[num].ioaddr.command_addr);
sata_inb (port[num].ioaddr.altstatus_addr);
udelay (10);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000);
if (status & ATA_ERR) {
printf ("\ndevice not responding\n");
port[num].dev_mask &= ~mask;
return;
}
input_data (&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS);
PRINTF ("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
"86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49],
iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86],
iobuf[87], iobuf[88]);
/* we require LBA and DMA support (bits 8 & 9 of word 49) */
if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
PRINTF ("ata%u: no dma/lba\n", num);
}
ata_dump_id (iobuf);
if (ata_id_has_lba48 (iobuf)) {
n_sectors = ata_id_u64 (iobuf, 100);
} else {
n_sectors = ata_id_u32 (iobuf, 60);
}
PRINTF ("no. of sectors %u\n", ata_id_u64 (iobuf, 100));
PRINTF ("no. of sectors %u\n", ata_id_u32 (iobuf, 60));
if (n_sectors == 0) {
port[num].dev_mask &= ~mask;
return;
}
sata_cpy (sata_dev_desc[devno].revision, iop->fw_rev,
sizeof (sata_dev_desc[devno].revision));
sata_cpy (sata_dev_desc[devno].vendor, iop->model,
sizeof (sata_dev_desc[devno].vendor));
sata_cpy (sata_dev_desc[devno].product, iop->serial_no,
sizeof (sata_dev_desc[devno].product));
strswab (sata_dev_desc[devno].revision);
strswab (sata_dev_desc[devno].vendor);
if ((iop->config & 0x0080) == 0x0080) {
sata_dev_desc[devno].removable = 1;
} else {
sata_dev_desc[devno].removable = 0;
}
sata_dev_desc[devno].lba = iop->lba_capacity;
PRINTF ("lba=0x%x", sata_dev_desc[devno].lba);
#ifdef CONFIG_LBA48
if (iop->command_set_2 & 0x0400) {
sata_dev_desc[devno].lba48 = 1;
lba = (unsigned long long) iop->lba48_capacity[0] |
((unsigned long long) iop->lba48_capacity[1] << 16) |
((unsigned long long) iop->lba48_capacity[2] << 32) |
((unsigned long long) iop->lba48_capacity[3] << 48);
} else {
sata_dev_desc[devno].lba48 = 0;
}
#endif
/* assuming HD */
sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
sata_dev_desc[devno].blksz = ATA_BLOCKSIZE;
sata_dev_desc[devno].lun = 0; /* just to fill something in... */
}
void
set_Feature_cmd (int num, int dev)
{
u8 mask = 0x00, status = 0;
if (dev == 0)
mask = 0x01;
else
mask = 0x02;
if (!(port[num].dev_mask & mask)) {
PRINTF ("dev%d is not present on port#%d\n", dev, num);
return;
}
dev_select (&port[num].ioaddr, dev);
sata_outb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
sata_outb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
sata_outb (0, port[num].ioaddr.lbal_addr);
sata_outb (0, port[num].ioaddr.lbam_addr);
sata_outb (0, port[num].ioaddr.lbah_addr);
sata_outb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_SETF, port[num].ioaddr.command_addr);
udelay (50);
msleep (150);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000);
if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) {
printf ("Error : status 0x%02x\n", status);
port[num].dev_mask &= ~mask;
}
}
void
sata_port (struct sata_ioports *ioport)
{
ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
}
int
sata_devchk (struct sata_ioports *ioaddr, int dev)
{
u8 nsect, lbal;
dev_select (ioaddr, dev);
sata_outb (0x55, ioaddr->nsect_addr);
sata_outb (0xaa, ioaddr->lbal_addr);
sata_outb (0xaa, ioaddr->nsect_addr);
sata_outb (0x55, ioaddr->lbal_addr);
sata_outb (0x55, ioaddr->nsect_addr);
sata_outb (0xaa, ioaddr->lbal_addr);
nsect = sata_inb (ioaddr->nsect_addr);
lbal = sata_inb (ioaddr->lbal_addr);
if ((nsect == 0x55) && (lbal == 0xaa))
return 1; /* we found a device */
else
return 0; /* nothing found */
}
void
dev_select (struct sata_ioports *ioaddr, int dev)
{
u8 tmp = 0;
if (dev == 0)
tmp = ATA_DEVICE_OBS;
else
tmp = ATA_DEVICE_OBS | ATA_DEV1;
sata_outb (tmp, ioaddr->device_addr);
sata_inb (ioaddr->altstatus_addr);
udelay (5);
}
u8
sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max)
{
u8 status;
do {
udelay (1000);
status = sata_chk_status (ioaddr);
max--;
} while ((status & bits) && (max > 0));
return status;
}
u8
sata_chk_status (struct sata_ioports * ioaddr)
{
return sata_inb (ioaddr->status_addr);
}
void
msleep (int count)
{
int i;
for (i = 0; i < count; i++)
udelay (1000);
}
ulong
sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buff)
{
ulong n = 0, *buffer = (ulong *)buff;
u8 dev = 0, num = 0, mask = 0, status = 0;
#ifdef CONFIG_LBA48
unsigned char lba48 = 0;
if (blknr & 0x0000fffff0000000) {
if (!sata_dev_desc[devno].lba48) {
printf ("Drive doesn't support 48-bit addressing\n");
return 0;
}
/* more than 28 bits used, use 48bit mode */
lba48 = 1;
}
#endif
/*Port Number */
num = device / CFG_SATA_DEVS_PER_BUS;
/*dev on the port */
if (device >= CFG_SATA_DEVS_PER_BUS)
dev = device - CFG_SATA_DEVS_PER_BUS;
else
dev = device;
if (dev == 0)
mask = 0x01;
else
mask = 0x02;
if (!(port[num].dev_mask & mask)) {
printf ("dev%d is not present on port#%d\n", dev, num);
return 0;
}
/* Select device */
dev_select (&port[num].ioaddr, dev);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
printf ("ata%u failed to respond\n", port[num].port_no);
return n;
}
while (blkcnt-- > 0) {
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
printf ("ata%u failed to respond\n", 0);
return n;
}
#ifdef CONFIG_LBA48
if (lba48) {
/* write high bits */
sata_outb (0, port[num].ioaddr.nsect_addr);
sata_outb ((blknr >> 24) & 0xFF,
port[num].ioaddr.lbal_addr);
sata_outb ((blknr >> 32) & 0xFF,
port[num].ioaddr.lbam_addr);
sata_outb ((blknr >> 40) & 0xFF,
port[num].ioaddr.lbah_addr);
}
#endif
sata_outb (1, port[num].ioaddr.nsect_addr);
sata_outb (((blknr) >> 0) & 0xFF,
port[num].ioaddr.lbal_addr);
sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
#ifdef CONFIG_LBA48
if (lba48) {
sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_READ_EXT,
port[num].ioaddr.command_addr);
} else
#endif
{
sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_READ,
port[num].ioaddr.command_addr);
}
msleep (50);
/*may take up to 4 sec */
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
!= ATA_STAT_DRQ) {
u8 err = 0;
printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
device, (ulong) blknr, status);
err = sata_inb (port[num].ioaddr.error_addr);
printf ("Error reg = 0x%x\n", err);
return (n);
}
input_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
sata_inb (port[num].ioaddr.altstatus_addr);
udelay (50);
++n;
++blknr;
buffer += ATA_SECTORWORDS;
}
return n;
}
ulong
sata_write (int device, ulong blknr,lbaint_t blkcnt, void * buff)
{
ulong n = 0, *buffer = (ulong *)buff;
unsigned char status = 0, num = 0, dev = 0, mask = 0;
#ifdef CONFIG_LBA48
unsigned char lba48 = 0;
if (blknr & 0x0000fffff0000000) {
if (!sata_dev_desc[devno].lba48) {
printf ("Drive doesn't support 48-bit addressing\n");
return 0;
}
/* more than 28 bits used, use 48bit mode */
lba48 = 1;
}
#endif
/*Port Number */
num = device / CFG_SATA_DEVS_PER_BUS;
/*dev on the Port */
if (device >= CFG_SATA_DEVS_PER_BUS)
dev = device - CFG_SATA_DEVS_PER_BUS;
else
dev = device;
if (dev == 0)
mask = 0x01;
else
mask = 0x02;
/* Select device */
dev_select (&port[num].ioaddr, dev);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
printf ("ata%u failed to respond\n", port[num].port_no);
return n;
}
while (blkcnt-- > 0) {
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
printf ("ata%u failed to respond\n",
port[num].port_no);
return n;
}
#ifdef CONFIG_LBA48
if (lba48) {
/* write high bits */
sata_outb (0, port[num].ioaddr.nsect_addr);
sata_outb ((blknr >> 24) & 0xFF,
port[num].ioaddr.lbal_addr);
sata_outb ((blknr >> 32) & 0xFF,
port[num].ioaddr.lbam_addr);
sata_outb ((blknr >> 40) & 0xFF,
port[num].ioaddr.lbah_addr);
}
#endif
sata_outb (1, port[num].ioaddr.nsect_addr);
sata_outb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
#ifdef CONFIG_LBA48
if (lba48) {
sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_WRITE_EXT,
port[num].ioaddr.command_addr);
} else
#endif
{
sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_WRITE,
port[num].ioaddr.command_addr);
}
msleep (50);
/*may take up to 4 sec */
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
!= ATA_STAT_DRQ) {
printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
device, (ulong) blknr, status);
return (n);
}
output_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
sata_inb (port[num].ioaddr.altstatus_addr);
udelay (50);
++n;
++blknr;
buffer += ATA_SECTORWORDS;
}
return n;
}
block_dev_desc_t *sata_get_dev (int dev);
block_dev_desc_t *
sata_get_dev (int dev)
{
return ((block_dev_desc_t *) & sata_dev_desc[dev]);
}
int
do_sata (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
switch (argc) {
case 0:
case 1:
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
case 2:
if (strncmp (argv[1], "init", 4) == 0) {
int rcode = 0;
rcode = init_sata ();
if (rcode)
printf ("Sata initialization Failed\n");
return rcode;
} else if (strncmp (argv[1], "inf", 3) == 0) {
int i;
putc ('\n');
for (i = 0; i < CFG_SATA_MAXDEVICES; ++i) {
/*List only known devices */
if (sata_dev_desc[i].type ==
DEV_TYPE_UNKNOWN)
continue;
printf ("sata dev %d: ", i);
dev_print (&sata_dev_desc[i]);
}
return 0;
}
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
case 3:
if (strcmp (argv[1], "dev") == 0) {
int dev = (int) simple_strtoul (argv[2], NULL, 10);
if (dev >= CFG_SATA_MAXDEVICES) {
printf ("\nSata dev %d not available\n",
dev);
return 1;
}
printf ("\nSATA dev %d: ", dev);
dev_print (&sata_dev_desc[dev]);
if (sata_dev_desc[dev].type == DEV_TYPE_UNKNOWN)
return 1;
curr_dev = dev;
return 0;
} else if (strcmp (argv[1], "part") == 0) {
int dev = (int) simple_strtoul (argv[2], NULL, 10);
if (dev >= CFG_SATA_MAXDEVICES) {
printf ("\nSata dev %d not available\n",
dev);
return 1;
}
PRINTF ("\nSATA dev %d: ", dev);
if (sata_dev_desc[dev].part_type !=
PART_TYPE_UNKNOWN) {
print_part (&sata_dev_desc[dev]);
} else {
printf ("\nSata dev %d partition type "
"unknown\n", dev);
return 1;
}
return 0;
}
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
default:
if (argc < 5) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
if (strcmp (argv[1], "read") == 0) {
ulong addr = simple_strtoul (argv[2], NULL, 16);
ulong cnt = simple_strtoul (argv[4], NULL, 16);
ulong n;
lbaint_t blk = simple_strtoul (argv[3], NULL, 16);
memset ((int *) addr, 0, cnt * 512);
printf ("\nSATA read: dev %d blk # %ld,"
"count %ld ... ", curr_dev, blk, cnt);
n = sata_read (curr_dev, blk, cnt, (ulong *) addr);
/* flush cache after read */
flush_cache (addr, cnt * 512);
printf ("%ld blocks read: %s\n", n,
(n == cnt) ? "OK" : "ERR");
if (n == cnt)
return 1;
else
return 0;
} else if (strcmp (argv[1], "write") == 0) {
ulong addr = simple_strtoul (argv[2], NULL, 16);
ulong cnt = simple_strtoul (argv[4], NULL, 16);
ulong n;
lbaint_t blk = simple_strtoul (argv[3], NULL, 16);
printf ("\nSata write: dev %d blk # %ld,"
"count %ld ... ", curr_dev, blk, cnt);
n = sata_write (curr_dev, blk, cnt, (ulong *) addr);
printf ("%ld blocks written: %s\n", n,
(n == cnt) ? "OK" : "ERR");
if (n == cnt)
return 1;
else
return 0;
} else {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
} /*End OF SWITCH */
}
U_BOOT_CMD (sata, 5, 1, do_sata,
"sata init\n"
"sata info\n"
"sata part device\n"
"sata dev device\n"
"sata read addr blk# cnt\n"
"sata write addr blk# cnt\n", "cmd for init,rw and dev-info\n");
#endif

2
cpu/i386/start.S
View file

@ -149,7 +149,7 @@ data_ok:
.progress3: .progress3:
/* clear bss section in ram, size must be 4-byte aligned */ /* clear bss section in ram, size must be 4-byte aligned */
movl $_i386boot_bss_start, %eax /* BSS start */ movl $_i386boot_bss_start, %edi /* MK_CHG BSS start */
movl $_i386boot_bss_size, %ecx /* BSS size */ movl $_i386boot_bss_size, %ecx /* BSS size */
movl %ecx, %eax movl %ecx, %eax
andl $3, %eax andl $3, %eax

8
cpu/mpc83xx/cpu.c
View file

@ -415,7 +415,7 @@ static const struct {
"clock-frequency", "clock-frequency",
fdt_set_busfreq fdt_set_busfreq
}, },
#ifdef CONFIG_MPC83XX_TSEC1 #ifdef CONFIG_TSEC1
{ "/" OF_SOC "/ethernet@24000, { "/" OF_SOC "/ethernet@24000,
"mac-address", "mac-address",
fdt_set_eth0 fdt_set_eth0
@ -425,7 +425,7 @@ static const struct {
fdt_set_eth0 fdt_set_eth0
}, },
#endif #endif
#ifdef CONFIG_MPC83XX_TSEC2 #ifdef CONFIG_TSEC2
{ "/" OF_SOC "/ethernet@25000, { "/" OF_SOC "/ethernet@25000,
"mac-address", "mac-address",
fdt_set_eth1 fdt_set_eth1
@ -525,7 +525,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
if (p != NULL) if (p != NULL)
*p = cpu_to_be32(clock); *p = cpu_to_be32(clock);
#ifdef CONFIG_MPC83XX_TSEC1 #ifdef CONFIG_TSEC1
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
if (p != NULL) if (p != NULL)
memcpy(p, bd->bi_enetaddr, 6); memcpy(p, bd->bi_enetaddr, 6);
@ -535,7 +535,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
memcpy(p, bd->bi_enetaddr, 6); memcpy(p, bd->bi_enetaddr, 6);
#endif #endif
#ifdef CONFIG_MPC83XX_TSEC2 #ifdef CONFIG_TSEC2
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
if (p != NULL) if (p != NULL)
memcpy(p, bd->bi_enet1addr, 6); memcpy(p, bd->bi_enet1addr, 6);

2
cpu/mpc85xx/cpu.c
View file

@ -280,7 +280,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
if (p != NULL) if (p != NULL)
*p = cpu_to_be32(clock); *p = cpu_to_be32(clock);
#if defined(CONFIG_MPC85XX_TSEC1) #if defined(CONFIG_TSEC1)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
if (p) if (p)
memcpy(p, bd->bi_enetaddr, 6); memcpy(p, bd->bi_enetaddr, 6);

8
cpu/mpc86xx/cpu.c
View file

@ -278,7 +278,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
if (p != NULL) if (p != NULL)
*p = cpu_to_be32(clock); *p = cpu_to_be32(clock);
#if defined(CONFIG_MPC86XX_TSEC1) #if defined(CONFIG_TSEC1)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
if (p != NULL) if (p != NULL)
memcpy(p, bd->bi_enetaddr, 6); memcpy(p, bd->bi_enetaddr, 6);
@ -287,7 +287,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
memcpy(p, bd->bi_enetaddr, 6); memcpy(p, bd->bi_enetaddr, 6);
#endif #endif
#if defined(CONFIG_MPC86XX_TSEC2) #if defined(CONFIG_TSEC2)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
if (p != NULL) if (p != NULL)
memcpy(p, bd->bi_enet1addr, 6); memcpy(p, bd->bi_enet1addr, 6);
@ -296,7 +296,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
memcpy(p, bd->bi_enet1addr, 6); memcpy(p, bd->bi_enet1addr, 6);
#endif #endif
#if defined(CONFIG_MPC86XX_TSEC3) #if defined(CONFIG_TSEC3)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len); p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
if (p != NULL) if (p != NULL)
memcpy(p, bd->bi_enet2addr, 6); memcpy(p, bd->bi_enet2addr, 6);
@ -305,7 +305,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
memcpy(p, bd->bi_enet2addr, 6); memcpy(p, bd->bi_enet2addr, 6);
#endif #endif
#if defined(CONFIG_MPC86XX_TSEC4) #if defined(CONFIG_TSEC4)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len); p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
if (p != NULL) if (p != NULL)
memcpy(p, bd->bi_enet3addr, 6); memcpy(p, bd->bi_enet3addr, 6);

2
drivers/Makefile
View file

@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libdrivers.a LIB = $(obj)libdrivers.a
COBJS = 3c589.o 5701rls.o ali512x.o atmel_usart.o \ COBJS = 3c589.o 5701rls.o ali512x.o ata_piix.o atmel_usart.o \
bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \ bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \ cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
e1000.o eepro100.o enc28j60.o \ e1000.o eepro100.o enc28j60.o \

216
drivers/ata_piix.c Normal file
View file

@ -0,0 +1,216 @@
/*
* Copyright (C) Procsys. All rights reserved.
* Author: Mushtaq Khan <mushtaq_k@procsys.com>
* <mushtaqk_921@yahoo.co.in>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* with the reference to ata_piix driver in kernel 2.4.32
*/
/*
* This file contains SATA controller and SATA drive initialization functions
*/
#include <common.h>
#include <pci.h>
#include <command.h>
#include <config.h>
#include <asm/byteorder.h>
#include <ide.h>
#include <ata.h>
#ifdef CFG_ATA_PIIX /*ata_piix driver */
#define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */
#define DRV_DECL /*For file specific declarations */
#include <sata.h>
#undef DRV_DECL
/*Macros realted to PCI*/
#define PCI_SATA_BUS 0x00
#define PCI_SATA_DEV 0x1f
#define PCI_SATA_FUNC 0x02
#define PCI_SATA_BASE1 0x10
#define PCI_SATA_BASE2 0x14
#define PCI_SATA_BASE3 0x18
#define PCI_SATA_BASE4 0x1c
#define PCI_SATA_BASE5 0x20
#define PCI_PMR 0x90
#define PCI_PI 0x09
#define PCI_PCS 0x92
#define PCI_DMA_CTL 0x48
#define PORT_PRESENT (1<<0)
#define PORT_ENABLED (1<<4)
u32 bdf;
u32 iobase1 = 0; /*Primary cmd block */
u32 iobase2 = 0; /*Primary ctl block */
u32 iobase3 = 0; /*Sec cmd block */
u32 iobase4 = 0; /*sec ctl block */
u32 iobase5 = 0; /*BMDMA*/
int
pci_sata_init (void)
{
u32 bus = PCI_SATA_BUS;
u32 dev = PCI_SATA_DEV;
u32 fun = PCI_SATA_FUNC;
u16 cmd = 0;
u8 lat = 0, pcibios_max_latency = 0xff;
u8 pmr; /*Port mapping reg */
u8 pi; /*Prgming Interface reg */
bdf = PCI_BDF (bus, dev, fun);
pci_read_config_dword (bdf, PCI_SATA_BASE1, &iobase1);
pci_read_config_dword (bdf, PCI_SATA_BASE2, &iobase2);
pci_read_config_dword (bdf, PCI_SATA_BASE3, &iobase3);
pci_read_config_dword (bdf, PCI_SATA_BASE4, &iobase4);
pci_read_config_dword (bdf, PCI_SATA_BASE5, &iobase5);
if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) ||
(iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) ||
(iobase5 == 0xFFFFFFFF)) {
printf ("error no base addr for SATA controller\n");
return 1;
/*ERROR*/}
iobase1 &= 0xFFFFFFFE;
iobase2 &= 0xFFFFFFFE;
iobase3 &= 0xFFFFFFFE;
iobase4 &= 0xFFFFFFFE;
iobase5 &= 0xFFFFFFFE;
/*check for mode */
pci_read_config_byte (bdf, PCI_PMR, &pmr);
if (pmr > 1) {
printf ("combined mode not supported\n");
return 1;
}
pci_read_config_byte (bdf, PCI_PI, &pi);
if ((pi & 0x05) != 0x05) {
printf ("Sata is in Legacy mode\n");
return 1;
} else {
printf ("sata is in Native mode\n");
}
/*MASTER CFG AND IO CFG */
pci_read_config_word (bdf, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
pci_write_config_word (bdf, PCI_COMMAND, cmd);
pci_read_config_byte (dev, PCI_LATENCY_TIMER, &lat);
if (lat < 16)
lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
else if (lat > pcibios_max_latency)
lat = pcibios_max_latency;
pci_write_config_byte (dev, PCI_LATENCY_TIMER, lat);
return 0;
}
int
sata_bus_probe (int port_no)
{
int orig_mask, mask;
u16 pcs;
mask = (PORT_PRESENT << port_no);
pci_read_config_word (bdf, PCI_PCS, &pcs);
orig_mask = (int) pcs & 0xff;
if ((orig_mask & mask) != mask)
return 0;
else
return 1;
}
int
init_sata (void)
{
u8 i, rv = 0;
for (i = 0; i < CFG_SATA_MAXDEVICES; i++) {
sata_dev_desc[i].type = DEV_TYPE_UNKNOWN;
sata_dev_desc[i].if_type = IF_TYPE_IDE;
sata_dev_desc[i].dev = i;
sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
sata_dev_desc[i].blksz = 0;
sata_dev_desc[i].lba = 0;
sata_dev_desc[i].block_read = sata_read;
}
rv = pci_sata_init ();
if (rv == 1) {
printf ("pci initialization failed\n");
return 1;
}
port[0].port_no = 0;
port[0].ioaddr.cmd_addr = iobase1;
port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
iobase2 | ATA_PCI_CTL_OFS;
port[0].ioaddr.bmdma_addr = iobase5;
port[1].port_no = 1;
port[1].ioaddr.cmd_addr = iobase3;
port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
iobase4 | ATA_PCI_CTL_OFS;
port[1].ioaddr.bmdma_addr = iobase5 + 0x8;
for (i = 0; i < CFG_SATA_MAXBUS; i++)
sata_port (&port[i].ioaddr);
for (i = 0; i < CFG_SATA_MAXBUS; i++) {
if (!(sata_bus_probe (i))) {
port[i].port_state = 0;
printf ("SATA#%d port is not present \n", i);
} else {
printf ("SATA#%d port is present\n", i);
if (sata_bus_softreset (i)) {
port[i].port_state = 0;
} else {
port[i].port_state = 1;
}
}
}
for (i = 0; i < CFG_SATA_MAXBUS; i++) {
u8 j, devno;
if (port[i].port_state == 0)
continue;
for (j = 0; j < CFG_SATA_DEVS_PER_BUS; j++) {
sata_identify (i, j);
set_Feature_cmd (i, j);
devno = i * CFG_SATA_DEVS_PER_BUS + j;
if ((sata_dev_desc[devno].lba > 0) &&
(sata_dev_desc[devno].blksz > 0)) {
dev_print (&sata_dev_desc[devno]);
/* initialize partition type */
init_part (&sata_dev_desc[devno]);
if (curr_dev < 0)
curr_dev =
i * CFG_SATA_DEVS_PER_BUS + j;
}
}
}
return 0;
}
#endif

46
drivers/tsec.c
View file

@ -65,33 +65,31 @@ struct tsec_info_struct {
* FEC_PHYIDX * FEC_PHYIDX
*/ */
static struct tsec_info_struct tsec_info[] = { static struct tsec_info_struct tsec_info[] = {
#if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1) #if defined(CONFIG_TSEC1)
#if defined(CONFIG_MPC8544DS) #if defined(CONFIG_MPC8544DS) || defined(CONFIG_MPC8641HPCN)
{TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX}, {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
#else #else
{TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX}, {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
#endif #endif
#elif defined(CONFIG_MPC86XX_TSEC1)
{TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
#else
{0, 0, 0}, {0, 0, 0},
#endif #endif
#if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2) #if defined(CONFIG_TSEC2)
{TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX}, #if defined(CONFIG_MPC8641HPCN)
#elif defined(CONFIG_MPC86XX_TSEC2)
{TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX}, {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
#else #else
{TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
#endif
{0, 0, 0}, {0, 0, 0},
#endif #endif
#ifdef CONFIG_MPC85XX_FEC #ifdef CONFIG_MPC85XX_FEC
{FEC_PHY_ADDR, 0, FEC_PHYIDX}, {FEC_PHY_ADDR, 0, FEC_PHYIDX},
#else #else
#if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3) #if defined(CONFIG_TSEC3)
{TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX}, {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
#else #else
{0, 0, 0}, {0, 0, 0},
#endif #endif
#if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4) #if defined(CONFIG_TSEC4)
{TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX}, {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
#else #else
{0, 0, 0}, {0, 0, 0},
@ -928,6 +926,33 @@ struct phy_info phy_info_BCM5461S = {
}, },
}; };
struct phy_info phy_info_BCM5464S = {
0x02060b1, /* 5464 ID */
"Broadcom BCM5464S",
0, /* not clear to me what minor revisions we can shift away */
(struct phy_cmd[]) { /* config */
/* Reset and configure the PHY */
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
{miim_end,}
},
(struct phy_cmd[]) { /* startup */
/* Status is read once to clear old link state */
{MIIM_STATUS, miim_read, NULL},
/* Auto-negotiate */
{MIIM_STATUS, miim_read, &mii_parse_sr},
/* Read the status */
{MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
{miim_end,}
},
(struct phy_cmd[]) { /* shutdown */
{miim_end,}
},
};
struct phy_info phy_info_M88E1011S = { struct phy_info phy_info_M88E1011S = {
0x01410c6, 0x01410c6,
"Marvell 88E1011S", "Marvell 88E1011S",
@ -1292,6 +1317,7 @@ struct phy_info *phy_info[] = {
&phy_info_cis8204, &phy_info_cis8204,
&phy_info_cis8201, &phy_info_cis8201,
&phy_info_BCM5461S, &phy_info_BCM5461S,
&phy_info_BCM5464S,
&phy_info_M88E1011S, &phy_info_M88E1011S,
&phy_info_M88E1111S, &phy_info_M88E1111S,
&phy_info_M88E1145, &phy_info_M88E1145,

60
include/ata.h
View file

@ -83,6 +83,66 @@
#define ATA_DEVICE(x) ((x & 1)<<4) #define ATA_DEVICE(x) ((x & 1)<<4)
#define ATA_LBA 0xE0 #define ATA_LBA 0xE0
enum {
ATA_MAX_DEVICES = 1, /* per bus/port */
ATA_MAX_PRD = 256, /* we could make these 256/256 */
ATA_SECT_SIZE = 256, /*256 words per sector */
/* bits in ATA command block registers */
ATA_HOB = (1 << 7), /* LBA48 selector */
ATA_NIEN = (1 << 1), /* disable-irq flag */
/*ATA_LBA = (1 << 6), */ /* LBA28 selector */
ATA_DEV1 = (1 << 4), /* Select Device 1 (slave) */
ATA_DEVICE_OBS = (1 << 7) | (1 << 5), /* obs bits in dev reg */
ATA_DEVCTL_OBS = (1 << 3), /* obsolete bit in devctl reg */
ATA_BUSY = (1 << 7), /* BSY status bit */
ATA_DRDY = (1 << 6), /* device ready */
ATA_DF = (1 << 5), /* device fault */
ATA_DRQ = (1 << 3), /* data request i/o */
ATA_ERR = (1 << 0), /* have an error */
ATA_SRST = (1 << 2), /* software reset */
ATA_ABORTED = (1 << 2), /* command aborted */
/* ATA command block registers */
ATA_REG_DATA = 0x00,
ATA_REG_ERR = 0x01,
ATA_REG_NSECT = 0x02,
ATA_REG_LBAL = 0x03,
ATA_REG_LBAM = 0x04,
ATA_REG_LBAH = 0x05,
ATA_REG_DEVICE = 0x06,
ATA_REG_STATUS = 0x07,
ATA_PCI_CTL_OFS = 0x02,
/* and their aliases */
ATA_REG_FEATURE = ATA_REG_ERR,
ATA_REG_CMD = ATA_REG_STATUS,
ATA_REG_BYTEL = ATA_REG_LBAM,
ATA_REG_BYTEH = ATA_REG_LBAH,
ATA_REG_DEVSEL = ATA_REG_DEVICE,
ATA_REG_IRQ = ATA_REG_NSECT,
/* SETFEATURES stuff */
SETFEATURES_XFER = 0x03,
XFER_UDMA_7 = 0x47,
XFER_UDMA_6 = 0x46,
XFER_UDMA_5 = 0x45,
XFER_UDMA_4 = 0x44,
XFER_UDMA_3 = 0x43,
XFER_UDMA_2 = 0x42,
XFER_UDMA_1 = 0x41,
XFER_UDMA_0 = 0x40,
XFER_MW_DMA_2 = 0x22,
XFER_MW_DMA_1 = 0x21,
XFER_MW_DMA_0 = 0x20,
XFER_PIO_4 = 0x0C,
XFER_PIO_3 = 0x0B,
XFER_PIO_2 = 0x0A,
XFER_PIO_1 = 0x09,
XFER_PIO_0 = 0x08,
XFER_SW_DMA_2 = 0x12,
XFER_SW_DMA_1 = 0x11,
XFER_SW_DMA_0 = 0x10,
XFER_PIO_SLOW = 0x00
};
/* /*
* ATA Commands (only mandatory commands listed here) * ATA Commands (only mandatory commands listed here)
*/ */

1
include/configs/JSE.h
View file

@ -49,6 +49,7 @@
/* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */ /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
#define CONFIG_SYSTEMACE 1 #define CONFIG_SYSTEMACE 1
#define CFG_SYSTEMACE_BASE 0xf0000000 #define CFG_SYSTEMACE_BASE 0xf0000000
#define CFG_SYSTEMACE_WIDTH 8
#define CONFIG_DOS_PARTITION 1 #define CONFIG_DOS_PARTITION 1
/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */

8
include/configs/MPC8313ERDB.h
View file

@ -303,11 +303,11 @@
#endif #endif
#define CONFIG_GMII 1 /* MII PHY management */ #define CONFIG_GMII 1 /* MII PHY management */
#define CONFIG_MPC83XX_TSEC1 1 #define CONFIG_TSEC1 1
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" #define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_MPC83XX_TSEC2 1 #define CONFIG_TSEC2 1
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" #define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0x1c #define TSEC1_PHY_ADDR 0x1c
#define TSEC2_PHY_ADDR 4 #define TSEC2_PHY_ADDR 4
#define TSEC1_PHYIDX 0 #define TSEC1_PHYIDX 0

8
include/configs/MPC8349EMDS.h
View file

@ -432,10 +432,10 @@
#endif #endif
#define CONFIG_GMII 1 /* MII PHY management */ #define CONFIG_GMII 1 /* MII PHY management */
#define CONFIG_MPC83XX_TSEC1 1 #define CONFIG_TSEC1 1
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" #define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_MPC83XX_TSEC2 1 #define CONFIG_TSEC2 1
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" #define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0 #define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1 #define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0 #define TSEC1_PHYIDX 0

14
include/configs/MPC8349ITX.h
View file

@ -374,18 +374,18 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_MII #define CONFIG_MII
#define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ #define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */
#define CONFIG_MPC83XX_TSEC1 #define CONFIG_TSEC1
#ifdef CONFIG_MPC83XX_TSEC1 #ifdef CONFIG_TSEC1
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" #define CONFIG_TSEC1_NAME "TSEC0"
#define CFG_TSEC1_OFFSET 0x24000 #define CFG_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
#define TSEC1_PHYIDX 0 #define TSEC1_PHYIDX 0
#endif #endif
#ifdef CONFIG_MPC83XX_TSEC2 #ifdef CONFIG_TSEC2
#define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH1
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" #define CONFIG_TSEC2_NAME "TSEC1"
#define CFG_TSEC2_OFFSET 0x25000 #define CFG_TSEC2_OFFSET 0x25000
#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */
#define TSEC2_PHY_ADDR 4 #define TSEC2_PHY_ADDR 4
@ -628,11 +628,11 @@ boards, we say we have two, but don't display a message if we find only one. */
*/ */
#define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_MPC83XX_TSEC1 #ifdef CONFIG_TSEC1
#define CONFIG_ETHADDR 00:E0:0C:00:8C:01 #define CONFIG_ETHADDR 00:E0:0C:00:8C:01
#endif #endif
#ifdef CONFIG_MPC83XX_TSEC2 #ifdef CONFIG_TSEC2
#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02
#endif #endif

8
include/configs/MPC8540ADS.h
View file

@ -366,10 +366,10 @@
#endif #endif
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1 #define CONFIG_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" #define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1 #define CONFIG_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" #define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0 #define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1 #define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0 #define TSEC1_PHYIDX 0

8
include/configs/MPC8540EVAL.h
View file

@ -212,10 +212,10 @@
#elif defined(CONFIG_TSEC_ENET) #elif defined(CONFIG_TSEC_ENET)
#define CONFIG_NET_MULTI 1 #define CONFIG_NET_MULTI 1
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1 #define CONFIG_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" #define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1 #define CONFIG_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" #define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_MPC85XX_FEC 1 #define CONFIG_MPC85XX_FEC 1
#define CONFIG_MPC85XX_FEC_NAME "FEC" #define CONFIG_MPC85XX_FEC_NAME "FEC"
#define TSEC1_PHY_ADDR 7 #define TSEC1_PHY_ADDR 7

8
include/configs/MPC8541CDS.h
View file

@ -373,10 +373,10 @@ extern unsigned long get_clock_freq(void);
#endif #endif
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1 #define CONFIG_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" #define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1 #define CONFIG_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" #define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC #undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0 #define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1 #define TSEC2_PHY_ADDR 1

8
include/configs/MPC8544DS.h
View file

@ -359,10 +359,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
#define CONFIG_MPC85XX_TSEC1 1 #define CONFIG_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC1" #define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_MPC85XX_TSEC3 1 #define CONFIG_TSEC3 1
#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC3" #define CONFIG_TSEC3_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC #undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0 #define TSEC1_PHY_ADDR 0

16
include/configs/MPC8548CDS.h
View file

@ -391,14 +391,14 @@ extern unsigned long get_clock_freq(void);
#endif #endif
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1 #define CONFIG_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" #define CONFIG_TSEC1_NAME "eTSEC0"
#define CONFIG_MPC85XX_TSEC2 1 #define CONFIG_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" #define CONFIG_TSEC2_NAME "eTSEC1"
#define CONFIG_MPC85XX_TSEC3 1 #define CONFIG_TSEC3 1
#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" #define CONFIG_TSEC3_NAME "eTSEC2"
#undef CONFIG_MPC85XX_TSEC4 #undef CONFIG_TSEC4
#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" #define CONFIG_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC #undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0 #define TSEC1_PHY_ADDR 0

8
include/configs/MPC8555CDS.h
View file

@ -373,10 +373,10 @@ extern unsigned long get_clock_freq(void);
#endif #endif
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1 #define CONFIG_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" #define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1 #define CONFIG_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" #define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC #undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0 #define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1 #define TSEC2_PHY_ADDR 1

8
include/configs/MPC8560ADS.h
View file

@ -356,10 +356,10 @@
#endif #endif
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1 #define CONFIG_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" #define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1 #define CONFIG_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" #define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC #undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0 #define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1 #define TSEC2_PHY_ADDR 1

12
include/configs/MPC8568MDS.h
View file

@ -353,12 +353,12 @@ extern unsigned long get_clock_freq(void);
#endif #endif
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1 #define CONFIG_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" #define CONFIG_TSEC1_NAME "eTSEC0"
#define CONFIG_MPC85XX_TSEC2 1 #define CONFIG_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" #define CONFIG_TSEC2_NAME "eTSEC1"
#undef CONFIG_MPC85XX_TSEC3 #undef CONFIG_TSEC3
#undef CONFIG_MPC85XX_TSEC4 #undef CONFIG_TSEC4
#undef CONFIG_MPC85XX_FEC #undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 2 #define TSEC1_PHY_ADDR 2

16
include/configs/MPC8641HPCN.h
View file

@ -359,14 +359,14 @@
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC86XX_TSEC1 1 #define CONFIG_TSEC1 1
#define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1" #define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_MPC86XX_TSEC2 1 #define CONFIG_TSEC2 1
#define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2" #define CONFIG_TSEC2_NAME "eTSEC2"
#define CONFIG_MPC86XX_TSEC3 1 #define CONFIG_TSEC3 1
#define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3" #define CONFIG_TSEC3_NAME "eTSEC3"
#define CONFIG_MPC86XX_TSEC4 1 #define CONFIG_TSEC4 1
#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" #define CONFIG_TSEC4_NAME "eTSEC4"
#define TSEC1_PHY_ADDR 0 #define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1 #define TSEC2_PHY_ADDR 1

8
include/configs/PM854.h
View file

@ -262,10 +262,10 @@
#endif #endif
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1 #define CONFIG_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" #define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1 #define CONFIG_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" #define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0 #define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1 #define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0 #define TSEC1_PHYIDX 0

8
include/configs/PM856.h
View file

@ -258,10 +258,10 @@
#endif #endif
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1 #define CONFIG_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" #define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1 #define CONFIG_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" #define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC #undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0 #define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1 #define TSEC2_PHY_ADDR 1

8
include/configs/TQM834x.h
View file

@ -248,10 +248,10 @@ extern int tqm834x_num_flash_banks;
#define CONFIG_NET_MULTI #define CONFIG_NET_MULTI
#endif #endif
#define CONFIG_MPC83XX_TSEC1 1 #define CONFIG_TSEC1 1
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" #define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_MPC83XX_TSEC2 1 #define CONFIG_TSEC2 1
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" #define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 2 #define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 1 #define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0 #define TSEC1_PHYIDX 0

8
include/configs/TQM85xx.h
View file

@ -258,10 +258,10 @@
#define CONFIG_NET_MULTI 1 #define CONFIG_NET_MULTI 1
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1 #define CONFIG_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" #define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1 #define CONFIG_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" #define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 2 #define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 1 #define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0 #define TSEC1_PHYIDX 0

8
include/configs/sbc8349.h
View file

@ -401,10 +401,10 @@
#define CONFIG_NET_MULTI 1 #define CONFIG_NET_MULTI 1
#endif #endif
#define CONFIG_MPC83XX_TSEC1 1 #define CONFIG_TSEC1 1
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" #define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_MPC83XX_TSEC2 1 #define CONFIG_TSEC2 1
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" #define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_PHY_BCM5421S 1 #define CONFIG_PHY_BCM5421S 1
#define TSEC1_PHY_ADDR 0x19 #define TSEC1_PHY_ADDR 0x19
#define TSEC2_PHY_ADDR 0x1a #define TSEC2_PHY_ADDR 0x1a

9
include/configs/sc520_cdp.h
View file

@ -181,6 +181,15 @@
#undef CONFIG_IDE_RESET /* reset for ide unsupported... */ #undef CONFIG_IDE_RESET /* reset for ide unsupported... */
#undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */ #undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */
/************************************************************
*SATA/Native Stuff
************************************************************/
#define CFG_SATA_SUPPORTED 1
#define CFG_SATA_MAXBUS 2 /*Max Sata buses supported */
#define CFG_SATA_DEVS_PER_BUS 2 /*Max no. of devices per bus/port */
#define CFG_SATA_MAXDEVICES (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS)
#define CFG_ATA_PIIX 1 /*Supports ata_piix driver */
/************************************************************ /************************************************************
* ATAPI support (experimental) * ATAPI support (experimental)
************************************************************/ ************************************************************/

8
include/configs/stxgp3.h
View file

@ -230,10 +230,10 @@
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1 #define CONFIG_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" #define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1 #define CONFIG_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" #define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPS85XX_FEC #undef CONFIG_MPS85XX_FEC
#define TSEC1_PHY_ADDR 2 #define TSEC1_PHY_ADDR 2

8
include/configs/stxssa.h
View file

@ -256,10 +256,10 @@
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1 #define CONFIG_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" #define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1 #define CONFIG_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" #define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPS85XX_FEC #undef CONFIG_MPS85XX_FEC
#define TSEC1_PHY_ADDR 2 #define TSEC1_PHY_ADDR 2

108
include/sata.h Normal file
View file

@ -0,0 +1,108 @@
#if (DEBUG_SATA)
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
struct sata_ioports {
unsigned long cmd_addr;
unsigned long data_addr;
unsigned long error_addr;
unsigned long feature_addr;
unsigned long nsect_addr;
unsigned long lbal_addr;
unsigned long lbam_addr;
unsigned long lbah_addr;
unsigned long device_addr;
unsigned long status_addr;
unsigned long command_addr;
unsigned long altstatus_addr;
unsigned long ctl_addr;
unsigned long bmdma_addr;
unsigned long scr_addr;
};
struct sata_port {
unsigned char port_no; /* primary=0, secondary=1 */
struct sata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */
unsigned char ctl_reg;
unsigned char last_ctl;
unsigned char port_state; /* 1-port is available and */
/* 0-port is not available */
unsigned char dev_mask;
};
/***********SATA LIBRARY SPECIFIC DEFINITIONS AND DECLARATIONS**************/
#ifdef SATA_DECL /*SATA library specific declarations */
#define ata_id_has_lba48(id) ((id)[83] & (1 << 10))
#define ata_id_has_lba(id) ((id)[49] & (1 << 9))
#define ata_id_has_dma(id) ((id)[49] & (1 << 8))
#define ata_id_u32(id,n) \
(((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)]))
#define ata_id_u64(id,n) \
(((u64) (id)[(n) + 3] << 48) | \
((u64) (id)[(n) + 2] << 32) | \
((u64) (id)[(n) + 1] << 16) | \
((u64) (id)[(n) + 0]) )
#endif
#ifdef SATA_DECL /*SATA library specific declarations */
static inline void
ata_dump_id (u16 * id)
{
PRINTF ("49==0x%04x "
"53==0x%04x "
"63==0x%04x "
"64==0x%04x "
"75==0x%04x \n", id[49], id[53], id[63], id[64], id[75]);
PRINTF ("80==0x%04x "
"81==0x%04x "
"82==0x%04x "
"83==0x%04x "
"84==0x%04x \n", id[80], id[81], id[82], id[83], id[84]);
PRINTF ("88==0x%04x " "93==0x%04x\n", id[88], id[93]);
}
#endif
#ifdef SATA_DECL /*SATA library specific declarations */
int sata_bus_softreset (int num);
void sata_identify (int num, int dev);
void sata_port (struct sata_ioports *ioport);
void set_Feature_cmd (int num, int dev);
int sata_devchk (struct sata_ioports *ioaddr, int dev);
void dev_select (struct sata_ioports *ioaddr, int dev);
u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max);
u8 sata_chk_status (struct sata_ioports *ioaddr);
ulong sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buffer);
ulong sata_write (int device,ulong blknr, lbaint_t blkcnt, void * buffer);
void msleep (int count);
#else
extern int sata_bus_softreset (int num);
extern void sata_identify (int num, int dev);
extern void sata_port (struct sata_ioports *ioport);
extern void set_Feature_cmd (int num, int dev);
extern ulong sata_read (int device, ulong blknr,
lbaint_t blkcnt, void * buffer);
extern ulong sata_write (int device, ulong blknr,
lbaint_t blkcnt, void * buffer);
extern void msleep (int count);
#endif
/************DRIVER SPECIFIC DEFINITIONS AND DECLARATIONS**************/
#ifdef DRV_DECL /*Driver specific declaration */
int init_sata (void);
#else
extern int init_sata (void);
#endif
#ifdef DRV_DECL /*Defines Driver Specific variables */
struct sata_port port[CFG_SATA_MAXBUS];
block_dev_desc_t sata_dev_desc[CFG_SATA_MAXDEVICES];
int curr_dev = -1;
#else
extern struct sata_port port[CFG_SATA_MAXBUS];
extern block_dev_desc_t sata_dev_desc[CFG_SATA_MAXDEVICES];
extern int curr_dev;
#endif

23
lib_ppc/extable.c
View file

@ -52,30 +52,27 @@ search_one_table(const struct exception_table_entry *first,
const struct exception_table_entry *last, const struct exception_table_entry *last,
unsigned long value) unsigned long value)
{ {
while (first <= last) {
const struct exception_table_entry *mid;
long diff; long diff;
if ((ulong) first > CFG_MONITOR_BASE) {
mid = (last - first) / 2 + first;
if ((ulong) mid > CFG_MONITOR_BASE) {
/* exception occurs in FLASH, before u-boot relocation. /* exception occurs in FLASH, before u-boot relocation.
* No relocation offset is needed. * No relocation offset is needed.
*/ */
diff = mid->insn - value; while (first <= last) {
diff = first->insn - value;
if (diff == 0) if (diff == 0)
return mid->fixup; return first->fixup;
first++;
}
} else { } else {
/* exception occurs in RAM, after u-boot relocation. /* exception occurs in RAM, after u-boot relocation.
* A relocation offset should be added. * A relocation offset should be added.
*/ */
diff = (mid->insn + gd->reloc_off) - value; while (first <= last) {
diff = (first->insn + gd->reloc_off) - value;
if (diff == 0) if (diff == 0)
return (mid->fixup + gd->reloc_off); return (first->fixup + gd->reloc_off);
first++;
} }
if (diff < 0)
first = mid + 1;
else
last = mid - 1;
} }
return 0; return 0;
} }

39
net/eth.c
View file

@ -173,28 +173,20 @@ int eth_initialize(bd_t *bis)
#if defined(CONFIG_SK98) #if defined(CONFIG_SK98)
skge_initialize(bis); skge_initialize(bis);
#endif #endif
#if defined(CONFIG_MPC85XX_TSEC1) #if defined(CONFIG_TSEC1)
tsec_initialize(bis, 0, CONFIG_MPC85XX_TSEC1_NAME); tsec_initialize(bis, 0, CONFIG_TSEC1_NAME);
#elif defined(CONFIG_MPC83XX_TSEC1)
tsec_initialize(bis, 0, CONFIG_MPC83XX_TSEC1_NAME);
#endif #endif
#if defined(CONFIG_MPC85XX_TSEC2) #if defined(CONFIG_TSEC2)
tsec_initialize(bis, 1, CONFIG_MPC85XX_TSEC2_NAME); tsec_initialize(bis, 1, CONFIG_TSEC2_NAME);
#elif defined(CONFIG_MPC83XX_TSEC2)
tsec_initialize(bis, 1, CONFIG_MPC83XX_TSEC2_NAME);
#endif #endif
#if defined(CONFIG_MPC85XX_FEC) #if defined(CONFIG_MPC85XX_FEC)
tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME); tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME);
#else #else
# if defined(CONFIG_MPC85XX_TSEC3) # if defined(CONFIG_TSEC3)
tsec_initialize(bis, 2, CONFIG_MPC85XX_TSEC3_NAME); tsec_initialize(bis, 2, CONFIG_TSEC3_NAME);
# elif defined(CONFIG_MPC83XX_TSEC3)
tsec_initialize(bis, 2, CONFIG_MPC83XX_TSEC3_NAME);
# endif # endif
# if defined(CONFIG_MPC85XX_TSEC4) # if defined(CONFIG_TSEC4)
tsec_initialize(bis, 3, CONFIG_MPC85XX_TSEC4_NAME); tsec_initialize(bis, 3, CONFIG_TSEC4_NAME);
# elif defined(CONFIG_MPC83XX_TSEC4)
tsec_initialize(bis, 3, CONFIG_MPC83XX_TSEC4_NAME);
# endif # endif
#endif #endif
#if defined(CONFIG_UEC_ETH1) #if defined(CONFIG_UEC_ETH1)
@ -203,21 +195,6 @@ int eth_initialize(bd_t *bis)
#if defined(CONFIG_UEC_ETH2) #if defined(CONFIG_UEC_ETH2)
uec_initialize(1); uec_initialize(1);
#endif #endif
#if defined(CONFIG_MPC86XX_TSEC1)
tsec_initialize(bis, 0, CONFIG_MPC86XX_TSEC1_NAME);
#endif
#if defined(CONFIG_MPC86XX_TSEC2)
tsec_initialize(bis, 1, CONFIG_MPC86XX_TSEC2_NAME);
#endif
#if defined(CONFIG_MPC86XX_TSEC3)
tsec_initialize(bis, 2, CONFIG_MPC86XX_TSEC3_NAME);
#endif
#if defined(CONFIG_MPC86XX_TSEC4)
tsec_initialize(bis, 3, CONFIG_MPC86XX_TSEC4_NAME);
#endif
#if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC) #if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
fec_initialize(bis); fec_initialize(bis);

2
tools/Makefile
View file

@ -74,7 +74,7 @@ TOOLSUBDIRS =
ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc)
HOST_CFLAGS = -traditional-cpp -Wall HOST_CFLAGS = -traditional-cpp -Wall
HOST_LDFLAGS =-multiply_defined suppress HOST_LDFLAGS =-multiply_defined suppress
HOST_ENVIRO_CFLAGS = -traditional-cpp HOST_ENVIRO_CFLAGS =
else else
ifeq ($(HOSTOS)-$(HOSTARCH),netbsd-ppc) ifeq ($(HOSTOS)-$(HOSTARCH),netbsd-ppc)

4
tools/mkimage.c
View file

@ -446,7 +446,7 @@ NXTARG: ;
} }
/* We're a bit of paranoid */ /* We're a bit of paranoid */
#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) #if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) && !defined(__APPLE__)
(void) fdatasync (ifd); (void) fdatasync (ifd);
#else #else
(void) fsync (ifd); (void) fsync (ifd);
@ -496,7 +496,7 @@ NXTARG: ;
(void) munmap((void *)ptr, sbuf.st_size); (void) munmap((void *)ptr, sbuf.st_size);
/* We're a bit of paranoid */ /* We're a bit of paranoid */
#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) #if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) && !defined(__APPLE__)
(void) fdatasync (ifd); (void) fdatasync (ifd);
#else #else
(void) fsync (ifd); (void) fsync (ifd);