mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
[FIX] Change configuration for XUPV2P Microblaze board
This commit is contained in:
Michal Simek
parent
537091b4ee
commit
98889edd50
4 changed files with 72 additions and 39 deletions
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@ -22,32 +22,17 @@
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#
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include $(TOPDIR)/config.mk
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ifneq ($(OBJTREE),$(SRCTREE))
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$(shell mkdir -p $(obj)../common)
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$(shell mkdir -p $(obj)../xilinx_enet)
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endif
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INCS := -I../common -I../xilinx_enet
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CFLAGS += $(INCS)
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HOST_CFLAGS += $(INCS)
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o \
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../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \
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../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \
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../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \
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../xilinx_enet/xemac_intr_dma.o ../common/xipif_v1_23_b.o \
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../common/xbasic_types.o ../common/xdma_channel.o \
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../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \
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../common/xversion.o \
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COBJS = $(BOARD).o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $^
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$(LIB): $(obj).depend $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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@ -25,8 +25,8 @@
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# Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
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#
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TEXT_BASE = 0x38000000
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TEXT_BASE = 0x30000000
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PLATFORM_CPPFLAGS += -mxl-pattern-compare
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PLATFORM_CPPFLAGS += -mno-xl-soft-mul
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PLATFORM_CPPFLAGS += -mno-xl-soft-div
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PLATFORM_CPPFLAGS += -mxl-barrel-shift
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PLATFORM_CPPFLAGS += -mcpu=v5.00.c
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@ -28,17 +28,24 @@
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/* System Clock Frequency */
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#define XILINX_CLOCK_FREQ 100000000
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/* Microblaze is microblaze_0 */
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#define XILINX_USE_MSR_INSTR 1
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#define XILINX_PVR 0
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#define XILINX_FSL_NUMBER 0
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/* Interrupt controller is opb_intc_0 */
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#define XILINX_INTC_BASEADDR 0x41200000
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#define XILINX_INTC_NUM_INTR_INPUTS 11
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#define XILINX_INTC_NUM_INTR_INPUTS 7
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/* Timer pheriphery is opb_timer_1 */
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#define XILINX_TIMER_BASEADDR 0x41c00000
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#define XILINX_TIMER_IRQ 1
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#define XILINX_TIMER_IRQ 0
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/* Uart pheriphery is RS232_Uart_1 */
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#define XILINX_UART_BASEADDR 0x40600000
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#define XILINX_UART_BAUDRATE 115200
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#define XILINX_UARTLITE_BASEADDR 0x40600000
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#define XILINX_UARTLITE_BAUDRATE 115200
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/* IIC doesn't exist */
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/* GPIO is LEDs_4Bit*/
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#define XILINX_GPIO_BASEADDR 0x40000000
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@ -51,14 +58,10 @@
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/* Sysace Controller is SysACE_CompactFlash */
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#define XILINX_SYSACE_BASEADDR 0x41800000
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#define XILINX_SYSACE_HIGHADDR 0x4180ffff
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#define XILINX_SYSACE_MEM_WIDTH 16
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/* Ethernet controller is Ethernet_MAC */
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#define XPAR_XEMAC_NUM_INSTANCES 1
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#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
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#define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000
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#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0ffff
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#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
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#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
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#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
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#define XILINX_EMAC_BASEADDR 0x40c00000
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#define XILINX_EMAC_DMA_PRESENT 3
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#define XILINX_EMAC_HALF_DUPLEX_EXIST 1
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#define XILINX_EMAC_MII_EXIST 1
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@ -31,13 +31,33 @@
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#define CONFIG_XUPV2P 1
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/* uart */
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#define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR
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#define CONFIG_BAUDRATE XILINX_UART_BAUDRATE
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#ifdef XILINX_UARTLITE_BASEADDR
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#define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
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#define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
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#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
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#else
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#ifdef XILINX_UART16550_BASEADDR
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE 4
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#define CONFIG_CONS_INDEX 1
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#define CFG_NS16550_COM1 XILINX_UART16550_BASEADDR
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#define CFG_NS16550_CLK XILINX_UART16550_CLOCK_HZ
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#define CONFIG_BAUDRATE 115200
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#define CFG_BAUDRATE_TABLE { 9600, 115200 }
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#endif
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#endif
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/* ethernet */
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#define CONFIG_EMAC 1
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#define XPAR_EMAC_0_DEVICE_ID XPAR_XEMAC_NUM_INSTANCES
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#ifdef XILINX_EMAC_BASEADDR
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#define XILINX_EMAC 1
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#else
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#ifdef XILINX_EMACLITE_BASEADDR
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#define XILINX_EMACLITE 1
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#endif
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#endif
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#undef ET_DEBUG
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/*
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* setting reset address
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@ -48,11 +68,13 @@
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* U-BOOT auto-relocate to TEXT_BASE. After RESET command Microblaze
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* jump to CFG_RESET_ADDRESS where is the original U-BOOT code.
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*/
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#define CFG_RESET_ADDRESS 0x36000000
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/* #define CFG_RESET_ADDRESS 0x36000000 */
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/* gpio */
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#ifdef XILINX_GPIO_BASEADDR
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#define CFG_GPIO_0 1
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#define CFG_GPIO_0_ADDR XILINX_GPIO_BASEADDR
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#endif
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/* interrupt controller */
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#define CFG_INTC_0 1
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@ -118,6 +140,25 @@
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#define CFG_ENV_IS_NOWHERE 1
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#define CFG_ENV_SIZE 0x1000
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
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#ifndef XILINX_SYSACE_BASEADDR
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#define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
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CFG_CMD_MEMORY |\
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CFG_CMD_IRQ |\
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CFG_CMD_BDI |\
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CFG_CMD_NET |\
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CFG_CMD_IMI |\
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CFG_CMD_ECHO |\
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CFG_CMD_CACHE |\
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CFG_CMD_RUN |\
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CFG_CMD_AUTOSCRIPT |\
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CFG_CMD_ASKENV |\
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CFG_CMD_LOADS |\
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CFG_CMD_LOADB |\
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CFG_CMD_MISC |\
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CFG_CMD_MFSL |\
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CFG_CMD_PING \
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)
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#else
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#define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
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CFG_CMD_MEMORY |\
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CFG_CMD_IRQ |\
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@ -134,8 +175,10 @@
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CFG_CMD_MISC |\
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CFG_CMD_FAT |\
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CFG_CMD_EXT2 |\
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CFG_CMD_MFSL |\
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CFG_CMD_PING \
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)
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#endif
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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@ -150,7 +193,7 @@
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#define CONFIG_BOOTDELAY 30
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#define CONFIG_BOOTARGS "root=romfs"
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#define CONFIG_HOSTNAME "ml401"
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#define CONFIG_HOSTNAME "xupv2p"
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#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
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#define CONFIG_IPADDR 192.168.0.3
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#define CONFIG_SERVERIP 192.168.0.5
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@ -166,11 +209,13 @@
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"echo"
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/* system ace */
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#ifdef XILINX_SYSACE_BASEADDR
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#define CONFIG_SYSTEMACE
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/* #define DEBUG_SYSTEMACE */
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#define SYSTEMACE_CONFIG_FPGA
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#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
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#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
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#define CONFIG_DOS_PARTITION
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#endif
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#endif /* __CONFIG_H */
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