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Merge branch 'for-next' of https://github.com/lftan/u-boot

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This commit is contained in:
Tom Rini 2020-10-12 07:55:17 -04:00
commit 9885313b9a
34 changed files with 1190 additions and 548 deletions
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27
Makefile
View file

@ -1574,21 +1574,30 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
$(call if_changed,pad_cat)
ifneq ($(CONFIG_ARCH_SOCFPGA),)
quiet_cmd_gensplx4 = GENSPLX4 $@
cmd_gensplx4 = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
spl/u-boot-spl.sfp spl/u-boot-spl.sfp > $@ || rm -f $@
spl/u-boot-splx4.sfp: spl/u-boot-spl.sfp FORCE
$(call if_changed,gensplx4)
quiet_cmd_socboot = SOCBOOT $@
cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
u-boot.img > $@ || rm -f $@
u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE
cmd_socboot = cat spl/u-boot-splx4.sfp u-boot.img > $@ || rm -f $@
u-boot-with-spl.sfp: spl/u-boot-splx4.sfp u-boot.img FORCE
$(call if_changed,socboot)
quiet_cmd_socnandboot = SOCNANDBOOT $@
cmd_socnandboot = dd if=/dev/zero of=spl/u-boot-spl.pad bs=64 count=1024 ; \
quiet_cmd_gensplpadx4 = GENSPLPADX4 $@
cmd_gensplpadx4 = dd if=/dev/zero of=spl/u-boot-spl.pad bs=64 count=1024 ; \
cat spl/u-boot-spl.sfp spl/u-boot-spl.pad \
spl/u-boot-spl.sfp spl/u-boot-spl.pad \
spl/u-boot-spl.sfp spl/u-boot-spl.pad \
spl/u-boot-spl.sfp spl/u-boot-spl.pad \
u-boot.img > $@ || rm -f $@ spl/u-boot-spl.pad
u-boot-with-nand-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE
spl/u-boot-spl.sfp spl/u-boot-spl.pad > $@ || \
rm -f $@ spl/u-boot-spl.pad
u-boot-spl-padx4.sfp: spl/u-boot-spl.sfp FORCE
$(call if_changed,gensplpadx4)
quiet_cmd_socnandboot = SOCNANDBOOT $@
cmd_socnandboot = cat u-boot-spl-padx4.sfp u-boot.img > $@ || rm -f $@
u-boot-with-nand-spl.sfp: u-boot-spl-padx4.sfp u-boot.img FORCE
$(call if_changed,socnandboot)
endif

2
arch/arm/Kconfig
View file

@ -994,7 +994,7 @@ config ARCH_SOCFPGA
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET
select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET_SOCFPGA_S10 if TARGET_SOCFPGA_STRATIX10
select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY

4
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
View file

@ -40,3 +40,7 @@
&qspi {
status = "okay";
};
&watchdog0 {
u-boot,dm-pre-reloc;
};

290
arch/arm/dts/socfpga_arria10-handoff.dtsi Normal file
View file

@ -0,0 +1,290 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/ {
clocks {
#address-cells = <1>;
#size-cells = <1>;
u-boot,dm-pre-reloc;
altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <EOSC1_CLK_HZ>;
clock-output-names = "altera_arria10_hps_eosc1-clk";
u-boot,dm-pre-reloc;
};
altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <CB_INTOSC_LS_CLK_HZ>;
clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
u-boot,dm-pre-reloc;
};
/* Clock source: altera_arria10_hps_f2h_free */
altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <F2H_FREE_CLK_HZ>;
clock-output-names = "altera_arria10_hps_f2h_free-clk";
u-boot,dm-pre-reloc;
};
};
clkmgr@0xffd04000 {
compatible = "altr,socfpga-a10-clk-init";
reg = <0xffd04000 0x00000200>;
reg-names = "soc_clock_manager_OCP_SLV";
u-boot,dm-pre-reloc;
mainpll {
vco0-psrc = <MAINPLLGRP_VCO0_PSRC>;
vco1-denom = <MAINPLLGRP_VCO1_DENOM>;
vco1-numer = <MAINPLLGRP_VCO1_NUMER>;
mpuclk-cnt = <MAINPLLGRP_MPUCLK_CNT>;
mpuclk-src = <MAINPLLGRP_MPUCLK_SRC>;
nocclk-cnt = <MAINPLLGRP_NOCCLK_CNT>;
nocclk-src = <MAINPLLGRP_NOCCLK_SRC>;
cntr2clk-cnt = <MAINPLLGRP_CNTR2CLK_CNT>;
cntr3clk-cnt = <MAINPLLGRP_CNTR3CLK_CNT>;
cntr4clk-cnt = <MAINPLLGRP_CNTR4CLK_CNT>;
cntr5clk-cnt = <MAINPLLGRP_CNTR5CLK_CNT>;
cntr6clk-cnt = <MAINPLLGRP_CNTR6CLK_CNT>;
cntr7clk-cnt = <MAINPLLGRP_CNTR7CLK_CNT>;
cntr7clk-src = <MAINPLLGRP_CNTR7CLK_SRC>;
cntr8clk-cnt = <MAINPLLGRP_CNTR8CLK_CNT>;
cntr9clk-cnt = <MAINPLLGRP_CNTR9CLK_CNT>;
cntr9clk-src = <MAINPLLGRP_CNTR9CLK_SRC>;
cntr15clk-cnt = <MAINPLLGRP_CNTR15CLK_CNT>;
nocdiv-l4mainclk = <MAINPLLGRP_NOCDIV_L4MAINCLK>;
nocdiv-l4mpclk = <MAINPLLGRP_NOCDIV_L4MPCLK>;
nocdiv-l4spclk = <MAINPLLGRP_NOCDIV_L4SPCLK>;
nocdiv-csatclk = <MAINPLLGRP_NOCDIV_CSATCLK>;
nocdiv-cstraceclk = <MAINPLLGRP_NOCDIV_CSTRACECLK>;
nocdiv-cspdbgclk = <MAINPLLGRP_NOCDIV_CSPDBGCLK>;
u-boot,dm-pre-reloc;
};
perpll {
vco0-psrc = <PERPLLGRP_VCO0_PSRC>;
vco1-denom = <PERPLLGRP_VCO1_DENOM>;
vco1-numer = <PERPLLGRP_VCO1_NUMER>;
cntr2clk-cnt = <PERPLLGRP_CNTR2CLK_CNT>;
cntr2clk-src = <PERPLLGRP_CNTR2CLK_SRC>;
cntr3clk-cnt = <PERPLLGRP_CNTR3CLK_CNT>;
cntr3clk-src = <PERPLLGRP_CNTR3CLK_SRC>;
cntr4clk-cnt = <PERPLLGRP_CNTR4CLK_CNT>;
cntr4clk-src = <PERPLLGRP_CNTR4CLK_SRC>;
cntr5clk-cnt = <PERPLLGRP_CNTR5CLK_CNT>;
cntr5clk-src = <PERPLLGRP_CNTR5CLK_SRC>;
cntr6clk-cnt = <PERPLLGRP_CNTR6CLK_CNT>;
cntr6clk-src = <PERPLLGRP_CNTR6CLK_SRC>;
cntr7clk-cnt = <PERPLLGRP_CNTR7CLK_CNT>;
cntr8clk-cnt = <PERPLLGRP_CNTR8CLK_CNT>;
cntr8clk-src = <PERPLLGRP_CNTR8CLK_SRC>;
cntr9clk-cnt = <PERPLLGRP_CNTR9CLK_CNT>;
emacctl-emac0sel = <PERPLLGRP_EMACCTL_EMAC0SEL>;
emacctl-emac1sel = <PERPLLGRP_EMACCTL_EMAC1SEL>;
emacctl-emac2sel = <PERPLLGRP_EMACCTL_EMAC2SEL>;
gpiodiv-gpiodbclk = <PERPLLGRP_GPIODIV_GPIODBCLK>;
u-boot,dm-pre-reloc;
};
alteragrp {
nocclk = <ALTERAGRP_NOCCLK>;
mpuclk = <ALTERAGRP_MPUCLK>;
u-boot,dm-pre-reloc;
};
};
i_io48_pin_mux: pinmux@0xffd07000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "pinctrl-single";
reg = <0xffd07000 0x00000800>;
reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
u-boot,dm-pre-reloc;
shared {
reg = <0xffd07000 0x00000200>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
pinctrl-single,pins =
<0x00000000 PINMUX_SHARED_IO_Q1_1_SEL>,
<0x00000004 PINMUX_SHARED_IO_Q1_2_SEL>,
<0x00000008 PINMUX_SHARED_IO_Q1_3_SEL>,
<0x0000000c PINMUX_SHARED_IO_Q1_4_SEL>,
<0x00000010 PINMUX_SHARED_IO_Q1_5_SEL>,
<0x00000014 PINMUX_SHARED_IO_Q1_6_SEL>,
<0x00000018 PINMUX_SHARED_IO_Q1_7_SEL>,
<0x0000001c PINMUX_SHARED_IO_Q1_8_SEL>,
<0x00000020 PINMUX_SHARED_IO_Q1_9_SEL>,
<0x00000024 PINMUX_SHARED_IO_Q1_10_SEL>,
<0x00000028 PINMUX_SHARED_IO_Q1_11_SEL>,
<0x0000002c PINMUX_SHARED_IO_Q1_12_SEL>,
<0x00000030 PINMUX_SHARED_IO_Q2_1_SEL>,
<0x00000034 PINMUX_SHARED_IO_Q2_2_SEL>,
<0x00000038 PINMUX_SHARED_IO_Q2_3_SEL>,
<0x0000003c PINMUX_SHARED_IO_Q2_4_SEL>,
<0x00000040 PINMUX_SHARED_IO_Q2_5_SEL>,
<0x00000044 PINMUX_SHARED_IO_Q2_6_SEL>,
<0x00000048 PINMUX_SHARED_IO_Q2_7_SEL>,
<0x0000004c PINMUX_SHARED_IO_Q2_8_SEL>,
<0x00000050 PINMUX_SHARED_IO_Q2_9_SEL>,
<0x00000054 PINMUX_SHARED_IO_Q2_10_SEL>,
<0x00000058 PINMUX_SHARED_IO_Q2_11_SEL>,
<0x0000005c PINMUX_SHARED_IO_Q2_12_SEL>,
<0x00000060 PINMUX_SHARED_IO_Q3_1_SEL>,
<0x00000064 PINMUX_SHARED_IO_Q3_2_SEL>,
<0x00000068 PINMUX_SHARED_IO_Q3_3_SEL>,
<0x0000006c PINMUX_SHARED_IO_Q3_4_SEL>,
<0x00000070 PINMUX_SHARED_IO_Q3_5_SEL>,
<0x00000074 PINMUX_SHARED_IO_Q3_6_SEL>,
<0x00000078 PINMUX_SHARED_IO_Q3_7_SEL>,
<0x0000007c PINMUX_SHARED_IO_Q3_8_SEL>,
<0x00000080 PINMUX_SHARED_IO_Q3_9_SEL>,
<0x00000084 PINMUX_SHARED_IO_Q3_10_SEL>,
<0x00000088 PINMUX_SHARED_IO_Q3_11_SEL>,
<0x0000008c PINMUX_SHARED_IO_Q3_12_SEL>,
<0x00000090 PINMUX_SHARED_IO_Q4_1_SEL>,
<0x00000094 PINMUX_SHARED_IO_Q4_2_SEL>,
<0x00000098 PINMUX_SHARED_IO_Q4_3_SEL>,
<0x0000009c PINMUX_SHARED_IO_Q4_4_SEL>,
<0x000000a0 PINMUX_SHARED_IO_Q4_5_SEL>,
<0x000000a4 PINMUX_SHARED_IO_Q4_6_SEL>,
<0x000000a8 PINMUX_SHARED_IO_Q4_7_SEL>,
<0x000000ac PINMUX_SHARED_IO_Q4_8_SEL>,
<0x000000b0 PINMUX_SHARED_IO_Q4_9_SEL>,
<0x000000b4 PINMUX_SHARED_IO_Q4_10_SEL>,
<0x000000b8 PINMUX_SHARED_IO_Q4_11_SEL>,
<0x000000bc PINMUX_SHARED_IO_Q4_12_SEL>;
u-boot,dm-pre-reloc;
};
dedicated {
reg = <0xffd07200 0x00000200>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
pinctrl-single,pins =
<0x0000000c PINMUX_DEDICATED_IO_4_SEL>,
<0x00000010 PINMUX_DEDICATED_IO_5_SEL>,
<0x00000014 PINMUX_DEDICATED_IO_6_SEL>,
<0x00000018 PINMUX_DEDICATED_IO_7_SEL>,
<0x0000001c PINMUX_DEDICATED_IO_8_SEL>,
<0x00000020 PINMUX_DEDICATED_IO_9_SEL>,
<0x00000024 PINMUX_DEDICATED_IO_10_SEL>,
<0x00000028 PINMUX_DEDICATED_IO_11_SEL>,
<0x0000002c PINMUX_DEDICATED_IO_12_SEL>,
<0x00000030 PINMUX_DEDICATED_IO_13_SEL>,
<0x00000034 PINMUX_DEDICATED_IO_14_SEL>,
<0x00000038 PINMUX_DEDICATED_IO_15_SEL>,
<0x0000003c PINMUX_DEDICATED_IO_16_SEL>,
<0x00000040 PINMUX_DEDICATED_IO_17_SEL>;
u-boot,dm-pre-reloc;
};
dedicated_cfg {
reg = <0xffd07200 0x00000200>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x003f3f3f>;
pinctrl-single,pins =
<0x00000100 CONFIG_IO_BANK_VSEL>,
<0x00000104 CONFIG_IO_MACRO (CONFIG_IO_1)>,
<0x00000108 CONFIG_IO_MACRO (CONFIG_IO_2)>,
<0x0000010c CONFIG_IO_MACRO (CONFIG_IO_3)>,
<0x00000110 CONFIG_IO_MACRO (CONFIG_IO_4)>,
<0x00000114 CONFIG_IO_MACRO (CONFIG_IO_5)>,
<0x00000118 CONFIG_IO_MACRO (CONFIG_IO_6)>,
<0x0000011c CONFIG_IO_MACRO (CONFIG_IO_7)>,
<0x00000120 CONFIG_IO_MACRO (CONFIG_IO_8)>,
<0x00000124 CONFIG_IO_MACRO (CONFIG_IO_9)>,
<0x00000128 CONFIG_IO_MACRO (CONFIG_IO_10)>,
<0x0000012c CONFIG_IO_MACRO (CONFIG_IO_11)>,
<0x00000130 CONFIG_IO_MACRO (CONFIG_IO_12)>,
<0x00000134 CONFIG_IO_MACRO (CONFIG_IO_13)>,
<0x00000138 CONFIG_IO_MACRO (CONFIG_IO_14)>,
<0x0000013c CONFIG_IO_MACRO (CONFIG_IO_15)>,
<0x00000140 CONFIG_IO_MACRO (CONFIG_IO_16)>,
<0x00000144 CONFIG_IO_MACRO (CONFIG_IO_17)>;
u-boot,dm-pre-reloc;
};
fpga {
reg = <0xffd07400 0x00000100>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x00000001>;
pinctrl-single,pins =
<0x00000000 PINMUX_RGMII0_USEFPGA_SEL>,
<0x00000004 PINMUX_RGMII1_USEFPGA_SEL>,
<0x00000008 PINMUX_RGMII2_USEFPGA_SEL>,
<0x0000000c PINMUX_I2C0_USEFPGA_SEL>,
<0x00000010 PINMUX_I2C1_USEFPGA_SEL>,
<0x00000014 PINMUX_I2CEMAC0_USEFPGA_SEL>,
<0x00000018 PINMUX_I2CEMAC1_USEFPGA_SEL>,
<0x0000001c PINMUX_I2CEMAC2_USEFPGA_SEL>,
<0x00000020 PINMUX_NAND_USEFPGA_SEL>,
<0x00000024 PINMUX_QSPI_USEFPGA_SEL>,
<0x00000028 PINMUX_SDMMC_USEFPGA_SEL>,
<0x0000002c PINMUX_SPIM0_USEFPGA_SEL>,
<0x00000030 PINMUX_SPIM1_USEFPGA_SEL>,
<0x00000034 PINMUX_SPIS0_USEFPGA_SEL>,
<0x00000038 PINMUX_SPIS1_USEFPGA_SEL>,
<0x0000003c PINMUX_UART0_USEFPGA_SEL>,
<0x00000040 PINMUX_UART1_USEFPGA_SEL>;
u-boot,dm-pre-reloc;
};
};
i_noc: noc@0xffd10000 {
compatible = "altr,socfpga-a10-noc";
reg = <0xffd10000 0x00008000>;
reg-names = "mpu_m0";
u-boot,dm-pre-reloc;
firewall {
mpu0 = <0x00000000 0x0000ffff>;
l3-0 = <0x00000000 0x0000ffff>;
fpga2sdram0-0 = <0x00000000 0x0000ffff>;
fpga2sdram1-0 = <0x00000000 0x0000ffff>;
fpga2sdram2-0 = <0x00000000 0x0000ffff>;
u-boot,dm-pre-reloc;
};
};
hps_fpgabridge0: fpgabridge@0 {
compatible = "altr,socfpga-hps2fpga-bridge";
init-val = <H2F_AXI_MASTER>;
u-boot,dm-pre-reloc;
};
hps_fpgabridge1: fpgabridge@1 {
compatible = "altr,socfpga-lwhps2fpga-bridge";
init-val = <LWH2F_AXI_MASTER>;
u-boot,dm-pre-reloc;
};
hps_fpgabridge2: fpgabridge@2 {
compatible = "altr,socfpga-fpga2hps-bridge";
init-val = <F2H_AXI_SLAVE>;
u-boot,dm-pre-reloc;
};
hps_fpgabridge3: fpgabridge@3 {
compatible = "altr,socfpga-fpga2sdram0-bridge";
init-val = <F2SDRAM0_AXI_SLAVE>;
u-boot,dm-pre-reloc;
};
hps_fpgabridge4: fpgabridge@4 {
compatible = "altr,socfpga-fpga2sdram1-bridge";
init-val = <F2SDRAM1_AXI_SLAVE>;
u-boot,dm-pre-reloc;
};
hps_fpgabridge5: fpgabridge@5 {
compatible = "altr,socfpga-fpga2sdram2-bridge";
init-val = <F2SDRAM2_AXI_SLAVE>;
u-boot,dm-pre-reloc;
};
};

4
arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
View file

@ -15,3 +15,7 @@
&uart1 {
u-boot,dm-pre-reloc;
};
&watchdog1 {
u-boot,dm-pre-reloc;
};

3
arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
View file

@ -3,7 +3,8 @@
* Copyright (C) 2014-2015, 2020 Intel. All rights reserved.
*/
#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
#include "socfpga_arria10_socdk_sdmmc_handoff.h"
#include "socfpga_arria10-handoff.dtsi"
#include "socfpga_arria10_handoff_u-boot.dtsi"
#include "socfpga_arria10_socdk-u-boot.dtsi"

329
arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
View file

@ -1,329 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright (C) 2016-2017 Intel Corporation
*
*<auto-generated>
* This code was generated by a tool based on
* handoffs from both Qsys and Quartus.
*
* Changes to this file may be lost if
* the code is regenerated.
*</auto-generated>
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
/* Clock sources */
clocks {
#address-cells = <1>;
#size-cells = <1>;
/* Clock source: altera_arria10_hps_eosc1 */
altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "altera_arria10_hps_eosc1-clk";
};
/* Clock source: altera_arria10_hps_cb_intosc_ls */
altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <60000000>;
clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
};
/* Clock source: altera_arria10_hps_f2h_free */
altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
clock-output-names = "altera_arria10_hps_f2h_free-clk";
};
};
/*
* Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver
* Version: 1.0
* Binding: device
*/
i_clk_mgr: clock_manager@0xffd04000 {
compatible = "altr,socfpga-a10-clk-init";
reg = <0xffd04000 0x00000200>;
reg-names = "soc_clock_manager_OCP_SLV";
/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */
mainpll {
vco0-psrc = <0>; /* Field: vco0.psrc */
vco1-denom = <1>; /* Field: vco1.denom */
vco1-numer = <191>; /* Field: vco1.numer */
mpuclk-cnt = <0>; /* Field: mpuclk.cnt */
mpuclk-src = <0>; /* Field: mpuclk.src */
nocclk-cnt = <0>; /* Field: nocclk.cnt */
nocclk-src = <0>; /* Field: nocclk.src */
cntr2clk-cnt = <900>; /* Field: cntr2clk.cnt */
cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */
cntr4clk-cnt = <900>; /* Field: cntr4clk.cnt */
cntr5clk-cnt = <900>; /* Field: cntr5clk.cnt */
cntr6clk-cnt = <900>; /* Field: cntr6clk.cnt */
cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */
cntr7clk-src = <0>; /* Field: cntr7clk.src */
cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */
cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */
cntr9clk-src = <0>; /* Field: cntr9clk.src */
cntr15clk-cnt = <900>; /* Field: cntr15clk.cnt */
nocdiv-l4mainclk = <0>; /* Field: nocdiv.l4mainclk */
nocdiv-l4mpclk = <0>; /* Field: nocdiv.l4mpclk */
nocdiv-l4spclk = <2>; /* Field: nocdiv.l4spclk */
nocdiv-csatclk = <0>; /* Field: nocdiv.csatclk */
nocdiv-cstraceclk = <1>; /* Field: nocdiv.cstraceclk */
nocdiv-cspdbgclk = <1>; /* Field: nocdiv.cspdbgclk */
};
/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */
perpll {
vco0-psrc = <0>; /* Field: vco0.psrc */
vco1-denom = <1>; /* Field: vco1.denom */
vco1-numer = <159>; /* Field: vco1.numer */
cntr2clk-cnt = <7>; /* Field: cntr2clk.cnt */
cntr2clk-src = <1>; /* Field: cntr2clk.src */
cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */
cntr3clk-src = <1>; /* Field: cntr3clk.src */
cntr4clk-cnt = <19>; /* Field: cntr4clk.cnt */
cntr4clk-src = <1>; /* Field: cntr4clk.src */
cntr5clk-cnt = <499>; /* Field: cntr5clk.cnt */
cntr5clk-src = <1>; /* Field: cntr5clk.src */
cntr6clk-cnt = <9>; /* Field: cntr6clk.cnt */
cntr6clk-src = <1>; /* Field: cntr6clk.src */
cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */
cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */
cntr8clk-src = <0>; /* Field: cntr8clk.src */
cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */
emacctl-emac0sel = <0>; /* Field: emacctl.emac0sel */
emacctl-emac1sel = <0>; /* Field: emacctl.emac1sel */
emacctl-emac2sel = <0>; /* Field: emacctl.emac2sel */
gpiodiv-gpiodbclk = <32000>; /* Field: gpiodiv.gpiodbclk */
};
/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */
alteragrp {
nocclk = <0x0384000b>; /* Register: nocclk */
mpuclk = <0x03840001>; /* Register: mpuclk */
};
};
/*
* Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
* Version: 1.0
* Binding: pinmux
*/
i_io48_pin_mux: pinmux@0xffd07000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "pinctrl-single";
reg = <0xffd07000 0x00000800>;
reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */
shared {
reg = <0xffd07000 0x00000200>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
pinctrl-single,pins =
<0x00000000 0x00000008>, /* Register: pinmux_shared_io_q1_1 */
<0x00000004 0x00000008>, /* Register: pinmux_shared_io_q1_2 */
<0x00000008 0x00000008>, /* Register: pinmux_shared_io_q1_3 */
<0x0000000c 0x00000008>, /* Register: pinmux_shared_io_q1_4 */
<0x00000010 0x00000008>, /* Register: pinmux_shared_io_q1_5 */
<0x00000014 0x00000008>, /* Register: pinmux_shared_io_q1_6 */
<0x00000018 0x00000008>, /* Register: pinmux_shared_io_q1_7 */
<0x0000001c 0x00000008>, /* Register: pinmux_shared_io_q1_8 */
<0x00000020 0x00000008>, /* Register: pinmux_shared_io_q1_9 */
<0x00000024 0x00000008>, /* Register: pinmux_shared_io_q1_10 */
<0x00000028 0x00000008>, /* Register: pinmux_shared_io_q1_11 */
<0x0000002c 0x00000008>, /* Register: pinmux_shared_io_q1_12 */
<0x00000030 0x00000004>, /* Register: pinmux_shared_io_q2_1 */
<0x00000034 0x00000004>, /* Register: pinmux_shared_io_q2_2 */
<0x00000038 0x00000004>, /* Register: pinmux_shared_io_q2_3 */
<0x0000003c 0x00000004>, /* Register: pinmux_shared_io_q2_4 */
<0x00000040 0x00000004>, /* Register: pinmux_shared_io_q2_5 */
<0x00000044 0x00000004>, /* Register: pinmux_shared_io_q2_6 */
<0x00000048 0x00000004>, /* Register: pinmux_shared_io_q2_7 */
<0x0000004c 0x00000004>, /* Register: pinmux_shared_io_q2_8 */
<0x00000050 0x00000004>, /* Register: pinmux_shared_io_q2_9 */
<0x00000054 0x00000004>, /* Register: pinmux_shared_io_q2_10 */
<0x00000058 0x00000004>, /* Register: pinmux_shared_io_q2_11 */
<0x0000005c 0x00000004>, /* Register: pinmux_shared_io_q2_12 */
<0x00000060 0x00000003>, /* Register: pinmux_shared_io_q3_1 */
<0x00000064 0x00000003>, /* Register: pinmux_shared_io_q3_2 */
<0x00000068 0x00000003>, /* Register: pinmux_shared_io_q3_3 */
<0x0000006c 0x00000003>, /* Register: pinmux_shared_io_q3_4 */
<0x00000070 0x00000003>, /* Register: pinmux_shared_io_q3_5 */
<0x00000074 0x0000000f>, /* Register: pinmux_shared_io_q3_6 */
<0x00000078 0x0000000a>, /* Register: pinmux_shared_io_q3_7 */
<0x0000007c 0x0000000a>, /* Register: pinmux_shared_io_q3_8 */
<0x00000080 0x0000000a>, /* Register: pinmux_shared_io_q3_9 */
<0x00000084 0x0000000a>, /* Register: pinmux_shared_io_q3_10 */
<0x00000088 0x00000001>, /* Register: pinmux_shared_io_q3_11 */
<0x0000008c 0x00000001>, /* Register: pinmux_shared_io_q3_12 */
<0x00000090 0x00000000>, /* Register: pinmux_shared_io_q4_1 */
<0x00000094 0x00000000>, /* Register: pinmux_shared_io_q4_2 */
<0x00000098 0x0000000f>, /* Register: pinmux_shared_io_q4_3 */
<0x0000009c 0x0000000c>, /* Register: pinmux_shared_io_q4_4 */
<0x000000a0 0x0000000f>, /* Register: pinmux_shared_io_q4_5 */
<0x000000a4 0x0000000f>, /* Register: pinmux_shared_io_q4_6 */
<0x000000a8 0x0000000a>, /* Register: pinmux_shared_io_q4_7 */
<0x000000ac 0x0000000a>, /* Register: pinmux_shared_io_q4_8 */
<0x000000b0 0x0000000c>, /* Register: pinmux_shared_io_q4_9 */
<0x000000b4 0x0000000c>, /* Register: pinmux_shared_io_q4_10 */
<0x000000b8 0x0000000c>, /* Register: pinmux_shared_io_q4_11 */
<0x000000bc 0x0000000c>; /* Register: pinmux_shared_io_q4_12 */
};
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
dedicated {
reg = <0xffd07200 0x00000200>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
pinctrl-single,pins =
<0x0000000c 0x00000008>, /* Register: pinmux_dedicated_io_4 */
<0x00000010 0x00000008>, /* Register: pinmux_dedicated_io_5 */
<0x00000014 0x00000008>, /* Register: pinmux_dedicated_io_6 */
<0x00000018 0x00000008>, /* Register: pinmux_dedicated_io_7 */
<0x0000001c 0x00000008>, /* Register: pinmux_dedicated_io_8 */
<0x00000020 0x00000008>, /* Register: pinmux_dedicated_io_9 */
<0x00000024 0x0000000a>, /* Register: pinmux_dedicated_io_10 */
<0x00000028 0x0000000a>, /* Register: pinmux_dedicated_io_11 */
<0x0000002c 0x00000008>, /* Register: pinmux_dedicated_io_12 */
<0x00000030 0x00000008>, /* Register: pinmux_dedicated_io_13 */
<0x00000034 0x00000008>, /* Register: pinmux_dedicated_io_14 */
<0x00000038 0x00000008>, /* Register: pinmux_dedicated_io_15 */
<0x0000003c 0x0000000d>, /* Register: pinmux_dedicated_io_16 */
<0x00000040 0x0000000d>; /* Register: pinmux_dedicated_io_17 */
};
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
dedicated_cfg {
reg = <0xffd07200 0x00000200>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x003f3f3f>;
pinctrl-single,pins =
<0x00000100 0x00000101>, /* Register: configuration_dedicated_io_bank */
<0x00000104 0x000b080a>, /* Register: configuration_dedicated_io_1 */
<0x00000108 0x000b080a>, /* Register: configuration_dedicated_io_2 */
<0x0000010c 0x000b080a>, /* Register: configuration_dedicated_io_3 */
<0x00000110 0x000a282a>, /* Register: configuration_dedicated_io_4 */
<0x00000114 0x000a282a>, /* Register: configuration_dedicated_io_5 */
<0x00000118 0x0008282a>, /* Register: configuration_dedicated_io_6 */
<0x0000011c 0x000a282a>, /* Register: configuration_dedicated_io_7 */
<0x00000120 0x000a282a>, /* Register: configuration_dedicated_io_8 */
<0x00000124 0x000a282a>, /* Register: configuration_dedicated_io_9 */
<0x00000128 0x00090000>, /* Register: configuration_dedicated_io_10 */
<0x0000012c 0x00090000>, /* Register: configuration_dedicated_io_11 */
<0x00000130 0x000b282a>, /* Register: configuration_dedicated_io_12 */
<0x00000134 0x000b282a>, /* Register: configuration_dedicated_io_13 */
<0x00000138 0x000b282a>, /* Register: configuration_dedicated_io_14 */
<0x0000013c 0x000b282a>, /* Register: configuration_dedicated_io_15 */
<0x00000140 0x0008282a>, /* Register: configuration_dedicated_io_16 */
<0x00000144 0x000a282a>; /* Register: configuration_dedicated_io_17 */
};
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */
fpga {
reg = <0xffd07400 0x00000100>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x00000001>;
pinctrl-single,pins =
<0x00000000 0x00000000>, /* Register: pinmux_emac0_usefpga */
<0x00000004 0x00000000>, /* Register: pinmux_emac1_usefpga */
<0x00000008 0x00000000>, /* Register: pinmux_emac2_usefpga */
<0x0000000c 0x00000000>, /* Register: pinmux_i2c0_usefpga */
<0x00000010 0x00000000>, /* Register: pinmux_i2c1_usefpga */
<0x00000014 0x00000000>, /* Register: pinmux_i2c_emac0_usefpga */
<0x00000018 0x00000000>, /* Register: pinmux_i2c_emac1_usefpga */
<0x0000001c 0x00000000>, /* Register: pinmux_i2c_emac2_usefpga */
<0x00000020 0x00000000>, /* Register: pinmux_nand_usefpga */
<0x00000024 0x00000000>, /* Register: pinmux_qspi_usefpga */
<0x00000028 0x00000000>, /* Register: pinmux_sdmmc_usefpga */
<0x0000002c 0x00000000>, /* Register: pinmux_spim0_usefpga */
<0x00000030 0x00000000>, /* Register: pinmux_spim1_usefpga */
<0x00000034 0x00000000>, /* Register: pinmux_spis0_usefpga */
<0x00000038 0x00000000>, /* Register: pinmux_spis1_usefpga */
<0x0000003c 0x00000000>, /* Register: pinmux_uart0_usefpga */
<0x00000040 0x00000000>; /* Register: pinmux_uart1_usefpga */
};
};
/*
* Driver: altera_arria10_soc_noc_arria10_uboot_driver
* Version: 1.0
* Binding: device
*/
i_noc: noc@0xffd10000 {
compatible = "altr,socfpga-a10-noc";
reg = <0xffd10000 0x00008000>;
reg-names = "mpu_m0";
firewall {
/*
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit
*/
mpu0 = <0x00000000 0x0000ffff>;
/*
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit
*/
l3-0 = <0x00000000 0x0000ffff>;
/*
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.base
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.limit
*/
fpga2sdram0-0 = <0x00000000 0x0000ffff>;
/*
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.base
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.limit
*/
fpga2sdram1-0 = <0x00000000 0x0000ffff>;
/*
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.base
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.limit
*/
fpga2sdram2-0 = <0x00000000 0x0000ffff>;
};
};
hps_fpgabridge0: fpgabridge@0 {
compatible = "altr,socfpga-hps2fpga-bridge";
init-val = <1>;
};
hps_fpgabridge1: fpgabridge@1 {
compatible = "altr,socfpga-lwhps2fpga-bridge";
init-val = <1>;
};
hps_fpgabridge2: fpgabridge@2 {
compatible = "altr,socfpga-fpga2hps-bridge";
init-val = <1>;
};
hps_fpgabridge3: fpgabridge@3 {
compatible = "altr,socfpga-fpga2sdram0-bridge";
init-val = <1>;
};
hps_fpgabridge4: fpgabridge@4 {
compatible = "altr,socfpga-fpga2sdram1-bridge";
init-val = <0>;
};
hps_fpgabridge5: fpgabridge@5 {
compatible = "altr,socfpga-fpga2sdram2-bridge";
init-val = <1>;
};
};

305
arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h Normal file
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@ -0,0 +1,305 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Intel Arria 10 SoCFPGA configuration
*/
#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
#define __SOCFPGA_ARRIA10_CONFIG_H__
/* Clocks */
#define CB_INTOSC_LS_CLK_HZ 60000000
#define EMAC0_CLK_HZ 250000000
#define EMAC1_CLK_HZ 250000000
#define EMAC2_CLK_HZ 250000000
#define EOSC1_CLK_HZ 25000000
#define F2H_FREE_CLK_HZ 200000000
#define H2F_USER0_CLK_HZ 400000000
#define H2F_USER1_CLK_HZ 400000000
#define L3_MAIN_FREE_CLK_HZ 200000000
#define SDMMC_CLK_HZ 200000000
#define TPIU_CLK_HZ 100000000
#define MAINPLLGRP_CNTR15CLK_CNT 900
#define MAINPLLGRP_CNTR2CLK_CNT 900
#define MAINPLLGRP_CNTR3CLK_CNT 900
#define MAINPLLGRP_CNTR4CLK_CNT 900
#define MAINPLLGRP_CNTR5CLK_CNT 900
#define MAINPLLGRP_CNTR6CLK_CNT 900
#define MAINPLLGRP_CNTR7CLK_CNT 900
#define MAINPLLGRP_CNTR7CLK_SRC 0
#define MAINPLLGRP_CNTR8CLK_CNT 900
#define MAINPLLGRP_CNTR9CLK_CNT 900
#define MAINPLLGRP_CNTR9CLK_SRC 0
#define MAINPLLGRP_MPUCLK_CNT 0
#define MAINPLLGRP_MPUCLK_SRC 0
#define MAINPLLGRP_NOCCLK_CNT 0
#define MAINPLLGRP_NOCCLK_SRC 0
#define MAINPLLGRP_NOCDIV_CSATCLK 0
#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1
#define MAINPLLGRP_NOCDIV_CSTRACECLK 1
#define MAINPLLGRP_NOCDIV_L4MAINCLK 0
#define MAINPLLGRP_NOCDIV_L4MPCLK 0
#define MAINPLLGRP_NOCDIV_L4SPCLK 2
#define MAINPLLGRP_VCO0_PSRC 0
#define MAINPLLGRP_VCO1_DENOM 1
#define MAINPLLGRP_VCO1_NUMER 191
#define PERPLLGRP_CNTR2CLK_CNT 7
#define PERPLLGRP_CNTR2CLK_SRC 1
#define PERPLLGRP_CNTR3CLK_CNT 900
#define PERPLLGRP_CNTR3CLK_SRC 1
#define PERPLLGRP_CNTR4CLK_CNT 19
#define PERPLLGRP_CNTR4CLK_SRC 1
#define PERPLLGRP_CNTR5CLK_CNT 499
#define PERPLLGRP_CNTR5CLK_SRC 1
#define PERPLLGRP_CNTR6CLK_CNT 9
#define PERPLLGRP_CNTR6CLK_SRC 1
#define PERPLLGRP_CNTR7CLK_CNT 900
#define PERPLLGRP_CNTR8CLK_CNT 900
#define PERPLLGRP_CNTR8CLK_SRC 0
#define PERPLLGRP_CNTR9CLK_CNT 900
#define PERPLLGRP_EMACCTL_EMAC0SEL 0
#define PERPLLGRP_EMACCTL_EMAC1SEL 0
#define PERPLLGRP_EMACCTL_EMAC2SEL 0
#define PERPLLGRP_GPIODIV_GPIODBCLK 32000
#define PERPLLGRP_VCO0_PSRC 0
#define PERPLLGRP_VCO1_DENOM 1
#define PERPLLGRP_VCO1_NUMER 159
#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16
#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8
#define CLKMGR_TESTIOCTRL_PERICLKSEL 8
#define ALTERAGRP_MPUCLK_MAINCNT 1
#define ALTERAGRP_MPUCLK_PERICNT 900
#define ALTERAGRP_NOCCLK_MAINCNT 11
#define ALTERAGRP_NOCCLK_PERICNT 900
#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
(ALTERAGRP_MPUCLK_MAINCNT))
#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \
(ALTERAGRP_NOCCLK_MAINCNT))
/* Pin Mux Configuration */
#define CONFIG_IO_10_INPUT_BUF_EN 0
#define CONFIG_IO_10_PD_DRV_STRG 0
#define CONFIG_IO_10_PD_SLW_RT 0
#define CONFIG_IO_10_PU_DRV_STRG 0
#define CONFIG_IO_10_PU_SLW_RT 0
#define CONFIG_IO_10_RTRIM 1
#define CONFIG_IO_10_WK_PU_EN 1
#define CONFIG_IO_11_INPUT_BUF_EN 0
#define CONFIG_IO_11_PD_DRV_STRG 0
#define CONFIG_IO_11_PD_SLW_RT 0
#define CONFIG_IO_11_PU_DRV_STRG 0
#define CONFIG_IO_11_PU_SLW_RT 0
#define CONFIG_IO_11_RTRIM 1
#define CONFIG_IO_11_WK_PU_EN 1
#define CONFIG_IO_12_INPUT_BUF_EN 1
#define CONFIG_IO_12_PD_DRV_STRG 10
#define CONFIG_IO_12_PD_SLW_RT 1
#define CONFIG_IO_12_PU_DRV_STRG 8
#define CONFIG_IO_12_PU_SLW_RT 1
#define CONFIG_IO_12_RTRIM 1
#define CONFIG_IO_12_WK_PU_EN 1
#define CONFIG_IO_13_INPUT_BUF_EN 1
#define CONFIG_IO_13_PD_DRV_STRG 10
#define CONFIG_IO_13_PD_SLW_RT 1
#define CONFIG_IO_13_PU_DRV_STRG 8
#define CONFIG_IO_13_PU_SLW_RT 1
#define CONFIG_IO_13_RTRIM 1
#define CONFIG_IO_13_WK_PU_EN 1
#define CONFIG_IO_14_INPUT_BUF_EN 1
#define CONFIG_IO_14_PD_DRV_STRG 10
#define CONFIG_IO_14_PD_SLW_RT 1
#define CONFIG_IO_14_PU_DRV_STRG 8
#define CONFIG_IO_14_PU_SLW_RT 1
#define CONFIG_IO_14_RTRIM 1
#define CONFIG_IO_14_WK_PU_EN 1
#define CONFIG_IO_15_INPUT_BUF_EN 1
#define CONFIG_IO_15_PD_DRV_STRG 10
#define CONFIG_IO_15_PD_SLW_RT 1
#define CONFIG_IO_15_PU_DRV_STRG 8
#define CONFIG_IO_15_PU_SLW_RT 1
#define CONFIG_IO_15_RTRIM 1
#define CONFIG_IO_15_WK_PU_EN 1
#define CONFIG_IO_16_INPUT_BUF_EN 0
#define CONFIG_IO_16_PD_DRV_STRG 10
#define CONFIG_IO_16_PD_SLW_RT 1
#define CONFIG_IO_16_PU_DRV_STRG 8
#define CONFIG_IO_16_PU_SLW_RT 1
#define CONFIG_IO_16_RTRIM 1
#define CONFIG_IO_16_WK_PU_EN 0
#define CONFIG_IO_17_INPUT_BUF_EN 1
#define CONFIG_IO_17_PD_DRV_STRG 10
#define CONFIG_IO_17_PD_SLW_RT 1
#define CONFIG_IO_17_PU_DRV_STRG 8
#define CONFIG_IO_17_PU_SLW_RT 1
#define CONFIG_IO_17_RTRIM 1
#define CONFIG_IO_17_WK_PU_EN 0
#define CONFIG_IO_1_INPUT_BUF_EN 1
#define CONFIG_IO_1_PD_DRV_STRG 10
#define CONFIG_IO_1_PD_SLW_RT 0
#define CONFIG_IO_1_PU_DRV_STRG 8
#define CONFIG_IO_1_PU_SLW_RT 0
#define CONFIG_IO_1_RTRIM 1
#define CONFIG_IO_1_WK_PU_EN 1
#define CONFIG_IO_2_INPUT_BUF_EN 1
#define CONFIG_IO_2_PD_DRV_STRG 10
#define CONFIG_IO_2_PD_SLW_RT 0
#define CONFIG_IO_2_PU_DRV_STRG 8
#define CONFIG_IO_2_PU_SLW_RT 0
#define CONFIG_IO_2_RTRIM 1
#define CONFIG_IO_2_WK_PU_EN 1
#define CONFIG_IO_3_INPUT_BUF_EN 1
#define CONFIG_IO_3_PD_DRV_STRG 10
#define CONFIG_IO_3_PD_SLW_RT 0
#define CONFIG_IO_3_PU_DRV_STRG 8
#define CONFIG_IO_3_PU_SLW_RT 0
#define CONFIG_IO_3_RTRIM 1
#define CONFIG_IO_3_WK_PU_EN 1
#define CONFIG_IO_4_INPUT_BUF_EN 1
#define CONFIG_IO_4_PD_DRV_STRG 10
#define CONFIG_IO_4_PD_SLW_RT 1
#define CONFIG_IO_4_PU_DRV_STRG 8
#define CONFIG_IO_4_PU_SLW_RT 1
#define CONFIG_IO_4_RTRIM 1
#define CONFIG_IO_4_WK_PU_EN 0
#define CONFIG_IO_5_INPUT_BUF_EN 1
#define CONFIG_IO_5_PD_DRV_STRG 10
#define CONFIG_IO_5_PD_SLW_RT 1
#define CONFIG_IO_5_PU_DRV_STRG 8
#define CONFIG_IO_5_PU_SLW_RT 1
#define CONFIG_IO_5_RTRIM 1
#define CONFIG_IO_5_WK_PU_EN 0
#define CONFIG_IO_6_INPUT_BUF_EN 0
#define CONFIG_IO_6_PD_DRV_STRG 10
#define CONFIG_IO_6_PD_SLW_RT 1
#define CONFIG_IO_6_PU_DRV_STRG 8
#define CONFIG_IO_6_PU_SLW_RT 1
#define CONFIG_IO_6_RTRIM 1
#define CONFIG_IO_6_WK_PU_EN 0
#define CONFIG_IO_7_INPUT_BUF_EN 1
#define CONFIG_IO_7_PD_DRV_STRG 10
#define CONFIG_IO_7_PD_SLW_RT 1
#define CONFIG_IO_7_PU_DRV_STRG 8
#define CONFIG_IO_7_PU_SLW_RT 1
#define CONFIG_IO_7_RTRIM 1
#define CONFIG_IO_7_WK_PU_EN 0
#define CONFIG_IO_8_INPUT_BUF_EN 1
#define CONFIG_IO_8_PD_DRV_STRG 10
#define CONFIG_IO_8_PD_SLW_RT 1
#define CONFIG_IO_8_PU_DRV_STRG 8
#define CONFIG_IO_8_PU_SLW_RT 1
#define CONFIG_IO_8_RTRIM 1
#define CONFIG_IO_8_WK_PU_EN 0
#define CONFIG_IO_9_INPUT_BUF_EN 1
#define CONFIG_IO_9_PD_DRV_STRG 10
#define CONFIG_IO_9_PD_SLW_RT 1
#define CONFIG_IO_9_PU_DRV_STRG 8
#define CONFIG_IO_9_PU_SLW_RT 1
#define CONFIG_IO_9_RTRIM 1
#define CONFIG_IO_9_WK_PU_EN 0
#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
#define PINMUX_DEDICATED_IO_10_SEL 10
#define PINMUX_DEDICATED_IO_11_SEL 10
#define PINMUX_DEDICATED_IO_12_SEL 8
#define PINMUX_DEDICATED_IO_13_SEL 8
#define PINMUX_DEDICATED_IO_14_SEL 8
#define PINMUX_DEDICATED_IO_15_SEL 8
#define PINMUX_DEDICATED_IO_16_SEL 13
#define PINMUX_DEDICATED_IO_17_SEL 13
#define PINMUX_DEDICATED_IO_4_SEL 8
#define PINMUX_DEDICATED_IO_5_SEL 8
#define PINMUX_DEDICATED_IO_6_SEL 8
#define PINMUX_DEDICATED_IO_7_SEL 8
#define PINMUX_DEDICATED_IO_8_SEL 8
#define PINMUX_DEDICATED_IO_9_SEL 8
#define PINMUX_I2C0_USEFPGA_SEL 0
#define PINMUX_I2C1_USEFPGA_SEL 0
#define PINMUX_I2CEMAC0_USEFPGA_SEL 0
#define PINMUX_I2CEMAC1_USEFPGA_SEL 0
#define PINMUX_I2CEMAC2_USEFPGA_SEL 0
#define PINMUX_NAND_USEFPGA_SEL 0
#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0
#define PINMUX_QSPI_USEFPGA_SEL 0
#define PINMUX_RGMII0_USEFPGA_SEL 0
#define PINMUX_RGMII1_USEFPGA_SEL 0
#define PINMUX_RGMII2_USEFPGA_SEL 0
#define PINMUX_SDMMC_USEFPGA_SEL 0
#define PINMUX_SHARED_IO_Q1_10_SEL 8
#define PINMUX_SHARED_IO_Q1_11_SEL 8
#define PINMUX_SHARED_IO_Q1_12_SEL 8
#define PINMUX_SHARED_IO_Q1_1_SEL 8
#define PINMUX_SHARED_IO_Q1_2_SEL 8
#define PINMUX_SHARED_IO_Q1_3_SEL 8
#define PINMUX_SHARED_IO_Q1_4_SEL 8
#define PINMUX_SHARED_IO_Q1_5_SEL 8
#define PINMUX_SHARED_IO_Q1_6_SEL 8
#define PINMUX_SHARED_IO_Q1_7_SEL 8
#define PINMUX_SHARED_IO_Q1_8_SEL 8
#define PINMUX_SHARED_IO_Q1_9_SEL 8
#define PINMUX_SHARED_IO_Q2_10_SEL 4
#define PINMUX_SHARED_IO_Q2_11_SEL 4
#define PINMUX_SHARED_IO_Q2_12_SEL 4
#define PINMUX_SHARED_IO_Q2_1_SEL 4
#define PINMUX_SHARED_IO_Q2_2_SEL 4
#define PINMUX_SHARED_IO_Q2_3_SEL 4
#define PINMUX_SHARED_IO_Q2_4_SEL 4
#define PINMUX_SHARED_IO_Q2_5_SEL 4
#define PINMUX_SHARED_IO_Q2_6_SEL 4
#define PINMUX_SHARED_IO_Q2_7_SEL 4
#define PINMUX_SHARED_IO_Q2_8_SEL 4
#define PINMUX_SHARED_IO_Q2_9_SEL 4
#define PINMUX_SHARED_IO_Q3_10_SEL 10
#define PINMUX_SHARED_IO_Q3_11_SEL 1
#define PINMUX_SHARED_IO_Q3_12_SEL 1
#define PINMUX_SHARED_IO_Q3_1_SEL 3
#define PINMUX_SHARED_IO_Q3_2_SEL 3
#define PINMUX_SHARED_IO_Q3_3_SEL 3
#define PINMUX_SHARED_IO_Q3_4_SEL 3
#define PINMUX_SHARED_IO_Q3_5_SEL 3
#define PINMUX_SHARED_IO_Q3_6_SEL 15
#define PINMUX_SHARED_IO_Q3_7_SEL 10
#define PINMUX_SHARED_IO_Q3_8_SEL 10
#define PINMUX_SHARED_IO_Q3_9_SEL 10
#define PINMUX_SHARED_IO_Q4_10_SEL 12
#define PINMUX_SHARED_IO_Q4_11_SEL 12
#define PINMUX_SHARED_IO_Q4_12_SEL 12
#define PINMUX_SHARED_IO_Q4_1_SEL 0
#define PINMUX_SHARED_IO_Q4_2_SEL 0
#define PINMUX_SHARED_IO_Q4_3_SEL 15
#define PINMUX_SHARED_IO_Q4_4_SEL 12
#define PINMUX_SHARED_IO_Q4_5_SEL 15
#define PINMUX_SHARED_IO_Q4_6_SEL 15
#define PINMUX_SHARED_IO_Q4_7_SEL 10
#define PINMUX_SHARED_IO_Q4_8_SEL 15
#define PINMUX_SHARED_IO_Q4_9_SEL 12
#define PINMUX_SPIM0_USEFPGA_SEL 0
#define PINMUX_SPIM1_USEFPGA_SEL 0
#define PINMUX_SPIS0_USEFPGA_SEL 0
#define PINMUX_SPIS1_USEFPGA_SEL 0
#define PINMUX_UART0_USEFPGA_SEL 0
#define PINMUX_UART1_USEFPGA_SEL 0
#define PINMUX_USB0_USEFPGA_SEL 0
#define PINMUX_USB1_USEFPGA_SEL 0
/* Bridge Configuration */
#define F2H_AXI_SLAVE 1
#define F2SDRAM0_AXI_SLAVE 1
#define F2SDRAM1_AXI_SLAVE 0
#define F2SDRAM2_AXI_SLAVE 1
#define H2F_AXI_MASTER 1
#define LWH2F_AXI_MASTER 1
/* Voltage Select for Config IO */
#define CONFIG_IO_BANK_VSEL \
(((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
(CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
/* Macro for Config IO bit mapping */
#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
((NAME ## _WK_PU_EN & 0x1) << 16) | \
((NAME ## _PU_SLW_RT & 0x1) << 13) | \
((NAME ## _PU_DRV_STRG & 0xf) << 8) | \
((NAME ## _PD_SLW_RT & 0x1) << 5) | \
(NAME ## _PD_DRV_STRG & 0x1f))
#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */

1
arch/arm/dts/socfpga_stratix10.dtsi
View file

@ -386,7 +386,6 @@
reg = <0xffd00200 0x100>;
interrupts = <0 117 4>;
resets = <&rst WATCHDOG0_RESET>;
u-boot,dm-pre-reloc;
status = "disabled";
};

1
arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
View file

@ -33,5 +33,6 @@
};
&watchdog0 {
status = "okay";
u-boot,dm-pre-reloc;
};

3
arch/arm/mach-socfpga/Kconfig
View file

@ -35,6 +35,7 @@ config TARGET_SOCFPGA_AGILEX
select ARMV8_SET_SMPEN
select ARMV8_SPIN_TABLE
select CLK
select FPGA_INTEL_SDM_MAILBOX
select NCORE_CACHE
select SPL_CLK if SPL
@ -79,7 +80,7 @@ config TARGET_SOCFPGA_STRATIX10
select ARMV8_MULTIENTRY
select ARMV8_SET_SMPEN
select ARMV8_SPIN_TABLE
select FPGA_STRATIX10
select FPGA_INTEL_SDM_MAILBOX
choice
prompt "Altera SOCFPGA board select"

38
arch/arm/mach-socfpga/include/mach/mailbox_s10.h
View file

@ -67,8 +67,42 @@ enum ALT_SDM_MBOX_RESP_CODE {
MBOX_RESP_UNKNOWN_BR = 2,
/* CMD code not recognized by firmware */
MBOX_RESP_UNKNOWN = 3,
/* Indicates that the device is not configured */
MBOX_RESP_NOT_CONFIGURED = 256,
/* Length setting is not a valid length for this CMD type */
MBOX_RESP_INVALID_LEN = 4,
/* Indirect setting is not valid for this CMD type */
MBOX_RESP_INVALID_INDIRECT_SETTING = 5,
/* HW source which is not allowed to send CMD type */
MBOX_RESP_CMD_INVALID_ON_SRC = 6,
/* Client with ID not associated with any running PR CMD tries to run
* RECONFIG_DATA RECONFIG_STATUS and accessing QSPI / SDMMC using ID
* without exclusive access
*/
MBOX_RESP_CLIENT_ID_NO_MATCH = 8,
/* Address provided to the system is invalid (alignment, range
* permission)
*/
MBOX_RESP_INVALID_ADDR = 0x9,
/* Signature authentication failed */
MBOX_RESP_AUTH_FAIL = 0xA,
/* CMD timed out */
MBOX_RESP_TIMEOUT = 0xB,
/* HW (i.e. QSPI) is not ready (initialized or configured) */
MBOX_RESP_HW_NOT_RDY = 0xC,
/* Invalid license for IID registration */
MBOX_RESP_PUF_ACCCES_FAILED = 0x80,
MBOX_PUF_ENROLL_DISABLE = 0x81,
MBOX_RESP_PUF_ENROLL_FAIL = 0x82,
MBOX_RESP_PUF_RAM_TEST_FAIL = 0x83,
MBOX_RESP_ATTEST_CERT_GEN_FAIL = 0x84,
/* Operation not allowed under current security settings */
MBOX_RESP_NOT_ALLOWED_UNDER_SECURITY_SETTINGS = 0x85,
MBOX_RESP_PUF_TRNG_FAIL = 0x86,
MBOX_RESP_FUSE_ALREADY_BLOWN = 0x87,
MBOX_RESP_INVALID_SIGNATURE = 0x88,
MBOX_RESP_INVALID_HASH = 0x8b,
MBOX_RESP_INVALID_CERTIFICATE = 0x91,
/* Indicates that the device (FPGA or HPS) is not configured */
MBOX_RESP_NOT_CONFIGURED = 0x100,
/* Indicates that the device is busy */
MBOX_RESP_DEVICE_BUSY = 0x1FF,
/* Indicates that there is no valid response available */

12
arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
View file

@ -8,6 +8,7 @@
void reset_deassert_peripherals_handoff(void);
int cpu_has_been_warmreset(void);
void print_reset_info(void);
void socfpga_bridges_reset(int enable);
#define RSTMGR_SOC64_STATUS 0x00
@ -21,8 +22,15 @@ void socfpga_bridges_reset(int enable);
#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004
/* Watchdogs and MPU warm reset mask */
#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00
/* SDM, Watchdogs and MPU warm reset mask */
#define RSTMGR_STAT_SDMWARMRST BIT(1)
#define RSTMGR_STAT_MPU0RST_BITPOS 8
#define RSTMGR_STAT_L4WD0RST_BITPOS 16
#define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \
GENMASK(RSTMGR_STAT_MPU0RST_BITPOS + 3, \
RSTMGR_STAT_MPU0RST_BITPOS) | \
GENMASK(RSTMGR_STAT_L4WD0RST_BITPOS + 3, \
RSTMGR_STAT_L4WD0RST_BITPOS))
/*
* SocFPGA Stratix10 reset IDs, bank mapping is as follows:

8
arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
View file

@ -46,13 +46,21 @@ void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
#define SYSMGR_SOC64_GPO 0xe4
#define SYSMGR_SOC64_GPI 0xe8
#define SYSMGR_SOC64_MPU 0xf0
/* store qspi ref clock */
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200
/* store osc1 clock freq */
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204
/* store fpga clock freq */
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2 0x208
/* reserved for customer use */
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3 0x20c
/* store PSCI_CPU_ON value */
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4 0x210
/* store PSCI_CPU_ON value */
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5 0x214
/* store VBAR_EL3 value */
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6 0x218
/* store VBAR_EL3 value */
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7 0x21c
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8 0x220
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9 0x224

172
arch/arm/mach-socfpga/mailbox_s10.c
View file

@ -29,54 +29,107 @@ DECLARE_GLOBAL_DATA_PTR;
static __always_inline int mbox_polling_resp(u32 rout)
{
u32 rin;
unsigned long i = ~0;
unsigned long i = 2000;
while (i) {
rin = MBOX_READL(MBOX_RIN);
if (rout != rin)
return 0;
udelay(1000);
i--;
}
return -ETIMEDOUT;
}
static __always_inline int mbox_is_cmdbuf_full(u32 cin)
{
return (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == MBOX_READL(MBOX_COUT));
}
static __always_inline int mbox_is_cmdbuf_empty(u32 cin)
{
return (((MBOX_READL(MBOX_COUT) + 1) % MBOX_CMD_BUFFER_SIZE) == cin);
}
static __always_inline int mbox_wait_for_cmdbuf_empty(u32 cin)
{
int timeout = 2000;
while (timeout) {
if (mbox_is_cmdbuf_empty(cin))
return 0;
udelay(1000);
timeout--;
}
return -ETIMEDOUT;
}
static __always_inline int mbox_write_cmd_buffer(u32 *cin, u32 data,
int *is_cmdbuf_overflow)
{
int timeout = 1000;
while (timeout) {
if (mbox_is_cmdbuf_full(*cin)) {
if (is_cmdbuf_overflow &&
*is_cmdbuf_overflow == 0) {
/* Trigger SDM doorbell */
MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
*is_cmdbuf_overflow = 1;
}
udelay(1000);
} else {
/* write header to circular buffer */
MBOX_WRITE_CMD_BUF(data, (*cin)++);
*cin %= MBOX_CMD_BUFFER_SIZE;
MBOX_WRITEL(*cin, MBOX_CIN);
break;
}
timeout--;
}
if (!timeout)
return -ETIMEDOUT;
/* Wait for the SDM to drain the FIFO command buffer */
if (is_cmdbuf_overflow && *is_cmdbuf_overflow)
return mbox_wait_for_cmdbuf_empty(*cin);
return 0;
}
/* Check for available slot and write to circular buffer.
* It also update command valid offset (cin) register.
*/
static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len,
u32 *arg)
{
u32 cin;
u32 cout;
u32 i;
int i, ret;
int is_cmdbuf_overflow = 0;
u32 cin = MBOX_READL(MBOX_CIN) % MBOX_CMD_BUFFER_SIZE;
cin = MBOX_READL(MBOX_CIN) % MBOX_CMD_BUFFER_SIZE;
cout = MBOX_READL(MBOX_COUT) % MBOX_CMD_BUFFER_SIZE;
/* if command buffer is full or not enough free space
* to fit the data. Note, len is in u32 unit.
*/
if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout ||
((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) %
MBOX_CMD_BUFFER_SIZE) < (len + 1))
return -ENOMEM;
/* write header to circular buffer */
MBOX_WRITE_CMD_BUF(header, cin++);
/* wrapping around when it reach the buffer size */
cin %= MBOX_CMD_BUFFER_SIZE;
ret = mbox_write_cmd_buffer(&cin, header, &is_cmdbuf_overflow);
if (ret)
return ret;
/* write arguments */
for (i = 0; i < len; i++) {
MBOX_WRITE_CMD_BUF(arg[i], cin++);
/* wrapping around when it reach the buffer size */
cin %= MBOX_CMD_BUFFER_SIZE;
is_cmdbuf_overflow = 0;
ret = mbox_write_cmd_buffer(&cin, arg[i], &is_cmdbuf_overflow);
if (ret)
return ret;
}
/* write command valid offset */
MBOX_WRITEL(cin, MBOX_CIN);
/* If SDM doorbell is not triggered after the last data is
* written into mailbox FIFO command buffer, trigger the
* SDM doorbell again to ensure SDM able to read the remaining
* data.
*/
if (!is_cmdbuf_overflow)
MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
return 0;
}
@ -89,10 +142,6 @@ static __always_inline int mbox_prepare_cmd_only(u8 id, u32 cmd,
u32 header;
int ret;
/* Total length is command + argument length */
if ((len + 1) > MBOX_CMD_BUFFER_SIZE)
return -EINVAL;
if (cmd > MBOX_MAX_CMD_INDEX)
return -EINVAL;
@ -109,11 +158,7 @@ static __always_inline int mbox_send_cmd_only_common(u8 id, u32 cmd,
u8 is_indirect, u32 len,
u32 *arg)
{
int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
/* write doorbell */
MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
return ret;
return mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
}
/* Return number of responses received in buffer */
@ -166,21 +211,24 @@ static __always_inline int mbox_send_cmd_common(u8 id, u32 cmd, u8 is_indirect,
status = MBOX_READL(MBOX_STATUS) & MBOX_STATUS_UA_MSK;
/* Write urgent command to urgent register */
MBOX_WRITEL(cmd, MBOX_URG);
/* write doorbell */
MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
} else {
ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
if (ret)
return ret;
}
/* write doorbell */
MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
while (1) {
ret = ~0;
ret = 1000;
/* Wait for doorbell from SDM */
while (!MBOX_READL(MBOX_DOORBELL_FROM_SDM) && ret--)
;
do {
if (MBOX_READL(MBOX_DOORBELL_FROM_SDM))
break;
udelay(1000);
} while (--ret);
if (!ret)
return -ETIMEDOUT;
@ -216,9 +264,7 @@ static __always_inline int mbox_send_cmd_common(u8 id, u32 cmd, u8 is_indirect,
if ((MBOX_RESP_CLIENT_GET(resp) ==
MBOX_CLIENT_ID_UBOOT) &&
(MBOX_RESP_ID_GET(resp) == id)) {
ret = MBOX_RESP_ERR_GET(resp);
if (ret)
return ret;
int resp_err = MBOX_RESP_ERR_GET(resp);
if (resp_buf_len) {
buf_len = *resp_buf_len;
@ -247,14 +293,36 @@ static __always_inline int mbox_send_cmd_common(u8 id, u32 cmd, u8 is_indirect,
buf_len--;
}
}
return ret;
return resp_err;
}
}
};
}
return -EIO;
}
static __always_inline int mbox_send_cmd_common_retry(u8 id, u32 cmd,
u8 is_indirect,
u32 len, u32 *arg,
u8 urgent,
u32 *resp_buf_len,
u32 *resp_buf)
{
int ret;
int i;
for (i = 0; i < 3; i++) {
ret = mbox_send_cmd_common(id, cmd, is_indirect, len, arg,
urgent, resp_buf_len, resp_buf);
if (ret == MBOX_RESP_TIMEOUT || ret == MBOX_RESP_DEVICE_BUSY)
udelay(2000); /* wait for 2ms before resend */
else
break;
}
return ret;
}
int mbox_init(void)
{
int ret;
@ -349,10 +417,10 @@ static __always_inline int mbox_get_fpga_config_status_common(u32 cmd)
int ret;
reconfig_status_resp_len = RECONFIG_STATUS_RESPONSE_LEN;
ret = mbox_send_cmd_common(MBOX_ID_UBOOT, cmd,
MBOX_CMD_DIRECT, 0, NULL, 0,
&reconfig_status_resp_len,
reconfig_status_resp);
ret = mbox_send_cmd_common_retry(MBOX_ID_UBOOT, cmd,
MBOX_CMD_DIRECT, 0, NULL, 0,
&reconfig_status_resp_len,
reconfig_status_resp);
if (ret)
return ret;
@ -392,16 +460,16 @@ int __secure mbox_get_fpga_config_status_psci(u32 cmd)
int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
u8 urgent, u32 *resp_buf_len, u32 *resp_buf)
{
return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent,
resp_buf_len, resp_buf);
return mbox_send_cmd_common_retry(id, cmd, is_indirect, len, arg,
urgent, resp_buf_len, resp_buf);
}
int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len,
u32 *arg, u8 urgent, u32 *resp_buf_len,
u32 *resp_buf)
{
return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent,
resp_buf_len, resp_buf);
return mbox_send_cmd_common_retry(id, cmd, is_indirect, len, arg,
urgent, resp_buf_len, resp_buf);
}
int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg)

87
arch/arm/mach-socfpga/misc_s10.c
View file

@ -8,20 +8,13 @@
#include <common.h>
#include <env.h>
#include <errno.h>
#include <fdtdec.h>
#include <init.h>
#include <log.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/mailbox_s10.h>
#include <asm/arch/misc.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
#include <asm/arch/misc.h>
#include <asm/pl310.h>
#include <linux/libfdt.h>
#include <asm/arch/mailbox_s10.h>
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
DECLARE_GLOBAL_DATA_PTR;
@ -31,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
static Altera_desc altera_fpga[] = {
{
/* Family */
Intel_FPGA_Stratix10,
Intel_FPGA_SDM_Mailbox,
/* Interface type */
secure_device_manager_mailbox,
/* No limitation as additional data will be ignored */
@ -45,79 +38,6 @@ static Altera_desc altera_fpga[] = {
},
};
/*
* DesignWare Ethernet initialization
*/
#ifdef CONFIG_ETH_DESIGNWARE
static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
{
u32 modereg;
if (!phymode)
return -EINVAL;
if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii") ||
!strcmp(phymode, "sgmii"))
modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
else if (!strcmp(phymode, "rgmii"))
modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
else if (!strcmp(phymode, "rmii"))
modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
else
return -EINVAL;
clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0 +
(gmac_index * sizeof(u32)),
SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
return 0;
}
static int socfpga_set_phymode(void)
{
const void *fdt = gd->fdt_blob;
struct fdtdec_phandle_args args;
const char *phy_mode;
u32 gmac_index;
int nodes[3]; /* Max. 3 GMACs */
int ret, count;
int i, node;
count = fdtdec_find_aliases_for_id(fdt, "ethernet",
COMPAT_ALTERA_SOCFPGA_DWMAC,
nodes, ARRAY_SIZE(nodes));
for (i = 0; i < count; i++) {
node = nodes[i];
if (node <= 0)
continue;
ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
"#reset-cells", 1, 0,
&args);
if (ret || args.args_count != 1) {
debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
continue;
}
gmac_index = args.args[0] - EMAC0_RESET;
phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
ret = socfpga_phymode_setup(gmac_index, phy_mode);
if (ret) {
debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
continue;
}
}
return 0;
}
#else
static int socfpga_set_phymode(void)
{
return 0;
};
#endif
/*
* Print CPU information
@ -139,7 +59,6 @@ int arch_misc_init(void)
sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
env_set("qspi_clock", qspi_string);
socfpga_set_phymode();
return 0;
}
#endif

141
arch/arm/mach-socfpga/qts-filter-a10.sh Executable file
View file

@ -0,0 +1,141 @@
#!/bin/bash
#
# helper function to convert from DOS to Unix, if necessary, and handle
# lines ending in '\'.
#
fix_newlines_in_macros() {
sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1
}
#filter out only what we need from a10 hps.xml
grep_a10_hps_config() {
egrep "clk_hz|i_clk_mgr|i_io48_pin_mux|AXI_SLAVE|AXI_MASTER"
}
#
# Process hps.xml
# $1: hps.xml
# $2: Output File
#
process_a10_hps_config() {
hps_xml="$1"
outfile="$2"
(cat << EOF
// SPDX-License-Identifier: BSD-3-Clause
/*
* Intel Arria 10 SoCFPGA configuration
*/
#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
#define __SOCFPGA_ARRIA10_CONFIG_H__
EOF
echo "/* Clocks */"
fix_newlines_in_macros \
${hps_xml} | egrep "clk_hz" |
awk -F"'" '{ gsub("\\.","_",$2) ; \
print "#define" " " toupper($2) " " $4}' |
sed 's/\.[0-9]//' |
sed 's/I_CLK_MGR_//' |
sort
fix_newlines_in_macros \
${hps_xml} | egrep "i_clk_mgr_mainpll" |
awk -F"'" '{ gsub("\\.","_",$2) ; \
print "#define" " " toupper($2) " " $4}' |
sed 's/\.[0-9]//' |
sed 's/I_CLK_MGR_//' |
sort
fix_newlines_in_macros \
${hps_xml} | egrep "i_clk_mgr_perpll" |
awk -F"'" '{ gsub("\\.","_",$2) ; \
print "#define" " " toupper($2) " " $4}' |
sed 's/\.[0-9]//' |
sed 's/I_CLK_MGR_//' |
sort
fix_newlines_in_macros \
${hps_xml} | egrep "i_clk_mgr_clkmgr" |
awk -F"'" '{ gsub("\\.","_",$2) ; \
print "#define" " " toupper($2) " " $4}' |
sed 's/\.[0-9]//' |
sed 's/I_CLK_MGR_//' |
sort
fix_newlines_in_macros \
${hps_xml} | egrep "i_clk_mgr_alteragrp" |
awk -F"'" '{ gsub("\\.","_",$2) ; \
print "#define" " " toupper($2) " " $4}' |
sed 's/\.[0-9]//' |
sed 's/I_CLK_MGR_//' |
sort
echo "#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \\"
echo " (ALTERAGRP_MPUCLK_MAINCNT))"
echo "#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \\"
echo " (ALTERAGRP_NOCCLK_MAINCNT))"
echo
echo "/* Pin Mux Configuration */"
fix_newlines_in_macros \
${hps_xml} | egrep "i_io48_pin_mux" |
awk -F"'" '{ gsub("\\.","_",$2) ; \
print "#define" " " toupper($2) " " $4}' |
sed 's/I_IO48_PIN_MUX_//' |
sed 's/SHARED_3V_IO_GRP_//' |
sed 's/FPGA_INTERFACE_GRP_//' |
sed 's/DEDICATED_IO_GRP_//' |
sed 's/CONFIGURATION_DEDICATED/CONFIG/' |
sort
echo
echo "/* Bridge Configuration */"
fix_newlines_in_macros \
${hps_xml} | egrep "AXI_SLAVE|AXI_MASTER" |
awk -F"'" '{ gsub("\\.","_",$2) ; \
print "#define" " " toupper($2) " " $4}' |
sed 's/true/1/' |
sed 's/false/0/' |
sort
echo
echo "/* Voltage Select for Config IO */"
echo "#define CONFIG_IO_BANK_VSEL \\"
echo " (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \\"
echo " (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))"
echo
echo "/* Macro for Config IO bit mapping */"
echo -n "#define CONFIG_IO_MACRO(NAME) "
echo "(((NAME ## _RTRIM & 0xff) << 19) | \\"
echo " ((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \\"
echo " ((NAME ## _WK_PU_EN & 0x1) << 16) | \\"
echo " ((NAME ## _PU_SLW_RT & 0x1) << 13) | \\"
echo " ((NAME ## _PU_DRV_STRG & 0xf) << 8) | \\"
echo " ((NAME ## _PD_SLW_RT & 0x1) << 5) | \\"
echo " (NAME ## _PD_DRV_STRG & 0x1f))"
cat << EOF
#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */
EOF
) > "${outfile}"
}
usage() {
echo "$0 [hps_xml] [output_file]"
echo "Process QTS-generated hps.xml into devicetree header."
echo ""
echo " hps_xml - hps.xml file from hps_isw_handoff"
echo " output_file - Output header file for dtsi include"
echo ""
}
hps_xml="$1"
outfile="$2"
if [ "$#" -ne 2 ] ; then
usage
exit 1
fi
process_a10_hps_config "${hps_xml}" "${outfile}"

47
arch/arm/mach-socfpga/reset_manager_s10.c
View file

@ -9,6 +9,7 @@
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
#include <linux/iopoll.h>
DECLARE_GLOBAL_DATA_PTR;
@ -54,6 +55,8 @@ void socfpga_per_reset_all(void)
void socfpga_bridges_reset(int enable)
{
u32 reg;
if (enable) {
/* clear idle request to all bridges */
setbits_le32(socfpga_get_sysmgr_addr() +
@ -64,9 +67,9 @@ void socfpga_bridges_reset(int enable)
~0);
/* Poll until all idleack to 0 */
while (readl(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_NOC_IDLEACK))
;
read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_NOC_IDLEACK, reg, !reg, 1000,
300000);
} else {
/* set idle request to all bridges */
writel(~0,
@ -77,14 +80,18 @@ void socfpga_bridges_reset(int enable)
writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
/* Poll until all idleack to 1 */
while ((readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_IDLEACK) ^
(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
;
read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_NOC_IDLEACK, reg,
reg == (SYSMGR_NOC_H2F_MSK |
SYSMGR_NOC_LWH2F_MSK),
1000, 300000);
/* Poll until all idlestatus to 1 */
while ((readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_IDLESTATUS) ^
(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
;
read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_NOC_IDLESTATUS, reg,
reg == (SYSMGR_NOC_H2F_MSK |
SYSMGR_NOC_LWH2F_MSK),
1000, 300000);
/* Reset all bridges (except NOR DDR scheduler & F2S) */
setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
@ -104,3 +111,25 @@ int cpu_has_been_warmreset(void)
return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) &
RSTMGR_L4WD_MPU_WARMRESET_MASK;
}
void print_reset_info(void)
{
bool iswd;
int n;
u32 stat = cpu_has_been_warmreset();
printf("Reset state: %s%s", stat ? "Warm " : "Cold",
(stat & RSTMGR_STAT_SDMWARMRST) ? "[from SDM] " : "");
stat &= ~RSTMGR_STAT_SDMWARMRST;
if (!stat) {
puts("\n");
return;
}
n = generic_ffs(stat) - 1;
iswd = (n >= RSTMGR_STAT_L4WD0RST_BITPOS);
printf("(Triggered by %s %d)\n", iswd ? "Watchdog" : "MPU",
iswd ? (n - RSTMGR_STAT_L4WD0RST_BITPOS) :
(n - RSTMGR_STAT_MPU0RST_BITPOS));
}

3
arch/arm/mach-socfpga/spl_agilex.c
View file

@ -51,11 +51,11 @@ void board_init_f(ulong dummy)
socfpga_get_managers_addr();
#ifdef CONFIG_HW_WATCHDOG
/* Ensure watchdog is paused when debugging is happening */
writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
#ifdef CONFIG_HW_WATCHDOG
/* Enable watchdog before initializing the HW */
socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
@ -76,6 +76,7 @@ void board_init_f(ulong dummy)
}
preloader_console_init();
print_reset_info();
cm_print_clock_quick_summary();
firewall_setup();

3
arch/arm/mach-socfpga/spl_s10.c
View file

@ -53,11 +53,11 @@ void board_init_f(ulong dummy)
socfpga_get_managers_addr();
#ifdef CONFIG_HW_WATCHDOG
/* Ensure watchdog is paused when debugging is happening */
writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
#ifdef CONFIG_HW_WATCHDOG
/* Enable watchdog before initializing the HW */
socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
@ -81,6 +81,7 @@ void board_init_f(ulong dummy)
#endif
preloader_console_init();
print_reset_info();
cm_print_clock_quick_summary();
firewall_setup();

3
arch/arm/mach-socfpga/timer_s10.c
View file

@ -14,6 +14,7 @@
*/
int timer_init(void)
{
#ifdef CONFIG_SPL_BUILD
int enable = 0x3; /* timer enable + output signal masked */
int loadval = ~0;
@ -22,6 +23,6 @@ int timer_init(void)
/* enable processor pysical counter */
asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
#endif
return 0;
}

5
configs/socfpga_agilex_defconfig
View file

@ -12,6 +12,7 @@ CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
# CONFIG_PSCI_RESET is not set
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
@ -34,7 +35,6 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
@ -60,4 +60,7 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
CONFIG_DESIGNWARE_WATCHDOG=y
CONFIG_WDT=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_PANIC_HANG=y

3
configs/socfpga_stratix10_defconfig
View file

@ -14,6 +14,7 @@ CONFIG_SPL_FS_FAT=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
CONFIG_OPTIMIZE_INLINING=y
CONFIG_SPL_OPTIMIZE_INLINING=y
# CONFIG_PSCI_RESET is not set
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
@ -36,7 +37,6 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
@ -67,3 +67,4 @@ CONFIG_USB_STORAGE=y
CONFIG_DESIGNWARE_WATCHDOG=y
CONFIG_WDT=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_PANIC_HANG=y

37
doc/README.socfpga
View file

@ -16,9 +16,9 @@ controller support within SOCFPGA
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
-> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
--------------------------------------------------
Generating the handoff header files for U-Boot SPL
--------------------------------------------------
---------------------------------------------------------------------
Cyclone 5 / Arria 5 generating the handoff header files for U-Boot SPL
---------------------------------------------------------------------
This text is assuming quartus 16.1, but newer versions will probably work just fine too;
verified with DE1_SOC_Linux_FB demo project (https://github.com/VCTLabs/DE1_SOC_Linux_FB).
@ -32,7 +32,7 @@ Rebuilding your Quartus project
Choose one of the follwing methods, either command line or GUI.
Using the comaand line
Using the command line
~~~~~~~~~~~~~~~~~~~~~~
First run the embedded command shell, using your path to the Quartus install:
@ -147,3 +147,32 @@ Note: file sizes will differ slightly depending on the selected board.
Now your board is ready for full mainline support including U-Boot SPL.
The Preloader will not be needed any more.
----------------------------------------------------------
Arria 10 generating the handoff header files for U-Boot SPL
----------------------------------------------------------
A header file for inclusion in a devicetree for Arria10 can be generated
by the qts-filter-a10.sh script directly from the hps_isw_handoff/hps.xml
file generated during the FPGA project compilation. The header contains
all PLL, clock, pinmux, and bridge configurations required.
Please look at the socfpga_arria10_socdk_sdmmc-u-boot.dtsi for an example
that includes use of the generated handoff header.
Devicetree header generation
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The qts-filter-a10.sh script can process the compile time genetated hps.xml
to create the appropriate devicetree header.
$ ./arch/arm/mach-socfpga/qts-filter-a10.sh \
<hps_xml> \
<output_file>
hps_xml - hps_isw_handoff/hps.xml from Quartus project
output_file - Output filename and location for header file
The script generates a single header file names <output_file> that should
be placed in arch/arm/dts.

113
drivers/clk/altera/clk-agilex.c
View file

@ -47,8 +47,66 @@ static void clk_write_ctrl(struct socfpga_clk_platdata *plat, u32 val)
#define MEMBUS_MAINPLL 0
#define MEMBUS_PERPLL 1
#define MEMBUS_TIMEOUT 1000
#define MEMBUS_ADDR_CLKSLICE 0x27
#define MEMBUS_CLKSLICE_SYNC_MODE_EN 0x80
#define MEMBUS_CLKSLICE_REG 0x27
#define MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG 0xb3
#define MEMBUS_SYNTHPPM_WATCHDOGTMR_VF01_REG 0xe6
#define MEMBUS_CALCLKSLICE0_DUTY_LOCOVR_REG 0x03
#define MEMBUS_CALCLKSLICE1_DUTY_LOCOVR_REG 0x07
static const struct {
u32 reg;
u32 val;
u32 mask;
} membus_pll[] = {
{
MEMBUS_CLKSLICE_REG,
/*
* BIT[7:7]
* Enable source synchronous mode
*/
BIT(7),
BIT(7)
},
{
MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG,
/*
* BIT[0:0]
* Sets synthcalfosc_init_centerfreq=1 to limit overshoot
* frequency during lock
*/
BIT(0),
BIT(0)
},
{
MEMBUS_SYNTHPPM_WATCHDOGTMR_VF01_REG,
/*
* BIT[0:0]
* Sets synthppm_watchdogtmr_vf0=1 to give the pll more time
* to settle before lock is asserted.
*/
BIT(0),
BIT(0)
},
{
MEMBUS_CALCLKSLICE0_DUTY_LOCOVR_REG,
/*
* BIT[6:0]
* Centering duty cycle for clkslice0 output
*/
0x4a,
GENMASK(6, 0)
},
{
MEMBUS_CALCLKSLICE1_DUTY_LOCOVR_REG,
/*
* BIT[6:0]
* Centering duty cycle for clkslice1 output
*/
0x4a,
GENMASK(6, 0)
},
};
static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll,
int timeout)
@ -126,6 +184,20 @@ static int membus_read_pll(struct socfpga_clk_platdata *plat, u32 pll,
return 0;
}
static void membus_pll_configs(struct socfpga_clk_platdata *plat, u32 pll)
{
int i;
u32 rdata;
for (i = 0; i < ARRAY_SIZE(membus_pll); i++) {
membus_read_pll(plat, pll, membus_pll[i].reg,
&rdata, MEMBUS_TIMEOUT);
membus_write_pll(plat, pll, membus_pll[i].reg,
((rdata & ~membus_pll[i].mask) | membus_pll[i].val),
MEMBUS_TIMEOUT);
}
}
static u32 calc_vocalib_pll(u32 pllm, u32 pllglob)
{
u32 mdiv, refclkdiv, arefclkdiv, drefclkdiv, mscnt, hscnt, vcocalib;
@ -166,11 +238,20 @@ static void clk_basic_init(struct udevice *dev,
{
struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
u32 vcocalib;
u32 rdata;
if (!cfg)
return;
#ifdef CONFIG_SPL_BUILD
/* Always force clock manager into boot mode before any configuration */
clk_write_ctrl(plat,
CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
#else
/* Skip clock configuration in SSBL if it's not in boot mode */
if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE))
return;
#endif
/* Put both PLLs in bypass */
clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
@ -216,19 +297,10 @@ static void clk_basic_init(struct udevice *dev,
CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB,
CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
/* Membus programming to set mainpll and perripll to
* source synchronous mode
*/
membus_read_pll(plat, MEMBUS_MAINPLL, MEMBUS_ADDR_CLKSLICE, &rdata,
MEMBUS_TIMEOUT);
membus_write_pll(plat, MEMBUS_MAINPLL, MEMBUS_ADDR_CLKSLICE,
(rdata | MEMBUS_CLKSLICE_SYNC_MODE_EN),
MEMBUS_TIMEOUT);
membus_read_pll(plat, MEMBUS_PERPLL, MEMBUS_ADDR_CLKSLICE, &rdata,
MEMBUS_TIMEOUT);
membus_write_pll(plat, MEMBUS_PERPLL, MEMBUS_ADDR_CLKSLICE,
(rdata | MEMBUS_CLKSLICE_SYNC_MODE_EN),
MEMBUS_TIMEOUT);
/* Membus programming for mainpll */
membus_pll_configs(plat, MEMBUS_MAINPLL);
/* Membus programming for peripll */
membus_pll_configs(plat, MEMBUS_PERPLL);
cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
@ -533,12 +605,20 @@ static ulong socfpga_clk_get_rate(struct clk *clk)
case AGILEX_EMAC2_CLK:
return clk_get_emac_clk_hz(plat, clk->id);
case AGILEX_USB_CLK:
case AGILEX_NAND_X_CLK:
return clk_get_l4_mp_clk_hz(plat);
case AGILEX_NAND_CLK:
return clk_get_l4_mp_clk_hz(plat) / 4;
default:
return -ENXIO;
}
}
static int socfpga_clk_enable(struct clk *clk)
{
return 0;
}
static int socfpga_clk_probe(struct udevice *dev)
{
const struct cm_config *cm_default_cfg = cm_get_default_config();
@ -562,6 +642,7 @@ static int socfpga_clk_ofdata_to_platdata(struct udevice *dev)
}
static struct clk_ops socfpga_clk_ops = {
.enable = socfpga_clk_enable,
.get_rate = socfpga_clk_get_rate,
};

14
drivers/fpga/Kconfig
View file

@ -31,16 +31,16 @@ config FPGA_CYCLON2
Enable FPGA driver for loading bitstream in BIT and BIN format
on Altera Cyclone II device.
config FPGA_STRATIX10
bool "Enable Altera FPGA driver for Stratix 10"
depends on TARGET_SOCFPGA_STRATIX10
config FPGA_INTEL_SDM_MAILBOX
bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver"
depends on TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
select FPGA_ALTERA
help
Say Y here to enable the Altera Stratix 10 FPGA specific driver
Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver
This provides common functionality for Altera Stratix 10 devices.
Enable FPGA driver for writing bitstream into Altera Stratix10
device.
This provides common functionality for Intel FPGA devices.
Enable FPGA driver for writing full bitstream into Intel FPGA
devices through SDM (Secure Device Manager) Mailbox.
config FPGA_XILINX
bool "Enable Xilinx FPGA drivers"

2
drivers/fpga/Makefile
View file

@ -16,9 +16,9 @@ ifdef CONFIG_FPGA_ALTERA
obj-y += altera.o
obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
obj-$(CONFIG_FPGA_INTEL_SDM_MAILBOX) += intel_sdm_mb.o
obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
obj-$(CONFIG_FPGA_STRATIX10) += stratix10.o
obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o

7
drivers/fpga/altera.c
View file

@ -40,12 +40,13 @@ static const struct altera_fpga {
#if defined(CONFIG_FPGA_STRATIX_V)
{ Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
#endif
#if defined(CONFIG_FPGA_STRATIX10)
{ Intel_FPGA_Stratix10, "Stratix10", stratix10_load, NULL, NULL },
#endif
#if defined(CONFIG_FPGA_SOCFPGA)
{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
#endif
#if defined(CONFIG_FPGA_INTEL_SDM_MAILBOX)
{ Intel_FPGA_SDM_Mailbox, "Intel SDM Mailbox", intel_sdm_mb_load, NULL,
NULL },
#endif
};
static int altera_validate(Altera_desc *desc, const char *fn)

5
drivers/fpga/stratix10.c → drivers/fpga/intel_sdm_mb.c
View file

@ -6,6 +6,7 @@
#include <common.h>
#include <altera.h>
#include <log.h>
#include <watchdog.h>
#include <asm/arch/mailbox_s10.h>
#include <linux/delay.h>
@ -113,6 +114,7 @@ static int reconfig_status_polling_resp(void)
puts(".");
udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
WATCHDOG_RESET();
}
return -ETIMEDOUT;
@ -238,6 +240,7 @@ static int send_reconfig_data(const void *rbf_data, size_t rbf_size,
if (resp_err && !xfer_count)
return resp_err;
}
WATCHDOG_RESET();
}
return 0;
@ -247,7 +250,7 @@ static int send_reconfig_data(const void *rbf_data, size_t rbf_size,
* This is the interface used by FPGA driver.
* Return 0 for success, non-zero for error.
*/
int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
{
int ret;
u32 resp_len = 2;

8
drivers/sysreset/Kconfig
View file

@ -79,12 +79,12 @@ config SYSRESET_SOCFPGA
This enables the system reset driver support for Intel SOCFPGA SoCs
(Cyclone 5, Arria 5 and Arria 10).
config SYSRESET_SOCFPGA_S10
bool "Enable support for Intel SOCFPGA Stratix 10"
depends on ARCH_SOCFPGA && TARGET_SOCFPGA_STRATIX10
config SYSRESET_SOCFPGA_SOC64
bool "Enable support for Intel SOCFPGA SoC64 family (Stratix10/Agilex)"
depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX)
help
This enables the system reset driver support for Intel SOCFPGA
Stratix SoCs.
SoC64 SoCs.
config SYSRESET_TI_SCI
bool "TI System Control Interface (TI SCI) system reset driver"

2
drivers/sysreset/Makefile
View file

@ -13,7 +13,7 @@ obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o
obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o
obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o

0
drivers/sysreset/sysreset_socfpga_s10.c → drivers/sysreset/sysreset_socfpga_soc64.c
View file

9
include/altera.h
View file

@ -56,10 +56,10 @@ enum altera_family {
Altera_StratixII,
/* StratixV Family */
Altera_StratixV,
/* Stratix10 Family */
Intel_FPGA_Stratix10,
/* SoCFPGA Family */
Altera_SoCFPGA,
/* Intel FPGA Family with SDM (Secure Device Manager) Mailbox */
Intel_FPGA_SDM_Mailbox,
/* Add new models here */
@ -120,8 +120,9 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
#endif
#ifdef CONFIG_FPGA_STRATIX10
int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
#ifdef CONFIG_FPGA_INTEL_SDM_MAILBOX
int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data,
size_t rbf_size);
#endif
#endif /* _ALTERA_H_ */

50
tools/socfpgaimage.c
View file

@ -62,6 +62,9 @@
#define HEADER_OFFSET 0x40
#define VALIDATION_WORD 0x31305341
/* Minimum and default entry point offset */
#define ENTRY_POINT_OFFSET 0x14
static uint8_t buffer_v0[0x10000];
static uint8_t buffer_v1[0x40000];
@ -120,8 +123,10 @@ static uint16_t sfp_hdr_checksum(uint8_t *buf, unsigned char ver)
}
static void sfp_build_header(uint8_t *buf, uint8_t ver, uint8_t flags,
uint32_t length_bytes)
uint32_t length_bytes,
struct image_tool_params *params)
{
uint32_t entry_offset = params->eflag ? params->ep : ENTRY_POINT_OFFSET;
struct socfpga_header_v0 header_v0 = {
.validation = cpu_to_le32(VALIDATION_WORD),
.version = 0,
@ -136,7 +141,8 @@ static void sfp_build_header(uint8_t *buf, uint8_t ver, uint8_t flags,
.flags = flags,
.header_u8 = cpu_to_le16(sizeof(header_v1)),
.length_u8 = cpu_to_le32(length_bytes),
.entry_offset = cpu_to_le32(0x14), /* Trampoline offset */
/* Trampoline offset */
.entry_offset = cpu_to_le32(entry_offset),
.zero = 0,
};
@ -198,7 +204,8 @@ static int sfp_verify_header(const uint8_t *buf, uint8_t *ver)
/* Sign the buffer and return the signed buffer size */
static int sfp_sign_buffer(uint8_t *buf, uint8_t ver, uint8_t flags,
int len, int pad_64k)
int len, int pad_64k,
struct image_tool_params *params)
{
uint32_t calc_crc;
@ -206,7 +213,7 @@ static int sfp_sign_buffer(uint8_t *buf, uint8_t ver, uint8_t flags,
len = ALIGN(len, 4);
/* Build header, adding 4 bytes to length to hold the CRC32. */
sfp_build_header(buf + HEADER_OFFSET, ver, flags, len + 4);
sfp_build_header(buf + HEADER_OFFSET, ver, flags, len + 4, params);
/* Calculate and apply the CRC */
calc_crc = ~pbl_crc32(0, (char *)buf, len);
@ -275,7 +282,7 @@ static void socfpgaimage_print_header(const void *ptr)
printf("Not a sane SOCFPGA preloader\n");
}
static int socfpgaimage_check_params(struct image_tool_params *params)
static int socfpgaimage_check_params_v0(struct image_tool_params *params)
{
/* Not sure if we should be accepting fflags */
return (params->dflag && (params->fflag || params->lflag)) ||
@ -283,6 +290,26 @@ static int socfpgaimage_check_params(struct image_tool_params *params)
(params->lflag && (params->dflag || params->fflag));
}
static int socfpgaimage_check_params_v1(struct image_tool_params *params)
{
/*
* If the entry point is specified, ensure it is >= ENTRY_POINT_OFFSET
* and it is 4 bytes aligned.
*/
if (params->eflag && (params->ep < ENTRY_POINT_OFFSET ||
params->ep % 4 != 0)) {
fprintf(stderr,
"Error: Entry point must be greater than 0x%x.\n",
ENTRY_POINT_OFFSET);
return -1;
}
/* Not sure if we should be accepting fflags */
return (params->dflag && (params->fflag || params->lflag)) ||
(params->fflag && (params->dflag || params->lflag)) ||
(params->lflag && (params->dflag || params->fflag));
}
static int socfpgaimage_check_image_types_v0(uint8_t type)
{
if (type == IH_TYPE_SOCFPGAIMAGE)
@ -343,7 +370,8 @@ static int socfpgaimage_vrec_header_v1(struct image_tool_params *params,
return sfp_vrec_header(params, tparams, 1);
}
static void sfp_set_header(void *ptr, unsigned char ver)
static void sfp_set_header(void *ptr, unsigned char ver,
struct image_tool_params *params)
{
uint8_t *buf = (uint8_t *)ptr;
@ -357,19 +385,19 @@ static void sfp_set_header(void *ptr, unsigned char ver)
memmove(buf, buf + sfp_fake_header_size(data_size, ver), data_size);
memset(buf + data_size, 0, sfp_fake_header_size(data_size, ver));
sfp_sign_buffer(buf, ver, 0, data_size, 0);
sfp_sign_buffer(buf, ver, 0, data_size, 0, params);
}
static void socfpgaimage_set_header_v0(void *ptr, struct stat *sbuf, int ifd,
struct image_tool_params *params)
{
sfp_set_header(ptr, 0);
sfp_set_header(ptr, 0, params);
}
static void socfpgaimage_set_header_v1(void *ptr, struct stat *sbuf, int ifd,
struct image_tool_params *params)
{
sfp_set_header(ptr, 1);
sfp_set_header(ptr, 1, params);
}
U_BOOT_IMAGE_TYPE(
@ -377,7 +405,7 @@ U_BOOT_IMAGE_TYPE(
"Altera SoCFPGA Cyclone V / Arria V image support",
0, /* This will be modified by vrec_header() */
(void *)buffer_v0,
socfpgaimage_check_params,
socfpgaimage_check_params_v0,
socfpgaimage_verify_header,
socfpgaimage_print_header,
socfpgaimage_set_header_v0,
@ -392,7 +420,7 @@ U_BOOT_IMAGE_TYPE(
"Altera SoCFPGA Arria10 image support",
0, /* This will be modified by vrec_header() */
(void *)buffer_v1,
socfpgaimage_check_params,
socfpgaimage_check_params_v1,
socfpgaimage_verify_header,
socfpgaimage_print_header,
socfpgaimage_set_header_v1,