From 968597b85c9ac6331a64d9b3584672d9f48c4a11 Mon Sep 17 00:00:00 2001
From: Sumit Garg <sumit.garg@linaro.org>
Date: Thu, 4 Aug 2022 19:57:15 +0530
Subject: [PATCH] clocks: qcs404: Add support for USB clocks

Add support for USB controller and PHY clocks for QCS404 SoC.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
 arch/arm/mach-snapdragon/clock-qcs404.c       | 35 +++++++++++++++++++
 .../include/mach/sysmap-qcs404.h              | 17 +++++++++
 2 files changed, 52 insertions(+)

diff --git a/arch/arm/mach-snapdragon/clock-qcs404.c b/arch/arm/mach-snapdragon/clock-qcs404.c
index 230d7779a7..6fe92afe8d 100644
--- a/arch/arm/mach-snapdragon/clock-qcs404.c
+++ b/arch/arm/mach-snapdragon/clock-qcs404.c
@@ -47,6 +47,14 @@ static struct pll_vote_clk gpll0_vote_clk = {
 	.vote_bit = BIT(0),
 };
 
+static const struct bcr_regs usb30_master_regs = {
+	.cfg_rcgr = USB30_MASTER_CFG_RCGR,
+	.cmd_rcgr = USB30_MASTER_CMD_RCGR,
+	.M = USB30_MASTER_M,
+	.N = USB30_MASTER_N,
+	.D = USB30_MASTER_D,
+};
+
 ulong msm_set_rate(struct clk *clk, ulong rate)
 {
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -80,5 +88,32 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
 
 int msm_enable(struct clk *clk)
 {
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+	switch (clk->id) {
+	case GCC_USB30_MASTER_CLK:
+		clk_enable_cbc(priv->base + USB30_MASTER_CBCR);
+		clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 4, 0, 0,
+				     CFG_CLK_SRC_GPLL0);
+		break;
+	case GCC_SYS_NOC_USB3_CLK:
+		clk_enable_cbc(priv->base + SYS_NOC_USB3_CBCR);
+		break;
+	case GCC_USB30_SLEEP_CLK:
+		clk_enable_cbc(priv->base + USB30_SLEEP_CBCR);
+		break;
+	case GCC_USB30_MOCK_UTMI_CLK:
+		clk_enable_cbc(priv->base + USB30_MOCK_UTMI_CBCR);
+		break;
+	case GCC_USB_HS_PHY_CFG_AHB_CLK:
+		clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR);
+		break;
+	case GCC_USB2A_PHY_SLEEP_CLK:
+		clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR);
+		break;
+	default:
+		return 0;
+	}
+
 	return 0;
 }
diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
index 4dc96b9fbc..e448faad2d 100644
--- a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
+++ b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
@@ -37,4 +37,21 @@
 #define SDCC_APPS_CBCR(n)		(((n) * 0x1000) + 0x41018)
 #define SDCC_AHB_CBCR(n)		(((n) * 0x1000) + 0x4101C)
 
+/* USB-3.0 controller clock control registers */
+#define SYS_NOC_USB3_CBCR		(0x26014)
+#define USB30_BCR			(0x39000)
+#define USB3PHY_BCR			(0x39008)
+#define USB30_MASTER_CBCR		(0x3900C)
+#define USB30_SLEEP_CBCR		(0x39010)
+#define USB30_MOCK_UTMI_CBCR		(0x39014)
+#define USB30_MOCK_UTMI_CMD_RCGR	(0x3901C)
+#define USB30_MOCK_UTMI_CFG_RCGR	(0x39020)
+#define USB30_MASTER_CMD_RCGR		(0x39028)
+#define USB30_MASTER_CFG_RCGR		(0x3902C)
+#define USB30_MASTER_M			(0x39030)
+#define USB30_MASTER_N			(0x39034)
+#define USB30_MASTER_D			(0x39038)
+#define USB2A_PHY_SLEEP_CBCR		(0x4102C)
+#define USB_HS_PHY_CFG_AHB_CBCR		(0x41030)
+
 #endif