mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-01 00:49:43 +00:00
u-boot: Fix e500 v2 core reset bug
The following patch fixes the e500 v2 core reset bug. For e500 v2 core, a new reset control register is added to reset the processor. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
This commit is contained in:
parent
63247a5acd
commit
96629cbabd
1 changed files with 15 additions and 6 deletions
|
@ -140,16 +140,25 @@ int checkcpu (void)
|
||||||
|
|
||||||
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
|
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
|
||||||
{
|
{
|
||||||
|
uint pvr;
|
||||||
|
uint ver;
|
||||||
|
pvr = get_pvr();
|
||||||
|
ver = PVR_VER(pvr);
|
||||||
|
if (ver & 1){
|
||||||
|
/* e500 v2 core has reset control register */
|
||||||
|
volatile unsigned int * rstcr;
|
||||||
|
rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
|
||||||
|
*rstcr = 0x2; /* HRESET_REQ */
|
||||||
|
}else{
|
||||||
/*
|
/*
|
||||||
* Initiate hard reset in debug control register DBCR0
|
* Initiate hard reset in debug control register DBCR0
|
||||||
* Make sure MSR[DE] = 1
|
* Make sure MSR[DE] = 1
|
||||||
*/
|
*/
|
||||||
unsigned long val;
|
unsigned long val;
|
||||||
|
|
||||||
val = mfspr(DBCR0);
|
val = mfspr(DBCR0);
|
||||||
val |= 0x70000000;
|
val |= 0x70000000;
|
||||||
mtspr(DBCR0,val);
|
mtspr(DBCR0,val);
|
||||||
|
}
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue