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Merge branch 'master_sh/gen4/initial' of https://source.denx.de/u-boot/custodians/u-boot-sh

Browse source 
- Initial R-Car Generation 4 support
This commit is contained in:
Tom Rini 2023-04-07 15:55:50 -04:00
commit 965f74b5b3
72 changed files with 11402 additions and 136 deletions
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6
Kconfig
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@ -427,7 +427,7 @@ config REMAKE_ELF
config BUILD_TARGET
string "Build target special images"
default "u-boot-elf.srec" if RCAR_GEN3
default "u-boot-elf.srec" if RCAR_64
default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL
default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
@ -446,14 +446,14 @@ config BUILD_TARGET
config HAS_BOARD_SIZE_LIMIT
bool "Define a maximum size for the U-Boot image"
default y if RCAR_GEN3
default y if RCAR_64
help
In some cases, we need to enforce a hard limit on how big the U-Boot
image itself can be.
config BOARD_SIZE_LIMIT
int "Maximum size of the U-Boot image in bytes"
default 1048576 if RCAR_GEN3
default 1048576 if RCAR_64
depends on HAS_BOARD_SIZE_LIMIT
help
Maximum size of the U-Boot image. When defined, the build system

10
arch/arm/dts/Makefile
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@ -1044,10 +1044,14 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a77970-eagle-u-boot.dtb \
r8a77980-condor-u-boot.dtb \
r8a77990-ebisu-u-boot.dtb \
r8a77995-draak-u-boot.dtb \
r8a779a0-falcon-u-boot.dtb
r8a77995-draak-u-boot.dtb
ifdef CONFIG_RCAR_GEN3
dtb-$(CONFIG_RCAR_GEN4) += \
r8a779a0-falcon-u-boot.dtb \
r8a779f0-spider-u-boot.dtb \
r8a779g0-white-hawk-u-boot.dtb
ifdef CONFIG_RCAR_64
DTC_FLAGS += -R 4 -p 0x1000
endif

190
arch/arm/dts/r8a779f0-spider-cpu.dtsi Normal file
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@ -0,0 +1,190 @@
// SPDX-License-Identifier: (GPL-2.0 or MIT)
/*
* Device Tree Source for the Spider CPU board
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include "r8a779f0.dtsi"
/ {
model = "Renesas Spider CPU board";
compatible = "renesas,spider-cpu", "renesas,r8a779f0";
aliases {
serial0 = &hscif0;
serial1 = &scif0;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:1843200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
rc21012_ufs: clk-rc21012-ufs {
compatible = "fixed-clock";
clock-frequency = <38400000>;
#clock-cells = <0>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&extal_clk {
clock-frequency = <20000000>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
gpio_exp_20: gpio@20 {
compatible = "ti,tca9554";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&i2c4 {
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
eeprom@50 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "cpu-board";
reg = <0x50>;
pagesize = <8>;
};
};
/*
* This board also has a microSD slot which we will not support upstream
* because we cannot directly switch voltages in software.
*/
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
full-pwr-cycle-in-suspend;
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
hscif0_pins: hscif0 {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c4_pins: i2c4 {
groups = "i2c4";
function = "i2c4";
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
scif0_pins: scif0 {
groups = "scif0_data", "scif0_ctrl";
function = "scif0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk";
function = "scif_clk";
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&scif_clk {
clock-frequency = <24000000>;
};
&ufs {
status = "okay";
};
&ufs30_clk {
compatible = "gpio-gate-clock";
clocks = <&rc21012_ufs>;
enable-gpios = <&gpio_exp_20 4 GPIO_ACTIVE_LOW>;
/delete-property/ clock-frequency;
};

105
arch/arm/dts/r8a779f0-spider-ethernet.dtsi Normal file
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@ -0,0 +1,105 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Spider Ethernet sub-board
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
&eth_serdes {
status = "okay";
};
&i2c4 {
eeprom@52 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "ethernet-sub-board";
reg = <0x52>;
pagesize = <8>;
};
};
&pfc {
tsn0_pins: tsn0 {
groups = "tsn0_mdio_b", "tsn0_link_b";
function = "tsn0";
power-source = <1800>;
};
tsn1_pins: tsn1 {
groups = "tsn1_mdio_b", "tsn1_link_b";
function = "tsn1";
power-source = <1800>;
};
tsn2_pins: tsn2 {
groups = "tsn2_mdio_b", "tsn2_link_b";
function = "tsn2";
power-source = <1800>;
};
};
&rswitch {
pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>;
pinctrl-names = "default";
status = "okay";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phy-handle = <&u101>;
phy-mode = "sgmii";
phys = <&eth_serdes 0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
u101: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c45";
interrupt-parent = <&gpio3>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
};
};
};
port@1 {
reg = <1>;
phy-handle = <&u201>;
phy-mode = "sgmii";
phys = <&eth_serdes 1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
u201: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c45";
interrupt-parent = <&gpio3>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
};
};
port@2 {
reg = <2>;
phy-handle = <&u301>;
phy-mode = "sgmii";
phys = <&eth_serdes 2>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
u301: ethernet-phy@3 {
reg = <3>;
compatible = "ethernet-phy-ieee802.3-c45";
interrupt-parent = <&gpio3>;
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
};
};
};
};
};

42
arch/arm/dts/r8a779f0-spider-u-boot.dts Normal file
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@ -0,0 +1,42 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot for the Spider board
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include "r8a779f0-spider.dts"
#include "r8a779f0-u-boot.dtsi"
/ {
aliases {
spi0 = &rpc;
};
};
&pfc {
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <40000000>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
spi-max-frequency = <40000000>;
};
};

24
arch/arm/dts/r8a779f0-spider.dts Normal file
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@ -0,0 +1,24 @@
// SPDX-License-Identifier: (GPL-2.0 or MIT)
/*
* Device Tree Source for the Spider CPU and BreakOut boards
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a779f0-spider-cpu.dtsi"
#include "r8a779f0-spider-ethernet.dtsi"
/ {
model = "Renesas Spider CPU and Breakout boards based on r8a779f0";
compatible = "renesas,spider-breakout", "renesas,spider-cpu", "renesas,r8a779f0";
};
&i2c4 {
eeprom@51 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "breakout-board";
reg = <0x51>;
pagesize = <8>;
};
};

28
arch/arm/dts/r8a779f0-u-boot.dtsi Normal file
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@ -0,0 +1,28 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on R-Car R8A779F0 SoC
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include "r8a779x-u-boot.dtsi"
/ {
soc {
rpc: spi@ee200000 {
compatible = "renesas,r8a779f0-rpc-if", "renesas,rcar-gen4-rpc-if";
reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 629>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 629>;
bank-width = <2>;
num-cs = <1>;
status = "disabled";
};
};
};
&extalr_clk {
bootph-all;
};

1179
arch/arm/dts/r8a779f0.dtsi Normal file
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File diff suppressed because it is too large Load diff

28
arch/arm/dts/r8a779g0-u-boot.dtsi Normal file
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@ -0,0 +1,28 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on R-Car R8A779G0 SoC
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include "r8a779x-u-boot.dtsi"
/ {
soc {
rpc: spi@ee200000 {
compatible = "renesas,r8a779g0-rpc-if", "renesas,rcar-gen4-rpc-if";
reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 629>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 629>;
bank-width = <2>;
num-cs = <1>;
status = "disabled";
};
};
};
&extalr_clk {
bootph-all;
};

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arch/arm/dts/r8a779g0-white-hawk-cpu.dtsi Normal file
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@ -0,0 +1,375 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the White Hawk CPU board
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include "r8a779g0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Renesas White Hawk CPU board";
compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0";
aliases {
ethernet0 = &avb0;
serial0 = &hscif0;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:921600n8";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&keys_pins>;
pinctrl-names = "default";
key-1 {
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
label = "SW47";
wakeup-source;
debounce-interval = <20>;
};
key-2 {
gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_2>;
label = "SW48";
wakeup-source;
debounce-interval = <20>;
};
key-3 {
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
label = "SW49";
wakeup-source;
debounce-interval = <20>;
};
};
leds {
compatible = "gpio-leds";
led-1 {
gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <1>;
};
led-2 {
gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <2>;
};
led-3 {
gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <3>;
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x1 0x00000000>;
};
mini-dp-con {
compatible = "dp-connector";
label = "CN5";
type = "mini";
port {
mini_dp_con_in: endpoint {
remote-endpoint = <&sn65dsi86_out>;
};
};
};
reg_1p2v: regulator-1p2v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sn65dsi86_refclk: clk-x6 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <38400000>;
};
};
&avb0 {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio7>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
};
};
&dsi0 {
status = "okay";
ports {
port@1 {
dsi0_out: endpoint {
remote-endpoint = <&sn65dsi86_in>;
data-lanes = <1 2 3 4>;
};
};
};
};
&du {
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&hscif0 {
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
io_expander_a: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
eeprom@50 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "cpu-board";
reg = <0x50>;
pagesize = <8>;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
bridge@2c {
compatible = "ti,sn65dsi86";
reg = <0x2c>;
clocks = <&sn65dsi86_refclk>;
clock-names = "refclk";
interrupt-parent = <&intc_ex>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
vccio-supply = <&reg_1p8v>;
vpll-supply = <&reg_1p8v>;
vcca-supply = <&reg_1p2v>;
vcc-supply = <&reg_1p2v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sn65dsi86_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
port@1 {
reg = <1>;
sn65dsi86_out: endpoint {
remote-endpoint = <&mini_dp_con_in>;
};
};
};
};
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
full-pwr-cycle-in-suspend;
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
avb0_pins: avb0 {
mux {
groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
"avb0_txcrefclk";
function = "avb0";
};
pins_mdio {
groups = "avb0_mdio";
drive-strength = <21>;
};
pins_mii {
groups = "avb0_rgmii";
drive-strength = <21>;
};
};
hscif0_pins: hscif0 {
groups = "hscif0_data";
function = "hscif0";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
keys_pins: keys {
pins = "GP_5_0", "GP_5_1", "GP_5_2";
bias-pull-up;
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk";
function = "scif_clk";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot@0 {
reg = <0x0 0x1200000>;
read-only;
};
user@1200000 {
reg = <0x1200000 0x2e00000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif_clk {
clock-frequency = <24000000>;
};

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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the R-Car V4H White Hawk CSI/DSI sub-board
*
* Copyright (C) 2022 Glider bv
*/
&i2c0 {
eeprom@52 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "csi-dsi-sub-board-id";
reg = <0x52>;
pagesize = <8>;
};
};

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arch/arm/dts/r8a779g0-white-hawk-ethernet.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the R-Car V4H White Hawk RAVB/Ethernet(1000Base-T1)
* sub-board
*
* Copyright (C) 2022 Glider bv
*/
&i2c0 {
eeprom@53 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "ethernet-sub-board-id";
reg = <0x53>;
pagesize = <8>;
};
};

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arch/arm/dts/r8a779g0-white-hawk-u-boot.dts Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot for the White Hawk board
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include "r8a779g0-white-hawk.dts"
#include "r8a779g0-u-boot.dtsi"
/ {
aliases {
spi0 = &rpc;
};
};
&pfc {
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <40000000>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
spi-max-frequency = <40000000>;
};
};

25
arch/arm/dts/r8a779g0-white-hawk.dts Normal file
View file

@ -0,0 +1,25 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the White Hawk CPU and BreakOut boards
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a779g0-white-hawk-cpu.dtsi"
#include "r8a779g0-white-hawk-csi-dsi.dtsi"
#include "r8a779g0-white-hawk-ethernet.dtsi"
/ {
model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0";
compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0";
};
&i2c0 {
eeprom@51 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "breakout-board";
reg = <0x51>;
pagesize = <8>;
};
};

1355
arch/arm/dts/r8a779g0.dtsi Normal file
View file

File diff suppressed because it is too large Load diff

4
arch/arm/mach-rmobile/Kconfig
View file

@ -40,6 +40,10 @@ config RCAR_GEN3
imply SPL_USE_TINY_PRINTF
imply SPL_YMODEM_SUPPORT
config RCAR_GEN4
bool "Renesas ARM SoCs R-Car Gen4 (64bit)"
select RCAR_64
config RZA1
prompt "Renesas ARM SoCs RZ/A1 (32bit)"
select CPU_V7A

1
arch/arm/mach-rmobile/Kconfig.64
View file

@ -7,5 +7,6 @@ config OF_LIBFDT_OVERLAY
default y if RCAR_64
source "arch/arm/mach-rmobile/Kconfig.rcar3"
source "arch/arm/mach-rmobile/Kconfig.rcar4"
endif

13
arch/arm/mach-rmobile/Kconfig.rcar3
View file

@ -70,12 +70,6 @@ config R8A77995
imply CLK_R8A77995
imply PINCTRL_PFC_R8A77995
config R8A779A0
bool "Renesas SoC R8A779A0"
select GICV3
imply CLK_R8A779A0
imply PINCTRL_PFC_R8A779A0
config RZ_G2
bool "Renesas ARM SoCs RZ/G2 (64bit)"
@ -123,12 +117,6 @@ config TARGET_EBISU
help
Support for Renesas R-Car Gen3 Ebisu platform
config TARGET_FALCON
bool "Falcon board"
imply R8A779A0
help
Support for Renesas R-Car Gen3 Falcon platform
config TARGET_HIHOPE_RZG2
bool "HiHope RZ/G2 board"
imply MULTI_DTB_FIT
@ -176,7 +164,6 @@ source "board/renesas/condor/Kconfig"
source "board/renesas/draak/Kconfig"
source "board/renesas/eagle/Kconfig"
source "board/renesas/ebisu/Kconfig"
source "board/renesas/falcon/Kconfig"
source "board/renesas/salvator-x/Kconfig"
source "board/renesas/ulcb/Kconfig"
source "board/beacon/beacon-rzg2m/Kconfig"

53
arch/arm/mach-rmobile/Kconfig.rcar4 Normal file
View file

@ -0,0 +1,53 @@
if RCAR_GEN4
menu "Select Target SoC"
config R8A779A0
bool "Renesas SoC R8A779A0"
select GICV3
imply CLK_R8A779A0
imply PINCTRL_PFC_R8A779A0
config R8A779F0
bool "Renesas SoC R8A779F0"
select GICV3
imply CLK_R8A779F0
imply PINCTRL_PFC_R8A779F0
config R8A779G0
bool "Renesas SoC R8A779G0"
select GICV3
imply CLK_R8A779G0
imply PINCTRL_PFC_R8A779G0
endmenu
choice
prompt "Renesas ARM64 SoCs board select"
optional
config TARGET_FALCON
bool "Falcon board"
imply R8A779A0
help
Support for Renesas R-Car Gen3 Falcon platform
config TARGET_SPIDER
bool "Spider board"
imply R8A779F0
help
Support for Renesas R-Car Gen4 Spider platform
config TARGET_WHITEHAWK
bool "White Hawk board"
imply R8A779G0
help
Support for Renesas R-Car Gen4 White Hawk platform
endchoice
source "board/renesas/falcon/Kconfig"
source "board/renesas/spider/Kconfig"
source "board/renesas/whitehawk/Kconfig"
endif

2
arch/arm/mach-rmobile/Makefile
View file

@ -10,7 +10,7 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o
ifneq ($(CONFIG_R8A779A0),)

2
arch/arm/mach-rmobile/cpu_info-rcar.c
View file

@ -14,7 +14,7 @@
static u32 rmobile_get_prr(void)
{
if (IS_ENABLED(CONFIG_RCAR_GEN3))
if (IS_ENABLED(CONFIG_RCAR_64))
return readl(0xFFF00044);
return readl(0xFF000044);

6
arch/arm/mach-rmobile/cpu_info.c
View file

@ -19,8 +19,8 @@ int arch_cpu_init(void)
}
#endif
/* R-Car Gen3 D-cache is enabled in memmap-gen3.c */
#ifndef CONFIG_RCAR_GEN3
/* R-Car Gen3 and Gen4 D-cache is enabled in memmap-gen3.c */
#ifndef CONFIG_RCAR_64
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
@ -76,6 +76,8 @@ static const struct {
{ RMOBILE_CPU_TYPE_R8A77990, "R8A77990" },
{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
{ RMOBILE_CPU_TYPE_R8A779A0, "R8A779A0" },
{ RMOBILE_CPU_TYPE_R8A779F0, "R8A779F0" },
{ RMOBILE_CPU_TYPE_R8A779G0, "R8A779G0" },
{ 0x0, "CPU" },
};

75
arch/arm/mach-rmobile/include/mach/rcar-gen4-base.h Normal file
View file

@ -0,0 +1,75 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* ./arch/arm/mach-rmobile/include/mach/rcar-gen4-base.h
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#ifndef __ASM_ARCH_RCAR_GEN4_BASE_H
#define __ASM_ARCH_RCAR_GEN4_BASE_H
/*
* R-Car (R8A779F0) I/O Addresses
*/
#define RWDT_BASE 0xE6020000
#define SWDT_BASE 0xE6030000
#define TMU_BASE 0xE61E0000
/* SCIF */
#define SCIF0_BASE 0xE6E60000
#define SCIF1_BASE 0xE6E68000
#define SCIF2_BASE 0xE6E88000
#define SCIF3_BASE 0xE6C50000
#define SCIF4_BASE 0xE6C40000
#define SCIF5_BASE 0xE6F30000
/* CPG */
#define CPGWPR 0xE6150000
#define CPGWPCR 0xE6150004
/* Reset */
#define RST_BASE 0xE6160000 /* Domain0 */
#define RST_SRESCR0 (RST_BASE + 0x18)
#define RST_SPRES 0x5AA58000
/* Arm Generic Timer */
#define CNTCR_BASE 0xE6080000
#define CNTFID0 (CNTCR_BASE + 0x020)
#define CNTCR_EN BIT(0)
/* GICv3 */
/* Distributor Registers */
#define GICD_BASE 0xF1000000
#define GICR_BASE (GICR_LPI_BASE)
/* ReDistributor Registers for Control and Physical LPIs */
#define GICR_LPI_BASE 0xF1060000
#define GICR_WAKER 0x0014
#define GICR_PWRR 0x0024
#define GICR_LPI_WAKER (GICR_LPI_BASE + GICR_WAKER)
#define GICR_LPI_PWRR (GICR_LPI_BASE + GICR_PWRR)
/* ReDistributor Registers for SGIs and PPIs */
#define GICR_SGI_BASE 0xF1070000
#define GICR_IGROUPR0 0x0080
#ifndef __ASSEMBLY__
#include <asm/types.h>
#include <linux/bitops.h>
/* RWDT */
struct rcar_rwdt {
u32 rwtcnt;
u32 rwtcsra;
u32 rwtcsrb;
};
/* SWDT */
struct rcar_swdt {
u32 swtcnt;
u32 swtcsra;
u32 swtcsrb;
};
#endif
#endif /* __ASM_ARCH_RCAR_GEN4_BASE_H */

4
arch/arm/mach-rmobile/include/mach/rmobile.h
View file

@ -16,6 +16,8 @@
#include <asm/arch/r8a7794.h>
#elif defined(CONFIG_RCAR_GEN3)
#include <asm/arch/rcar-gen3-base.h>
#elif defined(CONFIG_RCAR_GEN4)
#include <asm/arch/rcar-gen4-base.h>
#elif defined(CONFIG_R7S72100)
#else
#error "SOC Name not defined"
@ -37,6 +39,8 @@
#define RMOBILE_CPU_TYPE_R8A77990 0x57
#define RMOBILE_CPU_TYPE_R8A77995 0x58
#define RMOBILE_CPU_TYPE_R8A779A0 0x59
#define RMOBILE_CPU_TYPE_R8A779F0 0x5A
#define RMOBILE_CPU_TYPE_R8A779G0 0x5C
#ifndef __ASSEMBLY__
const u8 *rzg_get_cpu_name(void);

2
board/renesas/rcar-common/common.c
View file

@ -16,7 +16,7 @@
#include <asm/arch/rmobile.h>
#include <linux/libfdt.h>
#ifdef CONFIG_RCAR_GEN3
#ifdef CONFIG_RCAR_64
DECLARE_GLOBAL_DATA_PTR;

15
board/renesas/spider/Kconfig Normal file
View file

@ -0,0 +1,15 @@
if TARGET_SPIDER
config SYS_SOC
default "rmobile"
config SYS_BOARD
default "spider"
config SYS_VENDOR
default "renesas"
config SYS_CONFIG_NAME
default "spider"
endif

9
board/renesas/spider/Makefile Normal file
View file

@ -0,0 +1,9 @@
#
# board/renesas/spider/Makefile
#
# Copyright (C) 2020 Renesas Electronics Corp.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := spider.o ../rcar-common/common.o

72
board/renesas/spider/spider.c Normal file
View file

@ -0,0 +1,72 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* board/renesas/spider/spider.c
* This file is Spider board support.
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <common.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <linux/errno.h>
DECLARE_GLOBAL_DATA_PTR;
static void init_generic_timer(void)
{
const u32 freq = CONFIG_SYS_CLK_FREQ;
/* Update memory mapped and register based freqency */
asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
writel(freq, CNTFID0);
/* Enable counter */
setbits_le32(CNTCR_BASE, CNTCR_EN);
}
static void init_gic_v3(void)
{
/* GIC v3 power on */
writel(BIT(1), GICR_LPI_PWRR);
/* Wait till the WAKER_CA_BIT changes to 0 */
clrbits_le32(GICR_LPI_WAKER, BIT(1));
while (readl(GICR_LPI_WAKER) & BIT(2))
;
writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
}
void s_init(void)
{
if (current_el() == 3)
init_generic_timer();
}
int board_early_init_f(void)
{
/* Unlock CPG access */
writel(0x5A5AFFFF, CPGWPR);
writel(0xA5A50000, CPGWPCR);
return 0;
}
int board_init(void)
{
if (current_el() == 3)
init_gic_v3();
return 0;
}
void reset_cpu(void)
{
writel(RST_SPRES, RST_SRESCR0);
}

15
board/renesas/whitehawk/Kconfig Normal file
View file

@ -0,0 +1,15 @@
if TARGET_WHITEHAWK
config SYS_SOC
default "rmobile"
config SYS_BOARD
default "whitehawk"
config SYS_VENDOR
default "renesas"
config SYS_CONFIG_NAME
default "whitehawk"
endif

9
board/renesas/whitehawk/Makefile Normal file
View file

@ -0,0 +1,9 @@
#
# board/renesas/whitehawk/Makefile
#
# Copyright (C) 2021 Renesas Electronics Corp.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := whitehawk.o ../rcar-common/common.o

72
board/renesas/whitehawk/whitehawk.c Normal file
View file

@ -0,0 +1,72 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* board/renesas/whitehawk/whitehawk.c
* This file is White Hawk board support.
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <common.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/processor.h>
#include <linux/errno.h>
#include <asm/system.h>
DECLARE_GLOBAL_DATA_PTR;
static void init_generic_timer(void)
{
const u32 freq = CONFIG_SYS_CLK_FREQ;
/* Update memory mapped and register based freqency */
asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
writel(freq, CNTFID0);
/* Enable counter */
setbits_le32(CNTCR_BASE, CNTCR_EN);
}
static void init_gic_v3(void)
{
/* GIC v3 power on */
writel(BIT(1), GICR_LPI_PWRR);
/* Wait till the WAKER_CA_BIT changes to 0 */
clrbits_le32(GICR_LPI_WAKER, BIT(1));
while (readl(GICR_LPI_WAKER) & BIT(2))
;
writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
}
void s_init(void)
{
if (current_el() == 3)
init_generic_timer();
}
int board_early_init_f(void)
{
/* Unlock CPG access */
writel(0x5A5AFFFF, CPGWPR);
writel(0xA5A50000, CPGWPCR);
return 0;
}
int board_init(void)
{
if (current_el() == 3)
init_gic_v3();
return 0;
}
void reset_cpu(void)
{
writel(RST_SPRES, RST_SRESCR0);
}

2
common/Kconfig
View file

@ -742,7 +742,7 @@ config SYS_MALLOC_BOOTPARAMS
config SYS_BOOTPARAMS_LEN
hex "Size of the bootparam buffer to malloc in bytes"
depends on SYS_MALLOC_BOOTPARAMS
default 0x20000 if MIPS || RCAR_GEN3
default 0x20000 if MIPS || RCAR_64
default 0x10000
config ID_EEPROM

2
configs/r8a779a0_falcon_defconfig
View file

@ -10,7 +10,7 @@ CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a779a0-falcon-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_RCAR_GEN3=y
CONFIG_RCAR_GEN4=y
CONFIG_TARGET_FALCON=y
CONFIG_SPL_STACK=0xe6304000
CONFIG_SYS_CLK_FREQ=16666666

69
configs/r8a779f0_spider_defconfig Normal file
View file

@ -0,0 +1,69 @@
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xD00000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a779f0-spider-u-boot"
CONFIG_RCAR_GEN4=y
CONFIG_TARGET_SPIDER=y
CONFIG_SYS_CLK_FREQ=20000000
# CONFIG_PSCI_RESET is not set
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_SYS_BOOT_GET_CMDLINE=y
CONFIG_SYS_BARGSIZE=2048
CONFIG_REMAKE_ELF=y
CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image && tftp 0x48000000 Image-r8a779f0-spider.dtb && booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a779f0-spider.dtb"
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_CBSIZE=2048
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_BAUDRATE=1843200
CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_RENESAS_RPC_SPI=y

74
configs/r8a779g0_whitehawk_defconfig Normal file
View file

@ -0,0 +1,74 @@
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a779g0-white-hawk-u-boot"
CONFIG_RCAR_GEN4=y
CONFIG_TARGET_WHITEHAWK=y
CONFIG_SYS_CLK_FREQ=16666666
# CONFIG_PSCI_RESET is not set
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_SYS_BOOT_GET_CMDLINE=y
CONFIG_SYS_BARGSIZE=2048
CONFIG_REMAKE_ELF=y
CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image && tftp 0x48000000 Image-r8a779g0-white-hawk.dtb && booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a779g0-white-hawk.dtb"
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_CBSIZE=2048
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_VERSION_VARIABLE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_RENESAS_RAVB=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_BAUDRATE=921600
CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_RENESAS_RPC_SPI=y

2
doc/device-tree-bindings/serial/sh.txt
View file

@ -1,6 +1,6 @@
* Renesas SCI serial interface
Required properties:
- compatible: must be "renesas,scif", "renesas,scifa" or "renesas,sci"
- compatible: must be "renesas,scif", "renesas,hscif", "renesas,scifa" or "renesas,sci"
- reg: exactly one register range with length
- clock: input clock frequency for the SCI unit

18
drivers/clk/renesas/Kconfig
View file

@ -45,13 +45,13 @@ config CLK_R8A7794
Enable this to support the clocks on Renesas R8A7794 SoC.
config CLK_RCAR_GEN3
bool "Renesas RCar Gen3 clock driver"
def_bool y if RCAR_GEN3
bool "Renesas RCar Gen3 and Gen4 clock driver"
def_bool y if RCAR_64
depends on CLK_RENESAS
select CLK_RCAR_CPG_LIB
select DM_RESET
help
Enable this to support the clocks on Renesas RCar Gen3 SoC.
Enable this to support the clocks on Renesas RCar Gen3 and Gen4 SoCs.
config CLK_R8A774A1
bool "Renesas R8A774A1 clock driver"
@ -131,3 +131,15 @@ config CLK_R8A779A0
depends on CLK_RCAR_GEN3
help
Enable this to support the clocks on Renesas R8A779A0 SoC.
config CLK_R8A779F0
bool "Renesas R8A779F0 clock driver"
depends on CLK_RCAR_GEN3
help
Enable this to support the clocks on Renesas R8A779F0 SoC.
config CLK_R8A779G0
bool "Renesas R8A779G0 clock driver"
depends on CLK_RCAR_GEN3
help
Enable this to support the clocks on Renesas R8A779G0 SoC.

2
drivers/clk/renesas/Makefile
View file

@ -20,3 +20,5 @@ obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o

109
drivers/clk/renesas/clk-rcar-gen3.c
View file

@ -35,10 +35,16 @@
#define CPG_PLL2CR 0x002c
#define CPG_PLL4CR 0x01f4
static const struct clk_div_table cpg_rpcsrc_div_table[] = {
#define SD0CKCR1 0x08a4
static const struct clk_div_table gen3_cpg_rpcsrc_div_table[] = {
{ 2, 5 }, { 3, 6 }, { 0, 0 },
};
static const struct clk_div_table gen4_cpg_rpcsrc_div_table[] = {
{ 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 },
};
static const struct clk_div_table r8a77970_cpg_sd0h_div_table[] = {
{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
@ -181,8 +187,10 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
struct cpg_mssr_info *info = priv->info;
struct clk parent;
const struct cpg_core_clk *core;
const struct rcar_gen3_cpg_pll_config *pll_config =
priv->cpg_pll_config;
const struct rcar_gen3_cpg_pll_config *gen3_pll_config =
priv->gen3_cpg_pll_config;
const struct rcar_gen4_cpg_pll_config *gen4_pll_config =
priv->gen4_cpg_pll_config;
u32 value, div;
u64 rate = 0;
u8 shift;
@ -227,7 +235,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
case CLK_TYPE_GEN3_MAIN:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, 1, pll_config->extal_div,
0, 1, gen3_pll_config->extal_div,
"MAIN");
case CLK_TYPE_GEN3_PLL0:
@ -236,8 +244,9 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
case CLK_TYPE_GEN3_PLL1:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, pll_config->pll1_mult,
pll_config->pll1_div, "PLL1");
0, gen3_pll_config->pll1_mult,
gen3_pll_config->pll1_div,
"PLL1");
case CLK_TYPE_GEN3_PLL2:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
@ -245,8 +254,9 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
case CLK_TYPE_GEN3_PLL3:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, pll_config->pll3_mult,
pll_config->pll3_div, "PLL3");
0, gen3_pll_config->pll3_mult,
gen3_pll_config->pll3_div,
"PLL3");
case CLK_TYPE_GEN3_PLL4:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
@ -254,25 +264,48 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
case CLK_TYPE_GEN4_MAIN:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, 1, pll_config->extal_div,
"V3U_MAIN");
0, 1, gen4_pll_config->extal_div,
"MAIN");
case CLK_TYPE_GEN4_PLL1:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, pll_config->pll1_mult,
pll_config->pll1_div,
"V3U_PLL1");
0, gen4_pll_config->pll1_mult,
gen4_pll_config->pll1_div,
"PLL1");
case CLK_TYPE_GEN4_PLL2:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, gen4_pll_config->pll2_mult,
gen4_pll_config->pll2_div,
"PLL2");
case CLK_TYPE_GEN4_PLL2X_3X:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
core->offset, 0, 0,
"V3U_PLL2X_3X");
core->offset, 0, 0, "PLL2X_3X");
case CLK_TYPE_GEN4_PLL3:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, gen4_pll_config->pll3_mult,
gen4_pll_config->pll3_div,
"PLL3");
case CLK_TYPE_GEN4_PLL4:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, gen4_pll_config->pll4_mult,
gen4_pll_config->pll4_div,
"PLL4");
case CLK_TYPE_GEN4_PLL5:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, pll_config->pll5_mult,
pll_config->pll5_div,
"V3U_PLL5");
0, gen4_pll_config->pll5_mult,
gen4_pll_config->pll5_div,
"PLL5");
case CLK_TYPE_GEN4_PLL6:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, gen4_pll_config->pll6_mult,
gen4_pll_config->pll6_div,
"PLL6");
case CLK_TYPE_FF:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
@ -288,6 +321,13 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
div, rate);
return rate;
case CLK_TYPE_GEN4_SDSRC:
div = ((readl(priv->base + SD0CKCR1) >> 29) & 0x03) + 4;
rate = gen3_clk_get_rate64(&parent) / div;
debug("%s[%i] SDSRC clk: parent=%i div=%u => rate=%llu\n",
__func__, __LINE__, core->parent, div, rate);
return rate;
case CLK_TYPE_GEN3_SDH: /* Fixed factor 1:1 */
fallthrough;
case CLK_TYPE_GEN4_SDH: /* Fixed factor 1:1 */
@ -321,7 +361,16 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
gen3_clk_get_rate64(&parent),
priv->base + CPG_RPCCKCR,
CPG_RPCCKCR_DIV_POST_MASK,
cpg_rpcsrc_div_table, "RPCSRC");
gen3_cpg_rpcsrc_div_table,
"RPCSRC");
case CLK_TYPE_GEN4_RPCSRC:
return rcar_clk_get_rate64_div_table(core->parent,
gen3_clk_get_rate64(&parent),
priv->base + CPG_RPCCKCR,
CPG_RPCCKCR_DIV_POST_MASK,
gen4_cpg_rpcsrc_div_table,
"RPCSRC");
case CLK_TYPE_GEN3_D3_RPCSRC:
case CLK_TYPE_GEN3_E3_RPCSRC:
@ -409,6 +458,7 @@ static int gen3_clk_probe(struct udevice *dev)
struct gen3_clk_priv *priv = dev_get_priv(dev);
struct cpg_mssr_info *info =
(struct cpg_mssr_info *)dev_get_driver_data(dev);
const void *pll_config;
fdt_addr_t rst_base;
int ret;
@ -427,21 +477,24 @@ static int gen3_clk_probe(struct udevice *dev)
priv->cpg_mode = readl(rst_base + info->reset_modemr_offset);
priv->cpg_pll_config =
(struct rcar_gen3_cpg_pll_config *)info->get_pll_config(priv->cpg_mode);
if (!priv->cpg_pll_config->extal_div)
return -EINVAL;
pll_config = info->get_pll_config(priv->cpg_mode);
if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
priv->info->status_regs = mstpsr;
priv->info->control_regs = smstpcr;
priv->info->reset_regs = srcr;
priv->info->reset_clear_regs = srstclr;
} else if (info->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) {
priv->info->status_regs = mstpsr_for_v3u;
priv->info->control_regs = mstpcr_for_v3u;
priv->info->reset_regs = srcr_for_v3u;
priv->info->reset_clear_regs = srstclr_for_v3u;
priv->gen3_cpg_pll_config = pll_config;
if (!priv->gen3_cpg_pll_config->extal_div)
return -EINVAL;
} else if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) {
priv->info->status_regs = mstpsr_for_gen4;
priv->info->control_regs = mstpcr_for_gen4;
priv->info->reset_regs = srcr_for_gen4;
priv->info->reset_clear_regs = srstclr_for_gen4;
priv->gen4_cpg_pll_config = pll_config;
if (!priv->gen4_cpg_pll_config->extal_div)
return -EINVAL;
} else {
return -EINVAL;
}

20
drivers/clk/renesas/r8a779a0-cpg-mssr.c
View file

@ -232,11 +232,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
* 14 13 (MHz) 21 31
* --------------------------------------------------------
* ----------------------------------------------------------------
* 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16
* 0 1 20 x 1 x106 x180 x106 x120 x160 /19
* 1 0 Prohibited setting
@ -244,13 +243,12 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] = {
/* EXTAL div PLL1 mult/div Not used OSC prediv PLL5 mult/div */
{ 1, 128, 1, 128, 1, 16, 192, 1, },
{ 1, 106, 1, 106, 1, 19, 160, 1, },
{ 0, 0, 0, 0, 0, 0, 0, 0, },
{ 2, 128, 1, 128, 1, 32, 192, 1, },
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
{ 1, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 16, },
{ 1, 106, 1, 0, 0, 0, 0, 120, 1, 160, 1, 0, 0, 19, },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 2, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 32, },
};
/*
@ -292,13 +290,13 @@ static const struct cpg_mssr_info r8a779a0_cpg_mssr_info = {
.mstp_table = r8a779a0_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a779a0_mstp_table),
.reset_node = "renesas,r8a779a0-rst",
.reset_modemr_offset = 0x00,
.reset_modemr_offset = CPG_RST_MODEMR0,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
.clk_extalr_id = CLK_EXTALR,
.get_pll_config = r8a779a0_get_pll_config,
.reg_layout = CLK_REG_LAYOUT_RCAR_V3U,
.reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
};
static const struct udevice_id r8a779a0_cpg_ids[] = {

250
drivers/clk/renesas/r8a779f0-cpg-mssr.c Normal file
View file

@ -0,0 +1,250 @@
// SPDX-License-Identifier: GPL-2.0
/*
* r8a779f0 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2021 Renesas Electronics Corp.
*
* Based on r8a779a0-cpg-mssr.c
*/
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A779F0_CLK_R,
/* External Input Clocks */
CLK_EXTAL,
CLK_EXTALR,
/* Internal Core Clocks */
CLK_MAIN,
CLK_PLL1,
CLK_PLL2,
CLK_PLL3,
CLK_PLL5,
CLK_PLL6,
CLK_PLL1_DIV2,
CLK_PLL2_DIV2,
CLK_PLL3_DIV2,
CLK_PLL5_DIV2,
CLK_PLL5_DIV4,
CLK_PLL6_DIV2,
CLK_S0,
CLK_SASYNCPER,
CLK_SDSRC,
CLK_RPCSRC,
CLK_OCO,
/* Module Clocks */
MOD_CLK_BASE
};
static const struct cpg_core_clk r8a779f0_core_clks[] = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1),
DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1),
DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
DEF_RATE(".oco", CLK_OCO, 32768),
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
/* Core Clock Outputs */
DEF_GEN4_Z("z0", R8A779F0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 0),
DEF_GEN4_Z("z1", R8A779F0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 8),
DEF_FIXED("s0d2", R8A779F0_CLK_S0D2, CLK_S0, 2, 1),
DEF_FIXED("s0d3", R8A779F0_CLK_S0D3, CLK_S0, 3, 1),
DEF_FIXED("s0d4", R8A779F0_CLK_S0D4, CLK_S0, 4, 1),
DEF_FIXED("cl16m", R8A779F0_CLK_CL16M, CLK_S0, 48, 1),
DEF_FIXED("s0d2_mm", R8A779F0_CLK_S0D2_MM, CLK_S0, 2, 1),
DEF_FIXED("s0d3_mm", R8A779F0_CLK_S0D3_MM, CLK_S0, 3, 1),
DEF_FIXED("s0d4_mm", R8A779F0_CLK_S0D4_MM, CLK_S0, 4, 1),
DEF_FIXED("cl16m_mm", R8A779F0_CLK_CL16M_MM, CLK_S0, 48, 1),
DEF_FIXED("s0d2_rt", R8A779F0_CLK_S0D2_RT, CLK_S0, 2, 1),
DEF_FIXED("s0d3_rt", R8A779F0_CLK_S0D3_RT, CLK_S0, 3, 1),
DEF_FIXED("s0d4_rt", R8A779F0_CLK_S0D4_RT, CLK_S0, 4, 1),
DEF_FIXED("s0d6_rt", R8A779F0_CLK_S0D6_RT, CLK_S0, 6, 1),
DEF_FIXED("cl16m_rt", R8A779F0_CLK_CL16M_RT, CLK_S0, 48, 1),
DEF_FIXED("s0d3_per", R8A779F0_CLK_S0D3_PER, CLK_S0, 3, 1),
DEF_FIXED("s0d6_per", R8A779F0_CLK_S0D6_PER, CLK_S0, 6, 1),
DEF_FIXED("s0d12_per", R8A779F0_CLK_S0D12_PER, CLK_S0, 12, 1),
DEF_FIXED("s0d24_per", R8A779F0_CLK_S0D24_PER, CLK_S0, 24, 1),
DEF_FIXED("cl16m_per", R8A779F0_CLK_CL16M_PER, CLK_S0, 48, 1),
DEF_FIXED("s0d2_hsc", R8A779F0_CLK_S0D2_HSC, CLK_S0, 2, 1),
DEF_FIXED("s0d3_hsc", R8A779F0_CLK_S0D3_HSC, CLK_S0, 3, 1),
DEF_FIXED("s0d4_hsc", R8A779F0_CLK_S0D4_HSC, CLK_S0, 4, 1),
DEF_FIXED("s0d6_hsc", R8A779F0_CLK_S0D6_HSC, CLK_S0, 6, 1),
DEF_FIXED("s0d12_hsc", R8A779F0_CLK_S0D12_HSC, CLK_S0, 12, 1),
DEF_FIXED("cl16m_hsc", R8A779F0_CLK_CL16M_HSC, CLK_S0, 48, 1),
DEF_FIXED("s0d2_cc", R8A779F0_CLK_S0D2_CC, CLK_S0, 2, 1),
DEF_FIXED("rsw2", R8A779F0_CLK_RSW2, CLK_PLL5_DIV2, 5, 1),
DEF_FIXED("cbfusa", R8A779F0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A779F0_CLK_CPEX, CLK_EXTAL, 2, 1),
DEF_FIXED("sasyncrt", R8A779F0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1),
DEF_FIXED("sasyncperd1",R8A779F0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),
DEF_FIXED("sasyncperd2",R8A779F0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
DEF_FIXED("sasyncperd4",R8A779F0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
DEF_GEN4_SDH("sd0h", R8A779F0_CLK_SD0H, CLK_SDSRC, 0x870),
DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, R8A779F0_CLK_SD0H, 0x870),
DEF_BASE("rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC),
DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8),
DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
};
static const struct mssr_mod_clk r8a779f0_mod_clks[] = {
DEF_MOD("hscif0", 514, R8A779F0_CLK_SASYNCPERD1),
DEF_MOD("hscif1", 515, R8A779F0_CLK_SASYNCPERD1),
DEF_MOD("hscif2", 516, R8A779F0_CLK_SASYNCPERD1),
DEF_MOD("hscif3", 517, R8A779F0_CLK_SASYNCPERD1),
DEF_MOD("i2c0", 518, R8A779F0_CLK_S0D6_PER),
DEF_MOD("i2c1", 519, R8A779F0_CLK_S0D6_PER),
DEF_MOD("i2c2", 520, R8A779F0_CLK_S0D6_PER),
DEF_MOD("i2c3", 521, R8A779F0_CLK_S0D6_PER),
DEF_MOD("i2c4", 522, R8A779F0_CLK_S0D6_PER),
DEF_MOD("i2c5", 523, R8A779F0_CLK_S0D6_PER),
DEF_MOD("msiof0", 618, R8A779F0_CLK_MSO),
DEF_MOD("msiof1", 619, R8A779F0_CLK_MSO),
DEF_MOD("msiof2", 620, R8A779F0_CLK_MSO),
DEF_MOD("msiof3", 621, R8A779F0_CLK_MSO),
DEF_MOD("pcie0", 624, R8A779F0_CLK_S0D2),
DEF_MOD("pcie1", 625, R8A779F0_CLK_S0D2),
DEF_MOD("scif0", 702, R8A779F0_CLK_SASYNCPERD4),
DEF_MOD("scif1", 703, R8A779F0_CLK_SASYNCPERD4),
DEF_MOD("scif3", 704, R8A779F0_CLK_SASYNCPERD4),
DEF_MOD("scif4", 705, R8A779F0_CLK_SASYNCPERD4),
DEF_MOD("sdhi0", 706, R8A779F0_CLK_SD0),
DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER),
DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER),
DEF_MOD("tmu0", 713, R8A779F0_CLK_SASYNCRT),
DEF_MOD("tmu1", 714, R8A779F0_CLK_SASYNCPERD2),
DEF_MOD("tmu2", 715, R8A779F0_CLK_SASYNCPERD2),
DEF_MOD("tmu3", 716, R8A779F0_CLK_SASYNCPERD2),
DEF_MOD("tmu4", 717, R8A779F0_CLK_SASYNCPERD2),
DEF_MOD("wdt", 907, R8A779F0_CLK_R),
DEF_MOD("cmt0", 910, R8A779F0_CLK_R),
DEF_MOD("cmt1", 911, R8A779F0_CLK_R),
DEF_MOD("cmt2", 912, R8A779F0_CLK_R),
DEF_MOD("cmt3", 913, R8A779F0_CLK_R),
DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M),
DEF_MOD("tsc", 919, R8A779F0_CLK_CL16M),
DEF_MOD("rswitch2", 1505, R8A779F0_CLK_RSW2),
DEF_MOD("ether-serdes", 1506, R8A779F0_CLK_S0D2_HSC),
DEF_MOD("ufs", 1514, R8A779F0_CLK_S0D4_HSC),
};
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
* 14 13 (MHz)
* ------------------------------------------------------------------------
* 0 0 16 / 1 x200 x150 x200 n/a x200 x134 /15
* 0 1 20 / 1 x160 x120 x160 n/a x160 x106 /19
* 1 0 Prohibited setting
* 1 1 40 / 2 x160 x120 x160 n/a x160 x106 /38
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
{ 1, 200, 1, 150, 1, 200, 1, 0, 0, 200, 1, 134, 1, 15, },
{ 1, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 19, },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 2, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 38, },
};
/*
* Note that the only clock left running before booting Linux are now
* MFIS, INTC-AP, INTC-EX and HSCIF0/SCIF3 on S4
*/
#define MSTPCR5_HSCIF0 BIT(14)
#define MSTPCR7_SCIF3 BIT(4) /* No information: MFIS, INTC-AP, INTC-EX */
static const struct mstp_stop_table r8a779f0_mstp_table[] = {
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x00800000, 0x0, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x0003c000, MSTPCR5_HSCIF0, 0x0, 0x0 },
{ 0x03000000, 0x0, 0x0, 0x0 },
{ 0x1ffbe040, MSTPCR7_SCIF3, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x00003c78, 0x0, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x9e800000, 0x0, 0x0, 0x0 },
{ 0x00000027, 0x0, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x00005800, 0x0, 0x0, 0x0 },
};
static const void *r8a779f0_get_pll_config(const u32 cpg_mode)
{
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
}
static const struct cpg_mssr_info r8a779f0_cpg_mssr_info = {
.core_clk = r8a779f0_core_clks,
.core_clk_size = ARRAY_SIZE(r8a779f0_core_clks),
.mod_clk = r8a779f0_mod_clks,
.mod_clk_size = ARRAY_SIZE(r8a779f0_mod_clks),
.mstp_table = r8a779f0_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a779f0_mstp_table),
.reset_node = "renesas,r8a779f0-rst",
.reset_modemr_offset = CPG_RST_MODEMR0,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
.clk_extalr_id = CLK_EXTALR,
.get_pll_config = r8a779f0_get_pll_config,
.reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
};
static const struct udevice_id r8a779f0_cpg_ids[] = {
{
.compatible = "renesas,r8a779f0-cpg-mssr",
.data = (ulong)&r8a779f0_cpg_mssr_info
},
{ }
};
U_BOOT_DRIVER(cpg_r8a779f0) = {
.name = "cpg_r8a779f0",
.id = UCLASS_NOP,
.of_match = r8a779f0_cpg_ids,
.bind = gen3_cpg_bind,
};

312
drivers/clk/renesas/r8a779g0-cpg-mssr.c Normal file
View file

@ -0,0 +1,312 @@
// SPDX-License-Identifier: GPL-2.0
/*
* r8a779g0 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2022 Renesas Electronics Corp.
*
* Based on r8a779f0-cpg-mssr.c
*/
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A779G0_CLK_R,
/* External Input Clocks */
CLK_EXTAL,
CLK_EXTALR,
/* Internal Core Clocks */
CLK_MAIN,
CLK_PLL1,
CLK_PLL2,
CLK_PLL3,
CLK_PLL4,
CLK_PLL5,
CLK_PLL6,
CLK_PLL1_DIV2,
CLK_PLL2_DIV2,
CLK_PLL3_DIV2,
CLK_PLL4_DIV2,
CLK_PLL5_DIV2,
CLK_PLL5_DIV4,
CLK_PLL6_DIV2,
CLK_S0,
CLK_S0_VIO,
CLK_S0_VC,
CLK_S0_HSC,
CLK_SASYNCPER,
CLK_SV_VIP,
CLK_SV_IR,
CLK_SDSRC,
CLK_RPCSRC,
CLK_VIO,
CLK_VC,
CLK_OCO,
/* Module Clocks */
MOD_CLK_BASE
};
static const struct cpg_core_clk r8a779g0_core_clks[] = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN),
DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1),
DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1),
DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s0_vio", CLK_S0_VIO, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s0_vc", CLK_S0_VC, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s0_hsc", CLK_S0_HSC, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1),
DEF_FIXED(".sv_vip", CLK_SV_VIP, CLK_PLL1, 5, 1),
DEF_FIXED(".sv_ir", CLK_SV_IR, CLK_PLL1, 5, 1),
DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
DEF_RATE(".oco", CLK_OCO, 32768),
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
DEF_FIXED(".vio", CLK_VIO, CLK_PLL5_DIV2, 3, 1),
DEF_FIXED(".vc", CLK_VC, CLK_PLL5_DIV2, 3, 1),
/* Core Clock Outputs */
DEF_GEN4_Z("z0", R8A779G0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 0),
DEF_FIXED("s0d2", R8A779G0_CLK_S0D2, CLK_S0, 2, 1),
DEF_FIXED("s0d3", R8A779G0_CLK_S0D3, CLK_S0, 3, 1),
DEF_FIXED("s0d4", R8A779G0_CLK_S0D4, CLK_S0, 4, 1),
DEF_FIXED("cl16m", R8A779G0_CLK_CL16M, CLK_S0, 48, 1),
DEF_FIXED("s0d1_vio", R8A779G0_CLK_S0D1_VIO, CLK_S0_VIO, 1, 1),
DEF_FIXED("s0d2_vio", R8A779G0_CLK_S0D2_VIO, CLK_S0_VIO, 2, 1),
DEF_FIXED("s0d4_vio", R8A779G0_CLK_S0D4_VIO, CLK_S0_VIO, 4, 1),
DEF_FIXED("s0d8_vio", R8A779G0_CLK_S0D8_VIO, CLK_S0_VIO, 8, 1),
DEF_FIXED("s0d1_vc", R8A779G0_CLK_S0D1_VC, CLK_S0_VC, 1, 1),
DEF_FIXED("s0d2_vc", R8A779G0_CLK_S0D2_VC, CLK_S0_VC, 2, 1),
DEF_FIXED("s0d4_vc", R8A779G0_CLK_S0D4_VC, CLK_S0_VC, 4, 1),
DEF_FIXED("s0d2_mm", R8A779G0_CLK_S0D2_MM, CLK_S0, 2, 1),
DEF_FIXED("s0d4_mm", R8A779G0_CLK_S0D4_MM, CLK_S0, 4, 1),
DEF_FIXED("cl16m_mm", R8A779G0_CLK_CL16M_MM, CLK_S0, 48, 1),
DEF_FIXED("s0d2_u3dg", R8A779G0_CLK_S0D2_U3DG, CLK_S0, 2, 1),
DEF_FIXED("s0d4_u3dg", R8A779G0_CLK_S0D4_U3DG, CLK_S0, 4, 1),
DEF_FIXED("s0d2_rt", R8A779G0_CLK_S0D2_RT, CLK_S0, 2, 1),
DEF_FIXED("s0d3_rt", R8A779G0_CLK_S0D3_RT, CLK_S0, 3, 1),
DEF_FIXED("s0d4_rt", R8A779G0_CLK_S0D4_RT, CLK_S0, 4, 1),
DEF_FIXED("s0d6_rt", R8A779G0_CLK_S0D6_RT, CLK_S0, 6, 1),
DEF_FIXED("s0d24_rt", R8A779G0_CLK_S0D24_RT, CLK_S0, 24, 1),
DEF_FIXED("cl16m_rt", R8A779G0_CLK_CL16M_RT, CLK_S0, 48, 1),
DEF_FIXED("s0d2_per", R8A779G0_CLK_S0D2_PER, CLK_S0, 2, 1),
DEF_FIXED("s0d3_per", R8A779G0_CLK_S0D3_PER, CLK_S0, 3, 1),
DEF_FIXED("s0d4_per", R8A779G0_CLK_S0D4_PER, CLK_S0, 4, 1),
DEF_FIXED("s0d6_per", R8A779G0_CLK_S0D6_PER, CLK_S0, 6, 1),
DEF_FIXED("s0d12_per", R8A779G0_CLK_S0D12_PER, CLK_S0, 12, 1),
DEF_FIXED("s0d24_per", R8A779G0_CLK_S0D24_PER, CLK_S0, 24, 1),
DEF_FIXED("cl16m_per", R8A779G0_CLK_CL16M_PER, CLK_S0, 48, 1),
DEF_FIXED("s0d1_hsc", R8A779G0_CLK_S0D1_HSC, CLK_S0_HSC, 1, 1),
DEF_FIXED("s0d2_hsc", R8A779G0_CLK_S0D2_HSC, CLK_S0_HSC, 2, 1),
DEF_FIXED("s0d4_hsc", R8A779G0_CLK_S0D4_HSC, CLK_S0_HSC, 4, 1),
DEF_FIXED("cl16m_hsc", R8A779G0_CLK_CL16M_HSC, CLK_S0_HSC, 48, 1),
DEF_FIXED("s0d2_cc", R8A779G0_CLK_S0D2_CC, CLK_S0, 2, 1),
DEF_FIXED("sasyncrt", R8A779G0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1),
DEF_FIXED("sasyncperd1",R8A779G0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),
DEF_FIXED("sasyncperd2",R8A779G0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
DEF_FIXED("sasyncperd4",R8A779G0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
DEF_FIXED("svd1_ir", R8A779G0_CLK_SVD1_IR, CLK_SV_IR, 1, 1),
DEF_FIXED("svd2_ir", R8A779G0_CLK_SVD2_IR, CLK_SV_IR, 2, 1),
DEF_FIXED("svd1_vip", R8A779G0_CLK_SVD1_VIP, CLK_SV_VIP, 1, 1),
DEF_FIXED("svd2_vip", R8A779G0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1),
DEF_FIXED("cbfusa", R8A779G0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A779G0_CLK_CPEX, CLK_EXTAL, 2, 1),
DEF_FIXED("viobus", R8A779G0_CLK_VIOBUS, CLK_VIO, 1, 1),
DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1),
DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, 0x870),
DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, 0x870),
DEF_DIV6P1("mso", R8A779G0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
DEF_BASE("rpc", R8A779G0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
DEF_BASE("rpcd2", R8A779G0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779G0_CLK_RPC),
DEF_GEN4_OSC("osc", R8A779G0_CLK_OSC, CLK_EXTAL, 8),
DEF_GEN4_MDSEL("r", R8A779G0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
};
static const struct mssr_mod_clk r8a779g0_mod_clks[] = {
DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC),
DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),
DEF_MOD("canfd0", 328, R8A779G0_CLK_SASYNCPERD2),
DEF_MOD("dis0", 411, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("fcpvd0", 508, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("fcpvd1", 509, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("hscif0", 514, R8A779G0_CLK_SASYNCPERD1),
DEF_MOD("hscif1", 515, R8A779G0_CLK_SASYNCPERD1),
DEF_MOD("hscif2", 516, R8A779G0_CLK_SASYNCPERD1),
DEF_MOD("hscif3", 517, R8A779G0_CLK_SASYNCPERD1),
DEF_MOD("i2c0", 518, R8A779G0_CLK_S0D6_PER),
DEF_MOD("i2c1", 519, R8A779G0_CLK_S0D6_PER),
DEF_MOD("i2c2", 520, R8A779G0_CLK_S0D6_PER),
DEF_MOD("i2c3", 521, R8A779G0_CLK_S0D6_PER),
DEF_MOD("i2c4", 522, R8A779G0_CLK_S0D6_PER),
DEF_MOD("i2c5", 523, R8A779G0_CLK_S0D6_PER),
DEF_MOD("irqc", 611, R8A779G0_CLK_CL16M),
DEF_MOD("msi0", 618, R8A779G0_CLK_MSO),
DEF_MOD("msi1", 619, R8A779G0_CLK_MSO),
DEF_MOD("msi2", 620, R8A779G0_CLK_MSO),
DEF_MOD("msi3", 621, R8A779G0_CLK_MSO),
DEF_MOD("msi4", 622, R8A779G0_CLK_MSO),
DEF_MOD("msi5", 623, R8A779G0_CLK_MSO),
DEF_MOD("pwm", 628, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("rpc-if", 629, R8A779G0_CLK_RPCD2),
DEF_MOD("scif0", 702, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("scif1", 703, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("scif3", 704, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("scif4", 705, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("sdhi", 706, R8A779G0_CLK_SD0),
DEF_MOD("sys-dmac0", 709, R8A779G0_CLK_S0D6_PER),
DEF_MOD("sys-dmac1", 710, R8A779G0_CLK_S0D6_PER),
DEF_MOD("tmu0", 713, R8A779G0_CLK_SASYNCRT),
DEF_MOD("tmu1", 714, R8A779G0_CLK_SASYNCPERD2),
DEF_MOD("tmu2", 715, R8A779G0_CLK_SASYNCPERD2),
DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2),
DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2),
DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("vspd0", 830, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("vspd1", 831, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R),
DEF_MOD("cmt0", 910, R8A779G0_CLK_R),
DEF_MOD("cmt1", 911, R8A779G0_CLK_R),
DEF_MOD("cmt2", 912, R8A779G0_CLK_R),
DEF_MOD("cmt3", 913, R8A779G0_CLK_R),
DEF_MOD("pfc0", 915, R8A779G0_CLK_CL16M),
DEF_MOD("pfc1", 916, R8A779G0_CLK_CL16M),
DEF_MOD("pfc2", 917, R8A779G0_CLK_CL16M),
DEF_MOD("pfc3", 918, R8A779G0_CLK_CL16M),
};
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
* 14 13 (MHz)
* ------------------------------------------------------------------------
* 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16
* 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19
* 1 0 Prohibited setting
* 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /32
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
{ 1, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 16, },
{ 1, 160, 1, 170, 1, 160, 1, 120, 1, 160, 1, 140, 1, 19, },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 2, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 32, },
};
/*
* Note that the only clock left running before booting Linux are now
* MFIS, INTC-AP, INTC-EX, SCIF0, HSCIF0 on V4H
*/
#define MSTPCR5_HSCIF0 BIT(14) /* No information: MFIS, INTC-AP */
#define MSTPCR6_INTCEX BIT(11) /* No information: MFIS, INTC-AP */
#define MSTPCR7_SCIF0 BIT(2) /* No information: MFIS, INTC-AP */
static const struct mstp_stop_table r8a779g0_mstp_table[] = {
{ 0x0FC302A1, 0x0, 0x0, 0x0 },
{ 0x00D50038, 0x0, 0x0, 0x0 },
{ 0x00003800, 0x0, 0x0, 0x0 },
{ 0xF0000000, 0x0, 0x0, 0x0 },
{ 0x0001CE01, 0x0, 0x0, 0x0 },
{ 0xEEFFE380, MSTPCR5_HSCIF0, 0x0, 0x0 },
{ 0xF3FD3901, MSTPCR6_INTCEX, 0x0, 0x0 },
{ 0xE007E6FF, MSTPCR7_SCIF0, 0x0, 0x0 },
{ 0xC0003FFF, 0x0, 0x0, 0x0 },
{ 0x001FBCF8, 0x0, 0x0, 0x0 },
{ 0x30000000, 0x0, 0x0, 0x0 },
{ 0x000000C3, 0x0, 0x0, 0x0 },
{ 0xDE800000, 0x0, 0x0, 0x0 },
{ 0x00000017, 0x0, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x00000000, 0x0, 0x0, 0x0 },
{ 0x000033C0, 0x0, 0x0, 0x0 },
{ 0x402A001E, 0x0, 0x0, 0x0 },
{ 0x0C010080, 0x0, 0x0, 0x0 },
};
static const void *r8a779g0_get_pll_config(const u32 cpg_mode)
{
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
}
static const struct cpg_mssr_info r8a779g0_cpg_mssr_info = {
.core_clk = r8a779g0_core_clks,
.core_clk_size = ARRAY_SIZE(r8a779g0_core_clks),
.mod_clk = r8a779g0_mod_clks,
.mod_clk_size = ARRAY_SIZE(r8a779g0_mod_clks),
.mstp_table = r8a779g0_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a779g0_mstp_table),
.reset_node = "renesas,r8a779g0-rst",
.reset_modemr_offset = CPG_RST_MODEMR0,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
.clk_extalr_id = CLK_EXTALR,
.get_pll_config = r8a779g0_get_pll_config,
.reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
};
static const struct udevice_id r8a779g0_cpg_ids[] = {
{
.compatible = "renesas,r8a779g0-cpg-mssr",
.data = (ulong)&r8a779g0_cpg_mssr_info
},
{ }
};
U_BOOT_DRIVER(cpg_r8a779g0) = {
.name = "cpg_r8a779g0",
.id = UCLASS_NOP,
.of_match = r8a779g0_cpg_ids,
.bind = gen3_cpg_bind,
};

28
drivers/clk/renesas/rcar-gen3-cpg.h
View file

@ -34,8 +34,13 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN4_MAIN,
CLK_TYPE_GEN4_PLL1,
CLK_TYPE_GEN4_PLL2X_3X, /* PLL[23][01] */
CLK_TYPE_GEN4_PLL2,
CLK_TYPE_GEN4_PLL2X_3X, /* R8A779A0 only */
CLK_TYPE_GEN4_PLL3,
CLK_TYPE_GEN4_PLL5,
CLK_TYPE_GEN4_PLL4,
CLK_TYPE_GEN4_PLL6,
CLK_TYPE_GEN4_SDSRC,
CLK_TYPE_GEN4_SDH,
CLK_TYPE_GEN4_SD,
CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */
@ -107,11 +112,27 @@ struct rcar_gen3_cpg_pll_config {
u8 pll3_mult;
u8 pll3_div;
u8 osc_prediv;
};
struct rcar_gen4_cpg_pll_config {
u8 extal_div;
u8 pll1_mult;
u8 pll1_div;
u8 pll2_mult;
u8 pll2_div;
u8 pll3_mult;
u8 pll3_div;
u8 pll4_mult;
u8 pll4_div;
u8 pll5_mult;
u8 pll5_div;
u8 pll6_mult;
u8 pll6_div;
u8 osc_prediv;
};
#define CPG_RST_MODEMR 0x060
#define CPG_RST_MODEMR0 0x000
#define CPG_SDCKCR_STPnHCK BIT(9)
#define CPG_SDCKCR_STPnCK BIT(8)
@ -133,7 +154,10 @@ struct gen3_clk_priv {
struct clk clk_extal;
struct clk clk_extalr;
u32 cpg_mode;
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
union {
const struct rcar_gen3_cpg_pll_config *gen3_cpg_pll_config;
const struct rcar_gen4_cpg_pll_config *gen4_cpg_pll_config;
};
};
int gen3_cpg_bind(struct udevice *parent);

2
drivers/clk/renesas/renesas-cpg-mssr.c
View file

@ -128,7 +128,7 @@ int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info)
info->mstp_table[i].sdis,
info->mstp_table[i].sen);
if (info->reg_layout == CLK_REG_LAYOUT_RCAR_V3U)
if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4)
continue;
clrsetbits_le32(base + RMSTPCR(i),

28
drivers/clk/renesas/renesas-cpg-mssr.h
View file

@ -17,7 +17,7 @@
enum clk_reg_layout {
CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
CLK_REG_LAYOUT_RCAR_V3U,
CLK_REG_LAYOUT_RCAR_GEN4,
};
struct cpg_mssr_info {
@ -134,7 +134,7 @@ int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
* Module Standby and Software Reset register offets.
*
* If the registers exist, these are valid for SH-Mobile, R-Mobile,
* R-Car Gen2, R-Car Gen3, and RZ/G1.
* R-Car Gen2, R-Car Gen3, R-Car Gen4 and RZ/G1.
* These are NOT valid for R-Car Gen1 and RZ/A1!
*/
@ -147,9 +147,11 @@ static const u16 mstpsr[] = {
0x9A0, 0x9A4, 0x9A8, 0x9AC,
};
static const u16 mstpsr_for_v3u[] = {
static const u16 mstpsr_for_gen4[] = {
0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, 0x2E3C,
0x2E40, 0x2E44, 0x2E48, 0x2E4C, 0x2E50, 0x2E54, 0x2E58, 0x2E5C,
0x2E60, 0x2E64, 0x2E68, 0x2E6C,
};
/*
@ -161,9 +163,11 @@ static const u16 smstpcr[] = {
0x990, 0x994, 0x998, 0x99C,
};
static const u16 mstpcr_for_v3u[] = {
static const u16 mstpcr_for_gen4[] = {
0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38,
0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, 0x2D3C,
0x2D40, 0x2D44, 0x2D48, 0x2D4C, 0x2D50, 0x2D54, 0x2D58, 0x2D5C,
0x2D60, 0x2D64, 0x2D68, 0x2D6C,
};
/*
@ -175,9 +179,11 @@ static const u16 srcr[] = {
0x920, 0x924, 0x928, 0x92C,
};
static const u16 srcr_for_v3u[] = {
static const u16 srcr_for_gen4[] = {
0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38,
0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, 0x2C3C,
0x2C40, 0x2C44, 0x2C48, 0x2C4C, 0x2C50, 0x2C54, 0x2C58, 0x2C5C,
0x2C60, 0x2C64, 0x2C68, 0x2C6C,
};
/* Realtime Module Stop Control Register offsets */
@ -193,9 +199,11 @@ static const u16 srstclr[] = {
0x960, 0x964, 0x968, 0x96C,
};
static const u16 srstclr_for_v3u[] = {
static const u16 srstclr_for_gen4[] = {
0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8,
0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, 0x2CBC,
0x2CC0, 0x2CC4, 0x2CC8, 0x2CCC, 0x2CD0, 0x2CD4, 0x2CD8, 0x2CDC,
0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC,
};
#endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */

1
drivers/gpio/gpio-rcar.c
View file

@ -195,6 +195,7 @@ static const struct udevice_id rcar_gpio_ids[] = {
{ .compatible = "renesas,gpio-r8a779a0", .data = RCAR_GPIO_HAS_INEN },
{ .compatible = "renesas,rcar-gen2-gpio" },
{ .compatible = "renesas,rcar-gen3-gpio" },
{ .compatible = "renesas,rcar-gen4-gpio", .data = RCAR_GPIO_HAS_INEN },
{ /* sentinel */ }
};

2
drivers/gpio/sh_pfc.c
View file

@ -569,7 +569,7 @@ static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
return -1;
if (IS_ENABLED(CONFIG_RCAR_GEN3) &&
if (IS_ENABLED(CONFIG_RCAR_64) &&
((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_INPUT))
offset += 4;

2
drivers/i2c/Kconfig
View file

@ -496,7 +496,7 @@ config SYS_I2C_OMAP24XX
config SYS_I2C_RCAR_I2C
bool "Renesas RCar I2C driver"
depends on (RCAR_GEN2 || RCAR_GEN3) && DM_I2C
depends on (RCAR_GEN2 || RCAR_64) && DM_I2C
help
Support for Renesas RCar I2C controller.

1
drivers/i2c/rcar_i2c.c
View file

@ -369,6 +369,7 @@ static const struct dm_i2c_ops rcar_i2c_ops = {
static const struct udevice_id rcar_i2c_ids[] = {
{ .compatible = "renesas,rcar-gen2-i2c", .data = RCAR_I2C_TYPE_GEN2 },
{ .compatible = "renesas,rcar-gen3-i2c", .data = RCAR_I2C_TYPE_GEN3 },
{ .compatible = "renesas,rcar-gen4-i2c", .data = RCAR_I2C_TYPE_GEN3 },
{ }
};

1
drivers/mmc/renesas-sdhi.c
View file

@ -843,6 +843,7 @@ static const struct udevice_id renesas_sdhi_match[] = {
{ .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,rcar-gen4-sdhi", .data = RENESAS_GEN3_QUIRKS },
{ /* sentinel */ }
};

31
drivers/mmc/tmio-common.c
View file

@ -369,22 +369,23 @@ static bool tmio_sd_addr_is_dmaable(struct mmc_data *data)
if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
return false;
#if defined(CONFIG_RCAR_GEN3)
if (IS_ENABLED(CONFIG_RCAR_64)) {
if (!(data->flags & MMC_DATA_READ) && !IS_ALIGNED(addr, 128))
return false;
/* Gen3 DMA has 32bit limit */
if (addr >> 32)
if (sizeof(addr) > 4 && addr >> 32)
return false;
#endif
}
#if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
defined(CONFIG_SPL_BUILD)
#ifdef CONFIG_SPL_BUILD
if (IS_ENABLED(CONFIG_ARCH_UNIPHIER) && !CONFIG_IS_ENABLED(CONFIG_ARM64)) {
/*
* For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
* of L2, which is unreachable from the DMA engine.
* For UniPhier ARMv7 SoCs, the stack is allocated in locked
* ways of L2, which is unreachable from the DMA engine.
*/
if (addr < CONFIG_SPL_STACK)
return false;
}
#endif
return true;
@ -622,25 +623,22 @@ static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, struct mmc *mmc)
static void tmio_sd_set_pins(struct udevice *dev)
{
__maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
#ifdef CONFIG_DM_REGULATOR
struct tmio_sd_priv *priv = dev_get_priv(dev);
if (priv->vqmmc_dev) {
if (CONFIG_IS_ENABLED(DM_REGULATOR) && priv->vqmmc_dev) {
if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
regulator_set_value(priv->vqmmc_dev, 1800000);
else
regulator_set_value(priv->vqmmc_dev, 3300000);
regulator_set_enable(priv->vqmmc_dev, true);
}
#endif
#ifdef CONFIG_PINCTRL
if (CONFIG_IS_ENABLED(PINCTRL)) {
if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
pinctrl_select_state(dev, "state_uhs");
else
pinctrl_select_state(dev, "default");
#endif
}
}
int tmio_sd_set_ios(struct udevice *dev)
@ -734,11 +732,12 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks)
if (!priv->regbase)
return -ENOMEM;
#ifdef CONFIG_DM_REGULATOR
device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
device_get_supply_regulator(dev, "vqmmc-supply",
&priv->vqmmc_dev);
if (priv->vqmmc_dev)
regulator_set_value(priv->vqmmc_dev, 3300000);
#endif
}
ret = mmc_of_parse(dev, &plat->cfg);
if (ret < 0) {

2
drivers/mmc/tmio-common.h
View file

@ -133,9 +133,7 @@ struct tmio_sd_priv {
#define TMIO_SD_CAP_RCAR_UHS BIT(7) /* Renesas RCar UHS/SDR modes */
#define TMIO_SD_CAP_RCAR \
(TMIO_SD_CAP_RCAR_GEN2 | TMIO_SD_CAP_RCAR_GEN3)
#ifdef CONFIG_DM_REGULATOR
struct udevice *vqmmc_dev;
#endif
#if CONFIG_IS_ENABLED(CLK)
struct clk clk;
struct clk clkh;

2
drivers/net/Kconfig
View file

@ -754,7 +754,7 @@ config GMAC_ROCKCHIP
config RENESAS_RAVB
bool "Renesas Ethernet AVB MAC"
depends on RCAR_GEN3
depends on RCAR_64
select PHYLIB
help
This driver implements support for the Ethernet AVB block in

1
drivers/net/ravb.c
View file

@ -692,6 +692,7 @@ int ravb_of_to_plat(struct udevice *dev)
static const struct udevice_id ravb_ids[] = {
{ .compatible = "renesas,etheravb-rcar-gen3" },
{ .compatible = "renesas,etheravb-rcar-gen4" },
{ }
};

12
drivers/pinctrl/renesas/Kconfig
View file

@ -119,6 +119,18 @@ config PINCTRL_PFC_R8A779A0
help
Support pin multiplexing control on Renesas RCar Gen3 R8A779A0 SoCs.
config PINCTRL_PFC_R8A779F0
bool "Renesas RCar Gen4 R8A779F0 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen4 R8A779F0 SoCs.
config PINCTRL_PFC_R8A779G0
bool "Renesas RCar Gen4 R8A779G0 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen4 R8A779G0 SoCs.
config PINCTRL_PFC_R7S72100
bool "Renesas RZ/A1 R7S72100 pin control driver"
depends on CPU_RZA1

2
drivers/pinctrl/renesas/Makefile
View file

@ -17,4 +17,6 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o
obj-$(CONFIG_PINCTRL_PFC_R8A779G0) += pfc-r8a779g0.o
obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o

2106
drivers/pinctrl/renesas/pfc-r8a779f0.c Normal file
View file

File diff suppressed because it is too large Load diff

4265
drivers/pinctrl/renesas/pfc-r8a779g0.c Normal file
View file

File diff suppressed because it is too large Load diff

28
drivers/pinctrl/renesas/pfc.c
View file

@ -43,6 +43,8 @@ enum sh_pfc_model {
SH_PFC_R8A77990,
SH_PFC_R8A77995,
SH_PFC_R8A779A0,
SH_PFC_R8A779F0,
SH_PFC_R8A779G0,
};
struct sh_pfc_pin_config {
@ -810,6 +812,8 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
void __iomem *pocctrl;
u32 addr, val;
int bit, ret;
int idx = sh_pfc_get_pin_index(pfc, _pin);
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
if (!sh_pfc_pinconf_validate(pfc, _pin, param))
return -ENOTSUPP;
@ -842,13 +846,13 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
return bit;
}
if (arg != 1800 && arg != 3300)
if (arg != 1800 && arg != 2500 && arg != 3300)
return -EINVAL;
pocctrl = (void __iomem *)(uintptr_t)addr;
val = sh_pfc_read_raw_reg(pocctrl, 32);
if (arg == 3300)
if (arg == ((pin->configs & SH_PFC_PIN_VOLTAGE_18_25) ? 2500 : 3300))
val |= BIT(bit);
else
val &= ~BIT(bit);
@ -1025,6 +1029,14 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev)
if (model == SH_PFC_R8A779A0)
priv->pfc.info = &r8a779a0_pinmux_info;
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A779F0
if (model == SH_PFC_R8A779F0)
priv->pfc.info = &r8a779f0_pinmux_info;
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A779G0
if (model == SH_PFC_R8A779G0)
priv->pfc.info = &r8a779g0_pinmux_info;
#endif
priv->pmx.pfc = &priv->pfc;
sh_pfc_init_ranges(&priv->pfc);
@ -1142,6 +1154,18 @@ static const struct udevice_id sh_pfc_pinctrl_ids[] = {
.data = SH_PFC_R8A779A0,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A779F0
{
.compatible = "renesas,pfc-r8a779f0",
.data = SH_PFC_R8A779F0,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A779G0
{
.compatible = "renesas,pfc-r8a779g0",
.data = SH_PFC_R8A779G0,
},
#endif
{ },
};

5
drivers/pinctrl/renesas/sh_pfc.h
View file

@ -31,11 +31,14 @@ enum {
#define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6)
#define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6)
#define SH_PFC_PIN_VOLTAGE_18_25 (2 << 6)
#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
SH_PFC_PIN_VOLTAGE_18_33)
#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
SH_PFC_PIN_VOLTAGE_25_33)
#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_25 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
SH_PFC_PIN_VOLTAGE_18_25)
#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
@ -309,6 +312,8 @@ extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
extern const struct sh_pfc_soc_info r8a779a0_pinmux_info;
extern const struct sh_pfc_soc_info r8a779f0_pinmux_info;
extern const struct sh_pfc_soc_info r8a779g0_pinmux_info;
/* -----------------------------------------------------------------------------
* Helper macros to create pin and port lists

6
drivers/serial/serial_sh.c
View file

@ -57,6 +57,9 @@ static void sh_serial_init_generic(struct uart_port *port)
#if defined(CONFIG_RZA1)
sci_out(port, SCSPTR, 0x0003);
#endif
if (port->type == PORT_HSCIF)
sci_out(port, HSSRR, HSSRR_SRE | HSSRR_SRCYC8);
}
static void
@ -205,6 +208,7 @@ static const struct udevice_id sh_serial_id[] ={
{.compatible = "renesas,sci", .data = PORT_SCI},
{.compatible = "renesas,scif", .data = PORT_SCIF},
{.compatible = "renesas,scifa", .data = PORT_SCIFA},
{.compatible = "renesas,hscif", .data = PORT_HSCIF},
{}
};
@ -257,6 +261,8 @@ U_BOOT_DRIVER(serial_sh) = {
#define SCIF_BASE_PORT PORT_SCIFA
#elif defined(CFG_SCI)
#define SCIF_BASE_PORT PORT_SCI
#elif defined(CFG_HSCIF)
#define SCIF_BASE_PORT PORT_HSCIF
#else
#define SCIF_BASE_PORT PORT_SCIF
#endif

28
drivers/serial/serial_sh.h
View file

@ -89,7 +89,7 @@ struct uart_port {
# define SCSPTR7 0xe800a820 /* 16 bit SCIF */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
# define SCIF_ORER 0x0001 /* overrun error bit */
#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || \
#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_64) || \
defined(CONFIG_R7S72100)
# if defined(CFG_SCIF_A)
# define SCIF_ORER 0x0200
@ -213,6 +213,10 @@ struct uart_port {
#define SCFCR_TCRST 0x4000
#define SCFCR_MCE 0x0008
/* HSSRR */
#define HSSRR_SRE BIT(15)
#define HSSRR_SRCYC8 0x0007
#define SCI_MAJOR 204
#define SCI_MINOR_START 8
@ -242,7 +246,8 @@ struct uart_port {
#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
if (port->type == PORT_SCIF || port->type == PORT_SCIFB ||\
port->type == PORT_HSCIF) {\
SCI_IN(scif_size, scif_offset)\
} else { /* PORT_SCI or PORT_SCIFA */\
SCI_IN(sci_size, sci_offset);\
@ -250,7 +255,8 @@ struct uart_port {
}\
static inline void sci_##name##_out(struct uart_port *port,\
unsigned int value) {\
if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
if (port->type == PORT_SCIF || port->type == PORT_SCIFB ||\
port->type == PORT_HSCIF) {\
SCI_OUT(scif_size, scif_offset, value)\
} else { /* PORT_SCI or PORT_SCIFA */\
SCI_OUT(sci_size, sci_offset, value);\
@ -375,6 +381,7 @@ SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
SCIF_FNS(DL, 0, 0, 0x30, 16)
SCIF_FNS(CKS, 0, 0, 0x34, 16)
SCIF_FNS(HSSRR, 0, 0, 0x40, 16) /* HSCIF only */
#if defined(CFG_SCIF_A)
SCIF_FNS(SCLSR, 0, 0, 0x14, 16)
#else
@ -414,7 +421,9 @@ SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
#endif
SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
#endif
SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */
SCIF_FNS(DL, 0, 0, 0x30, 16)
SCIF_FNS(CKS, 0, 0, 0x34, 16)
SCIF_FNS(HSSRR, 0, 0, 0x40, 16) /* HSCIF only */
#endif
#define sci_in(port, reg) sci_##reg##_in(port)
#define sci_out(port, reg, value) sci_##reg##_out(port, value)
@ -485,11 +494,20 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
#elif defined(CONFIG_RCAR_GEN2)
#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
#if defined(CFG_SCIF_A)
#if defined(CFG_SCIF_A) || defined(CFG_HSCIF)
#define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */
#else
#define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
#endif
#elif defined(CONFIG_RCAR_64)
static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
{
if (port->type == PORT_SCIF)
return (clk + 16 * bps) / (32 * bps) - 1;
else /* PORT_HSCIF */
return clk / bps / 8 / 2 - 1; /* Internal Clock, Sampling rate = 8 */
}
#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
#else /* Generic SH */
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
#endif

2
drivers/spi/Kconfig
View file

@ -381,7 +381,7 @@ config SPI_QUP
config RENESAS_RPC_SPI
bool "Renesas RPC SPI driver"
depends on RCAR_GEN3 || RZA1
depends on RCAR_64 || RZA1
imply SPI_FLASH_BAR
help
Enable the Renesas RPC SPI driver, used to access SPI NOR flash

12
include/configs/falcon.h
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@ -9,17 +9,7 @@
#ifndef __FALCON_H
#define __FALCON_H
#include "rcar-gen3-common.h"
/*
* Generic Interrupt Controller Definitions. Undefine v2 locations and define
* v3 locations.
*/
#undef GICD_BASE
#undef GICC_BASE
#undef GICR_BASE
#define GICD_BASE 0xF1000000
#define GICR_BASE 0xF1060000
#include "rcar-gen4-common.h"
/* Board Clock */
/* XTAL_CLK : 16.66MHz */

30
include/configs/rcar-gen4-common.h Normal file
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@ -0,0 +1,30 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* include/configs/rcar-gen4-common.h
* This file is R-Car Gen4 common configuration file.
*
* Copyright (C) 2021 Renesas Electronics Corporation
*/
#ifndef __RCAR_GEN4_COMMON_H
#define __RCAR_GEN4_COMMON_H
#include <asm/arch/rmobile.h>
/* Console */
#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200 }
/* Memory */
#define DRAM_RSV_SIZE 0x08000000
#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
#define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
/* PHY needs a longer autoneg timeout */
#define PHY_ANEG_TIMEOUT 20000
/* Environment setting */
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
#endif /* __RCAR_GEN4_COMMON_H */

14
include/configs/spider.h Normal file
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@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* include/configs/spider.h
* This file is Spider board configuration.
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#ifndef __SPIDER_H
#define __SPIDER_H
#include "rcar-gen4-common.h"
#endif /* __SPIDER_H */

14
include/configs/whitehawk.h Normal file
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@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* include/configs/whitehawk.h
* This file is White Hawk board configuration.
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#ifndef __WHITEHAWK_H
#define __WHITEHAWK_H
#include "rcar-gen4-common.h"
#endif /* __WHITEHAWK_H */

1
include/dm/platform_data/serial_sh.h
View file

@ -17,6 +17,7 @@ enum sh_serial_type {
PORT_SCIF,
PORT_SCIFA,
PORT_SCIFB,
PORT_HSCIF,
};
/*

64
include/dt-bindings/clock/r8a779f0-cpg-mssr.h Normal file
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@ -0,0 +1,64 @@
/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
/*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a779f0 CPG Core Clocks */
#define R8A779F0_CLK_ZX 0
#define R8A779F0_CLK_ZS 1
#define R8A779F0_CLK_ZT 2
#define R8A779F0_CLK_ZTR 3
#define R8A779F0_CLK_S0D2 4
#define R8A779F0_CLK_S0D3 5
#define R8A779F0_CLK_S0D4 6
#define R8A779F0_CLK_S0D2_MM 7
#define R8A779F0_CLK_S0D3_MM 8
#define R8A779F0_CLK_S0D4_MM 9
#define R8A779F0_CLK_S0D2_RT 10
#define R8A779F0_CLK_S0D3_RT 11
#define R8A779F0_CLK_S0D4_RT 12
#define R8A779F0_CLK_S0D6_RT 13
#define R8A779F0_CLK_S0D3_PER 14
#define R8A779F0_CLK_S0D6_PER 15
#define R8A779F0_CLK_S0D12_PER 16
#define R8A779F0_CLK_S0D24_PER 17
#define R8A779F0_CLK_S0D2_HSC 18
#define R8A779F0_CLK_S0D3_HSC 19
#define R8A779F0_CLK_S0D4_HSC 20
#define R8A779F0_CLK_S0D6_HSC 21
#define R8A779F0_CLK_S0D12_HSC 22
#define R8A779F0_CLK_S0D2_CC 23
#define R8A779F0_CLK_CL 24
#define R8A779F0_CLK_CL16M 25
#define R8A779F0_CLK_CL16M_MM 26
#define R8A779F0_CLK_CL16M_RT 27
#define R8A779F0_CLK_CL16M_PER 28
#define R8A779F0_CLK_CL16M_HSC 29
#define R8A779F0_CLK_Z0 30
#define R8A779F0_CLK_Z1 31
#define R8A779F0_CLK_ZB3 32
#define R8A779F0_CLK_ZB3D2 33
#define R8A779F0_CLK_ZB3D4 34
#define R8A779F0_CLK_SD0H 35
#define R8A779F0_CLK_SD0 36
#define R8A779F0_CLK_RPC 37
#define R8A779F0_CLK_RPCD2 38
#define R8A779F0_CLK_MSO 39
#define R8A779F0_CLK_SASYNCRT 40
#define R8A779F0_CLK_SASYNCPERD1 41
#define R8A779F0_CLK_SASYNCPERD2 42
#define R8A779F0_CLK_SASYNCPERD4 43
#define R8A779F0_CLK_DBGSOC_HSC 44
#define R8A779F0_CLK_RSW2 45
#define R8A779F0_CLK_OSC 46
#define R8A779F0_CLK_ZR 47
#define R8A779F0_CLK_CPEX 48
#define R8A779F0_CLK_CBFUSA 49
#define R8A779F0_CLK_R 50
#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */

90
include/dt-bindings/clock/r8a779g0-cpg-mssr.h Normal file
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@ -0,0 +1,90 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a779g0 CPG Core Clocks */
#define R8A779G0_CLK_ZX 0
#define R8A779G0_CLK_ZS 1
#define R8A779G0_CLK_ZT 2
#define R8A779G0_CLK_ZTR 3
#define R8A779G0_CLK_S0D2 4
#define R8A779G0_CLK_S0D3 5
#define R8A779G0_CLK_S0D4 6
#define R8A779G0_CLK_S0D1_VIO 7
#define R8A779G0_CLK_S0D2_VIO 8
#define R8A779G0_CLK_S0D4_VIO 9
#define R8A779G0_CLK_S0D8_VIO 10
#define R8A779G0_CLK_S0D1_VC 11
#define R8A779G0_CLK_S0D2_VC 12
#define R8A779G0_CLK_S0D4_VC 13
#define R8A779G0_CLK_S0D2_MM 14
#define R8A779G0_CLK_S0D4_MM 15
#define R8A779G0_CLK_S0D2_U3DG 16
#define R8A779G0_CLK_S0D4_U3DG 17
#define R8A779G0_CLK_S0D2_RT 18
#define R8A779G0_CLK_S0D3_RT 19
#define R8A779G0_CLK_S0D4_RT 20
#define R8A779G0_CLK_S0D6_RT 21
#define R8A779G0_CLK_S0D24_RT 22
#define R8A779G0_CLK_S0D2_PER 23
#define R8A779G0_CLK_S0D3_PER 24
#define R8A779G0_CLK_S0D4_PER 25
#define R8A779G0_CLK_S0D6_PER 26
#define R8A779G0_CLK_S0D12_PER 27
#define R8A779G0_CLK_S0D24_PER 28
#define R8A779G0_CLK_S0D1_HSC 29
#define R8A779G0_CLK_S0D2_HSC 30
#define R8A779G0_CLK_S0D4_HSC 31
#define R8A779G0_CLK_S0D2_CC 32
#define R8A779G0_CLK_SVD1_IR 33
#define R8A779G0_CLK_SVD2_IR 34
#define R8A779G0_CLK_SVD1_VIP 35
#define R8A779G0_CLK_SVD2_VIP 36
#define R8A779G0_CLK_CL 37
#define R8A779G0_CLK_CL16M 38
#define R8A779G0_CLK_CL16M_MM 39
#define R8A779G0_CLK_CL16M_RT 40
#define R8A779G0_CLK_CL16M_PER 41
#define R8A779G0_CLK_CL16M_HSC 42
#define R8A779G0_CLK_Z0 43
#define R8A779G0_CLK_ZB3 44
#define R8A779G0_CLK_ZB3D2 45
#define R8A779G0_CLK_ZB3D4 46
#define R8A779G0_CLK_ZG 47
#define R8A779G0_CLK_SD0H 48
#define R8A779G0_CLK_SD0 49
#define R8A779G0_CLK_RPC 50
#define R8A779G0_CLK_RPCD2 51
#define R8A779G0_CLK_MSO 52
#define R8A779G0_CLK_CANFD 53
#define R8A779G0_CLK_CSI 54
#define R8A779G0_CLK_FRAY 55
#define R8A779G0_CLK_IPC 56
#define R8A779G0_CLK_SASYNCRT 57
#define R8A779G0_CLK_SASYNCPERD1 58
#define R8A779G0_CLK_SASYNCPERD2 59
#define R8A779G0_CLK_SASYNCPERD4 60
#define R8A779G0_CLK_VIOBUS 61
#define R8A779G0_CLK_VIOBUSD2 62
#define R8A779G0_CLK_VCBUS 63
#define R8A779G0_CLK_VCBUSD2 64
#define R8A779G0_CLK_DSIEXT 65
#define R8A779G0_CLK_DSIREF 66
#define R8A779G0_CLK_ADGH 67
#define R8A779G0_CLK_OSC 68
#define R8A779G0_CLK_ZR0 69
#define R8A779G0_CLK_ZR1 70
#define R8A779G0_CLK_ZR2 71
#define R8A779G0_CLK_IMPA 72
#define R8A779G0_CLK_IMPAD4 73
#define R8A779G0_CLK_CPEX 74
#define R8A779G0_CLK_CBFUSA 75
#define R8A779G0_CLK_R 76
#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */

30
include/dt-bindings/power/r8a779f0-sysc.h Normal file
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@ -0,0 +1,30 @@
/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
/*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A779F0_SYSC_H__
#define __DT_BINDINGS_POWER_R8A779F0_SYSC_H__
/*
* These power domain indices match the Power Domain Register Numbers (PDR)
*/
#define R8A779F0_PD_A1E0D0C0 0
#define R8A779F0_PD_A1E0D0C1 1
#define R8A779F0_PD_A1E0D1C0 2
#define R8A779F0_PD_A1E0D1C1 3
#define R8A779F0_PD_A1E1D0C0 4
#define R8A779F0_PD_A1E1D0C1 5
#define R8A779F0_PD_A1E1D1C0 6
#define R8A779F0_PD_A1E1D1C1 7
#define R8A779F0_PD_A2E0D0 16
#define R8A779F0_PD_A2E0D1 17
#define R8A779F0_PD_A2E1D0 18
#define R8A779F0_PD_A2E1D1 19
#define R8A779F0_PD_A3E0 20
#define R8A779F0_PD_A3E1 21
/* Always-on power area */
#define R8A779F0_PD_ALWAYS_ON 64
#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__*/

46
include/dt-bindings/power/r8a779g0-sysc.h Normal file
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@ -0,0 +1,46 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
#define __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
/*
* These power domain indices match the Power Domain Register Numbers (PDR)
*/
#define R8A779G0_PD_A1E0D0C0 0
#define R8A779G0_PD_A1E0D0C1 1
#define R8A779G0_PD_A1E0D1C0 2
#define R8A779G0_PD_A1E0D1C1 3
#define R8A779G0_PD_A2E0D0 16
#define R8A779G0_PD_A2E0D1 17
#define R8A779G0_PD_A3E0 20
#define R8A779G0_PD_A33DGA 24
#define R8A779G0_PD_A23DGB 25
#define R8A779G0_PD_A1DSP0 33
#define R8A779G0_PD_A2IMP01 34
#define R8A779G0_PD_A2PSC 35
#define R8A779G0_PD_A2CV0 36
#define R8A779G0_PD_A2CV1 37
#define R8A779G0_PD_A1CNN0 41
#define R8A779G0_PD_A2CN0 42
#define R8A779G0_PD_A3IR 43
#define R8A779G0_PD_A1DSP1 45
#define R8A779G0_PD_A2IMP23 46
#define R8A779G0_PD_A2DMA 47
#define R8A779G0_PD_A2CV2 48
#define R8A779G0_PD_A2CV3 49
#define R8A779G0_PD_A1DSP2 53
#define R8A779G0_PD_A1DSP3 54
#define R8A779G0_PD_A3VIP0 56
#define R8A779G0_PD_A3VIP1 57
#define R8A779G0_PD_A3VIP2 58
#define R8A779G0_PD_A3ISP0 60
#define R8A779G0_PD_A3ISP1 61
#define R8A779G0_PD_A3DUL 62
/* Always-on power area */
#define R8A779G0_PD_ALWAYS_ON 64
#endif /* __DT_BINDINGS_POWER_R8A779G0_SYSC_H__*/