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https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-i2c
- Fix for mxc_i2c driver in DM mode, thanks to Trent!
This commit is contained in:
Tom Rini
commit
956520cd70
3 changed files with 116 additions and 37 deletions
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@ -46,6 +46,15 @@ DECLARE_GLOBAL_DATA_PTR;
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#define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13)
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#define REV_DETECTION IMX_GPIO_NR(2, 28)
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/* Speed defined in Kconfig is only applicable when not using DM_I2C. */
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#ifdef CONFIG_DM_I2C
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#define I2C1_SPEED_NON_DM 0
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#define I2C2_SPEED_NON_DM 0
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#else
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#define I2C1_SPEED_NON_DM CONFIG_SYS_MXC_I2C1_SPEED
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#define I2C2_SPEED_NON_DM CONFIG_SYS_MXC_I2C2_SPEED
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#endif
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static bool with_pmic;
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int dram_init(void)
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@ -463,13 +472,13 @@ int board_init(void)
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#if defined(CONFIG_VIDEO_IPUV3)
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setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
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setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
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if (is_mx6dq() || is_mx6dqp()) {
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setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6q_i2c2_pad_info);
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setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6q_i2c3_pad_info);
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setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info);
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setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info);
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} else {
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setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
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setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
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setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
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setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info);
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}
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setup_display();
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@ -161,7 +161,10 @@ config SYS_I2C_MXC
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channels and operating on standard mode up to 100 kbits/s and fast
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mode up to 400 kbits/s.
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if SYS_I2C_MXC
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# These settings are not used with DM_I2C, however SPL doesn't use
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# DM_I2C even if DM_I2C is enabled, and so might use these settings even
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# when main u-boot does not!
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if SYS_I2C_MXC && (!DM_I2C || SPL)
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config SYS_I2C_MXC_I2C1
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bool "NXP MXC I2C1"
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help
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@ -482,8 +482,13 @@ static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
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return ret;
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}
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/* Will generate a STOP after the last byte if "last" is true, i.e. this is the
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* final message of a transaction. If not, it switches the bus back to TX mode
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* and does not send a STOP, leaving the bus in a state where a repeated start
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* and address can be sent for another message.
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*/
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static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
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int len)
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int len, bool last)
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{
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int ret;
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unsigned int temp;
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@ -513,17 +518,31 @@ static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
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return ret;
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}
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/*
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* It must generate STOP before read I2DR to prevent
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* controller from generating another clock cycle
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*/
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if (i == (len - 1)) {
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i2c_imx_stop(i2c_bus);
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/* Final byte has already been received by master! When
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* we read it from I2DR, the master will start another
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* cycle. We must program it first to send a STOP or
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* switch to TX to avoid this.
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*/
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if (last) {
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i2c_imx_stop(i2c_bus);
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} else {
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/* Final read, no stop, switch back to tx */
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temp = readb(base + (I2CR << reg_shift));
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temp |= I2CR_MTX | I2CR_TX_NO_AK;
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writeb(temp, base + (I2CR << reg_shift));
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}
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} else if (i == (len - 2)) {
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/* Master has already recevied penultimate byte. When
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* we read it from I2DR, master will start RX of final
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* byte. We must set TX_NO_AK now so it does not ACK
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* that final byte.
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*/
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temp = readb(base + (I2CR << reg_shift));
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temp |= I2CR_TX_NO_AK;
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writeb(temp, base + (I2CR << reg_shift));
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}
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writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
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buf[i] = readb(base + (I2DR << reg_shift));
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}
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@ -533,13 +552,34 @@ static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
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debug(" 0x%02x", buf[ret]);
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debug("\n");
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i2c_imx_stop(i2c_bus);
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/* It is not clear to me that this is necessary */
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if (last)
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i2c_imx_stop(i2c_bus);
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return 0;
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}
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#ifndef CONFIG_DM_I2C
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/*
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* Read data from I2C device
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*
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* The transactions use the syntax defined in the Linux kernel I2C docs.
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*
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* If alen is > 0, then this function will send a transaction of the form:
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* S Chip Wr [A] Addr [A] S Chip Rd [A] [data] A ... NA P
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* This is a normal I2C register read: writing the register address, then doing
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* a repeated start and reading the data.
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*
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* If alen == 0, then we get this transaction:
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* S Chip Wr [A] S Chip Rd [A] [data] A ... NA P
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* This is somewhat unusual, though valid, transaction. It addresses the chip
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* in write mode, but doesn't actually write any register address or data, then
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* does a repeated start and reads data.
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*
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* If alen < 0, then we get this transaction:
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* S Chip Rd [A] [data] A ... NA P
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* The chip is addressed in read mode and then data is read. No register
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* address is written first. This is perfectly valid on most devices and
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* required on some (usually those that don't act like an array of registers).
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*/
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static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
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int alen, u8 *buf, int len)
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@ -566,7 +606,7 @@ static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
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return ret;
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}
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ret = i2c_read_data(i2c_bus, chip, buf, len);
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ret = i2c_read_data(i2c_bus, chip, buf, len, true);
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i2c_imx_stop(i2c_bus);
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return ret;
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@ -574,6 +614,20 @@ static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
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/*
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* Write data to I2C device
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*
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* If alen > 0, we get this transaction:
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* S Chip Wr [A] addr [A] data [A] ... [A] P
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* An ordinary write register command.
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*
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* If alen == 0, then we get this:
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* S Chip Wr [A] data [A] ... [A] P
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* This is a simple I2C write.
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*
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* If alen < 0, then we get this:
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* S data [A] ... [A] P
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* This is most likely NOT something that should be used. It doesn't send the
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* chip address first, so in effect, the first byte of data will be used as the
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* address.
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*/
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static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
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int alen, const u8 *buf, int len)
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@ -881,6 +935,7 @@ static int mxc_i2c_probe(struct udevice *bus)
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return 0;
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}
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/* Sends: S Addr Wr [A|NA] P */
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static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
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u32 chip_flags)
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{
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@ -905,42 +960,54 @@ static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
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ulong base = i2c_bus->base;
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int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
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VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
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int read_mode;
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/*
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* Here the 3rd parameter addr and the 4th one alen are set to 0,
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* because here we only want to send out chip address. The register
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* address is wrapped in msg.
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/* Here address len is set to -1 to not send any address at first.
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* Otherwise i2c_init_transfer will send the chip address with write
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* mode set. This is wrong if the 1st message is read.
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*/
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ret = i2c_init_transfer(i2c_bus, msg->addr, 0, 0);
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ret = i2c_init_transfer(i2c_bus, msg->addr, 0, -1);
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if (ret < 0) {
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debug("i2c_init_transfer error: %d\n", ret);
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return ret;
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}
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read_mode = -1; /* So it's always different on the first message */
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for (; nmsgs > 0; nmsgs--, msg++) {
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bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
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debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
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if (msg->flags & I2C_M_RD)
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ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
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msg->len);
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else {
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ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
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msg->len);
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if (ret)
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break;
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if (next_is_read) {
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/* Reuse ret */
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const int msg_is_read = !!(msg->flags & I2C_M_RD);
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debug("i2c_xfer: chip=0x%x, len=0x%x, dir=%c\n", msg->addr,
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msg->len, msg_is_read ? 'R' : 'W');
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if (msg_is_read != read_mode) {
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/* Send repeated start if not 1st message */
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if (read_mode != -1) {
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debug("i2c_xfer: [RSTART]\n");
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ret = readb(base + (I2CR << reg_shift));
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ret |= I2CR_RSTA;
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writeb(ret, base + (I2CR << reg_shift));
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ret = tx_byte(i2c_bus, (msg->addr << 1) | 1);
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if (ret < 0) {
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i2c_imx_stop(i2c_bus);
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break;
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}
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}
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debug("i2c_xfer: [ADDR %02x | %c]\n", msg->addr,
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msg_is_read ? 'R' : 'W');
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ret = tx_byte(i2c_bus, (msg->addr << 1) | msg_is_read);
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if (ret < 0) {
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debug("i2c_xfer: [STOP]\n");
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i2c_imx_stop(i2c_bus);
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break;
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}
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read_mode = msg_is_read;
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}
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if (msg->flags & I2C_M_RD)
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ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
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msg->len, nmsgs == 1 ||
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(msg->flags & I2C_M_STOP));
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else
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ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
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msg->len);
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if (ret < 0)
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break;
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}
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if (ret)
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