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Merge branch '2023-02-07-Kconfig-cleanup-dead-code-removal'

Browse source 
To quote the author:
This series adds source scanning to moveconfig.py so that it can look
for Kconfig options mentioned in the source which do not appear in
Kconfig, and vice versa.

This tool is then used to clean up the unused or obsolete options
mentioned in Makefiles, along with any attached source code.
This commit is contained in:
Tom Rini 2023-02-07 20:36:16 -05:00
commit 94fe4ed945
134 changed files with 371 additions and 16258 deletions
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23
Makefile
View file

@ -1082,7 +1082,7 @@ expect = $(foreach cfg,$(1),y)
# Show a deprecation message
# Args:
# 1: List of CONFIG_DM_... to migrate to (e.g. "CONFIG_DM_MMC CONFIG_BLK")
# 1: List of options to migrate to (e.g. "CONFIG_DM_MMC CONFIG_BLK")
# 2: Name of component (e.g . "Ethernet drivers")
# 3: Release deadline (e.g. "v202.07")
# 4: Condition to require before checking (e.g. "$(CONFIG_NET)")
@ -1454,9 +1454,6 @@ u-boot-with-spl.kwb: u-boot.bin spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
$(BOARD_SIZE_CHECK)
u-boot.sha1: u-boot.bin
tools/ubsha1 u-boot.bin
u-boot.dis: u-boot
$(OBJDUMP) -d $< > $@
@ -1531,8 +1528,7 @@ MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_TEXT_BASE)
u-boot.ubl: u-boot-with-spl.bin FORCE
$(call if_changed,mkimage)
MKIMAGEFLAGS_u-boot-spl.ais = -s -n $(if $(CONFIG_AIS_CONFIG_FILE), \
$(srctree)/$(CONFIG_AIS_CONFIG_FILE:"%"=%),"/dev/null") \
MKIMAGEFLAGS_u-boot-spl.ais = -s -n "/dev/null" \
-T aisimage -e $(CONFIG_SPL_TEXT_BASE)
spl/u-boot-spl.ais: spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
@ -1656,17 +1652,6 @@ OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL
u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl $(UBOOT_BINLOAD) FORCE
$(call if_changed,pad_cat)
# PPC4xx needs the SPL at the end of the image, since the reset vector
# is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target
# and need to introduce a new build target with the full blown U-Boot
# at the start padded up to the start of the SPL image. And then concat
# the SPL image to the end.
OBJCOPYFLAGS_u-boot-img-spl-at-end.bin := -I binary -O binary \
--pad-to=$(CONFIG_UBOOT_PAD_TO) --gap-fill=0xff
u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE
$(call if_changed,pad_cat)
quiet_cmd_u-boot-elf ?= LD $@
cmd_u-boot-elf ?= $(LD) u-boot-elf.o -o $@ \
$(if $(CONFIG_SYS_BIG_ENDIAN),-EB,-EL) \
@ -2008,10 +1993,6 @@ dtbs: prepare3 scripts_dtc
dtbs_install:
$(Q)$(MAKE) $(dtbinst)=$(dtstree)
ifdef CONFIG_OF_EARLY_FLATTREE
all: dtbs
endif
endif
# Check dtc and pylibfdt, if DTC is provided, else build them

7
README
View file

@ -286,13 +286,6 @@ The following options need to be configured:
same as CFG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
it could be different for ARM SoCs.
- MIPS CPU options:
CONFIG_XWAY_SWAP_BYTES
Enable compilation of tools/xway-swap-bytes needed for Lantiq
XWAY SoCs for booting from NOR flash. The U-Boot image needs to
be swapped if a flash programmer is used.
- ARM options:
CFG_SYS_EXCEPTION_VECTORS_HIGH

4
arch/arc/config.mk
View file

@ -12,10 +12,6 @@ KBUILD_LDFLAGS += -EB
PLATFORM_CPPFLAGS += -mbig-endian
endif
ifdef CONFIG_ARC_MMU_VER
CONFIG_MMU = 1
endif
PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2 -mno-sdata
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -fno-common

5
arch/arc/lib/ints_low.S
View file

@ -76,13 +76,8 @@
.endm
.macro SAVE_EXCEPTION_SOURCE
#ifdef CONFIG_MMU
/* If MMU exists exception faulting address is loaded in EFA reg */
lr %r0, [%efa]
#else
/* Otherwise in ERET (exception return) reg */
lr %r0, [%eret]
#endif
.endm
ENTRY(memory_error)

2
arch/arm/cpu/arm920t/Makefile
View file

@ -7,8 +7,6 @@ extra-y = start.o
obj-y += cpu.o
obj-$(CONFIG_IMX) += imx/
# some files can only build in ARM mode
ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD

2
arch/arm/cpu/armv7/Makefile
View file

@ -26,7 +26,6 @@ obj-$(CONFIG_ARMV7_NONSEC) += nonsec_virt.o virt-v7.o virt-dt.o
obj-$(CONFIG_ARMV7_PSCI) += psci.o psci-common.o
obj-$(CONFIG_IPROC) += iproc-common/
obj-$(CONFIG_KONA) += kona-common/
obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o
ifneq (,$(filter s5pc1xx exynos,$(SOC)))
@ -38,7 +37,6 @@ obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
obj-$(CONFIG_RMOBILE) += rmobile/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_VF610) += vf610/

8
arch/arm/cpu/armv7/kona-common/Makefile
View file

@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2013 Broadcom Corporation.
obj-y += s_init.o
obj-y += hwinit-common.o
obj-y += clk-stubs.o
obj-${CONFIG_KONA_RESET_S} += reset.o

25
arch/arm/cpu/armv7/kona-common/clk-stubs.c
View file

@ -1,25 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
*/
#include <common.h>
/*
* These weak functions are available to kona architectures that don't
* require clock enables from the driver code.
*/
int __weak clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep)
{
return 0;
}
int __weak clk_bsc_enable(void *base)
{
return 0;
}
int __weak clk_usb_otg_enable(void *base)
{
return 0;
}

17
arch/arm/cpu/armv7/kona-common/hwinit-common.c
View file

@ -1,17 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/cache.h>
#include <linux/sizes.h>
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif

25
arch/arm/cpu/armv7/kona-common/reset.S
View file

@ -1,25 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2013 Broadcom Corporation.
*/
.globl reset_cpu
reset_cpu:
ldr r1, =0x35001f00
ldr r2, [r1]
ldr r4, =0x80000000
and r4, r2, r4
ldr r3, =0xA5A500
orr r4, r4, r3
orr r4, r4, #0x1
str r4, [r1]
ldr r1, =0x35001f04
ldr r2, [r1]
ldr r4, =0x80000000
and r4, r2, r4
str r4, [r1]
_loop_forever:
b _loop_forever

11
arch/arm/cpu/armv7/kona-common/s_init.c
View file

@ -1,11 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Broadcom Corporation.
*/
/*
* Early system init. Currently empty.
*/
void s_init(void)
{
}

1
arch/arm/cpu/armv8/Makefile
View file

@ -39,7 +39,6 @@ obj-$(CONFIG_SPL_RECOVER_DATA_SECTION) += spl_data.o
endif
obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
obj-$(CONFIG_S32V234) += s32v234/
obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
obj-$(CONFIG_ARMV8_PSCI) += psci.o
obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/

21
arch/arm/lib/debug.S
View file

@ -21,22 +21,10 @@
#include CONFIG_DEBUG_LL_INCLUDE
#endif
#ifdef CONFIG_MMU
.macro addruart_current, rx, tmp1, tmp2
addruart \tmp1, \tmp2, \rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1
moveq \rx, \tmp1
movne \rx, \tmp2
.endm
#else /* !CONFIG_MMU */
.macro addruart_current, rx, tmp1, tmp2
addruart \rx, \tmp1, \tmp2
.endm
#endif /* CONFIG_MMU */
/*
* Useful debugging routines
*/
@ -97,15 +85,6 @@ ENTRY(printch)
b 1b
ENDPROC(printch)
#ifdef CONFIG_MMU
ENTRY(debug_ll_addr)
addruart r2, r3, ip
str r2, [r0]
str r3, [r1]
mov pc, lr
ENDPROC(debug_ll_addr)
#endif
#else
ENTRY(printascii)

4
arch/arm/mach-mvebu/Makefile
View file

@ -35,10 +35,10 @@ endif
extra-y += kwbimage.cfg
ifneq ($(CONFIG_ARMADA_370)$(CONFIG_ARMADA_XP),)
ifneq ($(CONFIG_ARMADA_XP),)
KWB_REPLACE += CPU
KWB_CFG_CPU = SHEEVA
else ifneq ($(CONFIG_ARMADA_375)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X),)
else ifneq ($(CONFIG_ARMADA_375)$(CONFIG_ARMADA_38X),)
KWB_REPLACE += CPU
KWB_CFG_CPU = A9
endif

2
arch/arm/mach-rmobile/Makefile
View file

@ -7,9 +7,7 @@ obj-y = cpu_info.o
obj-y += emac.o
obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
obj-$(CONFIG_GLOBAL_TIMER) += timer.o
obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o

43
arch/arm/mach-rmobile/cpu_info-sh73a0.c
View file

@ -1,43 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012 Renesas Solutions Corp.
*/
#include <common.h>
#include <asm/io.h>
u32 rmobile_get_cpu_type(void)
{
u32 id;
u32 type;
struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
id = readl(&hpb->cccr);
type = (id >> 8) & 0xFF;
return type;
}
u32 rmobile_get_cpu_rev_integer(void)
{
u32 id;
u32 rev;
struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
id = readl(&hpb->cccr);
rev = ((id >> 4) & 0xF) + 1;
return rev;
}
u32 rmobile_get_cpu_rev_fraction(void)
{
u32 id;
u32 rev;
struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
id = readl(&hpb->cccr);
rev = id & 0xF;
return rev;
}

1
arch/arm/mach-rmobile/cpu_info.c
View file

@ -62,7 +62,6 @@ static const struct {
u16 cpu_type;
u8 cpu_name[10];
} rmobile_cpuinfo[] = {
{ RMOBILE_CPU_TYPE_SH73A0, "SH73A0" },
{ RMOBILE_CPU_TYPE_R8A7740, "R8A7740" },
{ RMOBILE_CPU_TYPE_R8A7790, "R8A7790" },
{ RMOBILE_CPU_TYPE_R8A7791, "R8A7791" },

146
arch/arm/mach-rmobile/include/mach/ehci-rmobile.h
View file

@ -1,146 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2013,2014 Renesas Electronics Corporation
* Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
*/
#ifndef __EHCI_RMOBILE_H__
#define __EHCI_RMOBILE_H__
/* Register offset */
#define OHCI_OFFSET 0x00
#define OHCI_SIZE 0x1000
#define EHCI_OFFSET 0x1000
#define EHCI_SIZE 0x1000
#define EHCI_USBCMD (EHCI_OFFSET + 0x0020)
/* USBCTR */
#define DIRPD (1 << 8)
#define PLL_RST (1 << 2)
#define PCICLK_MASK (1 << 1)
#define USBH_RST (1 << 0)
/* CMND_STS */
#define SERREN (1 << 8)
#define PERREN (1 << 6)
#define MASTEREN (1 << 2)
#define MEMEN (1 << 1)
/* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */
#define PCIAHB_WIN_PREFETCH ((1 << 1)|(1 << 0))
/* AHBPCI_WIN1_CTR */
#define PCIWIN1_PCICMD ((1 << 3)|(1 << 1))
#define AHB_CFG_AHBPCI 0x40000000
#define AHB_CFG_HOST 0x80000000
/* AHBPCI_WIN2_CTR */
#define PCIWIN2_PCICMD ((1 << 2)|(1 << 1))
/* PCI_INT_ENABLE */
#define USBH_PMEEN (1 << 19)
#define USBH_INTBEN (1 << 17)
#define USBH_INTAEN (1 << 16)
/* AHB_BUS_CTR */
#define SMODE_READY_CTR (1 << 17)
#define SMODE_READ_BURST (1 << 16)
#define MMODE_HBUSREQ (1 << 7)
#define MMODE_BOUNDARY ((1 << 6)|(1 << 5))
#define MMODE_BURST_WIDTH ((1 << 4)|(1 << 3))
#define MMODE_SINGLE_MODE ((1 << 4)|(1 << 3))
#define MMODE_WR_INCR (1 << 2)
#define MMODE_BYTE_BURST (1 << 1)
#define MMODE_HTRANS (1 << 0)
/* PCI_ARBITER_CTR */
#define PCIBUS_PARK_TIMER 0x00FF0000
#define PCIBUS_PARK_TIMER_SET 0x00070000
#define PCIBP_MODE (1 << 12)
#define PCIREQ7 (1 << 7)
#define PCIREQ6 (1 << 6)
#define PCIREQ5 (1 << 5)
#define PCIREQ4 (1 << 4)
#define PCIREQ3 (1 << 3)
#define PCIREQ2 (1 << 2)
#define PCIREQ1 (1 << 1)
#define PCIREQ0 (1 << 0)
#define SMSTPCR7 0xE615014C
#define SMSTPCR703 (1 << 3)
/* Init AHB master and slave functions of the host logic */
#define AHB_BUS_CTR_INIT \
(SMODE_READY_CTR | MMODE_HBUSREQ | MMODE_WR_INCR | \
MMODE_BYTE_BURST | MMODE_HTRANS)
#define USBCTR_WIN_SIZE_1GB 0x800
/* PCI Configuration Registers */
#define PCI_CONF_OHCI_OFFSET 0x10000
#define PCI_CONF_EHCI_OFFSET 0x10100
struct ahb_pciconf {
u32 vid_did;
u32 cmnd_sts;
u32 rev;
u32 cache_line;
u32 basead;
};
/* PCI Configuration Registers for AHB-PCI Bridge Registers */
#define PCI_CONF_AHBPCI_OFFSET 0x10000
struct ahbconf_pci_bridge {
u32 vid_did; /* 0x00 */
u32 cmnd_sts;
u32 revid_cc;
u32 cls_lt_ht_bist;
u32 basead; /* 0x10 */
u32 win1_basead;
u32 win2_basead;
u32 dummy0[5];
u32 ssvdi_ssid; /* 0x2C */
u32 dummy1[4];
u32 intr_line_pin;
};
/* AHB-PCI Bridge PCI Communication Registers */
#define AHBPCI_OFFSET 0x10800
struct ahbcom_pci_bridge {
u32 pciahb_win1_ctr; /* 0x00 */
u32 pciahb_win2_ctr;
u32 pciahb_dct_ctr;
u32 dummy0;
u32 ahbpci_win1_ctr; /* 0x10 */
u32 ahbpci_win2_ctr;
u32 dummy1;
u32 ahbpci_dct_ctr;
u32 pci_int_enable; /* 0x20 */
u32 pci_int_status;
u32 dummy2[2];
u32 ahb_bus_ctr; /* 0x30 */
u32 usbctr;
u32 dummy3[2];
u32 pci_arbiter_ctr; /* 0x40 */
u32 dummy4;
u32 pci_unit_rev; /* 0x48 */
};
struct rmobile_ehci_reg {
u32 hciversion; /* hciversion/caplength */
u32 hcsparams; /* hcsparams */
u32 hccparams; /* hccparams */
u32 hcsp_portroute; /* hcsp_portroute */
u32 usbcmd; /* usbcmd */
u32 usbsts; /* usbsts */
u32 usbintr; /* usbintr */
u32 frindex; /* frindex */
u32 ctrldssegment; /* ctrldssegment */
u32 periodiclistbase; /* periodiclistbase */
u32 asynclistaddr; /* asynclistaddr */
u32 dummy[9];
u32 configflag; /* configflag */
u32 portsc; /* portsc */
};
#endif /* __EHCI_RMOBILE_H__ */

5
arch/arm/mach-rmobile/include/mach/gpio.h
View file

@ -1,10 +1,7 @@
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H
#if defined(CONFIG_SH73A0)
#include "sh73a0-gpio.h"
void sh73a0_pinmux_init(void);
#elif defined(CONFIG_R8A7740)
#if defined(CONFIG_R8A7740)
#include "r8a7740-gpio.h"
void r8a7740_pinmux_init(void);
#endif

5
arch/arm/mach-rmobile/include/mach/rmobile.h
View file

@ -2,9 +2,7 @@
#define __ASM_ARCH_RMOBILE_H
#if defined(CONFIG_ARCH_RMOBILE)
#if defined(CONFIG_SH73A0)
#include <asm/arch/sh73a0.h>
#elif defined(CONFIG_R8A7740)
#if defined(CONFIG_R8A7740)
#include <asm/arch/r8a7740.h>
#elif defined(CONFIG_R8A7790)
#include <asm/arch/r8a7790.h>
@ -25,7 +23,6 @@
#endif /* CONFIG_ARCH_RMOBILE */
/* PRR CPU IDs */
#define RMOBILE_CPU_TYPE_SH73A0 0x37
#define RMOBILE_CPU_TYPE_R8A7740 0x40
#define RMOBILE_CPU_TYPE_R8A7790 0x45
#define RMOBILE_CPU_TYPE_R8A7791 0x47

553
arch/arm/mach-rmobile/include/mach/sh73a0-gpio.h
View file

@ -1,553 +0,0 @@
#ifndef __ASM_SH73A0_H__
#define __ASM_SH73A0_H__
/* Pin Function Controller:
* GPIO_FN_xx - GPIO used to select pin function and MSEL switch
* GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
*/
enum {
/* Hardware manual Table 25-1 (GPIO) */
GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118,
GPIO_PORT128, GPIO_PORT129,
GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274,
GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279,
GPIO_PORT280, GPIO_PORT281, GPIO_PORT282,
GPIO_PORT288, GPIO_PORT289,
GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294,
GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299,
GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304,
GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
/* Table 25-1 (Function 0-7) */
GPIO_FN_VBUS_0,
GPIO_FN_GPI0,
GPIO_FN_GPI1,
GPIO_FN_GPI2,
GPIO_FN_GPI3,
GPIO_FN_GPI4,
GPIO_FN_GPI5,
GPIO_FN_GPI6,
GPIO_FN_GPI7,
GPIO_FN_SCIFA7_RXD,
GPIO_FN_SCIFA7_CTS_,
GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \
GPIO_FN_PORT16_VIO_CKOR,
GPIO_FN_SCIFA0_TXD,
GPIO_FN_SCIFA7_TXD,
GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2,
GPIO_FN_GPO0,
GPIO_FN_GPO1,
GPIO_FN_GPO2, GPIO_FN_STATUS0,
GPIO_FN_GPO3, GPIO_FN_STATUS1,
GPIO_FN_GPO4, GPIO_FN_STATUS2,
GPIO_FN_VINT,
GPIO_FN_TCKON,
GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \
GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \
GPIO_FN_PORT28_TPU1TO1,
GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
GPIO_FN_SCIFA4_TXD,
GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
GPIO_FN_SCIFA4_RTS_,
GPIO_FN_SCIFA4_CTS_,
GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
GPIO_FN_FSIBOSLD,
GPIO_FN_FSIBISLD,
GPIO_FN_VACK,
GPIO_FN_XTAL1L,
GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2,
GPIO_FN_SCIFA0_RXD,
GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1,
GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT,
GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR,
GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF,
GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD,
GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \
GPIO_FN_FSIAOMC,
GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR,
GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT,
GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2,
GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \
GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF,
GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \
GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC,
GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0,
GPIO_FN_A0, GPIO_FN_BS_,
GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2,
GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1,
GPIO_FN_A14, GPIO_FN_KEYOUT5,
GPIO_FN_A15, GPIO_FN_KEYOUT4,
GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1,
GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD,
GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK,
GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0,
GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1,
GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD,
GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2,
GPIO_FN_A26, GPIO_FN_KEYIN6,
GPIO_FN_KEYIN7,
GPIO_FN_D0_NAF0,
GPIO_FN_D1_NAF1,
GPIO_FN_D2_NAF2,
GPIO_FN_D3_NAF3,
GPIO_FN_D4_NAF4,
GPIO_FN_D5_NAF5,
GPIO_FN_D6_NAF6,
GPIO_FN_D7_NAF7,
GPIO_FN_D8_NAF8,
GPIO_FN_D9_NAF9,
GPIO_FN_D10_NAF10,
GPIO_FN_D11_NAF11,
GPIO_FN_D12_NAF12,
GPIO_FN_D13_NAF13,
GPIO_FN_D14_NAF14,
GPIO_FN_D15_NAF15,
GPIO_FN_CS4_,
GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR,
GPIO_FN_CS5B_, GPIO_FN_FCE1_,
GPIO_FN_CS6B_, GPIO_FN_DACK0,
GPIO_FN_FCE0_, GPIO_FN_CS6A_,
GPIO_FN_WAIT_, GPIO_FN_DREQ0,
GPIO_FN_RD__FSC,
GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE,
GPIO_FN_WE1_,
GPIO_FN_FRB,
GPIO_FN_CKO,
GPIO_FN_NBRSTOUT_,
GPIO_FN_NBRST_,
GPIO_FN_BBIF2_TXD,
GPIO_FN_BBIF2_RXD,
GPIO_FN_BBIF2_SYNC,
GPIO_FN_BBIF2_SCK,
GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2,
GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1,
GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1,
GPIO_FN_SCIFA3_TXD,
GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \
GPIO_FN_PORT115_I2C_SCL3,
GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \
GPIO_FN_PORT116_I2C_SDA3,
GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
GPIO_FN_HSI_TX_FLAG,
GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \
GPIO_FN_LCD2D0,
GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \
GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1,
GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10,
GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \
GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11,
GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \
GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12,
GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13,
GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14,
GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15,
GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16,
GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17,
GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \
GPIO_FN_LCD2D6,
GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \
GPIO_FN_LCD2D7,
GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8,
GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9,
GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \
GPIO_FN_LCD2D2,
GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \
GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3,
GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
GPIO_FN_LCD2D4,
GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \
GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5,
GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \
GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18,
GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19,
GPIO_FN_VIO_CKO,
GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \
GPIO_FN_PORT149_KEYOUT9,
GPIO_FN_MFG0_IN2,
GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2,
GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD,
GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD,
GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_,
GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
GPIO_FN_TPU3TO0,
GPIO_FN_LCDD0,
GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1,
GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1,
GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1,
GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD,
GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \
GPIO_FN_TPU2TO1,
GPIO_FN_LCDD6,
GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
GPIO_FN_LCDD8, GPIO_FN_D16,
GPIO_FN_LCDD9, GPIO_FN_D17,
GPIO_FN_LCDD10, GPIO_FN_D18,
GPIO_FN_LCDD11, GPIO_FN_D19,
GPIO_FN_LCDD12, GPIO_FN_D20,
GPIO_FN_LCDD13, GPIO_FN_D21,
GPIO_FN_LCDD14, GPIO_FN_D22,
GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
GPIO_FN_LCDD17, GPIO_FN_D25,
GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
GPIO_FN_LCDDCK, GPIO_FN_LCDWR_,
GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \
GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP,
GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \
GPIO_FN_PORT218_VIO_CKOR,
GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \
GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
GPIO_FN_LCD2DCK_2,
GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2,
GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \
GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
GPIO_FN_PORT221_LCD2HSYN,
GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \
GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN,
GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2,
GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN,
GPIO_FN_SCIFA1_RXD,
GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1,
GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2,
GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_,
GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2,
GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
GPIO_FN_LCD2D20,
GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
GPIO_FN_LCD2D21,
GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2,
GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2,
GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22,
GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23,
GPIO_FN_SCIFA6_TXD,
GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
GPIO_FN_TPU4TO0,
GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \
GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD,
GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \
GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD,
GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \
GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \
GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \
GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \
GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK,
GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC,
GPIO_FN_SDHICLK0,
GPIO_FN_SDHICD0,
GPIO_FN_SDHID0_0,
GPIO_FN_SDHID0_1,
GPIO_FN_SDHID0_2,
GPIO_FN_SDHID0_3,
GPIO_FN_SDHICMD0,
GPIO_FN_SDHIWP0,
GPIO_FN_SDHICLK1,
GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2,
GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2,
GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2,
GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2,
GPIO_FN_SDHICMD1,
GPIO_FN_SDHICLK2,
GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4,
GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4,
GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4,
GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4,
GPIO_FN_SDHICMD2,
GPIO_FN_MMCCLK0,
GPIO_FN_MMCD0_0,
GPIO_FN_MMCD0_1,
GPIO_FN_MMCD0_2,
GPIO_FN_MMCD0_3,
GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5,
GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5,
GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5,
GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5,
GPIO_FN_MMCCMD0,
GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT,
GPIO_FN_MCP_WAIT__MCP_FRB,
GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1,
GPIO_FN_MCP_D15_MCP_NAF15,
GPIO_FN_MCP_D14_MCP_NAF14,
GPIO_FN_MCP_D13_MCP_NAF13,
GPIO_FN_MCP_D12_MCP_NAF12,
GPIO_FN_MCP_D11_MCP_NAF11,
GPIO_FN_MCP_D10_MCP_NAF10,
GPIO_FN_MCP_D9_MCP_NAF9,
GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1,
GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7,
GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6,
GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5,
GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4,
GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3,
GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2,
GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1,
GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0,
GPIO_FN_MCP_NBRSTOUT_,
GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE,
/* MSEL2 special case */
GPIO_FN_TSIF2_TS_XX1,
GPIO_FN_TSIF2_TS_XX2,
GPIO_FN_TSIF2_TS_XX3,
GPIO_FN_TSIF2_TS_XX4,
GPIO_FN_TSIF2_TS_XX5,
GPIO_FN_TSIF1_TS_XX1,
GPIO_FN_TSIF1_TS_XX2,
GPIO_FN_TSIF1_TS_XX3,
GPIO_FN_TSIF1_TS_XX4,
GPIO_FN_TSIF1_TS_XX5,
GPIO_FN_TSIF0_TS_XX1,
GPIO_FN_TSIF0_TS_XX2,
GPIO_FN_TSIF0_TS_XX3,
GPIO_FN_TSIF0_TS_XX4,
GPIO_FN_TSIF0_TS_XX5,
GPIO_FN_MST1_TS_XX1,
GPIO_FN_MST1_TS_XX2,
GPIO_FN_MST1_TS_XX3,
GPIO_FN_MST1_TS_XX4,
GPIO_FN_MST1_TS_XX5,
GPIO_FN_MST0_TS_XX1,
GPIO_FN_MST0_TS_XX2,
GPIO_FN_MST0_TS_XX3,
GPIO_FN_MST0_TS_XX4,
GPIO_FN_MST0_TS_XX5,
/* MSEL3 special cases */
GPIO_FN_SDHI0_VCCQ_MC0_ON,
GPIO_FN_SDHI0_VCCQ_MC0_OFF,
GPIO_FN_DEBUG_MON_VIO,
GPIO_FN_DEBUG_MON_LCDD,
GPIO_FN_LCDC_LCDC0,
GPIO_FN_LCDC_LCDC1,
/* MSEL4 special cases */
GPIO_FN_IRQ9_MEM_INT,
GPIO_FN_IRQ9_MCP_INT,
GPIO_FN_A11,
GPIO_FN_KEYOUT8,
GPIO_FN_TPU4TO3,
GPIO_FN_RESETA_N_PU_ON,
GPIO_FN_RESETA_N_PU_OFF,
GPIO_FN_EDBGREQ_PD,
GPIO_FN_EDBGREQ_PU,
/* Functions with pull-ups */
GPIO_FN_KEYIN0_PU,
GPIO_FN_KEYIN1_PU,
GPIO_FN_KEYIN2_PU,
GPIO_FN_KEYIN3_PU,
GPIO_FN_KEYIN4_PU,
GPIO_FN_KEYIN5_PU,
GPIO_FN_KEYIN6_PU,
GPIO_FN_KEYIN7_PU,
GPIO_FN_SDHICD0_PU,
GPIO_FN_SDHID0_0_PU,
GPIO_FN_SDHID0_1_PU,
GPIO_FN_SDHID0_2_PU,
GPIO_FN_SDHID0_3_PU,
GPIO_FN_SDHICMD0_PU,
GPIO_FN_SDHIWP0_PU,
GPIO_FN_SDHID1_0_PU,
GPIO_FN_SDHID1_1_PU,
GPIO_FN_SDHID1_2_PU,
GPIO_FN_SDHID1_3_PU,
GPIO_FN_SDHICMD1_PU,
GPIO_FN_SDHID2_0_PU,
GPIO_FN_SDHID2_1_PU,
GPIO_FN_SDHID2_2_PU,
GPIO_FN_SDHID2_3_PU,
GPIO_FN_SDHICMD2_PU,
GPIO_FN_MMCCMD0_PU,
GPIO_FN_MMCCMD1_PU,
GPIO_FN_MMCD0_0_PU,
GPIO_FN_MMCD0_1_PU,
GPIO_FN_MMCD0_2_PU,
GPIO_FN_MMCD0_3_PU,
GPIO_FN_MMCD0_4_PU,
GPIO_FN_MMCD0_5_PU,
GPIO_FN_MMCD0_6_PU,
GPIO_FN_MMCD0_7_PU,
GPIO_FN_FSIACK_PU,
GPIO_FN_FSIAILR_PU,
GPIO_FN_FSIAIBT_PU,
GPIO_FN_FSIAISLD_PU,
/* end of GPIO */
GPIO_NR,
};
/* DMA slave IDs */
enum {
SHDMA_SLAVE_INVALID,
SHDMA_SLAVE_SCIF0_TX,
SHDMA_SLAVE_SCIF0_RX,
SHDMA_SLAVE_SCIF1_TX,
SHDMA_SLAVE_SCIF1_RX,
SHDMA_SLAVE_SCIF2_TX,
SHDMA_SLAVE_SCIF2_RX,
SHDMA_SLAVE_SCIF3_TX,
SHDMA_SLAVE_SCIF3_RX,
SHDMA_SLAVE_SCIF4_TX,
SHDMA_SLAVE_SCIF4_RX,
SHDMA_SLAVE_SCIF5_TX,
SHDMA_SLAVE_SCIF5_RX,
SHDMA_SLAVE_SCIF6_TX,
SHDMA_SLAVE_SCIF6_RX,
SHDMA_SLAVE_SCIF7_TX,
SHDMA_SLAVE_SCIF7_RX,
SHDMA_SLAVE_SCIF8_TX,
SHDMA_SLAVE_SCIF8_RX,
SHDMA_SLAVE_SDHI0_TX,
SHDMA_SLAVE_SDHI0_RX,
SHDMA_SLAVE_SDHI1_TX,
SHDMA_SLAVE_SDHI1_RX,
SHDMA_SLAVE_SDHI2_TX,
SHDMA_SLAVE_SDHI2_RX,
SHDMA_SLAVE_MMCIF_TX,
SHDMA_SLAVE_MMCIF_RX,
};
/*
* SH73A0 IRQ LOCATION TABLE
*
* 416 -----------------------------------------
* IRQ0-IRQ15
* 431 -----------------------------------------
* ...
* 448 -----------------------------------------
* sh73a0-intcs
* sh73a0-intca-irq-pins
* 680 -----------------------------------------
* ...
* 700 -----------------------------------------
* sh73a0-pint0
* 731 -----------------------------------------
* 732 -----------------------------------------
* sh73a0-pint1
* 739 -----------------------------------------
* ...
* 800 -----------------------------------------
* IRQ16-IRQ31
* 815 -----------------------------------------
* ...
* 928 -----------------------------------------
* sh73a0-intca-irq-pins
* 943 -----------------------------------------
*/
/* PINT interrupts are located at Linux IRQ 700 and up */
#define SH73A0_PINT0_IRQ(irq) ((irq) + 700)
#define SH73A0_PINT1_IRQ(irq) ((irq) + 732)
#endif /* __ASM_SH73A0_H__ */

289
arch/arm/mach-rmobile/include/mach/sh73a0.h
View file

@ -1,289 +0,0 @@
#ifndef __ASM_ARCH_RMOBILE_SH73A0_H
#define __ASM_ARCH_RMOBILE_SH73A0_H
/* Global Timer */
#define GLOBAL_TIMER_BASE_ADDR (0xF0000200)
#define MERAM_BASE (0xE5580000)
/* GIC */
#define GIC_BASE (0xF0000100)
#define ICCICR GIC_BASE
/* Secure control register */
#define LIFEC_SEC_SRC (0xE6110008)
/* RWDT */
#define RWDT_BASE (0xE6020000)
/* HPB Semaphore Control Registers */
#define HPB_BASE (0xE6001010)
/* Bus Semaphore Control Registers */
#define HPBSCR_BASE (0xE6001600)
/* SBSC1 */
#define SBSC1_BASE (0xFE400000)
#define SDMRA1A (SBSC1_BASE + 0x100000)
#define SDMRA2A (SBSC1_BASE + 0x1C0000)
#define SDMRA3A (SBSC1_BASE + 0x104000)
/* SBSC2 */
#define SBSC2_BASE (0xFB400000)
#define SDMRA1B (SBSC2_BASE + 0x100000)
#define SDMRA2B (SBSC2_BASE + 0x1C0000)
#define SDMRA3B (SBSC2_BASE + 0x104000)
/* CPG */
#define CPG_BASE (0xE6150000)
#define CPG_SRCR_BASE (CPG_BASE + 0x80A0)
#define WUPCR (CPG_BASE + 0x1010)
#define SRESCR (CPG_BASE + 0x1018)
#define PCLKCR (CPG_BASE + 0x1020)
/* SYSC */
#define SYSC_BASE (0xE6180000)
#define RESCNT2 (SYSC_BASE + 0x8020)
/* BSC */
#define BSC_BASE (0xFEC10000)
/* SCIF */
#define SCIF0_BASE (0xE6C40000)
#define SCIF1_BASE (0xE6C50000)
#define SCIF2_BASE (0xE6C60000)
#define SCIF3_BASE (0xE6C70000)
#define SCIF4_BASE (0xE6C80000)
#define SCIF5_BASE (0xE6CB0000)
#define SCIF6_BASE (0xE6CC0000)
#define SCIF7_BASE (0xE6CD0000)
#ifndef __ASSEMBLY__
#include <asm/types.h>
/* RWDT */
struct sh73a0_rwdt {
u16 rwtcnt0; /* 0x00 */
u16 dummy0; /* 0x02 */
u16 rwtcsra0; /* 0x04 */
u16 dummy1; /* 0x06 */
u16 rwtcsrb0; /* 0x08 */
};
/* HPB Semaphore Control Registers */
struct sh73a0_hpb {
u32 hpbctrl0;
u32 hpbctrl1;
u32 hpbctrl2;
u32 cccr;
u32 dummy0; /* 0x20 */
u32 hpbctrl4;
u32 hpbctrl5;
u32 dummy1; /* 0x2C */
u32 hpbctrl6;
};
/* Bus Semaphore Control Registers */
struct sh73a0_hpb_bscr {
u32 mpsrc; /* 0x00 */
u32 mpacctl; /* 0x04 */
u32 dummy0[6];
u32 smgpiosrc; /* 0x20 */
u32 smgpioerr;
u32 smgpiotime;
u32 smgpiocnt;
u32 dummy1[4]; /* 0x30 .. 0x3C */
u32 smcmt2src;
u32 smcmt2err;
u32 smcmt2time;
u32 smcmt2cnt;
u32 smcpgsrc;
u32 smcpgerr;
u32 smcpgtime;
u32 smcpgcnt;
u32 dummy2[4]; /* 0x60 - 0x6C */
u32 smsyscsrc;
u32 smsyscerr;
u32 smsysctime;
u32 smsysccnt;
};
/* SBSC */
struct sh73a0_sbsc {
u32 dummy0[2]; /* 0x00, 0x04 */
u32 sdcr0;
u32 sdcr1;
u32 sdpcr;
u32 dummy1; /* 0x14 */
u32 sdcr0s;
u32 sdcr1s;
u32 rtcsr;
u32 dummy2; /* 0x24 */
u32 rtcor;
u32 rtcorh;
u32 rtcors;
u32 rtcorsh;
u32 dummy3[2]; /* 0x38, 0x3C */
u32 sdwcrc0;
u32 sdwcrc1;
u32 sdwcr00;
u32 sdwcr01;
u32 sdwcr10;
u32 sdwcr11;
u32 sdpdcr0;
u32 dummy4; /* 0x5C */
u32 sdwcr2;
u32 sdwcrc2;
u32 zqccr;
u32 dummy5[6]; /* 0x6C .. 0x80 */
u32 sdmracr0;
u32 dummy6; /* 0x88 */
u32 sdmrtmpcr;
u32 dummy7; /* 0x90 */
u32 sdmrtmpmsk;
u32 dummy8; /* 0x98 */
u32 sdgencnt;
u32 dphycnt0;
u32 dphycnt1;
u32 dphycnt2;
u32 dummy9[2]; /* 0xAC .. 0xB0 */
u32 sddrvcr0;
u32 dummy10[14]; /* 0xB8 .. 0xEC */
u32 dptdivcr0;
u32 dptdivcr1;
u32 dptdivcr2;
u32 dummy11; /* 0xFC */
u32 sdptcr0;
u32 sdptcr1;
u32 sdptcr2;
u32 sdptcr3; /* 0x10C */
u32 dummy12[145]; /* 0x110 .. 0x350 */
u32 dllcnt0; /* 0x354 */
u32 sbscmon0;
};
/* CPG */
struct sh73a0_sbsc_cpg {
u32 frqcra; /* 0x00 */
u32 frqcrb;
u32 vclkcr1;
u32 vclkcr2;
u32 zbckcr;
u32 flckcr;
u32 fsiackcr;
u32 vclkcr3;
u32 rtstbcr;
u32 systbcr;
u32 pll1cr;
u32 pll2cr;
u32 mstpsr0;
u32 dummy0; /* 0x34 */
u32 mstpsr1;
u32 mstpsr5;
u32 mstpsr2;
u32 dummy1; /* 0x44 */
u32 mstpsr3;
u32 mstpsr4;
u32 dummy2; /* 0x50 */
u32 astat;
u32 dvfscr0;
u32 dvfscr1;
u32 dsitckcr;
u32 dsi0pckcr;
u32 dsi1pckcr;
u32 dsi0phycr;
u32 dsi1phycr;
u32 sd0ckcr;
u32 sd1ckcr;
u32 sd2ckcr;
u32 subckcr;
u32 spuackcr;
u32 msuckcr;
u32 hsickcr;
u32 fsibckcr;
u32 spuvckcr;
u32 mfck1cr;
u32 mfck2cr;
u32 dummy3[8]; /* 0xA0 .. 0xBC */
u32 ckscr;
u32 dummy4; /* 0xC4 */
u32 pll1stpcr;
u32 mpmode;
u32 pllecr;
u32 dummy5; /* 0xD4 */
u32 pll0cr;
u32 pll3cr;
u32 dummy6; /* 0xE0 */
u32 frqcrd;
u32 dummyi7; /* 0xE8 */
u32 vrefcr;
u32 pll0stpcr;
u32 dummy8; /* 0xF4 */
u32 pll2stpcr;
u32 pll3stpcr;
u32 dummy9[4]; /* 0x100 .. 0x10c */
u32 rmstpcr0;
u32 rmstpcr1;
u32 rmstpcr2;
u32 rmstpcr3;
u32 rmstpcr4;
u32 rmstpcr5;
u32 dummy10[2]; /* 0x128 .. 0x12c */
u32 smstpcr0;
u32 smstpcr1;
u32 smstpcr2;
u32 smstpcr3;
u32 smstpcr4;
u32 smstpcr5;
u32 dummy11[2]; /* 0x148 .. 0x14c */
u32 cpgxxcs4;
u32 dummy12[7]; /* 0x154 .. 0x16c */
u32 dvfscr2;
u32 dvfscr3;
u32 dvfscr4;
u32 dvfscr5; /* 0x17C */
};
/* CPG SRCR part OK */
struct sh73a0_sbsc_cpg_srcr {
u32 srcr0;
u32 dummy0; /* 0xA4 */
u32 srcr1;
u32 dummy1; /* 0xAC */
u32 srcr2;
u32 dummy2; /* 0xB4 */
u32 srcr3;
u32 srcr4;
u32 dummy3; /* 0xC0 */
u32 srcr5;
};
/* BSC */
struct sh73a0_bsc {
u32 cmncr;
u32 cs0bcr;
u32 cs2bcr;
u32 dummy0; /* 0x0C */
u32 cs4bcr;
u32 cs5abcr;
u32 cs5bbcr;
u32 cs6abcr;
u32 cs6bbcr;
u32 cs0wcr;
u32 cs2wcr;
u32 dummy1; /* 0x2C */
u32 cs4wcr;
u32 cs5awcr;
u32 cs5bwcr;
u32 cs6awcr;
u32 cs6bwcr;
u32 rbwtcnt;
u32 busycr;
u32 dummy2; /* 0x5c */
u32 cs7abcr;
u32 cs7awcr;
u32 dummy3[2]; /* 0x68, 0x6C */
u32 bromtimcr;
};
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_RMOBILE_SH73A0_H */

2807
arch/arm/mach-rmobile/pfc-sh73a0.c
View file

File diff suppressed because it is too large Load diff

87
arch/arm/mach-rmobile/timer.c
View file

@ -1,87 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012 Renesas Solutions Corp.
*/
#include <common.h>
#include <div64.h>
#include <init.h>
#include <time.h>
#include <asm/io.h>
#include <asm/arch-armv7/globaltimer.h>
#include <asm/arch/rmobile.h>
#include <linux/delay.h>
static struct globaltimer *global_timer = \
(struct globaltimer *)GLOBAL_TIMER_BASE_ADDR;
#define CLK2MHZ(clk) (clk / 1000 / 1000)
static u64 get_cpu_global_timer(void)
{
u32 low, high;
u64 timer;
u32 old = readl(&global_timer->cnt_h);
while (1) {
low = readl(&global_timer->cnt_l);
high = readl(&global_timer->cnt_h);
if (old == high)
break;
else
old = high;
}
timer = high;
return (u64)((timer << 32) | low);
}
static u64 get_time_us(void)
{
u64 timer = get_cpu_global_timer();
timer = ((timer << 2) + (CLK2MHZ(CFG_SYS_CPU_CLK) >> 1));
do_div(timer, CLK2MHZ(CFG_SYS_CPU_CLK));
return timer;
}
static ulong get_time_ms(void)
{
u64 us = get_time_us();
do_div(us, 1000);
return us;
}
int timer_init(void)
{
writel(0x01, &global_timer->ctl);
return 0;
}
void __udelay(unsigned long usec)
{
u64 start, current;
u64 wait;
start = get_cpu_global_timer();
wait = (u64)((usec * CLK2MHZ(CFG_SYS_CPU_CLK)) >> 2);
do {
current = get_cpu_global_timer();
} while ((current - start) < wait);
}
ulong get_timer(ulong base)
{
return get_time_ms() - base;
}
unsigned long long get_ticks(void)
{
return get_cpu_global_timer();
}
ulong get_tbclk(void)
{
return (ulong)(CFG_SYS_CPU_CLK >> 2);
}

2
arch/arm/mach-rockchip/Makefile
View file

@ -18,7 +18,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
# Always include boot_mode.o, as we bypass it (i.e. turn it off)
# inside of boot_mode.c when CONFIG_BOOT_MODE_REG is 0. This way,
# inside of boot_mode.c when CONFIG_ROCKCHIP_BOOT_MODE_REG is 0. This way,
# we can have the preprocessor correctly recognise both 0x0 and 0
# meaning "turn it off".
obj-y += boot_mode.o

1
arch/m68k/Makefile
View file

@ -7,7 +7,6 @@ libs-y += arch/m68k/lib/
cpuflags-$(CONFIG_M5208) := -mcpu=5208
cpuflags-$(CONFIG_M5235) := -mcpu=5235 -fPIC
cpuflags-$(CONFIG_M52277) := -mcpu=52277 -fPIC
cpuflags-$(CONFIG_M5249) := -mcpu=5249
cpuflags-$(CONFIG_M5253) := -mcpu=5253
cpuflags-$(CONFIG_M5271) := -mcpu=5271

43
arch/mips/mach-octeon/octeon_fdt.c
View file

@ -30,9 +30,6 @@
#ifdef CONFIG_PCF857X
#include <pcf857x.h>
#endif
#ifdef CONFIG_PCA9698
#include <pca9698.h>
#endif
#ifdef CONFIG_PCA9554
#include <pca9554.h>
#endif
@ -59,13 +56,6 @@ static const char * const pca9555_gpio_list[] = {
};
#endif
#ifdef CONFIG_PCA9698
/** List of compatible strings supported by pca9698 driver */
static const char * const pca9698_gpio_list[] = {
"nxp,pca9505", "pca9505", "nxp,pca9698", "pca9698", NULL,
};
#endif
#ifdef CONFIG_PCA953X
/** List of compatible strings supported by pca953x driver */
static const char * const pca953x_gpio_list[] = {
@ -807,19 +797,6 @@ int octeon_fdt_read_gpio(const void *fdt, int phandle, int pin)
}
value = (value >> pin) & 1;
break;
#endif
#ifdef CONFIG_PCA9698
case CVMX_GPIO_PIN_PCA9698:
node = fdt_node_offset_by_phandle(fdt, phandle);
if (octeon_fdt_get_i2c_bus_addr(fdt, node, &bus, &addr)) {
printf("%s: Could not get gpio bus and/or address\n", __func__);
return -1;
}
old_bus = i2c_get_bus_num();
i2c_set_bus_num(bus);
value = pca9698_get_value(addr, pin);
i2c_set_bus_num(old_bus);
break;
#endif
case CVMX_GPIO_PIN_OCTEON:
value = gpio_get_value(pin);
@ -880,18 +857,6 @@ int octeon_fdt_set_gpio(const void *fdt, int phandle, int pin, int val)
return -1;
}
return pcf957x_set_val(bus, addr, 1 << pin, val << pin);
#endif
#ifdef CONFIG_PCA9698
case CVMX_GPIO_PIN_PCA9698:
if (octeon_fdt_get_i2c_bus_addr(fdt, node, &bus, &addr)) {
printf("%s: Could not get gpio bus and/or address\n", __func__);
return -1;
}
old_bus = i2c_get_bus_num();
i2c_set_bus_num(bus);
rc = pca9698_set_value(addr, pin, val);
i2c_set_bus_num(old_bus);
return rc;
#endif
case CVMX_GPIO_PIN_OCTEON:
return gpio_set_value(pin, val);
@ -951,13 +916,7 @@ int octeon_fdt_get_gpio_info(int fdt_node, enum octeon_gpio_type *type,
*type = GPIO_TYPE_PCA953X;
}
#endif
#ifdef CONFIG_PCA9698
if (!octeon_fdt_node_check_compatible(fdt, fdt_node, pca9698_gpio_list)) {
debug("%s: Found PCA9698 compatible GPIO", __func__);
*type = GPIO_TYPE_PCA9698;
}
#endif
#if defined(CONFIG_PCA953X) || defined(CONFIG_PCA9698) || \
#if defined(CONFIG_PCA953X) || \
defined(CONFIG_PCA9555) || defined(CONFIG_PCA9554)
if (!i2c_addr || !i2c_bus) {
printf("%s: Error: i2c_addr or i2c_bus is NULL\n", __func__);

1
arch/powerpc/lib/Makefile
View file

@ -34,7 +34,6 @@ obj-y += ticks.o
endif
obj-y += reloc.o
obj-$(CONFIG_BAT_RW) += bat_rw.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += cache.o
obj-y += extable.o

244
arch/powerpc/lib/bat_rw.c
View file

@ -1,244 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
*/
#include <common.h>
#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <linux/compiler.h>
#ifdef CONFIG_ADDR_MAP
#include <addr_map.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
{
__maybe_unused int batn = -1;
sync();
switch (bat) {
case DBAT0:
mtspr (DBAT0L, lower);
mtspr (DBAT0U, upper);
batn = 0;
break;
case IBAT0:
mtspr (IBAT0L, lower);
mtspr (IBAT0U, upper);
break;
case DBAT1:
mtspr (DBAT1L, lower);
mtspr (DBAT1U, upper);
batn = 1;
break;
case IBAT1:
mtspr (IBAT1L, lower);
mtspr (IBAT1U, upper);
break;
case DBAT2:
mtspr (DBAT2L, lower);
mtspr (DBAT2U, upper);
batn = 2;
break;
case IBAT2:
mtspr (IBAT2L, lower);
mtspr (IBAT2U, upper);
break;
case DBAT3:
mtspr (DBAT3L, lower);
mtspr (DBAT3U, upper);
batn = 3;
break;
case IBAT3:
mtspr (IBAT3L, lower);
mtspr (IBAT3U, upper);
break;
#ifdef CONFIG_HIGH_BATS
case DBAT4:
mtspr (DBAT4L, lower);
mtspr (DBAT4U, upper);
batn = 4;
break;
case IBAT4:
mtspr (IBAT4L, lower);
mtspr (IBAT4U, upper);
break;
case DBAT5:
mtspr (DBAT5L, lower);
mtspr (DBAT5U, upper);
batn = 5;
break;
case IBAT5:
mtspr (IBAT5L, lower);
mtspr (IBAT5U, upper);
break;
case DBAT6:
mtspr (DBAT6L, lower);
mtspr (DBAT6U, upper);
batn = 6;
break;
case IBAT6:
mtspr (IBAT6L, lower);
mtspr (IBAT6U, upper);
break;
case DBAT7:
mtspr (DBAT7L, lower);
mtspr (DBAT7U, upper);
batn = 7;
break;
case IBAT7:
mtspr (IBAT7L, lower);
mtspr (IBAT7U, upper);
break;
#endif
default:
return (-1);
}
#ifdef CONFIG_ADDR_MAP
if ((gd->flags & GD_FLG_RELOC) && (batn >= 0)) {
phys_size_t size;
if (!BATU_VALID(upper))
size = 0;
else
size = BATU_SIZE(upper);
addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
size, batn);
}
#endif
sync();
isync();
return (0);
}
int read_bat (ppc_bat_t bat, unsigned long *upper, unsigned long *lower)
{
unsigned long register u;
unsigned long register l;
switch (bat) {
case DBAT0:
l = mfspr (DBAT0L);
u = mfspr (DBAT0U);
break;
case IBAT0:
l = mfspr (IBAT0L);
u = mfspr (IBAT0U);
break;
case DBAT1:
l = mfspr (DBAT1L);
u = mfspr (DBAT1U);
break;
case IBAT1:
l = mfspr (IBAT1L);
u = mfspr (IBAT1U);
break;
case DBAT2:
l = mfspr (DBAT2L);
u = mfspr (DBAT2U);
break;
case IBAT2:
l = mfspr (IBAT2L);
u = mfspr (IBAT2U);
break;
case DBAT3:
l = mfspr (DBAT3L);
u = mfspr (DBAT3U);
break;
case IBAT3:
l = mfspr (IBAT3L);
u = mfspr (IBAT3U);
break;
#ifdef CONFIG_HIGH_BATS
case DBAT4:
l = mfspr (DBAT4L);
u = mfspr (DBAT4U);
break;
case IBAT4:
l = mfspr (IBAT4L);
u = mfspr (IBAT4U);
break;
case DBAT5:
l = mfspr (DBAT5L);
u = mfspr (DBAT5U);
break;
case IBAT5:
l = mfspr (IBAT5L);
u = mfspr (IBAT5U);
break;
case DBAT6:
l = mfspr (DBAT6L);
u = mfspr (DBAT6U);
break;
case IBAT6:
l = mfspr (IBAT6L);
u = mfspr (IBAT6U);
break;
case DBAT7:
l = mfspr (DBAT7L);
u = mfspr (DBAT7U);
break;
case IBAT7:
l = mfspr (IBAT7L);
u = mfspr (IBAT7U);
break;
#endif
default:
return (-1);
}
*upper = u;
*lower = l;
return (0);
}
void print_bats(void)
{
printf("BAT registers:\n");
printf ("\tIBAT0L = 0x%08X ", mfspr (IBAT0L));
printf ("\tIBAT0U = 0x%08X\n", mfspr (IBAT0U));
printf ("\tDBAT0L = 0x%08X ", mfspr (DBAT0L));
printf ("\tDBAT0U = 0x%08X\n", mfspr (DBAT0U));
printf ("\tIBAT1L = 0x%08X ", mfspr (IBAT1L));
printf ("\tIBAT1U = 0x%08X\n", mfspr (IBAT1U));
printf ("\tDBAT1L = 0x%08X ", mfspr (DBAT1L));
printf ("\tDBAT1U = 0x%08X\n", mfspr (DBAT1U));
printf ("\tIBAT2L = 0x%08X ", mfspr (IBAT2L));
printf ("\tIBAT2U = 0x%08X\n", mfspr (IBAT2U));
printf ("\tDBAT2L = 0x%08X ", mfspr (DBAT2L));
printf ("\tDBAT2U = 0x%08X\n", mfspr (DBAT2U));
printf ("\tIBAT3L = 0x%08X ", mfspr (IBAT3L));
printf ("\tIBAT3U = 0x%08X\n", mfspr (IBAT3U));
printf ("\tDBAT3L = 0x%08X ", mfspr (DBAT3L));
printf ("\tDBAT3U = 0x%08X\n", mfspr (DBAT3U));
#ifdef CONFIG_HIGH_BATS
printf ("\tIBAT4L = 0x%08X ", mfspr (IBAT4L));
printf ("\tIBAT4U = 0x%08X\n", mfspr (IBAT4U));
printf ("\tDBAT4L = 0x%08X ", mfspr (DBAT4L));
printf ("\tDBAT4U = 0x%08X\n", mfspr (DBAT4U));
printf ("\tIBAT5L = 0x%08X ", mfspr (IBAT5L));
printf ("\tIBAT5U = 0x%08X\n", mfspr (IBAT5U));
printf ("\tDBAT5L = 0x%08X ", mfspr (DBAT5L));
printf ("\tDBAT5U = 0x%08X\n", mfspr (DBAT5U));
printf ("\tIBAT6L = 0x%08X ", mfspr (IBAT6L));
printf ("\tIBAT6U = 0x%08X\n", mfspr (IBAT6U));
printf ("\tDBAT6L = 0x%08X ", mfspr (DBAT6L));
printf ("\tDBAT6U = 0x%08X\n", mfspr (DBAT6U));
printf ("\tIBAT7L = 0x%08X ", mfspr (IBAT7L));
printf ("\tIBAT7U = 0x%08X\n", mfspr (IBAT7U));
printf ("\tDBAT7L = 0x%08X ", mfspr (DBAT7L));
printf ("\tDBAT7U = 0x%08X\n", mfspr (DBAT7U));
#endif
}

2
arch/sandbox/config.mk
View file

@ -44,8 +44,6 @@ cmd_u-boot-spl = (cd $(obj) && $(CC) -o $(SPL_BIN) -Wl,-T u-boot-spl.lds \
-Wl,--no-whole-archive \
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot-spl.map -Wl,--gc-sections)
CONFIG_ARCH_DEVICE_TREE := sandbox
ifeq ($(HOST_ARCH),$(HOST_ARCH_X86_64))
EFI_LDS := ${SRCDIR}/../../../arch/x86/lib/elf_x86_64_efi.lds
EFI_TARGET := --target=efi-app-x86_64

2
arch/sh/include/asm/pci.h
View file

@ -13,8 +13,6 @@
#include <pci.h>
#if defined(CONFIG_SH7751_PCI)
int pci_sh7751_init(struct pci_controller *hose);
#elif defined(CONFIG_SH7780_PCI)
int pci_sh7780_init(struct pci_controller *hose);
#else
#error "Not support PCI."
#endif

4
board/compulab/imx8mm-cl-iot-gate/ddr/Makefile
View file

@ -1,8 +1,4 @@
obj-y += ddr.o
obj-y += lpddr4_timing_ff020008.o
obj-y += lpddr4_timing_ff000110.o
ifdef CONFIG_TARGET_MCM_IMX8M_MINI
obj-y += lpddr4_timing_01061010.o
else
obj-y += lpddr4_timing_01061010.1_2.o
endif

1
board/davinci/da8xxevm/Makefile
View file

@ -5,6 +5,5 @@
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += da830evm.o
obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += da850evm.o
obj-$(CONFIG_TARGET_OMAPL138_LCDK) += omapl138_lcdk.o

8
board/freescale/common/Makefile
View file

@ -29,7 +29,6 @@ endif
obj-$(CONFIG_FSL_CADMUS) += cadmus.o
obj-$(CONFIG_FSL_VIA) += cds_via.o
obj-$(CONFIG_FMAN_ENET) += fman.o
obj-$(CONFIG_FSL_PIXIS) += pixis.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
endif
@ -37,7 +36,6 @@ obj-$(I2C_COMMON) += i2c_common.o
obj-$(CONFIG_FSL_USE_PCA9547_MUX) += i2c_mux.o
obj-$(CONFIG_$(SPL_)VID) += vid.o
obj-$(CONFIG_FSL_QIXIS) += qixis.o
obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o
endif
@ -53,14 +51,9 @@ endif
obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o
obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P1022DS) += ics307_clk.o
obj-$(CONFIG_P2020DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o
obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
obj-$(CONFIG_ZM7300) += zm7300.o
ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y)
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
endif
@ -78,7 +71,6 @@ obj-$(CONFIG_EMC2305) += emc2305.o
obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/
obj-$(CONFIG_TARGET_P3041DS) += p_corenet/
obj-$(CONFIG_TARGET_P4080DS) += p_corenet/
obj-$(CONFIG_TARGET_P5020DS) += p_corenet/
obj-$(CONFIG_TARGET_P5040DS) += p_corenet/
obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o

470
board/freescale/common/pixis.c
View file

@ -1,470 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2006,2010 Freescale Semiconductor
* Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#define pixis_base (u8 *)PIXIS_BASE
/*
* Simple board reset.
*/
void pixis_reset(void)
{
out_8(pixis_base + PIXIS_RST, 0);
while (1);
}
/*
* Per table 27, page 58 of MPC8641HPCN spec.
*/
static int set_px_sysclk(unsigned long sysclk)
{
u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
switch (sysclk) {
case 33:
sysclk_s = 0x04;
sysclk_r = 0x04;
sysclk_v = 0x07;
sysclk_aux = 0x00;
break;
case 40:
sysclk_s = 0x01;
sysclk_r = 0x1F;
sysclk_v = 0x20;
sysclk_aux = 0x01;
break;
case 50:
sysclk_s = 0x01;
sysclk_r = 0x1F;
sysclk_v = 0x2A;
sysclk_aux = 0x02;
break;
case 66:
sysclk_s = 0x01;
sysclk_r = 0x04;
sysclk_v = 0x04;
sysclk_aux = 0x03;
break;
case 83:
sysclk_s = 0x01;
sysclk_r = 0x1F;
sysclk_v = 0x4B;
sysclk_aux = 0x04;
break;
case 100:
sysclk_s = 0x01;
sysclk_r = 0x1F;
sysclk_v = 0x5C;
sysclk_aux = 0x05;
break;
case 134:
sysclk_s = 0x06;
sysclk_r = 0x1F;
sysclk_v = 0x3B;
sysclk_aux = 0x06;
break;
case 166:
sysclk_s = 0x06;
sysclk_r = 0x1F;
sysclk_v = 0x4B;
sysclk_aux = 0x07;
break;
default:
printf("Unsupported SYSCLK frequency.\n");
return 0;
}
vclkh = (sysclk_s << 5) | sysclk_r;
vclkl = sysclk_v;
out_8(pixis_base + PIXIS_VCLKH, vclkh);
out_8(pixis_base + PIXIS_VCLKL, vclkl);
out_8(pixis_base + PIXIS_AUX, sysclk_aux);
return 1;
}
/* Set the CFG_SYSPLL bits
*
* This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
* read_from_px_regs() is called.
*/
static int set_px_mpxpll(unsigned long mpxpll)
{
switch (mpxpll) {
case 2:
case 4:
case 6:
case 8:
case 10:
case 12:
case 14:
case 16:
clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
return 1;
}
printf("Unsupported MPXPLL ratio.\n");
return 0;
}
static int set_px_corepll(unsigned long corepll)
{
u8 val;
switch (corepll) {
case 20:
val = 0x08;
break;
case 25:
val = 0x0C;
break;
case 30:
val = 0x10;
break;
case 35:
val = 0x1C;
break;
case 40:
val = 0x14;
break;
case 45:
val = 0x0E;
break;
default:
printf("Unsupported COREPLL ratio.\n");
return 0;
}
clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
return 1;
}
#ifndef CFG_SYS_PIXIS_VCFGEN0_ENABLE
#define CFG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C
#endif
/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
*
* The PIXIS can be programmed to look at either the on-board dip switches
* or various other PIXIS registers to determine the values for COREPLL,
* MPXPLL, and SYSCLK.
*
* CFG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
* register that tells the pixis to use the various PIXIS register.
*/
static void read_from_px_regs(int set)
{
u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
if (set)
tmp = tmp | CFG_SYS_PIXIS_VCFGEN0_ENABLE;
else
tmp = tmp & ~CFG_SYS_PIXIS_VCFGEN0_ENABLE;
out_8(pixis_base + PIXIS_VCFGEN0, tmp);
}
/* CFG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
* register that tells the pixis to use the PX_VBOOT[LBMAP] register.
*/
#ifndef CFG_SYS_PIXIS_VBOOT_ENABLE
#define CFG_SYS_PIXIS_VBOOT_ENABLE 0x04
#endif
/* Configure the source of the boot location
*
* The PIXIS can be programmed to look at either the on-board dip switches
* or the PX_VBOOT[LBMAP] register to determine where we should boot.
*
* If we want to boot from the alternate boot bank, we need to tell the PIXIS
* to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
*/
static void read_from_px_regs_altbank(int set)
{
u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
if (set)
tmp = tmp | CFG_SYS_PIXIS_VBOOT_ENABLE;
else
tmp = tmp & ~CFG_SYS_PIXIS_VBOOT_ENABLE;
out_8(pixis_base + PIXIS_VCFGEN1, tmp);
}
/* CFG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
* tells the PIXIS what the alternate flash bank is.
*
* Note that it's not really a mask. It contains the actual LBMAP bits that
* must be set to select the alternate bank. This code assumes that the
* primary bank has these bits set to 0, and the alternate bank has these
* bits set to 1.
*/
#ifndef CFG_SYS_PIXIS_VBOOT_MASK
#define CFG_SYS_PIXIS_VBOOT_MASK (0x40)
#endif
/* Tell the PIXIS to boot from the default flash bank
*
* Program the default flash bank into the VBOOT register. This register is
* used only if PX_VCFGEN1[FLASH]=1.
*/
static void clear_altbank(void)
{
clrbits_8(pixis_base + PIXIS_VBOOT, CFG_SYS_PIXIS_VBOOT_MASK);
}
/* Tell the PIXIS to boot from the alternate flash bank
*
* Program the alternate flash bank into the VBOOT register. This register is
* used only if PX_VCFGEN1[FLASH]=1.
*/
static void set_altbank(void)
{
setbits_8(pixis_base + PIXIS_VBOOT, CFG_SYS_PIXIS_VBOOT_MASK);
}
/* Reset the board with watchdog disabled.
*
* This respects the altbank setting.
*/
static void set_px_go(void)
{
/* Disable the VELA sequencer and watchdog */
clrbits_8(pixis_base + PIXIS_VCTL, 9);
/* Reboot by starting the VELA sequencer */
setbits_8(pixis_base + PIXIS_VCTL, 0x1);
while (1);
}
/* Reset the board with watchdog enabled.
*
* This respects the altbank setting.
*/
static void set_px_go_with_watchdog(void)
{
/* Disable the VELA sequencer */
clrbits_8(pixis_base + PIXIS_VCTL, 1);
/* Enable the watchdog and reboot by starting the VELA sequencer */
setbits_8(pixis_base + PIXIS_VCTL, 0x9);
while (1);
}
/* Disable the watchdog
*
*/
static int pixis_disable_watchdog_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
/* Disable the VELA sequencer and the watchdog */
clrbits_8(pixis_base + PIXIS_VCTL, 9);
return 0;
}
U_BOOT_CMD(
diswd, 1, 0, pixis_disable_watchdog_cmd,
"Disable watchdog timer",
""
);
/*
* This function takes the non-integral cpu:mpx pll ratio
* and converts it to an integer that can be used to assign
* FPGA register values.
* input: strptr i.e. argv[2]
*/
static unsigned long strfractoint(char *strptr)
{
int i, j;
int mulconst;
int no_dec = 0;
unsigned long intval = 0, decval = 0;
char intarr[3], decarr[3];
/* Assign the integer part to intarr[]
* If there is no decimal point i.e.
* if the ratio is an integral value
* simply create the intarr.
*/
i = 0;
while (strptr[i] != '.') {
if (strptr[i] == 0) {
no_dec = 1;
break;
}
intarr[i] = strptr[i];
i++;
}
intarr[i] = '\0';
if (no_dec) {
/* Currently needed only for single digit corepll ratios */
mulconst = 10;
decval = 0;
} else {
j = 0;
i++; /* Skipping the decimal point */
while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
decarr[j] = strptr[i];
i++;
j++;
}
decarr[j] = '\0';
mulconst = 1;
for (i = 0; i < j; i++)
mulconst *= 10;
decval = dectoul(decarr, NULL);
}
intval = dectoul(intarr, NULL);
intval = intval * mulconst;
return intval + decval;
}
static int pixis_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
unsigned int i;
char *p_cf = NULL;
char *p_cf_sysclk = NULL;
char *p_cf_corepll = NULL;
char *p_cf_mpxpll = NULL;
char *p_altbank = NULL;
char *p_wd = NULL;
int unknown_param = 0;
/*
* No args is a simple reset request.
*/
if (argc <= 1) {
pixis_reset();
/* not reached */
}
for (i = 1; i < argc; i++) {
if (strcmp(argv[i], "cf") == 0) {
p_cf = argv[i];
if (i + 3 >= argc) {
break;
}
p_cf_sysclk = argv[i+1];
p_cf_corepll = argv[i+2];
p_cf_mpxpll = argv[i+3];
i += 3;
continue;
}
if (strcmp(argv[i], "altbank") == 0) {
p_altbank = argv[i];
continue;
}
if (strcmp(argv[i], "wd") == 0) {
p_wd = argv[i];
continue;
}
unknown_param = 1;
}
/*
* Check that cf has all required parms
*/
if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
|| unknown_param) {
#ifdef CONFIG_SYS_LONGHELP
puts(cmdtp->help);
putc('\n');
#endif
return 1;
}
/*
* PIXIS seems to be sensitive to the ordering of
* the registers that are touched.
*/
read_from_px_regs(0);
if (p_altbank)
read_from_px_regs_altbank(0);
clear_altbank();
/*
* Clock configuration specified.
*/
if (p_cf) {
unsigned long sysclk;
unsigned long corepll;
unsigned long mpxpll;
sysclk = dectoul(p_cf_sysclk, NULL);
corepll = strfractoint(p_cf_corepll);
mpxpll = dectoul(p_cf_mpxpll, NULL);
if (!(set_px_sysclk(sysclk)
&& set_px_corepll(corepll)
&& set_px_mpxpll(mpxpll))) {
#ifdef CONFIG_SYS_LONGHELP
puts(cmdtp->help);
putc('\n');
#endif
return 1;
}
read_from_px_regs(1);
}
/*
* Altbank specified
*
* NOTE CHANGE IN BEHAVIOR: previous code would default
* to enabling watchdog if altbank is specified.
* Now the watchdog must be enabled explicitly using 'wd'.
*/
if (p_altbank) {
set_altbank();
read_from_px_regs_altbank(1);
}
/*
* Reset with watchdog specified.
*/
if (p_wd)
set_px_go_with_watchdog();
else
set_px_go();
/*
* Shouldn't be reached.
*/
return 0;
}
U_BOOT_CMD(
pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
"Reset the board using the FPGA sequencer",
" pixis_reset\n"
" pixis_reset [altbank]\n"
" pixis_reset altbank wd\n"
" pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
" pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>"
);

54
board/freescale/common/pixis.h
View file

@ -1,54 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*/
#ifndef __PIXIS_H_
#define __PIXIS_H_ 1
/* PIXIS register set. */
#if defined(CONFIG_TARGET_MPC8536DS)
typedef struct pixis {
u8 id;
u8 ver;
u8 pver;
u8 csr;
u8 rst;
u8 rst2;
u8 aux1;
u8 spd;
u8 aux2;
u8 csr2;
u8 watch;
u8 led;
u8 pwr;
u8 res[3];
u8 vctl;
u8 vstat;
u8 vcfgen0;
u8 vcfgen1;
u8 vcore0;
u8 res1;
u8 vboot;
u8 vspeed[3];
u8 sclk[3];
u8 dclk[3];
u8 i2cdacr;
u8 vcoreacc[4];
u8 vcorecnt[3];
u8 vcoremax[2];
u8 vplatacc[4];
u8 vplatcnt[3];
u8 vplatmax[2];
u8 vtempacc[4];
u8 vtempcnt[3];
u8 vtempmax[2];
u8 res2[4];
} __attribute__ ((packed)) pixis_t;
#else
#error Need to define pixis_t for this board
#endif
/* Pointer to the PIXIS register set */
#define pixis ((pixis_t *)PIXIS_BASE)
#endif /* __PIXIS_H_ */

60
board/freescale/common/pq-mds-pib.c
View file

@ -1,60 +0,0 @@
/*
* Copyright (C) 2007 Freescale Semiconductor, Inc.
*
* Tony Li <tony.li@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation;
*/
#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include "pq-mds-pib.h"
int pib_init(void)
{
u8 val8;
u8 orig_i2c_bus;
/* Switch temporarily to I2C bus #2 */
orig_i2c_bus = i2c_get_bus_num();
i2c_set_bus_num(1);
val8 = 0;
#if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE)
/* Assign PIB PMC slot to desired PCI bus */
i2c_write(0x23, 0x6, 1, &val8, 1);
i2c_write(0x23, 0x7, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x23, 0x2, 1, &val8, 1);
i2c_write(0x23, 0x3, 1, &val8, 1);
val8 = 0;
i2c_write(0x26, 0x6, 1, &val8, 1);
val8 = 0x34;
i2c_write(0x26, 0x7, 1, &val8, 1);
val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */
i2c_write(0x26, 0x2, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x26, 0x3, 1, &val8, 1);
val8 = 0;
i2c_write(0x27, 0x6, 1, &val8, 1);
i2c_write(0x27, 0x7, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x27, 0x2, 1, &val8, 1);
val8 = 0xef;
i2c_write(0x27, 0x3, 1, &val8, 1);
eieio();
printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
#endif
/* Reset to original I2C bus */
i2c_set_bus_num(orig_i2c_bus);
return 0;
}

9
board/freescale/common/pq-mds-pib.h
View file

@ -1,9 +0,0 @@
/*
* Copyright (C) 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation;
*/
extern int pib_init(void);

530
board/freescale/common/vsc3316_3308.c
View file

@ -1,530 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
#include "vsc3316_3308.h"
#include <log.h>
#define REVISION_ID_REG 0x7E
#define INTERFACE_MODE_REG 0x79
#define CURRENT_PAGE_REGISTER 0x7F
#define CONNECTION_CONFIG_PAGE 0x00
#define INPUT_STATE_REG 0x13
#define GLOBAL_INPUT_ISE1 0x51
#define GLOBAL_INPUT_ISE2 0x52
#define GLOBAL_INPUT_GAIN 0x53
#define GLOBAL_INPUT_LOS 0x55
#define GLOBAL_OUTPUT_PE1 0x56
#define GLOBAL_OUTPUT_PE2 0x57
#define GLOBAL_OUTPUT_LEVEL 0x58
#define GLOBAL_OUTPUT_TERMINATION 0x5A
#define GLOBAL_CORE_CNTRL 0x5D
#define OUTPUT_MODE_PAGE 0x23
#define CORE_CONTROL_PAGE 0x25
#define CORE_CONFIG_REG 0x75
int vsc_if_enable(unsigned int vsc_addr)
{
u8 data;
debug("VSC:Configuring VSC at I2C address 0x%2x"
" for 2-wire interface\n", vsc_addr);
/* enable 2-wire Serial InterFace (I2C) */
data = 0x02;
#if CONFIG_IS_ENABLED(DM_I2C)
int ret, bus_num = 0;
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
return dm_i2c_write(dev, INTERFACE_MODE_REG, &data, 1);
#else
return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1);
#endif
}
int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
unsigned int num_con)
{
unsigned int i;
u8 rev_id = 0;
int ret;
debug("VSC:Initializing VSC3316 at I2C address 0x%2x"
" for Tx\n", vsc_addr);
#if CONFIG_IS_ENABLED(DM_I2C)
int bus_num = 0;
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1);
if (ret < 0) {
printf("VSC:0x%x could not read REV_ID from device.\n",
vsc_addr);
return ret;
}
if (rev_id != 0xab) {
printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
vsc_addr);
return -ENODEV;
}
ret = vsc_if_enable(vsc_addr);
if (ret) {
printf("VSC:0x%x could not configured for 2-wire I/F.\n",
vsc_addr);
return ret;
}
/* config connections - page 0x00 */
dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
/* Making crosspoint connections, by connecting required
* input to output
*/
for (i = 0; i < num_con ; i++)
dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]);
/* input state - page 0x13 */
dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
/* Configuring the required input of the switch */
for (i = 0; i < num_con ; i++)
dm_i2c_reg_write(dev, con_arr[i][0], 0x80);
/* Setting Global Input LOS threshold value */
dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60);
/* config output mode - page 0x23 */
dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
/* Turn ON the Output driver correspond to required output*/
for (i = 0; i < num_con ; i++)
dm_i2c_reg_write(dev, con_arr[i][1], 0);
/* configure global core control register, Turn on Global core power */
dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0);
#else
ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
if (ret < 0) {
printf("VSC:0x%x could not read REV_ID from device.\n",
vsc_addr);
return ret;
}
if (rev_id != 0xab) {
printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
vsc_addr);
return -ENODEV;
}
ret = vsc_if_enable(vsc_addr);
if (ret) {
printf("VSC:0x%x could not configured for 2-wire I/F.\n",
vsc_addr);
return ret;
}
/* config connections - page 0x00 */
i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
/* Making crosspoint connections, by connecting required
* input to output */
for (i = 0; i < num_con ; i++)
i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]);
/* input state - page 0x13 */
i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
/* Configuring the required input of the switch */
for (i = 0; i < num_con ; i++)
i2c_reg_write(vsc_addr, con_arr[i][0], 0x80);
/* Setting Global Input LOS threshold value */
i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60);
/* config output mode - page 0x23 */
i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
/* Turn ON the Output driver correspond to required output*/
for (i = 0; i < num_con ; i++)
i2c_reg_write(vsc_addr, con_arr[i][1], 0);
/* configure global core control register, Turn on Global core power */
i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
#endif
vsc_wp_config(vsc_addr);
return 0;
}
#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2],
unsigned int num_con)
{
unsigned int i;
u8 rev_id = 0;
int ret;
debug("VSC:Initializing VSC3308 at I2C address 0x%x for Tx\n",
vsc_addr);
#if CONFIG_IS_ENABLED(DM_I2C)
int bus_num = 0;
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1);
if (ret < 0) {
printf("VSC:0x%x could not read REV_ID from device.\n",
vsc_addr);
return ret;
}
if (rev_id != 0xab) {
printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
vsc_addr);
return -ENODEV;
}
ret = vsc_if_enable(vsc_addr);
if (ret) {
printf("VSC:0x%x could not configured for 2-wire I/F.\n",
vsc_addr);
return ret;
}
/* config connections - page 0x00 */
dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
/* Configure Global Input ISE */
dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0);
dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0);
/* Configure Tx/Rx Global Output PE1 */
dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE1, 0);
/* Configure Tx/Rx Global Output PE2 */
dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE2, 0);
/* Configure Tx/Rx Global Input GAIN */
dm_i2c_reg_write(dev, GLOBAL_INPUT_GAIN, 0x3F);
/* Setting Global Input LOS threshold value */
dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0xE0);
/* Setting Global output termination */
dm_i2c_reg_write(dev, GLOBAL_OUTPUT_TERMINATION, 0);
/* Configure Tx/Rx Global Output level */
if (vsc_addr == VSC3308_TX_ADDRESS)
dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 4);
else
dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 2);
/* Making crosspoint connections, by connecting required
* input to output
*/
for (i = 0; i < num_con ; i++)
dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]);
/* input state - page 0x13 */
dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
/* Turning off all the required input of the switch */
for (i = 0; i < num_con; i++)
dm_i2c_reg_write(dev, con_arr[i][0], 1);
/* only turn on specific Tx/Rx requested by the XFI erratum */
if (vsc_addr == VSC3308_TX_ADDRESS) {
dm_i2c_reg_write(dev, 2, 0);
dm_i2c_reg_write(dev, 3, 0);
} else {
dm_i2c_reg_write(dev, 0, 0);
dm_i2c_reg_write(dev, 1, 0);
}
/* config output mode - page 0x23 */
dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
/* Turn off the Output driver correspond to required output*/
for (i = 0; i < num_con ; i++)
dm_i2c_reg_write(dev, con_arr[i][1], 1);
/* only turn on specific Tx/Rx requested by the XFI erratum */
if (vsc_addr == VSC3308_TX_ADDRESS) {
dm_i2c_reg_write(dev, 0, 0);
dm_i2c_reg_write(dev, 1, 0);
} else {
dm_i2c_reg_write(dev, 3, 0);
dm_i2c_reg_write(dev, 4, 0);
}
/* configure global core control register, Turn on Global core power */
dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0);
#else
ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
if (ret < 0) {
printf("VSC:0x%x could not read REV_ID from device.\n",
vsc_addr);
return ret;
}
if (rev_id != 0xab) {
printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
vsc_addr);
return -ENODEV;
}
ret = vsc_if_enable(vsc_addr);
if (ret) {
printf("VSC:0x%x could not configured for 2-wire I/F.\n",
vsc_addr);
return ret;
}
/* config connections - page 0x00 */
i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
/* Configure Global Input ISE */
i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0);
i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0);
/* Configure Tx/Rx Global Output PE1 */
i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE1, 0);
/* Configure Tx/Rx Global Output PE2 */
i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE2, 0);
/* Configure Tx/Rx Global Input GAIN */
i2c_reg_write(vsc_addr, GLOBAL_INPUT_GAIN, 0x3F);
/* Setting Global Input LOS threshold value */
i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0xE0);
/* Setting Global output termination */
i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_TERMINATION, 0);
/* Configure Tx/Rx Global Output level */
if (vsc_addr == VSC3308_TX_ADDRESS)
i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 4);
else
i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 2);
/* Making crosspoint connections, by connecting required
* input to output */
for (i = 0; i < num_con ; i++)
i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]);
/* input state - page 0x13 */
i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
/* Turning off all the required input of the switch */
for (i = 0; i < num_con; i++)
i2c_reg_write(vsc_addr, con_arr[i][0], 1);
/* only turn on specific Tx/Rx requested by the XFI erratum */
if (vsc_addr == VSC3308_TX_ADDRESS) {
i2c_reg_write(vsc_addr, 2, 0);
i2c_reg_write(vsc_addr, 3, 0);
} else {
i2c_reg_write(vsc_addr, 0, 0);
i2c_reg_write(vsc_addr, 1, 0);
}
/* config output mode - page 0x23 */
i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
/* Turn off the Output driver correspond to required output*/
for (i = 0; i < num_con ; i++)
i2c_reg_write(vsc_addr, con_arr[i][1], 1);
/* only turn on specific Tx/Rx requested by the XFI erratum */
if (vsc_addr == VSC3308_TX_ADDRESS) {
i2c_reg_write(vsc_addr, 0, 0);
i2c_reg_write(vsc_addr, 1, 0);
} else {
i2c_reg_write(vsc_addr, 3, 0);
i2c_reg_write(vsc_addr, 4, 0);
}
/* configure global core control register, Turn on Global core power */
i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
#endif
vsc_wp_config(vsc_addr);
return 0;
}
#endif
int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
unsigned int num_con)
{
unsigned int i;
u8 rev_id = 0;
int ret;
debug("VSC:Initializing VSC3308 at I2C address 0x%x"
" for Tx\n", vsc_addr);
#if CONFIG_IS_ENABLED(DM_I2C)
int bus_num = 0;
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1);
if (ret < 0) {
printf("VSC:0x%x could not read REV_ID from device.\n",
vsc_addr);
return ret;
}
if (rev_id != 0xab) {
printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
vsc_addr);
return -ENODEV;
}
ret = vsc_if_enable(vsc_addr);
if (ret) {
printf("VSC:0x%x could not configured for 2-wire I/F.\n",
vsc_addr);
return ret;
}
/* config connections - page 0x00 */
dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
/* Making crosspoint connections, by connecting required
* input to output
*/
for (i = 0; i < num_con ; i++)
dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]);
/*Configure Global Input ISE and gain */
dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0x12);
dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0x12);
/* input state - page 0x13 */
dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
/* Turning ON the required input of the switch */
for (i = 0; i < num_con ; i++)
dm_i2c_reg_write(dev, con_arr[i][0], 0);
/* Setting Global Input LOS threshold value */
dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60);
/* config output mode - page 0x23 */
dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
/* Turn ON the Output driver correspond to required output*/
for (i = 0; i < num_con ; i++)
dm_i2c_reg_write(dev, con_arr[i][1], 0);
/* configure global core control register, Turn on Global core power */
dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0);
#else
ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
if (ret < 0) {
printf("VSC:0x%x could not read REV_ID from device.\n",
vsc_addr);
return ret;
}
if (rev_id != 0xab) {
printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
vsc_addr);
return -ENODEV;
}
ret = vsc_if_enable(vsc_addr);
if (ret) {
printf("VSC:0x%x could not configured for 2-wire I/F.\n",
vsc_addr);
return ret;
}
/* config connections - page 0x00 */
i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
/* Making crosspoint connections, by connecting required
* input to output */
for (i = 0; i < num_con ; i++)
i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]);
/*Configure Global Input ISE and gain */
i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0x12);
i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0x12);
/* input state - page 0x13 */
i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
/* Turning ON the required input of the switch */
for (i = 0; i < num_con ; i++)
i2c_reg_write(vsc_addr, con_arr[i][0], 0);
/* Setting Global Input LOS threshold value */
i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60);
/* config output mode - page 0x23 */
i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
/* Turn ON the Output driver correspond to required output*/
for (i = 0; i < num_con ; i++)
i2c_reg_write(vsc_addr, con_arr[i][1], 0);
/* configure global core control register, Turn on Global core power */
i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
#endif
vsc_wp_config(vsc_addr);
return 0;
}
void vsc_wp_config(unsigned int vsc_addr)
{
debug("VSC:Configuring VSC at address:0x%x for WP\n", vsc_addr);
/* For new crosspoint configuration to occur, WP bit of
* CORE_CONFIG_REG should be set 1 and then reset to 0 */
#if CONFIG_IS_ENABLED(DM_I2C)
int ret, bus_num = 0;
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return;
}
dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x01);
dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x0);
#else
i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x01);
i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x0);
#endif
}

232
board/freescale/common/zm7300.c
View file

@ -1,232 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
/* Power-One ZM7300 DPM */
#include "zm7300.h"
#include <log.h>
#define DPM_WP 0x96
#define WRP_OPCODE 0x01
#define WRM_OPCODE 0x02
#define RRP_OPCODE 0x11
#define DPM_SUCCESS 0x01
#define DPM_EXEC_FAIL 0x00
static const uint16_t hex_to_1_10mv[] = {
5000,
5125,
5250,
5375,
5500,
5625,
5750,
5875,
6000,
6125,
6250,
6375,
6500,
6625,
6750,
6875,
7000,
7125,
7250,
7375,
7500,
7625,
7750,
7875,
8000,
8125,
8250,
8375,
8500,
8625,
8750,
8875,
9000,
9125,
9250,
9375,
9500, /* 0.95mV */
9625,
9750,
9875,
10000, /* 1.0V */
10125,
10250,
10375,
10500,
10625,
10750,
10875,
11000,
11125,
11250,
11375,
11500,
11625,
11750,
11875,
12000,
12125,
12250,
12375,
0, /* reserved */
};
/* Read Data d from Register r of POL p */
u8 dpm_rrp(uchar r)
{
u8 ret[5];
ret[0] = RRP_OPCODE;
/* POL is 0 */
ret[1] = 0;
ret[2] = r;
i2c_read(I2C_DPM_ADDR, 0, -3, ret, 2);
if (ret[1] == DPM_SUCCESS) { /* the DPM returned success as status */
debug("RRP_OPCODE returned success data is %x\n", ret[0]);
return ret[0];
} else {
return -1;
}
}
/* Write Data d into DPM register r (RAM) */
int dpm_wrm(u8 r, u8 d)
{
u8 ret[5];
ret[0] = WRM_OPCODE;
ret[1] = r;
ret[2] = d;
i2c_read(I2C_DPM_ADDR, 0, -3, ret, 1);
if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
debug("WRM_OPCODE returned success data is %x\n", ret[0]);
return ret[0];
} else {
return -1;
}
}
/* Write Data d into Register r of POL(s) a */
int dpm_wrp(u8 r, u8 d)
{
u8 ret[7];
ret[0] = WRP_OPCODE;
/* only POL0 is present */
ret[1] = 0x01;
ret[2] = 0x00;
ret[3] = 0x00;
ret[4] = 0x00;
ret[5] = r;
ret[6] = d;
i2c_read(I2C_DPM_ADDR, 0, -7, ret, 1);
if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
debug("WRP_OPCODE returned success data is %x\n", ret[0]);
return 0;
} else {
return -1;
}
}
/* Uses the DPM command RRP */
u8 zm_read(uchar reg)
{
return dpm_rrp(reg);
}
/* ZM_write --
Steps:
a. Write data to the register
b. Read data from register and compare to written value
c. Return return_code & voltage_read
*/
u8 zm_write(u8 reg, u8 data)
{
u8 d;
/* write data to register */
dpm_wrp(reg, data);
/* read register and compare to written value */
d = dpm_rrp(reg);
if (d != data) {
printf("zm_write : Comparison register data failed\n");
return -1;
}
return d;
}
/* zm_write_out_voltage
* voltage in 1/10 mV
*/
int zm_write_voltage(int voltage)
{
u8 reg = 0x7, vid;
uint16_t voltage_read;
u8 ret;
vid = (voltage - 5000) / ZM_STEP;
ret = zm_write(reg, vid);
if (ret != -1) {
voltage_read = hex_to_1_10mv[ret];
debug("voltage set to %dmV\n", voltage_read/10);
return voltage_read;
}
return -1;
}
/* zm_read_out_voltage
* voltage in 1/10 mV
*/
int zm_read_voltage(void)
{
u8 reg = 0x7;
u8 ret;
int voltage;
ret = zm_read(reg);
if (ret != -1) {
voltage = hex_to_1_10mv[ret];
debug("Voltage read is %dmV\n", voltage/10);
return voltage;
} else {
return -1;
}
}
int zm_disable_wp()
{
u8 new_wp_value;
/* Disable using Write-Protect register 0x96 */
new_wp_value = 0x8;
if ((dpm_wrm(DPM_WP, new_wp_value)) < 0) {
printf("Disable Write-Protect register failed\n");
return -1;
}
return 0;
}
int zm_enable_wp()
{
u8 orig_wp_value;
orig_wp_value = 0x0;
/* Enable using Write-Protect register 0x96 */
if ((dpm_wrm(DPM_WP, orig_wp_value)) < 0) {
printf("Enable Write-Protect register failed\n");
return -1;
}
return 0;
}

21
board/freescale/common/zm7300.h
View file

@ -1,21 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#ifndef __ZM7300_H_
#define __ZM7300_H 1_
#include <common.h>
#include <i2c.h>
#include <errno.h>
#include <asm/io.h>
#define ZM_STEP 125
int zm7300_set_voltage(int voltage_1_10mv);
int zm_write_voltage(int voltage);
int zm_read_voltage(void);
int zm_disable_wp(void);
int zm_enable_wp(void);
#endif /* __ZM7300_H_ */

4
board/freescale/mx7ulp_evk/Makefile
View file

@ -2,7 +2,3 @@
# (C) Copyright 2016 Freescale Semiconductor, Inc.
obj-y := mx7ulp_evk.o
extra-$(CONFIG_USE_PLUGIN) := plugin.bin
$(obj)/plugin.bin: $(obj)/plugin.o
$(OBJCOPY) -O binary --gap-fill 0xff $< $@

1
board/gdsys/a38x/hre.c
View file

@ -15,7 +15,6 @@
#include <u-boot/sha1.h>
#include <asm/byteorder.h>
#include <asm/unaligned.h>
#include <pca9698.h>
#include "hre.h"

3
board/gdsys/common/Makefile
View file

@ -3,9 +3,8 @@
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o
obj-$(CONFIG_CONTROLCENTERD) += dp501.o
obj-$(CONFIG_TARGET_CONTROLCENTERDC) += dp501.o
obj-$(CONFIG_TARGET_GAZERBEAM) += osd.o ihs_mdio.o ioep-fpga.o
ifdef CONFIG_OSD

28
board/gdsys/common/fpga.c
View file

@ -1,28 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2013
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
#include <common.h>
#include <gdsys_fpga.h>
#include <asm/io.h>
int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
{
out_le16(reg, data);
return 0;
}
int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
{
*data = in_le16(reg);
return 0;
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

1
board/xes/common/Makefile
View file

@ -7,4 +7,3 @@ obj-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o
obj-$(CONFIG_ARCH_P2020) += fsl_8xxx_clk.o
obj-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o
obj-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o
obj-$(CONFIG_NAND_ACTL) += actl_nand.o

49
board/xes/common/actl_nand.c
View file

@ -1,49 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
* This driver support NAND devices which have address lines
* connected as ALE and CLE inputs.
*/
#include <common.h>
#include <nand.h>
#include <linux/mtd/rawnand.h>
#include <asm/io.h>
/*
* Hardware specific access to control-lines
*/
static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
{
struct nand_chip *this = mtd_to_nand(mtd);
ulong IO_ADDR_W;
if (ctrl & NAND_CTRL_CHANGE) {
IO_ADDR_W = (ulong)this->IO_ADDR_W;
IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE |
CONFIG_SYS_NAND_ACTL_ALE |
CONFIG_SYS_NAND_ACTL_NCE);
if (ctrl & NAND_CLE)
IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE;
if (ctrl & NAND_ALE)
IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE;
if (ctrl & NAND_NCE)
IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE;
this->IO_ADDR_W = (void *)IO_ADDR_W;
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
int board_nand_init(struct nand_chip *nand)
{
nand->ecc.mode = NAND_ECC_SOFT;
nand->cmd_ctrl = nand_addr_hwcontrol;
nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY;
return 0;
}

7
cmd/Kconfig
View file

@ -2021,6 +2021,13 @@ config CMD_LED
with led on/off/togle/blink. Any LED drivers can be controlled with
this command, e.g. led_gpio.
config CMD_INI
bool "ini"
help
Enable the 'ini' command which allows a .ini file to be parsed and
placed into environment variables. Please check the source code for
this as there is no documentation.
config CMD_DATE
bool "date"
default y if DM_RTC

2
cmd/Makefile
View file

@ -47,7 +47,6 @@ obj-$(CONFIG_CMD_CONFIG) += config.o
obj-$(CONFIG_CMD_CONITRACE) += conitrace.o
obj-$(CONFIG_CMD_CONSOLE) += console.o
obj-$(CONFIG_CMD_CPU) += cpu.o
obj-$(CONFIG_DATAFLASH_MMC_SELECT) += dataflash_mmc_mux.o
obj-$(CONFIG_CMD_DATE) += date.o
obj-$(CONFIG_CMD_DEMO) += demo.o
obj-$(CONFIG_CMD_DM) += dm.o
@ -108,7 +107,6 @@ obj-$(CONFIG_ID_EEPROM) += mac.o
obj-$(CONFIG_CMD_MD5SUM) += md5sum.o
obj-$(CONFIG_CMD_MEMORY) += mem.o
obj-$(CONFIG_CMD_IO) += io.o
obj-$(CONFIG_CMD_MFSL) += mfsl.o
obj-$(CONFIG_CMD_MII) += mii.o
obj-$(CONFIG_CMD_MISC) += misc.o
obj-$(CONFIG_CMD_MDIO) += mdio.o

48
cmd/dataflash_mmc_mux.c
View file

@ -1,48 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <common.h>
#include <command.h>
static int mmc_nspi (const char *);
int do_dataflash_mmc_mux(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
switch (argc) {
case 2: /* on / off */
switch (mmc_nspi (argv[1])) {
case 0: AT91F_SelectSPI ();
break;
case 1: AT91F_SelectMMC ();
break;
}
case 1: /* get status */
printf ("Mux is configured to be %s\n",
AT91F_GetMuxStatus () ? "MMC" : "SPI");
return 0;
default:
return CMD_RET_USAGE;
}
return 0;
}
static int mmc_nspi (const char *s)
{
if (strcmp (s, "mmc") == 0) {
return 1;
} else if (strcmp (s, "spi") == 0) {
return 0;
}
return -1;
}
U_BOOT_CMD(
dataflash_mmc_mux, 2, 1, do_dataflash_mmc_mux,
"enable or disable MMC or SPI\n",
"[mmc, spi]\n"
" - enable or disable MMC or SPI"
);

387
cmd/mfsl.c
View file

@ -1,387 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*/
/*
* Microblaze FSL support
*/
#include <common.h>
#include <config.h>
#include <command.h>
#include <asm/asm.h>
int do_frd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
unsigned int fslnum;
unsigned int num;
unsigned int blocking;
if (argc < 2)
return CMD_RET_USAGE;
fslnum = (unsigned int)hextoul(argv[1], NULL);
blocking = (unsigned int)hextoul(argv[2], NULL);
if (fslnum < 0 || fslnum >= XILINX_FSL_NUMBER) {
puts ("Bad number of FSL\n");
return CMD_RET_USAGE;
}
switch (fslnum) {
#if (XILINX_FSL_NUMBER > 0)
case 0:
switch (blocking) {
case 0: NGET (num, 0);
break;
case 1: NCGET (num, 0);
break;
case 2: GET (num, 0);
break;
case 3: CGET (num, 0);
break;
default:
return 2;
}
break;
#endif
#if (XILINX_FSL_NUMBER > 1)
case 1:
switch (blocking) {
case 0: NGET (num, 1);
break;
case 1: NCGET (num, 1);
break;
case 2: GET (num, 1);
break;
case 3: CGET (num, 1);
break;
default:
return 2;
}
break;
#endif
#if (XILINX_FSL_NUMBER > 2)
case 2:
switch (blocking) {
case 0: NGET (num, 2);
break;
case 1: NCGET (num, 2);
break;
case 2: GET (num, 2);
break;
case 3: CGET (num, 2);
break;
default:
return 2;
}
break;
#endif
#if (XILINX_FSL_NUMBER > 3)
case 3:
switch (blocking) {
case 0: NGET (num, 3);
break;
case 1: NCGET (num, 3);
break;
case 2: GET (num, 3);
break;
case 3: CGET (num, 3);
break;
default:
return 2;
}
break;
#endif
#if (XILINX_FSL_NUMBER > 4)
case 4:
switch (blocking) {
case 0: NGET (num, 4);
break;
case 1: NCGET (num, 4);
break;
case 2: GET (num, 4);
break;
case 3: CGET (num, 4);
break;
default:
return 2;
}
break;
#endif
#if (XILINX_FSL_NUMBER > 5)
case 5:
switch (blocking) {
case 0: NGET (num, 5);
break;
case 1: NCGET (num, 5);
break;
case 2: GET (num, 5);
break;
case 3: CGET (num, 5);
break;
default:
return 2;
}
break;
#endif
#if (XILINX_FSL_NUMBER > 6)
case 6:
switch (blocking) {
case 0: NGET (num, 6);
break;
case 1: NCGET (num, 6);
break;
case 2: GET (num, 6);
break;
case 3: CGET (num, 6);
break;
default:
return 2;
}
break;
#endif
#if (XILINX_FSL_NUMBER > 7)
case 7:
switch (blocking) {
case 0: NGET (num, 7);
break;
case 1: NCGET (num, 7);
break;
case 2: GET (num, 7);
break;
case 3: CGET (num, 7);
break;
default:
return 2;
}
break;
#endif
default:
return 1;
}
printf ("%01x: 0x%08x - %s %s read\n", fslnum, num,
blocking < 2 ? "non blocking" : "blocking",
((blocking == 1) || (blocking == 3)) ? "control" : "data" );
return 0;
}
int do_fwr(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
unsigned int fslnum;
unsigned int num;
unsigned int blocking;
if (argc < 3)
return CMD_RET_USAGE;
fslnum = (unsigned int)hextoul(argv[1], NULL);
num = (unsigned int)hextoul(argv[2], NULL);
blocking = (unsigned int)hextoul(argv[3], NULL);
if (fslnum < 0 || fslnum >= XILINX_FSL_NUMBER)
return CMD_RET_USAGE;
switch (fslnum) {
#if (XILINX_FSL_NUMBER > 0)
case 0:
switch (blocking) {
case 0: NPUT (num, 0);
break;
case 1: NCPUT (num, 0);
break;
case 2: PUT (num, 0);
break;
case 3: CPUT (num, 0);
break;
default:
return 2;
}
break;
#endif
#if (XILINX_FSL_NUMBER > 1)
case 1:
switch (blocking) {
case 0: NPUT (num, 1);
break;
case 1: NCPUT (num, 1);
break;
case 2: PUT (num, 1);
break;
case 3: CPUT (num, 1);
break;
default:
return 2;
}
break;
#endif
#if (XILINX_FSL_NUMBER > 2)
case 2:
switch (blocking) {
case 0: NPUT (num, 2);
break;
case 1: NCPUT (num, 2);
break;
case 2: PUT (num, 2);
break;
case 3: CPUT (num, 2);
break;
default:
return 2;
}
break;
#endif
#if (XILINX_FSL_NUMBER > 3)
case 3:
switch (blocking) {
case 0: NPUT (num, 3);
break;
case 1: NCPUT (num, 3);
break;
case 2: PUT (num, 3);
break;
case 3: CPUT (num, 3);
break;
default:
return 2;
}
break;
#endif
#if (XILINX_FSL_NUMBER > 4)
case 4:
switch (blocking) {
case 0: NPUT (num, 4);
break;
case 1: NCPUT (num, 4);
break;
case 2: PUT (num, 4);
break;
case 3: CPUT (num, 4);
break;
default:
return 2;
}
break;
#endif
#if (XILINX_FSL_NUMBER > 5)
case 5:
switch (blocking) {
case 0: NPUT (num, 5);
break;
case 1: NCPUT (num, 5);
break;
case 2: PUT (num, 5);
break;
case 3: CPUT (num, 5);
break;
default:
return 2;
}
break;
#endif
#if (XILINX_FSL_NUMBER > 6)
case 6:
switch (blocking) {
case 0: NPUT (num, 6);
break;
case 1: NCPUT (num, 6);
break;
case 2: PUT (num, 6);
break;
case 3: CPUT (num, 6);
break;
default:
return 2;
}
break;
#endif
#if (XILINX_FSL_NUMBER > 7)
case 7:
switch (blocking) {
case 0: NPUT (num, 7);
break;
case 1: NCPUT (num, 7);
break;
case 2: PUT (num, 7);
break;
case 3: CPUT (num, 7);
break;
default:
return 2;
}
break;
#endif
default:
return 1;
}
printf ("%01x: 0x%08x - %s %s write\n", fslnum, num,
blocking < 2 ? "non blocking" : "blocking",
((blocking == 1) || (blocking == 3)) ? "control" : "data" );
return 0;
}
int do_rspr(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
unsigned int reg = 0;
unsigned int val = 0;
if (argc < 2)
return CMD_RET_USAGE;
reg = (unsigned int)hextoul(argv[1], NULL);
val = (unsigned int)hextoul(argv[2], NULL);
switch (reg) {
case 0x1:
if (argc > 2) {
MTS (val, rmsr);
NOP;
MFS (val, rmsr);
} else {
MFS (val, rmsr);
}
puts ("MSR");
break;
case 0x3:
MFS (val, rear);
puts ("EAR");
break;
case 0x5:
MFS (val, resr);
puts ("ESR");
break;
default:
puts ("Unsupported register\n");
return 1;
}
printf (": 0x%08x\n", val);
return 0;
}
/***************************************************/
U_BOOT_CMD (frd, 3, 1, do_frd,
"read data from FSL",
"- [fslnum [0|1|2|3]]\n"
" 0 - non blocking data read\n"
" 1 - non blocking control read\n"
" 2 - blocking data read\n"
" 3 - blocking control read");
U_BOOT_CMD (fwr, 4, 1, do_fwr,
"write data to FSL",
"- [fslnum [0|1|2|3]]\n"
" 0 - non blocking data write\n"
" 1 - non blocking control write\n"
" 2 - blocking data write\n"
" 3 - blocking control write");
U_BOOT_CMD (rspr, 3, 1, do_rspr,
"read/write special purpose register",
"- reg_num [write value] read/write special purpose register\n"
" 1 - MSR - Machine status register\n"
" 3 - EAR - Exception address register\n"
" 5 - ESR - Exception status register");

1
cmd/nvedit.c
View file

@ -51,7 +51,6 @@ DECLARE_GLOBAL_DATA_PTR;
defined(CONFIG_ENV_IS_IN_NAND) || \
defined(CONFIG_ENV_IS_IN_NVRAM) || \
defined(CONFIG_ENV_IS_IN_ONENAND) || \
defined(CONFIG_ENV_IS_IN_SATA) || \
defined(CONFIG_ENV_IS_IN_SPI_FLASH) || \
defined(CONFIG_ENV_IS_IN_REMOTE) || \
defined(CONFIG_ENV_IS_IN_UBI)

6
common/usb_hub.c
View file

@ -506,11 +506,6 @@ static int usb_scan_port(struct usb_device_scan *usb_scan)
if (portchange & USB_PORT_STAT_C_ENABLE) {
debug("port %d enable change, status %x\n", i + 1, portstatus);
usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_C_ENABLE);
/*
* The following hack causes a ghost device problem
* to Faraday EHCI
*/
#ifndef CONFIG_USB_EHCI_FARADAY
/*
* EM interference sometimes causes bad shielded USB
* devices to be shutdown by the hub, this hack enables
@ -523,7 +518,6 @@ static int usb_scan_port(struct usb_device_scan *usb_scan)
i + 1);
usb_hub_port_connect_change(dev, i);
}
#endif
}
if (portstatus & USB_PORT_STAT_SUSPEND) {

1
drivers/Makefile
View file

@ -59,7 +59,6 @@ obj-$(CONFIG_SPL_USB_GADGET) += usb/common/
obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/udc/
obj-$(CONFIG_SPL_WATCHDOG) += watchdog/
obj-$(CONFIG_SPL_USB_HOST) += usb/host/
obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
obj-$(CONFIG_SPL_SATA) += ata/ scsi/
obj-$(CONFIG_SPL_LEGACY_BLOCK) += block/
obj-$(CONFIG_SPL_THERMAL) += thermal/

12
drivers/fpga/Kconfig
View file

@ -21,6 +21,12 @@ config FPGA_SOCFPGA
This provides common functionality for Gen5 and Arria10 devices.
config FPGA_STRATIX_II
bool "Enable Stratix II FPGA drivers"
depends on FPGA_ALTERA
help
Say Y here to enable the Altera Stratix II FPGA-specific driver.
config FPGA_STRATIX_V
bool "Enable Stratix V FPGA drivers"
depends on FPGA_ALTERA
@ -54,6 +60,12 @@ config FPGA_INTEL_SDM_MAILBOX
Enable FPGA driver for writing full bitstream into Intel FPGA
devices through SDM (Secure Device Manager) Mailbox.
config FPGA_LATTICE
bool "Enable Lattice FPGA driver"
help
This is used for the lattice FPGAs. Please check the source code as
there is no documentation for this at present.
config FPGA_XILINX
bool "Enable Xilinx FPGA drivers"
select FPGA

5
drivers/gpio/Makefile
View file

@ -23,13 +23,11 @@ obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o
obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o
obj-$(CONFIG_IPROC_GPIO) += iproc_gpio.o
obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
obj-$(CONFIG_KONA_GPIO) += kona_gpio.o
obj-$(CONFIG_MCP230XX_GPIO) += mcp230xx_gpio.o
obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o
obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o
obj-$(CONFIG_NPCM_GPIO) += npcm_gpio.o
obj-$(CONFIG_PCA953X) += pca953x.o
obj-$(CONFIG_PCA9698) += pca9698.o
obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o
obj-$(CONFIG_RCAR_GPIO) += gpio-rcar.o
obj-$(CONFIG_RZA1_GPIO) += gpio-rza1.o
@ -38,16 +36,13 @@ obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o sandbox_test.o
obj-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o
obj-$(CONFIG_TEGRA186_GPIO) += tegra186_gpio.o
obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
obj-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o
obj-$(CONFIG_ALTERA_PIO) += altera_pio.o
obj-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
obj-$(CONFIG_MPC8XXX_GPIO) += mpc8xxx_gpio.o
obj-$(CONFIG_MPC83XX_SPISEL_BOOT) += mpc83xx_spisel_boot.o
obj-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o
obj-$(CONFIG_OMAP_GPIO) += omap_gpio.o
obj-$(CONFIG_BCM2835_GPIO) += bcm2835_gpio.o
obj-$(CONFIG_XILINX_GPIO) += xilinx_gpio.o
obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
obj-$(CONFIG_TCA642X) += tca642x.o
obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o

425
drivers/gpio/adi_gpio2.c
View file

@ -1,425 +0,0 @@
/*
* ADI GPIO2 Abstraction Layer
* Support BF54x, BF60x and future processors.
*
* Copyright 2008-2013 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#include <common.h>
#include <malloc.h>
#include <linux/bug.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#define RESOURCE_LABEL_SIZE 16
static struct str_ident {
char name[RESOURCE_LABEL_SIZE];
} str_ident[MAX_RESOURCES];
static void gpio_error(unsigned gpio)
{
printf("adi_gpio2: GPIO %d wasn't requested!\n", gpio);
}
static void set_label(unsigned short ident, const char *label)
{
if (label) {
strncpy(str_ident[ident].name, label,
RESOURCE_LABEL_SIZE);
str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
}
}
static char *get_label(unsigned short ident)
{
return *str_ident[ident].name ? str_ident[ident].name : "UNKNOWN";
}
static int cmp_label(unsigned short ident, const char *label)
{
if (label == NULL)
printf("adi_gpio2: please provide none-null label\n");
if (label)
return strcmp(str_ident[ident].name, label);
else
return -EINVAL;
}
#define map_entry(m, i) reserved_##m##_map[gpio_bank(i)]
#define is_reserved(m, i, e) (map_entry(m, i) & gpio_bit(i))
#define reserve(m, i) (map_entry(m, i) |= gpio_bit(i))
#define unreserve(m, i) (map_entry(m, i) &= ~gpio_bit(i))
#define DECLARE_RESERVED_MAP(m, c) unsigned short reserved_##m##_map[c]
static DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM);
static DECLARE_RESERVED_MAP(peri, gpio_bank(MAX_RESOURCES));
inline int check_gpio(unsigned gpio)
{
#if defined(CONFIG_BF54x)
if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 ||
gpio == GPIO_PH14 || gpio == GPIO_PH15 ||
gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
return -EINVAL;
#endif
if (gpio >= MAX_GPIOS)
return -EINVAL;
return 0;
}
static void port_setup(unsigned gpio, unsigned short usage)
{
#if defined(CONFIG_BF54x)
if (usage == GPIO_USAGE)
gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
else
gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
#else
if (usage == GPIO_USAGE)
gpio_array[gpio_bank(gpio)]->port_fer_clear = gpio_bit(gpio);
else
gpio_array[gpio_bank(gpio)]->port_fer_set = gpio_bit(gpio);
#endif
}
inline void portmux_setup(unsigned short per)
{
u32 pmux;
u16 ident = P_IDENT(per);
u16 function = P_FUNCT2MUX(per);
pmux = gpio_array[gpio_bank(ident)]->port_mux;
pmux &= ~(0x3 << (2 * gpio_sub_n(ident)));
pmux |= (function & 0x3) << (2 * gpio_sub_n(ident));
gpio_array[gpio_bank(ident)]->port_mux = pmux;
}
inline u16 get_portmux(unsigned short per)
{
u32 pmux;
u16 ident = P_IDENT(per);
pmux = gpio_array[gpio_bank(ident)]->port_mux;
return pmux >> (2 * gpio_sub_n(ident)) & 0x3;
}
unsigned short get_gpio_dir(unsigned gpio)
{
return 0x01 &
(gpio_array[gpio_bank(gpio)]->dir_clear >> gpio_sub_n(gpio));
}
/***********************************************************
*
* FUNCTIONS: Peripheral Resource Allocation
* and PortMux Setup
*
* INPUTS/OUTPUTS:
* per Peripheral Identifier
* label String
*
* DESCRIPTION: Peripheral Resource Allocation and Setup API
**************************************************************/
int peripheral_request(unsigned short per, const char *label)
{
unsigned short ident = P_IDENT(per);
/*
* Don't cares are pins with only one dedicated function
*/
if (per & P_DONTCARE)
return 0;
if (!(per & P_DEFINED))
return -EINVAL;
BUG_ON(ident >= MAX_RESOURCES);
/* If a pin can be muxed as either GPIO or peripheral, make
* sure it is not already a GPIO pin when we request it.
*/
if (unlikely(!check_gpio(ident) && is_reserved(gpio, ident, 1))) {
printf("%s: Peripheral %d is already reserved as GPIO by %s!\n",
__func__, ident, get_label(ident));
return -EBUSY;
}
if (unlikely(is_reserved(peri, ident, 1))) {
/*
* Pin functions like AMC address strobes my
* be requested and used by several drivers
*/
if (!((per & P_MAYSHARE) &&
get_portmux(per) == P_FUNCT2MUX(per))) {
/*
* Allow that the identical pin function can
* be requested from the same driver twice
*/
if (cmp_label(ident, label) == 0)
goto anyway;
printf("%s: Peripheral %d function %d is already "
"reserved by %s!\n", __func__, ident,
P_FUNCT2MUX(per), get_label(ident));
return -EBUSY;
}
}
anyway:
reserve(peri, ident);
portmux_setup(per);
port_setup(ident, PERIPHERAL_USAGE);
set_label(ident, label);
return 0;
}
int peripheral_request_list(const unsigned short per[], const char *label)
{
u16 cnt;
int ret;
for (cnt = 0; per[cnt] != 0; cnt++) {
ret = peripheral_request(per[cnt], label);
if (ret < 0) {
for (; cnt > 0; cnt--)
peripheral_free(per[cnt - 1]);
return ret;
}
}
return 0;
}
void peripheral_free(unsigned short per)
{
unsigned short ident = P_IDENT(per);
if (per & P_DONTCARE)
return;
if (!(per & P_DEFINED))
return;
if (unlikely(!is_reserved(peri, ident, 0)))
return;
if (!(per & P_MAYSHARE))
port_setup(ident, GPIO_USAGE);
unreserve(peri, ident);
set_label(ident, "free");
}
void peripheral_free_list(const unsigned short per[])
{
u16 cnt;
for (cnt = 0; per[cnt] != 0; cnt++)
peripheral_free(per[cnt]);
}
/***********************************************************
*
* FUNCTIONS: GPIO Driver
*
* INPUTS/OUTPUTS:
* gpio PIO Number between 0 and MAX_GPIOS
* label String
*
* DESCRIPTION: GPIO Driver API
**************************************************************/
int gpio_request(unsigned gpio, const char *label)
{
if (check_gpio(gpio) < 0)
return -EINVAL;
/*
* Allow that the identical GPIO can
* be requested from the same driver twice
* Do nothing and return -
*/
if (cmp_label(gpio, label) == 0)
return 0;
if (unlikely(is_reserved(gpio, gpio, 1))) {
printf("adi_gpio2: GPIO %d is already reserved by %s!\n",
gpio, get_label(gpio));
return -EBUSY;
}
if (unlikely(is_reserved(peri, gpio, 1))) {
printf("adi_gpio2: GPIO %d is already reserved as Peripheral "
"by %s!\n", gpio, get_label(gpio));
return -EBUSY;
}
reserve(gpio, gpio);
set_label(gpio, label);
port_setup(gpio, GPIO_USAGE);
return 0;
}
int gpio_free(unsigned gpio)
{
if (check_gpio(gpio) < 0)
return -1;
if (unlikely(!is_reserved(gpio, gpio, 0))) {
gpio_error(gpio);
return -1;
}
unreserve(gpio, gpio);
set_label(gpio, "free");
return 0;
}
#ifdef ADI_SPECIAL_GPIO_BANKS
static DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES));
int special_gpio_request(unsigned gpio, const char *label)
{
/*
* Allow that the identical GPIO can
* be requested from the same driver twice
* Do nothing and return -
*/
if (cmp_label(gpio, label) == 0)
return 0;
if (unlikely(is_reserved(special_gpio, gpio, 1))) {
printf("adi_gpio2: GPIO %d is already reserved by %s!\n",
gpio, get_label(gpio));
return -EBUSY;
}
if (unlikely(is_reserved(peri, gpio, 1))) {
printf("adi_gpio2: GPIO %d is already reserved as Peripheral "
"by %s!\n", gpio, get_label(gpio));
return -EBUSY;
}
reserve(special_gpio, gpio);
reserve(peri, gpio);
set_label(gpio, label);
port_setup(gpio, GPIO_USAGE);
return 0;
}
void special_gpio_free(unsigned gpio)
{
if (unlikely(!is_reserved(special_gpio, gpio, 0))) {
gpio_error(gpio);
return;
}
unreserve(special_gpio, gpio);
unreserve(peri, gpio);
set_label(gpio, "free");
}
#endif
static inline void __gpio_direction_input(unsigned gpio)
{
gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
#if defined(CONFIG_BF54x)
gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
#else
gpio_array[gpio_bank(gpio)]->inen_set = gpio_bit(gpio);
#endif
}
int gpio_direction_input(unsigned gpio)
{
unsigned long flags;
if (!is_reserved(gpio, gpio, 0)) {
gpio_error(gpio);
return -EINVAL;
}
local_irq_save(flags);
__gpio_direction_input(gpio);
local_irq_restore(flags);
return 0;
}
int gpio_set_value(unsigned gpio, int arg)
{
if (arg)
gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
else
gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
return 0;
}
int gpio_direction_output(unsigned gpio, int value)
{
unsigned long flags;
if (!is_reserved(gpio, gpio, 0)) {
gpio_error(gpio);
return -EINVAL;
}
local_irq_save(flags);
#if defined(CONFIG_BF54x)
gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
#else
gpio_array[gpio_bank(gpio)]->inen_clear = gpio_bit(gpio);
#endif
gpio_set_value(gpio, value);
gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
local_irq_restore(flags);
return 0;
}
int gpio_get_value(unsigned gpio)
{
return 1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio));
}
void gpio_labels(void)
{
int c, gpio;
for (c = 0; c < MAX_RESOURCES; c++) {
gpio = is_reserved(gpio, c, 1);
if (!check_gpio(c) && gpio)
printf("GPIO_%d:\t%s\tGPIO %s\n", c, get_label(c),
get_gpio_dir(c) ? "OUTPUT" : "INPUT");
else if (is_reserved(peri, c, 1))
printf("GPIO_%d:\t%s\tPeripheral\n", c, get_label(c));
else
continue;
}
}

141
drivers/gpio/kona_gpio.c
View file

@ -1,141 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
*/
#include <common.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/arch/sysmap.h>
#define GPIO_BASE (void *)GPIO2_BASE_ADDR
#define GPIO_PASSWD 0x00a5a501
#define GPIO_PER_BANK 32
#define GPIO_MAX_BANK_NUM 8
#define GPIO_BANK(gpio) ((gpio) >> 5)
#define GPIO_BITMASK(gpio) \
(1UL << ((gpio) & (GPIO_PER_BANK - 1)))
#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
#define GPIO_CONTROL(bank) (0x00000100 + ((bank) << 2))
#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
#define GPIO_GPPWR_OFFSET 0x00000520
#define GPIO_GPCTR0_DBR_SHIFT 5
#define GPIO_GPCTR0_DBR_MASK 0x000001e0
#define GPIO_GPCTR0_ITR_SHIFT 3
#define GPIO_GPCTR0_ITR_MASK 0x00000018
#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
#define GPIO_GPCTR0_IOTR_MASK 0x00000001
#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
int gpio_request(unsigned gpio, const char *label)
{
unsigned int value, off;
writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET);
off = GPIO_PWD_STATUS(GPIO_BANK(gpio));
value = readl(GPIO_BASE + off) & ~GPIO_BITMASK(gpio);
writel(value, GPIO_BASE + off);
return 0;
}
int gpio_free(unsigned gpio)
{
unsigned int value, off;
writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET);
off = GPIO_PWD_STATUS(GPIO_BANK(gpio));
value = readl(GPIO_BASE + off) | GPIO_BITMASK(gpio);
writel(value, GPIO_BASE + off);
return 0;
}
int gpio_direction_input(unsigned gpio)
{
u32 val;
val = readl(GPIO_BASE + GPIO_CONTROL(gpio));
val &= ~GPIO_GPCTR0_IOTR_MASK;
val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
writel(val, GPIO_BASE + GPIO_CONTROL(gpio));
return 0;
}
int gpio_direction_output(unsigned gpio, int value)
{
int bank_id = GPIO_BANK(gpio);
int bitmask = GPIO_BITMASK(gpio);
u32 val, off;
val = readl(GPIO_BASE + GPIO_CONTROL(gpio));
val &= ~GPIO_GPCTR0_IOTR_MASK;
val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
writel(val, GPIO_BASE + GPIO_CONTROL(gpio));
off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
val = readl(GPIO_BASE + off);
val |= bitmask;
writel(val, GPIO_BASE + off);
return 0;
}
int gpio_get_value(unsigned gpio)
{
int bank_id = GPIO_BANK(gpio);
int bitmask = GPIO_BITMASK(gpio);
u32 val, off;
/* determine the GPIO pin direction */
val = readl(GPIO_BASE + GPIO_CONTROL(gpio));
val &= GPIO_GPCTR0_IOTR_MASK;
/* read the GPIO bank status */
off = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ?
GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id);
val = readl(GPIO_BASE + off);
/* return the specified bit status */
return !!(val & bitmask);
}
void gpio_set_value(unsigned gpio, int value)
{
int bank_id = GPIO_BANK(gpio);
int bitmask = GPIO_BITMASK(gpio);
u32 val, off;
/* determine the GPIO pin direction */
val = readl(GPIO_BASE + GPIO_CONTROL(gpio));
val &= GPIO_GPCTR0_IOTR_MASK;
/* this function only applies to output pin */
if (GPIO_GPCTR0_IOTR_CMD_INPUT == val) {
printf("%s: Cannot set an input pin %d\n", __func__, gpio);
return;
}
off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
val = readl(GPIO_BASE + off);
val |= bitmask;
writel(val, GPIO_BASE + off);
}

183
drivers/gpio/mpc83xx_gpio.c
View file

@ -1,183 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Freescale MPC83xx GPIO handling.
*/
#include <common.h>
#include <malloc.h>
#include <mpc83xx.h>
#include <asm/gpio.h>
#include <asm/io.h>
#ifndef CFG_MPC83XX_GPIO_0_INIT_DIRECTION
#define CFG_MPC83XX_GPIO_0_INIT_DIRECTION 0
#endif
#ifndef CFG_MPC83XX_GPIO_1_INIT_DIRECTION
#define CFG_MPC83XX_GPIO_1_INIT_DIRECTION 0
#endif
#ifndef CFG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN
#define CFG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN 0
#endif
#ifndef CFG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN
#define CFG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN 0
#endif
#ifndef CFG_MPC83XX_GPIO_0_INIT_VALUE
#define CFG_MPC83XX_GPIO_0_INIT_VALUE 0
#endif
#ifndef CFG_MPC83XX_GPIO_1_INIT_VALUE
#define CFG_MPC83XX_GPIO_1_INIT_VALUE 0
#endif
static unsigned int gpio_output_value[MPC83XX_GPIO_CTRLRS];
/*
* Generic_GPIO primitives.
*/
int gpio_request(unsigned gpio, const char *label)
{
if (gpio >= MAX_NUM_GPIOS)
return -1;
return 0;
}
int gpio_free(unsigned gpio)
{
/* Do not set to input */
return 0;
}
/* set GPIO pin 'gpio' as an input */
int gpio_direction_input(unsigned gpio)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
unsigned int ctrlr;
unsigned int line;
unsigned int line_mask;
/* 32-bits per controller */
ctrlr = gpio >> 5;
line = gpio & (0x1F);
/* Big endian */
line_mask = 1 << (31 - line);
clrbits_be32(&im->gpio[ctrlr].dir, line_mask);
return 0;
}
/* set GPIO pin 'gpio' as an output, with polarity 'value' */
int gpio_direction_output(unsigned gpio, int value)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
unsigned int ctrlr;
unsigned int line;
unsigned int line_mask;
if (value != 0 && value != 1) {
printf("Error: Value parameter must be 0 or 1.\n");
return -1;
}
gpio_set_value(gpio, value);
/* 32-bits per controller */
ctrlr = gpio >> 5;
line = gpio & (0x1F);
/* Big endian */
line_mask = 1 << (31 - line);
/* Make the line output */
setbits_be32(&im->gpio[ctrlr].dir, line_mask);
return 0;
}
/* read GPIO IN value of pin 'gpio' */
int gpio_get_value(unsigned gpio)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
unsigned int ctrlr;
unsigned int line;
unsigned int line_mask;
/* 32-bits per controller */
ctrlr = gpio >> 5;
line = gpio & (0x1F);
/* Big endian */
line_mask = 1 << (31 - line);
/* Read the value and mask off the bit */
return (in_be32(&im->gpio[ctrlr].dat) & line_mask) != 0;
}
/* write GPIO OUT value to pin 'gpio' */
int gpio_set_value(unsigned gpio, int value)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
unsigned int ctrlr;
unsigned int line;
unsigned int line_mask;
if (value != 0 && value != 1) {
printf("Error: Value parameter must be 0 or 1.\n");
return -1;
}
/* 32-bits per controller */
ctrlr = gpio >> 5;
line = gpio & (0x1F);
/* Big endian */
line_mask = 1 << (31 - line);
/* Update the local output buffer soft copy */
gpio_output_value[ctrlr] =
(gpio_output_value[ctrlr] & ~line_mask) | \
(value ? line_mask : 0);
/* Write the output */
out_be32(&im->gpio[ctrlr].dat, gpio_output_value[ctrlr]);
return 0;
}
/* Configure GPIO registers early */
void mpc83xx_gpio_init_f(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
#if MPC83XX_GPIO_CTRLRS >= 1
out_be32(&im->gpio[0].dir, CFG_MPC83XX_GPIO_0_INIT_DIRECTION);
out_be32(&im->gpio[0].odr, CFG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN);
out_be32(&im->gpio[0].dat, CFG_MPC83XX_GPIO_0_INIT_VALUE);
out_be32(&im->gpio[0].ier, 0xFFFFFFFF); /* Clear all events */
out_be32(&im->gpio[0].imr, 0);
out_be32(&im->gpio[0].icr, 0);
#endif
#if MPC83XX_GPIO_CTRLRS >= 2
out_be32(&im->gpio[1].dir, CFG_MPC83XX_GPIO_1_INIT_DIRECTION);
out_be32(&im->gpio[1].odr, CFG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN);
out_be32(&im->gpio[1].dat, CFG_MPC83XX_GPIO_1_INIT_VALUE);
out_be32(&im->gpio[1].ier, 0xFFFFFFFF); /* Clear all events */
out_be32(&im->gpio[1].imr, 0);
out_be32(&im->gpio[1].icr, 0);
#endif
}
/* Initialize GPIO soft-copies */
void mpc83xx_gpio_init_r(void)
{
#if MPC83XX_GPIO_CTRLRS >= 1
gpio_output_value[0] = CFG_MPC83XX_GPIO_0_INIT_VALUE;
#endif
#if MPC83XX_GPIO_CTRLRS >= 2
gpio_output_value[1] = CFG_MPC83XX_GPIO_1_INIT_VALUE;
#endif
}

127
drivers/gpio/pca9698.c
View file

@ -1,127 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2011
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
/*
* Driver for NXP's pca9698 40 bit I2C gpio expander
*/
#include <common.h>
#include <i2c.h>
#include <malloc.h>
#include <linux/errno.h>
#include <pca9698.h>
/*
* The pca9698 registers
*/
#define PCA9698_REG_INPUT 0x00
#define PCA9698_REG_OUTPUT 0x08
#define PCA9698_REG_POLARITY 0x10
#define PCA9698_REG_CONFIG 0x18
#define PCA9698_BUFFER_SIZE 5
#define PCA9698_GPIO_COUNT 40
static int pca9698_read40(u8 addr, u8 offset, u8 *buffer)
{
u8 command = offset | 0x80; /* autoincrement */
return i2c_read(addr, command, 1, buffer, PCA9698_BUFFER_SIZE);
}
static int pca9698_write40(u8 addr, u8 offset, u8 *buffer)
{
u8 command = offset | 0x80; /* autoincrement */
return i2c_write(addr, command, 1, buffer, PCA9698_BUFFER_SIZE);
}
static void pca9698_set_bit(unsigned gpio, u8 *buffer, unsigned value)
{
unsigned byte = gpio / 8;
unsigned bit = gpio % 8;
if (value)
buffer[byte] |= (1 << bit);
else
buffer[byte] &= ~(1 << bit);
}
int pca9698_request(unsigned gpio, const char *label)
{
if (gpio >= PCA9698_GPIO_COUNT)
return -EINVAL;
return 0;
}
void pca9698_free(unsigned gpio)
{
}
int pca9698_direction_input(u8 addr, unsigned gpio)
{
u8 data[PCA9698_BUFFER_SIZE];
int res;
res = pca9698_read40(addr, PCA9698_REG_CONFIG, data);
if (res)
return res;
pca9698_set_bit(gpio, data, 1);
return pca9698_write40(addr, PCA9698_REG_CONFIG, data);
}
int pca9698_direction_output(u8 addr, unsigned gpio, int value)
{
u8 data[PCA9698_BUFFER_SIZE];
int res;
res = pca9698_set_value(addr, gpio, value);
if (res)
return res;
res = pca9698_read40(addr, PCA9698_REG_CONFIG, data);
if (res)
return res;
pca9698_set_bit(gpio, data, 0);
return pca9698_write40(addr, PCA9698_REG_CONFIG, data);
}
int pca9698_get_value(u8 addr, unsigned gpio)
{
unsigned config_byte = gpio / 8;
unsigned config_bit = gpio % 8;
unsigned value;
u8 data[PCA9698_BUFFER_SIZE];
int res;
res = pca9698_read40(addr, PCA9698_REG_INPUT, data);
if (res)
return -1;
value = data[config_byte] & (1 << config_bit);
return !!value;
}
int pca9698_set_value(u8 addr, unsigned gpio, int value)
{
u8 data[PCA9698_BUFFER_SIZE];
int res;
res = pca9698_read40(addr, PCA9698_REG_OUTPUT, data);
if (res)
return res;
pca9698_set_bit(gpio, data, value);
return pca9698_write40(addr, PCA9698_REG_OUTPUT, data);
}

1
drivers/i2c/Makefile
View file

@ -25,7 +25,6 @@ obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o
obj-$(CONFIG_SYS_I2C_IPROC) += iproc_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o
obj-$(CONFIG_SYS_I2C_MICROCHIP) += i2c-microchip.o

728
drivers/i2c/kona_i2c.c
View file

@ -1,728 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
*
* NOTE: This driver should be converted to driver model before June 2017.
* Please see doc/driver-model/i2c-howto.rst for instructions.
*/
#include <common.h>
#include <log.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include <i2c.h>
/* Hardware register offsets and field defintions */
#define CS_OFFSET 0x00000020
#define CS_ACK_SHIFT 3
#define CS_ACK_MASK 0x00000008
#define CS_ACK_CMD_GEN_START 0x00000000
#define CS_ACK_CMD_GEN_RESTART 0x00000001
#define CS_CMD_SHIFT 1
#define CS_CMD_CMD_NO_ACTION 0x00000000
#define CS_CMD_CMD_START_RESTART 0x00000001
#define CS_CMD_CMD_STOP 0x00000002
#define CS_EN_SHIFT 0
#define CS_EN_CMD_ENABLE_BSC 0x00000001
#define TIM_OFFSET 0x00000024
#define TIM_PRESCALE_SHIFT 6
#define TIM_P_SHIFT 3
#define TIM_NO_DIV_SHIFT 2
#define TIM_DIV_SHIFT 0
#define DAT_OFFSET 0x00000028
#define TOUT_OFFSET 0x0000002c
#define TXFCR_OFFSET 0x0000003c
#define TXFCR_FIFO_FLUSH_MASK 0x00000080
#define TXFCR_FIFO_EN_MASK 0x00000040
#define IER_OFFSET 0x00000044
#define IER_READ_COMPLETE_INT_MASK 0x00000010
#define IER_I2C_INT_EN_MASK 0x00000008
#define IER_FIFO_INT_EN_MASK 0x00000002
#define IER_NOACK_EN_MASK 0x00000001
#define ISR_OFFSET 0x00000048
#define ISR_RESERVED_MASK 0xffffff60
#define ISR_CMDBUSY_MASK 0x00000080
#define ISR_READ_COMPLETE_MASK 0x00000010
#define ISR_SES_DONE_MASK 0x00000008
#define ISR_ERR_MASK 0x00000004
#define ISR_TXFIFOEMPTY_MASK 0x00000002
#define ISR_NOACK_MASK 0x00000001
#define CLKEN_OFFSET 0x0000004c
#define CLKEN_AUTOSENSE_OFF_MASK 0x00000080
#define CLKEN_M_SHIFT 4
#define CLKEN_N_SHIFT 1
#define CLKEN_CLKEN_MASK 0x00000001
#define FIFO_STATUS_OFFSET 0x00000054
#define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004
#define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010
#define HSTIM_OFFSET 0x00000058
#define HSTIM_HS_MODE_MASK 0x00008000
#define HSTIM_HS_HOLD_SHIFT 10
#define HSTIM_HS_HIGH_PHASE_SHIFT 5
#define HSTIM_HS_SETUP_SHIFT 0
#define PADCTL_OFFSET 0x0000005c
#define PADCTL_PAD_OUT_EN_MASK 0x00000004
#define RXFCR_OFFSET 0x00000068
#define RXFCR_NACK_EN_SHIFT 7
#define RXFCR_READ_COUNT_SHIFT 0
#define RXFIFORDOUT_OFFSET 0x0000006c
/* Locally used constants */
#define MAX_RX_FIFO_SIZE 64U /* bytes */
#define MAX_TX_FIFO_SIZE 64U /* bytes */
#define I2C_TIMEOUT 100000 /* usecs */
#define WAIT_INT_CHK 100 /* usecs */
#if I2C_TIMEOUT % WAIT_INT_CHK
#error I2C_TIMEOUT must be a multiple of WAIT_INT_CHK
#endif
/* Operations that can be commanded to the controller */
enum bcm_kona_cmd_t {
BCM_CMD_NOACTION = 0,
BCM_CMD_START,
BCM_CMD_RESTART,
BCM_CMD_STOP,
};
/* Internal divider settings for standard mode, fast mode and fast mode plus */
struct bus_speed_cfg {
uint8_t time_m; /* Number of cycles for setup time */
uint8_t time_n; /* Number of cycles for hold time */
uint8_t prescale; /* Prescale divider */
uint8_t time_p; /* Timing coefficient */
uint8_t no_div; /* Disable clock divider */
uint8_t time_div; /* Post-prescale divider */
};
static const struct bus_speed_cfg std_cfg_table[] = {
[IC_SPEED_MODE_STANDARD] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02},
[IC_SPEED_MODE_FAST] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02},
[IC_SPEED_MODE_FAST_PLUS] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03},
};
struct bcm_kona_i2c_dev {
void *base;
uint speed;
const struct bus_speed_cfg *std_cfg;
};
/* Keep these two defines in sync */
#define DEF_SPD I2C_SPEED_STANDARD_RATE
#define DEF_SPD_ENUM IC_SPEED_MODE_STANDARD
#define DEF_DEVICE(num) \
{(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]}
static struct bcm_kona_i2c_dev g_i2c_devs[CFG_SYS_MAX_I2C_BUS] = {
#ifdef CONFIG_SYS_I2C_BASE0
DEF_DEVICE(0),
#endif
#ifdef CONFIG_SYS_I2C_BASE1
DEF_DEVICE(1),
#endif
#ifdef CONFIG_SYS_I2C_BASE2
DEF_DEVICE(2),
#endif
#ifdef CONFIG_SYS_I2C_BASE3
DEF_DEVICE(3),
#endif
#ifdef CONFIG_SYS_I2C_BASE4
DEF_DEVICE(4),
#endif
#ifdef CONFIG_SYS_I2C_BASE5
DEF_DEVICE(5),
#endif
};
#define I2C_M_TEN 0x0010 /* ten bit address */
#define I2C_M_RD 0x0001 /* read data */
#define I2C_M_NOSTART 0x4000 /* no restart between msgs */
struct kona_i2c_msg {
uint16_t addr;
uint16_t flags;
uint16_t len;
uint8_t *buf;
};
static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev,
enum bcm_kona_cmd_t cmd)
{
debug("%s, %d\n", __func__, cmd);
switch (cmd) {
case BCM_CMD_NOACTION:
writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) |
(CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
dev->base + CS_OFFSET);
break;
case BCM_CMD_START:
writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) |
(CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
(CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
dev->base + CS_OFFSET);
break;
case BCM_CMD_RESTART:
writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) |
(CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
(CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
dev->base + CS_OFFSET);
break;
case BCM_CMD_STOP:
writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) |
(CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
dev->base + CS_OFFSET);
break;
default:
printf("Unknown command %d\n", cmd);
}
}
static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev)
{
writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,
dev->base + CLKEN_OFFSET);
}
static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev)
{
writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,
dev->base + CLKEN_OFFSET);
}
/* Wait until at least one of the mask bit(s) are set */
static unsigned long wait_for_int_timeout(struct bcm_kona_i2c_dev *dev,
unsigned long time_left,
uint32_t mask)
{
uint32_t status;
while (time_left) {
status = readl(dev->base + ISR_OFFSET);
if ((status & ~ISR_RESERVED_MASK) == 0) {
debug("Bogus I2C interrupt 0x%x\n", status);
continue;
}
/* Must flush the TX FIFO when NAK detected */
if (status & ISR_NOACK_MASK)
writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
dev->base + TXFCR_OFFSET);
writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);
if (status & mask) {
/* We are done since one of the mask bits are set */
return time_left;
}
udelay(WAIT_INT_CHK);
time_left -= WAIT_INT_CHK;
}
return 0;
}
/* Send command to I2C bus */
static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev,
enum bcm_kona_cmd_t cmd)
{
int rc = 0;
unsigned long time_left = I2C_TIMEOUT;
/* Send the command */
bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd);
/* Wait for transaction to finish or timeout */
time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
if (!time_left) {
printf("controller timed out\n");
rc = -ETIMEDOUT;
}
/* Clear command */
bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
return rc;
}
/* Read a single RX FIFO worth of data from the i2c bus */
static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev,
uint8_t *buf, unsigned int len,
unsigned int last_byte_nak)
{
unsigned long time_left = I2C_TIMEOUT;
/* Start the RX FIFO */
writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) |
(len << RXFCR_READ_COUNT_SHIFT), dev->base + RXFCR_OFFSET);
/* Wait for FIFO read to complete */
time_left =
wait_for_int_timeout(dev, time_left, IER_READ_COMPLETE_INT_MASK);
if (!time_left) {
printf("RX FIFO time out\n");
return -EREMOTEIO;
}
/* Read data from FIFO */
for (; len > 0; len--, buf++)
*buf = readl(dev->base + RXFIFORDOUT_OFFSET);
return 0;
}
/* Read any amount of data using the RX FIFO from the i2c bus */
static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev,
struct kona_i2c_msg *msg)
{
unsigned int bytes_to_read = MAX_RX_FIFO_SIZE;
unsigned int last_byte_nak = 0;
unsigned int bytes_read = 0;
int rc;
uint8_t *tmp_buf = msg->buf;
while (bytes_read < msg->len) {
if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) {
last_byte_nak = 1; /* NAK last byte of transfer */
bytes_to_read = msg->len - bytes_read;
}
rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read,
last_byte_nak);
if (rc < 0)
return -EREMOTEIO;
bytes_read += bytes_to_read;
tmp_buf += bytes_to_read;
}
return 0;
}
/* Write a single byte of data to the i2c bus */
static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data,
unsigned int nak_expected)
{
unsigned long time_left = I2C_TIMEOUT;
unsigned int nak_received;
/* Clear pending session done interrupt */
writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);
/* Send one byte of data */
writel(data, dev->base + DAT_OFFSET);
time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
if (!time_left) {
debug("controller timed out\n");
return -ETIMEDOUT;
}
nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0;
if (nak_received ^ nak_expected) {
debug("unexpected NAK/ACK\n");
return -EREMOTEIO;
}
return 0;
}
/* Write a single TX FIFO worth of data to the i2c bus */
static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev,
uint8_t *buf, unsigned int len)
{
int k;
unsigned long time_left = I2C_TIMEOUT;
unsigned int fifo_status;
/* Write data into FIFO */
for (k = 0; k < len; k++)
writel(buf[k], (dev->base + DAT_OFFSET));
/* Wait for FIFO to empty */
do {
time_left =
wait_for_int_timeout(dev, time_left,
(IER_FIFO_INT_EN_MASK |
IER_NOACK_EN_MASK));
fifo_status = readl(dev->base + FIFO_STATUS_OFFSET);
} while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK));
/* Check if there was a NAK */
if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) {
printf("unexpected NAK\n");
return -EREMOTEIO;
}
/* Check if a timeout occurred */
if (!time_left) {
printf("completion timed out\n");
return -EREMOTEIO;
}
return 0;
}
/* Write any amount of data using TX FIFO to the i2c bus */
static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev,
struct kona_i2c_msg *msg)
{
unsigned int bytes_to_write = MAX_TX_FIFO_SIZE;
unsigned int bytes_written = 0;
int rc;
uint8_t *tmp_buf = msg->buf;
while (bytes_written < msg->len) {
if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE)
bytes_to_write = msg->len - bytes_written;
rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf,
bytes_to_write);
if (rc < 0)
return -EREMOTEIO;
bytes_written += bytes_to_write;
tmp_buf += bytes_to_write;
}
return 0;
}
/* Send i2c address */
static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev,
struct kona_i2c_msg *msg)
{
unsigned char addr;
if (msg->flags & I2C_M_TEN) {
/* First byte is 11110XX0 where XX is upper 2 bits */
addr = 0xf0 | ((msg->addr & 0x300) >> 7);
if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
return -EREMOTEIO;
/* Second byte is the remaining 8 bits */
addr = msg->addr & 0xff;
if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
return -EREMOTEIO;
if (msg->flags & I2C_M_RD) {
/* For read, send restart command */
if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0)
return -EREMOTEIO;
/* Then re-send the first byte with the read bit set */
addr = 0xf0 | ((msg->addr & 0x300) >> 7) | 0x01;
if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
return -EREMOTEIO;
}
} else {
addr = msg->addr << 1;
if (msg->flags & I2C_M_RD)
addr |= 1;
if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
return -EREMOTEIO;
}
return 0;
}
static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev)
{
writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,
dev->base + CLKEN_OFFSET);
}
static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev)
{
writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,
dev->base + HSTIM_OFFSET);
writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) |
(dev->std_cfg->time_p << TIM_P_SHIFT) |
(dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) |
(dev->std_cfg->time_div << TIM_DIV_SHIFT),
dev->base + TIM_OFFSET);
writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) |
(dev->std_cfg->time_n << CLKEN_N_SHIFT) |
CLKEN_CLKEN_MASK, dev->base + CLKEN_OFFSET);
}
/* Master transfer function */
static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev,
struct kona_i2c_msg msgs[], int num)
{
struct kona_i2c_msg *pmsg;
int rc = 0;
int i;
/* Enable pad output */
writel(0, dev->base + PADCTL_OFFSET);
/* Enable internal clocks */
bcm_kona_i2c_enable_clock(dev);
/* Send start command */
rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START);
if (rc < 0) {
printf("Start command failed rc = %d\n", rc);
goto xfer_disable_pad;
}
/* Loop through all messages */
for (i = 0; i < num; i++) {
pmsg = &msgs[i];
/* Send restart for subsequent messages */
if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) {
rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
if (rc < 0) {
printf("restart cmd failed rc = %d\n", rc);
goto xfer_send_stop;
}
}
/* Send slave address */
if (!(pmsg->flags & I2C_M_NOSTART)) {
rc = bcm_kona_i2c_do_addr(dev, pmsg);
if (rc < 0) {
debug("NAK from addr %2.2x msg#%d rc = %d\n",
pmsg->addr, i, rc);
goto xfer_send_stop;
}
}
/* Perform data transfer */
if (pmsg->flags & I2C_M_RD) {
rc = bcm_kona_i2c_read_fifo(dev, pmsg);
if (rc < 0) {
printf("read failure\n");
goto xfer_send_stop;
}
} else {
rc = bcm_kona_i2c_write_fifo(dev, pmsg);
if (rc < 0) {
printf("write failure");
goto xfer_send_stop;
}
}
}
rc = num;
xfer_send_stop:
/* Send a STOP command */
bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP);
xfer_disable_pad:
/* Disable pad output */
writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
/* Stop internal clock */
bcm_kona_i2c_disable_clock(dev);
return rc;
}
static uint bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev,
uint speed)
{
switch (speed) {
case I2C_SPEED_STANDARD_RATE:
dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_STANDARD];
break;
case I2C_SPEED_FAST_RATE:
dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_FAST];
break;
case I2C_SPEED_FAST_PLUS_RATE:
dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_FAST_PLUS];
break;
default:
printf("%d hz bus speed not supported\n", speed);
return -EINVAL;
}
dev->speed = speed;
return 0;
}
static void bcm_kona_i2c_init(struct bcm_kona_i2c_dev *dev)
{
/* Parse bus speed */
bcm_kona_i2c_assign_bus_speed(dev, dev->speed);
/* Enable internal clocks */
bcm_kona_i2c_enable_clock(dev);
/* Configure internal dividers */
bcm_kona_i2c_config_timing(dev);
/* Disable timeout */
writel(0, dev->base + TOUT_OFFSET);
/* Enable autosense */
bcm_kona_i2c_enable_autosense(dev);
/* Enable TX FIFO */
writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
dev->base + TXFCR_OFFSET);
/* Mask all interrupts */
writel(0, dev->base + IER_OFFSET);
/* Clear all pending interrupts */
writel(ISR_CMDBUSY_MASK |
ISR_READ_COMPLETE_MASK |
ISR_SES_DONE_MASK |
ISR_ERR_MASK |
ISR_TXFIFOEMPTY_MASK | ISR_NOACK_MASK, dev->base + ISR_OFFSET);
/* Enable the controller but leave it idle */
bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
/* Disable pad output */
writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
}
/*
* uboot layer
*/
struct bcm_kona_i2c_dev *kona_get_dev(struct i2c_adapter *adap)
{
return &g_i2c_devs[adap->hwadapnr];
}
static void kona_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
if (clk_bsc_enable(dev->base))
return;
bcm_kona_i2c_init(dev);
}
static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
int alen, uchar *buffer, int len)
{
/* msg[0] writes the addr, msg[1] reads the data */
struct kona_i2c_msg msg[2];
unsigned char msgbuf0[64];
struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
msg[0].addr = chip;
msg[0].flags = 0;
msg[0].len = 1;
msg[0].buf = msgbuf0; /* msgbuf0 contains incrementing reg addr */
msg[1].addr = chip;
msg[1].flags = I2C_M_RD;
/* msg[1].buf dest ptr increments each read */
msgbuf0[0] = (unsigned char)addr;
msg[1].buf = buffer;
msg[1].len = len;
if (bcm_kona_i2c_xfer(dev, msg, 2) < 0) {
/* Sending 2 i2c messages */
kona_i2c_init(adap, adap->speed, adap->slaveaddr);
debug("I2C read: I/O error\n");
return -EIO;
}
return 0;
}
static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
int alen, uchar *buffer, int len)
{
struct kona_i2c_msg msg[1];
unsigned char msgbuf0[64];
unsigned int i;
struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
msg[0].addr = chip;
msg[0].flags = 0;
msg[0].len = 2; /* addr byte plus data */
msg[0].buf = msgbuf0;
for (i = 0; i < len; i++) {
msgbuf0[0] = addr++;
msgbuf0[1] = buffer[i];
if (bcm_kona_i2c_xfer(dev, msg, 1) < 0) {
kona_i2c_init(adap, adap->speed, adap->slaveaddr);
debug("I2C write: I/O error\n");
return -EIO;
}
}
return 0;
}
static int kona_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
uchar tmp;
/*
* read addr 0x0 of the given chip.
*/
return kona_i2c_read(adap, chip, 0x0, 1, &tmp, 1);
}
static uint kona_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
{
struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
return bcm_kona_i2c_assign_bus_speed(dev, speed);
}
/*
* Register kona i2c adapters. Keep the order below so
* that the bus number matches the adapter number.
*/
#define DEF_ADAPTER(num) \
U_BOOT_I2C_ADAP_COMPLETE(kona##num, kona_i2c_init, kona_i2c_probe, \
kona_i2c_read, kona_i2c_write, \
kona_i2c_set_bus_speed, DEF_SPD, 0x00, num)
#ifdef CONFIG_SYS_I2C_BASE0
DEF_ADAPTER(0)
#endif
#ifdef CONFIG_SYS_I2C_BASE1
DEF_ADAPTER(1)
#endif
#ifdef CONFIG_SYS_I2C_BASE2
DEF_ADAPTER(2)
#endif
#ifdef CONFIG_SYS_I2C_BASE3
DEF_ADAPTER(3)
#endif
#ifdef CONFIG_SYS_I2C_BASE4
DEF_ADAPTER(4)
#endif
#ifdef CONFIG_SYS_I2C_BASE5
DEF_ADAPTER(5)
#endif

5
drivers/i2c/sh_i2c.c
View file

@ -172,14 +172,9 @@ static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr)
{
int ret = -1;
#if defined(CONFIG_SH73A0)
if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
goto exit0;
#else
if (sh_i2c_set_addr(dev, chip, addr, 1) != 0)
goto exit0;
udelay(100);
#endif
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
sh_irq_dte(dev);

2
drivers/misc/Makefile
View file

@ -29,7 +29,6 @@ ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SANDBOX) += spltest_sandbox.o
endif
endif
obj-$(CONFIG_ALI152X) += ali512x.o
obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o
obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o
obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
@ -37,7 +36,6 @@ obj-$(CONFIG_DS4510) += ds4510.o
obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
obj-$(CONFIG_FSL_IIM) += fsl_iim.o
obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
obj-$(CONFIG_$(SPL_)FS_LOADER) += fs_loader.o
obj-$(CONFIG_GATEWORKS_SC) += gsc.o

401
drivers/misc/ali512x.c
View file

@ -1,401 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
*/
/*
* Based on sc520cdp.c from rolo 1.6:
*----------------------------------------------------------------------
* (C) Copyright 2000
* Sysgo Real-Time Solutions GmbH
* Klein-Winternheim, Germany
*----------------------------------------------------------------------
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <ali512x.h>
/* ALI M5123 Logical device numbers:
* 0 FDC
* 1 unused?
* 2 unused?
* 3 lpt
* 4 UART1
* 5 UART2
* 6 RTC
* 7 mouse/kbd
* 8 CIO
*/
/*
************************************************************
* Some access primitives for the ALi chip: *
************************************************************
*/
static void ali_write(u8 index, u8 value)
{
/* write an arbirary register */
outb(index, ALI_INDEX);
outb(value, ALI_DATA);
}
#if 0
static int ali_read(u8 index)
{
outb(index, ALI_INDEX);
return inb(ALI_DATA);
}
#endif
#define ALI_OPEN() \
outb(0x51, ALI_INDEX); \
outb(0x23, ALI_INDEX)
#define ALI_CLOSE() \
outb(0xbb, ALI_INDEX)
/* Select a logical device */
#define ALI_SELDEV(dev) \
ali_write(0x07, dev)
void ali512x_init(void)
{
ALI_OPEN();
ali_write(0x02, 0x01); /* soft reset */
ali_write(0x03, 0x03); /* disable access to CIOs */
ali_write(0x22, 0x00); /* disable direct powerdown */
ali_write(0x23, 0x00); /* disable auto powerdown */
ali_write(0x24, 0x00); /* IR 8 is active hi, pin26 is PDIR */
ALI_CLOSE();
}
void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel)
{
ALI_OPEN();
ALI_SELDEV(0);
ali_write(0x30, enabled?1:0);
if (enabled) {
ali_write(0x60, io >> 8);
ali_write(0x61, io & 0xff);
ali_write(0x70, irq);
ali_write(0x74, dma_channel);
/* AT mode, no drive swap */
ali_write(0xf0, 0x08);
ali_write(0xf1, 0x00);
ali_write(0xf2, 0xff);
ali_write(0xf4, 0x00);
}
ALI_CLOSE();
}
void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel)
{
ALI_OPEN();
ALI_SELDEV(3);
ali_write(0x30, enabled?1:0);
if (enabled) {
ali_write(0x60, io >> 8);
ali_write(0x61, io & 0xff);
ali_write(0x70, irq);
ali_write(0x74, dma_channel);
/* mode: EPP 1.9, ECP FIFO threshold = 7, IRQ active low */
ali_write(0xf0, 0xbc);
/* 12 MHz, Burst DMA in ECP */
ali_write(0xf1, 0x05);
}
ALI_CLOSE();
}
void ali512x_set_uart(int enabled, int index, u16 io, u8 irq)
{
ALI_OPEN();
ALI_SELDEV(index?5:4);
ali_write(0x30, enabled?1:0);
if (enabled) {
ali_write(0x60, io >> 8);
ali_write(0x61, io & 0xff);
ali_write(0x70, irq);
ali_write(0xf0, 0x00);
ali_write(0xf1, 0x00);
/* huh? write 0xf2 twice - a typo in rolo
* or some secret ali errata? Who knows?
*/
if (index) {
ali_write(0xf2, 0x00);
}
ali_write(0xf2, 0x0c);
}
ALI_CLOSE();
}
void ali512x_set_uart2_irda(int enabled)
{
ALI_OPEN();
ALI_SELDEV(5);
ali_write(0xf1, enabled?0x48:0x00); /* fullduplex IrDa */
ALI_CLOSE();
}
void ali512x_set_rtc(int enabled, u16 io, u8 irq)
{
ALI_OPEN();
ALI_SELDEV(6);
ali_write(0x30, enabled?1:0);
if (enabled) {
ali_write(0x60, io >> 8);
ali_write(0x61, io & 0xff);
ali_write(0x70, irq);
ali_write(0xf0, 0x00);
}
ALI_CLOSE();
}
void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq)
{
ALI_OPEN();
ALI_SELDEV(7);
ali_write(0x30, enabled?1:0);
if (enabled) {
ali_write(0x70, kbc_irq);
ali_write(0x72, mouse_irq);
ali_write(0xf0, 0x00);
}
ALI_CLOSE();
}
/* Common I/O
*
* (This descripotsion is base on several incompete sources
* since I have not been able to obtain any datasheet for the device
* there may be some mis-understandings burried in here.
* -- Daniel daniel@omicron.se)
*
* There are 22 CIO pins numbered
* 10-17
* 20-25
* 30-37
*
* 20-24 are dedicated CIO pins, the other 17 are muliplexed with
* other functions.
*
* Secondary
* CIO Pin Function Decription
* =======================================================
* CIO10 IRQIN1 Interrupt input 1?
* CIO11 IRQIN2 Interrupt input 2?
* CIO12 IRRX IrDa Receive
* CIO13 IRTX IrDa Transmit
* CIO14 P21 KBC P21 fucntion
* CIO15 P20 KBC P21 fucntion
* CIO16 I2C_CLK I2C Clock
* CIO17 I2C_DAT I2C Data
*
* CIO20 -
* CIO21 -
* CIO22 -
* CIO23 -
* CIO24 -
* CIO25 LOCK Keylock
*
* CIO30 KBC_CLK Keybaord Clock
* CIO31 CS0J General Chip Select decoder CS0J
* CIO32 CS1J General Chip Select decoder CS1J
* CIO33 ALT_KCLK Alternative Keyboard Clock
* CIO34 ALT_KDAT Alternative Keyboard Data
* CIO35 ALT_MCLK Alternative Mouse Clock
* CIO36 ALT_MDAT Alternative Mouse Data
* CIO37 ALT_KBC Alternative KBC select
*
* The CIO use an indirect address scheme.
*
* Reigster 3 in the SIO is used to select the index and data
* port addresses where the CIO I/O registers show up.
* The function selection registers are accessible under
* function SIO 8.
*
* SIO reigster 3 (CIO Address Selection) bit definitions:
* bit 7 CIO index and data registers enabled
* bit 1-0 CIO indirect registers port address select
* 0 index = 0xE0 data = 0xE1
* 1 index = 0xE2 data = 0xE3
* 2 index = 0xE4 data = 0xE5
* 3 index = 0xEA data = 0xEB
*
* There are three CIO I/O register accessed via CIO index port and CIO data port
* 0x01 CIO 10-17 data
* 0x02 CIO 20-25 data (bits 7-6 unused)
* 0x03 CIO 30-37 data
*
*
* The pin function is accessed through normal
* SIO registers, each register have the same format:
*
* Bit Function Value
* 0 Input/output 1=input
* 1 Polarity of signal 1=inverted
* 2 Unused ??
* 3 Function (normal or special) 1=special
* 7-4 Unused
*
* SIO REG
* 0xe0 CIO 10 Config
* 0xe1 CIO 11 Config
* 0xe2 CIO 12 Config
* 0xe3 CIO 13 Config
* 0xe4 CIO 14 Config
* 0xe5 CIO 15 Config
* 0xe6 CIO 16 Config
* 0xe7 CIO 16 Config
*
* 0xe8 CIO 20 Config
* 0xe9 CIO 21 Config
* 0xea CIO 22 Config
* 0xeb CIO 23 Config
* 0xec CIO 24 Config
* 0xed CIO 25 Config
*
* 0xf5 CIO 30 Config
* 0xf6 CIO 31 Config
* 0xf7 CIO 32 Config
* 0xf8 CIO 33 Config
* 0xf9 CIO 34 Config
* 0xfa CIO 35 Config
* 0xfb CIO 36 Config
* 0xfc CIO 37 Config
*
*/
#define ALI_CIO_PORT_SEL 0x83
#define ALI_CIO_INDEX 0xea
#define ALI_CIO_DATA 0xeb
void ali512x_set_cio(int enabled)
{
int i;
ALI_OPEN();
if (enabled) {
ali_write(0x3, ALI_CIO_PORT_SEL); /* Enable CIO data register */
} else {
ali_write(0x3, ALI_CIO_PORT_SEL & ~0x80);
}
ALI_SELDEV(8);
ali_write(0x30, enabled?1:0);
/* set all pins to input to start with */
for (i=0xe0;i<0xee;i++) {
ali_write(i, 1);
}
for (i=0xf5;i<0xfe;i++) {
ali_write(i, 1);
}
ALI_CLOSE();
}
void ali512x_cio_function(int pin, int special, int inv, int input)
{
u8 data;
u8 addr;
/* valid pins are 10-17, 20-25 and 30-37 */
if (pin >= 10 && pin <= 17) {
addr = 0xe0+(pin&7);
} else if (pin >= 20 && pin <= 25) {
addr = 0xe8+(pin&7);
} else if (pin >= 30 && pin <= 37) {
addr = 0xf5+(pin&7);
} else {
return;
}
ALI_OPEN();
ALI_SELDEV(8);
data=0xf4;
if (special) {
data |= 0x08;
} else {
if (inv) {
data |= 0x02;
}
if (input) {
data |= 0x01;
}
}
ali_write(addr, data);
ALI_CLOSE();
}
void ali512x_cio_out(int pin, int value)
{
u8 reg;
u8 data;
u8 bit;
reg = pin/10;
bit = 1 << (pin%10);
outb(reg, ALI_CIO_INDEX); /* select I/O register */
data = inb(ALI_CIO_DATA);
if (value) {
data |= bit;
} else {
data &= ~bit;
}
outb(data, ALI_CIO_DATA);
}
int ali512x_cio_in(int pin)
{
u8 reg;
u8 data;
u8 bit;
/* valid pins are 10-17, 20-25 and 30-37 */
reg = pin/10;
bit = 1 << (pin%10);
outb(reg, ALI_CIO_INDEX); /* select I/O register */
data = inb(ALI_CIO_DATA);
return data & bit;
}

34
drivers/misc/mc9sdz60.c
View file

@ -1,34 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010 Stefano Babic <sbabic@denx.de>
*/
#include <config.h>
#include <common.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <i2c.h>
#include <mc9sdz60.h>
#ifndef CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR
#error "You have to configure I2C address for MC9SDZ60"
#endif
u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg)
{
u8 val;
if (i2c_read(CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR, reg, 1, &val, 1)) {
puts("Error reading MC9SDZ60 register\n");
return -1;
}
return val;
}
void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val)
{
i2c_write(CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR, reg, 1, &val, 1);
}

4
drivers/mtd/nand/raw/Makefile
View file

@ -56,8 +56,6 @@ obj-$(CONFIG_NAND_DENALI) += denali.o
obj-$(CONFIG_NAND_DENALI_DT) += denali_dt.o
obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
obj-$(CONFIG_NAND_FSMC) += fsmc_nand.o
obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
@ -70,11 +68,9 @@ obj-$(CONFIG_NAND_MXS_DT) += mxs_nand_dt.o
obj-$(CONFIG_NAND_OCTEONTX) += octeontx_nand.o
obj-$(CONFIG_NAND_OCTEONTX_HW_ECC) += octeontx_bch.o
obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o
obj-$(CONFIG_NAND_SPEAR) += spr_nand.o
obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
obj-$(CONFIG_NAND_PLAT) += nand_plat.o
obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o
obj-$(CONFIG_NAND_MXIC) += mxic_nand.o
obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o

187
drivers/mtd/nand/raw/fsl_upm.c
View file

@ -1,187 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* FSL UPM NAND driver
*
* Copyright (C) 2007 MontaVista Software, Inc.
* Anton Vorontsov <avorontsov@ru.mvista.com>
*/
#include <config.h>
#include <common.h>
#include <log.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/fsl_upm.h>
#include <nand.h>
static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
{
clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset);
(void)in_be32(upm->mxmr);
}
static void fsl_upm_end_pattern(struct fsl_upm *upm)
{
clrbits_be32(upm->mxmr, MxMR_OP_RUNP);
while (in_be32(upm->mxmr) & MxMR_OP_RUNP)
eieio();
}
static void fsl_upm_run_pattern(struct fsl_upm *upm, int width,
void __iomem *io_addr, u32 mar)
{
out_be32(upm->mar, mar);
(void)in_be32(upm->mar);
switch (width) {
case 8:
out_8(io_addr, 0x0);
break;
case 16:
out_be16(io_addr, 0x0);
break;
case 32:
out_be32(io_addr, 0x0);
break;
}
}
static void fun_wait(struct fsl_upm_nand *fun)
{
if (fun->dev_ready) {
while (!fun->dev_ready(fun->chip_nr))
debug("unexpected busy state\n");
} else {
/*
* If the R/B pin is not connected,
* a short delay is necessary.
*/
udelay(1);
}
}
#if CONFIG_SYS_NAND_MAX_CHIPS > 1
static void fun_select_chip(struct mtd_info *mtd, int chip_nr)
{
struct nand_chip *chip = mtd_to_nand(mtd);
struct fsl_upm_nand *fun = nand_get_controller_data(chip);
if (chip_nr >= 0) {
fun->chip_nr = chip_nr;
chip->IO_ADDR_R = chip->IO_ADDR_W =
fun->upm.io_addr + fun->chip_offset * chip_nr;
} else if (chip_nr == -1) {
chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
}
}
#endif
static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *chip = mtd_to_nand(mtd);
struct fsl_upm_nand *fun = nand_get_controller_data(chip);
void __iomem *io_addr;
u32 mar;
if (!(ctrl & fun->last_ctrl)) {
fsl_upm_end_pattern(&fun->upm);
if (cmd == NAND_CMD_NONE)
return;
fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
}
if (ctrl & NAND_CTRL_CHANGE) {
if (ctrl & NAND_ALE)
fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
else if (ctrl & NAND_CLE)
fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
}
mar = cmd << (32 - fun->width);
io_addr = fun->upm.io_addr;
#if CONFIG_SYS_NAND_MAX_CHIPS > 1
if (fun->chip_nr > 0) {
io_addr += fun->chip_offset * fun->chip_nr;
if (fun->upm_mar_chip_offset)
mar |= fun->upm_mar_chip_offset * fun->chip_nr;
}
#endif
fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar);
/*
* Some boards/chips needs this. At least the MPC8360E-RDK
* needs it. Probably weird chip, because I don't see any
* need for this on MPC8555E + Samsung K9F1G08U0A. Usually
* here are 0-2 unexpected busy states per block read.
*/
if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
fun_wait(fun);
}
static u8 upm_nand_read_byte(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd_to_nand(mtd);
return in_8(chip->IO_ADDR_R);
}
static void upm_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
int i;
struct nand_chip *chip = mtd_to_nand(mtd);
struct fsl_upm_nand *fun = nand_get_controller_data(chip);
for (i = 0; i < len; i++) {
out_8(chip->IO_ADDR_W, buf[i]);
if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
fun_wait(fun);
}
if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
fun_wait(fun);
}
static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
int i;
struct nand_chip *chip = mtd_to_nand(mtd);
for (i = 0; i < len; i++)
buf[i] = in_8(chip->IO_ADDR_R);
}
static int nand_dev_ready(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd_to_nand(mtd);
struct fsl_upm_nand *fun = nand_get_controller_data(chip);
return fun->dev_ready(fun->chip_nr);
}
int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
{
if (fun->width != 8 && fun->width != 16 && fun->width != 32)
return -ENOSYS;
fun->last_ctrl = NAND_CLE;
nand_set_controller_data(chip, fun);
chip->chip_delay = fun->chip_delay;
chip->ecc.mode = NAND_ECC_SOFT;
chip->cmd_ctrl = fun_cmd_ctrl;
#if CONFIG_SYS_NAND_MAX_CHIPS > 1
chip->select_chip = fun_select_chip;
#endif
chip->read_byte = upm_nand_read_byte;
chip->read_buf = upm_nand_read_buf;
chip->write_buf = upm_nand_write_buf;
if (fun->dev_ready)
chip->dev_ready = nand_dev_ready;
return 0;
}

470
drivers/mtd/nand/raw/fsmc_nand.c
View file

@ -1,470 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
*
* (C) Copyright 2012
* Amit Virdi, STMicroelectronics, amit.virdi@st.com.
*/
#include <common.h>
#include <nand.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/fsmc_nand.h>
#include <asm/arch/hardware.h>
static u32 fsmc_version;
static struct fsmc_regs *const fsmc_regs_p = (struct fsmc_regs *)
CONFIG_SYS_FSMC_BASE;
/*
* ECC4 and ECC1 have 13 bytes and 3 bytes of ecc respectively for 512 bytes of
* data. ECC4 can correct up to 8 bits in 512 bytes of data while ECC1 can
* correct 1 bit in 512 bytes
*/
static struct nand_ecclayout fsmc_ecc4_lp_layout = {
.eccbytes = 104,
.eccpos = { 2, 3, 4, 5, 6, 7, 8,
9, 10, 11, 12, 13, 14,
18, 19, 20, 21, 22, 23, 24,
25, 26, 27, 28, 29, 30,
34, 35, 36, 37, 38, 39, 40,
41, 42, 43, 44, 45, 46,
50, 51, 52, 53, 54, 55, 56,
57, 58, 59, 60, 61, 62,
66, 67, 68, 69, 70, 71, 72,
73, 74, 75, 76, 77, 78,
82, 83, 84, 85, 86, 87, 88,
89, 90, 91, 92, 93, 94,
98, 99, 100, 101, 102, 103, 104,
105, 106, 107, 108, 109, 110,
114, 115, 116, 117, 118, 119, 120,
121, 122, 123, 124, 125, 126
},
.oobfree = {
{.offset = 15, .length = 3},
{.offset = 31, .length = 3},
{.offset = 47, .length = 3},
{.offset = 63, .length = 3},
{.offset = 79, .length = 3},
{.offset = 95, .length = 3},
{.offset = 111, .length = 3},
{.offset = 127, .length = 1}
}
};
/*
* ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
* of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
* bytes are free for use.
*/
static struct nand_ecclayout fsmc_ecc4_224_layout = {
.eccbytes = 104,
.eccpos = { 2, 3, 4, 5, 6, 7, 8,
9, 10, 11, 12, 13, 14,
18, 19, 20, 21, 22, 23, 24,
25, 26, 27, 28, 29, 30,
34, 35, 36, 37, 38, 39, 40,
41, 42, 43, 44, 45, 46,
50, 51, 52, 53, 54, 55, 56,
57, 58, 59, 60, 61, 62,
66, 67, 68, 69, 70, 71, 72,
73, 74, 75, 76, 77, 78,
82, 83, 84, 85, 86, 87, 88,
89, 90, 91, 92, 93, 94,
98, 99, 100, 101, 102, 103, 104,
105, 106, 107, 108, 109, 110,
114, 115, 116, 117, 118, 119, 120,
121, 122, 123, 124, 125, 126
},
.oobfree = {
{.offset = 15, .length = 3},
{.offset = 31, .length = 3},
{.offset = 47, .length = 3},
{.offset = 63, .length = 3},
{.offset = 79, .length = 3},
{.offset = 95, .length = 3},
{.offset = 111, .length = 3},
{.offset = 127, .length = 97}
}
};
/*
* ECC placement definitions in oobfree type format
* There are 13 bytes of ecc for every 512 byte block and it has to be read
* consecutively and immediately after the 512 byte data block for hardware to
* generate the error bit offsets in 512 byte data
* Managing the ecc bytes in the following way makes it easier for software to
* read ecc bytes consecutive to data bytes. This way is similar to
* oobfree structure maintained already in u-boot nand driver
*/
static struct fsmc_eccplace fsmc_eccpl_lp = {
.eccplace = {
{.offset = 2, .length = 13},
{.offset = 18, .length = 13},
{.offset = 34, .length = 13},
{.offset = 50, .length = 13},
{.offset = 66, .length = 13},
{.offset = 82, .length = 13},
{.offset = 98, .length = 13},
{.offset = 114, .length = 13}
}
};
static struct nand_ecclayout fsmc_ecc4_sp_layout = {
.eccbytes = 13,
.eccpos = { 0, 1, 2, 3, 6, 7, 8,
9, 10, 11, 12, 13, 14
},
.oobfree = {
{.offset = 15, .length = 1},
}
};
static struct fsmc_eccplace fsmc_eccpl_sp = {
.eccplace = {
{.offset = 0, .length = 4},
{.offset = 6, .length = 9}
}
};
static struct nand_ecclayout fsmc_ecc1_layout = {
.eccbytes = 24,
.eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
.oobfree = {
{.offset = 8, .length = 8},
{.offset = 24, .length = 8},
{.offset = 40, .length = 8},
{.offset = 56, .length = 8},
{.offset = 72, .length = 8},
{.offset = 88, .length = 8},
{.offset = 104, .length = 8},
{.offset = 120, .length = 8}
}
};
/* Count the number of 0's in buff upto a max of max_bits */
static int count_written_bits(uint8_t *buff, int size, int max_bits)
{
int k, written_bits = 0;
for (k = 0; k < size; k++) {
written_bits += hweight8(~buff[k]);
if (written_bits > max_bits)
break;
}
return written_bits;
}
static void fsmc_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
{
struct nand_chip *this = mtd_to_nand(mtd);
ulong IO_ADDR_W;
if (ctrl & NAND_CTRL_CHANGE) {
IO_ADDR_W = (ulong)this->IO_ADDR_W;
IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE);
if (ctrl & NAND_CLE)
IO_ADDR_W |= CONFIG_SYS_NAND_CLE;
if (ctrl & NAND_ALE)
IO_ADDR_W |= CONFIG_SYS_NAND_ALE;
if (ctrl & NAND_NCE) {
writel(readl(&fsmc_regs_p->pc) |
FSMC_ENABLE, &fsmc_regs_p->pc);
} else {
writel(readl(&fsmc_regs_p->pc) &
~FSMC_ENABLE, &fsmc_regs_p->pc);
}
this->IO_ADDR_W = (void *)IO_ADDR_W;
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
static int fsmc_bch8_correct_data(struct mtd_info *mtd, u_char *dat,
u_char *read_ecc, u_char *calc_ecc)
{
/* The calculated ecc is actually the correction index in data */
u32 err_idx[8];
u32 num_err, i;
u32 ecc1, ecc2, ecc3, ecc4;
num_err = (readl(&fsmc_regs_p->sts) >> 10) & 0xF;
if (likely(num_err == 0))
return 0;
if (unlikely(num_err > 8)) {
/*
* This is a temporary erase check. A newly erased page read
* would result in an ecc error because the oob data is also
* erased to FF and the calculated ecc for an FF data is not
* FF..FF.
* This is a workaround to skip performing correction in case
* data is FF..FF
*
* Logic:
* For every page, each bit written as 0 is counted until these
* number of bits are greater than 8 (the maximum correction
* capability of FSMC for each 512 + 13 bytes)
*/
int bits_ecc = count_written_bits(read_ecc, 13, 8);
int bits_data = count_written_bits(dat, 512, 8);
if ((bits_ecc + bits_data) <= 8) {
if (bits_data)
memset(dat, 0xff, 512);
return bits_data + bits_ecc;
}
return -EBADMSG;
}
ecc1 = readl(&fsmc_regs_p->ecc1);
ecc2 = readl(&fsmc_regs_p->ecc2);
ecc3 = readl(&fsmc_regs_p->ecc3);
ecc4 = readl(&fsmc_regs_p->sts);
err_idx[0] = (ecc1 >> 0) & 0x1FFF;
err_idx[1] = (ecc1 >> 13) & 0x1FFF;
err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
err_idx[3] = (ecc2 >> 7) & 0x1FFF;
err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
err_idx[5] = (ecc3 >> 1) & 0x1FFF;
err_idx[6] = (ecc3 >> 14) & 0x1FFF;
err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
i = 0;
while (i < num_err) {
err_idx[i] ^= 3;
if (err_idx[i] < 512 * 8)
__change_bit(err_idx[i], dat);
i++;
}
return num_err;
}
static int fsmc_read_hwecc(struct mtd_info *mtd,
const u_char *data, u_char *ecc)
{
u_int ecc_tmp;
int timeout = CONFIG_SYS_HZ;
ulong start;
switch (fsmc_version) {
case FSMC_VER8:
start = get_timer(0);
while (get_timer(start) < timeout) {
/*
* Busy waiting for ecc computation
* to finish for 512 bytes
*/
if (readl(&fsmc_regs_p->sts) & FSMC_CODE_RDY)
break;
}
ecc_tmp = readl(&fsmc_regs_p->ecc1);
ecc[0] = (u_char) (ecc_tmp >> 0);
ecc[1] = (u_char) (ecc_tmp >> 8);
ecc[2] = (u_char) (ecc_tmp >> 16);
ecc[3] = (u_char) (ecc_tmp >> 24);
ecc_tmp = readl(&fsmc_regs_p->ecc2);
ecc[4] = (u_char) (ecc_tmp >> 0);
ecc[5] = (u_char) (ecc_tmp >> 8);
ecc[6] = (u_char) (ecc_tmp >> 16);
ecc[7] = (u_char) (ecc_tmp >> 24);
ecc_tmp = readl(&fsmc_regs_p->ecc3);
ecc[8] = (u_char) (ecc_tmp >> 0);
ecc[9] = (u_char) (ecc_tmp >> 8);
ecc[10] = (u_char) (ecc_tmp >> 16);
ecc[11] = (u_char) (ecc_tmp >> 24);
ecc_tmp = readl(&fsmc_regs_p->sts);
ecc[12] = (u_char) (ecc_tmp >> 16);
break;
default:
ecc_tmp = readl(&fsmc_regs_p->ecc1);
ecc[0] = (u_char) (ecc_tmp >> 0);
ecc[1] = (u_char) (ecc_tmp >> 8);
ecc[2] = (u_char) (ecc_tmp >> 16);
break;
}
return 0;
}
void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
{
writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCPLEN_256,
&fsmc_regs_p->pc);
writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCEN,
&fsmc_regs_p->pc);
writel(readl(&fsmc_regs_p->pc) | FSMC_ECCEN,
&fsmc_regs_p->pc);
}
/*
* fsmc_read_page_hwecc
* @mtd: mtd info structure
* @chip: nand chip info structure
* @buf: buffer to store read data
* @oob_required: caller expects OOB data read to chip->oob_poi
* @page: page number to read
*
* This routine is needed for fsmc verison 8 as reading from NAND chip has to be
* performed in a strict sequence as follows:
* data(512 byte) -> ecc(13 byte)
* After this read, fsmc hardware generates and reports error data bits(upto a
* max of 8 bits)
*/
static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
uint8_t *buf, int oob_required, int page)
{
struct fsmc_eccplace *fsmc_eccpl;
int i, j, s, stat, eccsize = chip->ecc.size;
int eccbytes = chip->ecc.bytes;
int eccsteps = chip->ecc.steps;
uint8_t *p = buf;
uint8_t *ecc_calc = chip->buffers->ecccalc;
uint8_t *ecc_code = chip->buffers->ecccode;
int off, len, group = 0;
uint8_t oob[13] __attribute__ ((aligned (2)));
/* Differentiate between small and large page ecc place definitions */
if (mtd->writesize == 512)
fsmc_eccpl = &fsmc_eccpl_sp;
else
fsmc_eccpl = &fsmc_eccpl_lp;
for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
chip->ecc.hwctl(mtd, NAND_ECC_READ);
chip->read_buf(mtd, p, eccsize);
for (j = 0; j < eccbytes;) {
off = fsmc_eccpl->eccplace[group].offset;
len = fsmc_eccpl->eccplace[group].length;
group++;
/*
* length is intentionally kept a higher multiple of 2
* to read at least 13 bytes even in case of 16 bit NAND
* devices
*/
if (chip->options & NAND_BUSWIDTH_16)
len = roundup(len, 2);
chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
chip->read_buf(mtd, oob + j, len);
j += len;
}
memcpy(&ecc_code[i], oob, 13);
chip->ecc.calculate(mtd, p, &ecc_calc[i]);
stat = chip->ecc.correct(mtd, p, &ecc_code[i],
&ecc_calc[i]);
if (stat < 0)
mtd->ecc_stats.failed++;
else
mtd->ecc_stats.corrected += stat;
}
return 0;
}
int fsmc_nand_init(struct nand_chip *nand)
{
static int chip_nr;
struct mtd_info *mtd;
u32 peripid2 = readl(&fsmc_regs_p->peripid2);
fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) &
FSMC_REVISION_MSK;
writel(readl(&fsmc_regs_p->ctrl) | FSMC_WP, &fsmc_regs_p->ctrl);
#if defined(CONFIG_SYS_FSMC_NAND_16BIT)
writel(FSMC_DEVWID_16 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON,
&fsmc_regs_p->pc);
#elif defined(CONFIG_SYS_FSMC_NAND_8BIT)
writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON,
&fsmc_regs_p->pc);
#else
#error Please define CONFIG_SYS_FSMC_NAND_16BIT or CONFIG_SYS_FSMC_NAND_8BIT
#endif
writel(readl(&fsmc_regs_p->pc) | FSMC_TCLR_1 | FSMC_TAR_1,
&fsmc_regs_p->pc);
writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
&fsmc_regs_p->comm);
writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
&fsmc_regs_p->attrib);
nand->options = 0;
#if defined(CONFIG_SYS_FSMC_NAND_16BIT)
nand->options |= NAND_BUSWIDTH_16;
#endif
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.size = 512;
nand->ecc.calculate = fsmc_read_hwecc;
nand->ecc.hwctl = fsmc_enable_hwecc;
nand->cmd_ctrl = fsmc_nand_hwcontrol;
nand->IO_ADDR_R = nand->IO_ADDR_W =
(void __iomem *)CFG_SYS_NAND_BASE;
nand->badblockbits = 7;
mtd = nand_to_mtd(nand);
switch (fsmc_version) {
case FSMC_VER8:
nand->ecc.bytes = 13;
nand->ecc.strength = 8;
nand->ecc.correct = fsmc_bch8_correct_data;
nand->ecc.read_page = fsmc_read_page_hwecc;
if (mtd->writesize == 512)
nand->ecc.layout = &fsmc_ecc4_sp_layout;
else {
if (mtd->oobsize == 224)
nand->ecc.layout = &fsmc_ecc4_224_layout;
else
nand->ecc.layout = &fsmc_ecc4_lp_layout;
}
break;
default:
nand->ecc.bytes = 3;
nand->ecc.strength = 1;
nand->ecc.layout = &fsmc_ecc1_layout;
nand->ecc.correct = nand_correct_data;
break;
}
/* Detect NAND chips */
if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL))
return -ENXIO;
if (nand_scan_tail(mtd))
return -ENXIO;
if (nand_register(chip_nr++, mtd))
return -ENXIO;
return 0;
}

65
drivers/mtd/nand/raw/nand_plat.c
View file

@ -1,65 +0,0 @@
/*
* Genericish driver for memory mapped NAND devices
*
* Copyright (c) 2006-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
/* Your board must implement the following macros:
* NAND_PLAT_WRITE_CMD(chip, cmd)
* NAND_PLAT_WRITE_ADR(chip, cmd)
* NAND_PLAT_INIT()
*
* It may also implement the following:
* NAND_PLAT_DEV_READY(chip)
*/
#include <common.h>
#include <linux/mtd/rawnand.h>
#include <asm/io.h>
#ifdef NAND_PLAT_GPIO_DEV_READY
# include <asm/gpio.h>
# define NAND_PLAT_DEV_READY(chip) gpio_get_value(NAND_PLAT_GPIO_DEV_READY)
#endif
#include <nand.h>
static void plat_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd_to_nand(mtd);
if (cmd == NAND_CMD_NONE)
return;
if (ctrl & NAND_CLE)
NAND_PLAT_WRITE_CMD(this, cmd);
else
NAND_PLAT_WRITE_ADR(this, cmd);
}
#ifdef NAND_PLAT_DEV_READY
static int plat_dev_ready(struct mtd_info *mtd)
{
return NAND_PLAT_DEV_READY((struct nand_chip *)mtd_to_nand(mtd));
}
#else
# define plat_dev_ready NULL
#endif
int board_nand_init(struct nand_chip *nand)
{
#ifdef NAND_PLAT_GPIO_DEV_READY
gpio_request(NAND_PLAT_GPIO_DEV_READY, "nand-plat");
gpio_direction_input(NAND_PLAT_GPIO_DEV_READY);
#endif
#ifdef NAND_PLAT_INIT
NAND_PLAT_INIT();
#endif
nand->cmd_ctrl = plat_cmd_ctrl;
nand->dev_ready = plat_dev_ready;
nand->ecc.mode = NAND_ECC_SOFT;
return 0;
}

1
drivers/pci/Makefile
View file

@ -22,7 +22,6 @@ obj-$(CONFIG_PCI_MVEBU) += pci_mvebu.o
obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
obj-$(CONFIG_PCI_RCAR_GEN3) += pci-rcar-gen3.o
obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
obj-$(CONFIG_PCIE_IPROC) += pcie_iproc.o
obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o

92
drivers/pci/pci_sh7780.c
View file

@ -1,92 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* SH7780 PCI Controller (PCIC) for U-Boot.
* (C) Dustin McIntire (dustin@sensoria.com)
* (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
*/
#include <common.h>
#include <linux/delay.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/pci.h>
#include <asm/io.h>
#define SH7780_VENDOR_ID 0x1912
#define SH7780_DEVICE_ID 0x0002
#define SH7780_PCICR_PREFIX 0xA5000000
#define SH7780_PCICR_PFCS 0x00000800
#define SH7780_PCICR_FTO 0x00000400
#define SH7780_PCICR_PFE 0x00000200
#define SH7780_PCICR_TBS 0x00000100
#define SH7780_PCICR_ARBM 0x00000040
#define SH7780_PCICR_IOCS 0x00000004
#define SH7780_PCICR_PRST 0x00000002
#define SH7780_PCICR_CFIN 0x00000001
#define p4_in(addr) (*(vu_long *)addr)
#define p4_out(data, addr) (*(vu_long *)addr) = (data)
#define p4_inw(addr) (*(vu_short *)addr)
#define p4_outw(data, addr) (*(vu_short *)addr) = (data)
int pci_sh4_read_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32 *value)
{
u32 par_data = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), offset);
p4_out(par_data, SH7780_PCIPAR);
*value = p4_in(SH7780_PCIPDR);
return 0;
}
int pci_sh4_write_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32 value)
{
u32 par_data = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), offset);
p4_out(par_data, SH7780_PCIPAR);
p4_out(value, SH7780_PCIPDR);
return 0;
}
int pci_sh7780_init(struct pci_controller *hose)
{
p4_out(0x01, SH7780_PCIECR);
if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID
&& p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID) {
printf("PCI: Unknown PCI host bridge.\n");
return -1;
}
printf("PCI: SH7780 PCI host bridge found.\n");
/* Toggle PCI reset pin */
p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_PRST), SH7780_PCICR);
udelay(100000);
p4_out(SH7780_PCICR_PREFIX, SH7780_PCICR);
p4_outw(0x0047, SH7780_PCICMD);
p4_out(CONFIG_SH7780_PCI_LSR, SH7780_PCILSR0);
p4_out(CONFIG_SH7780_PCI_LAR, SH7780_PCILAR0);
p4_out(0x00000000, SH7780_PCILSR1);
p4_out(0, SH7780_PCILAR1);
p4_out(CONFIG_SH7780_PCI_BAR, SH7780_PCIMBAR0);
p4_out(0x00000000, SH7780_PCIMBAR1);
p4_out(0xFD000000, SH7780_PCIMBR0);
p4_out(0x00FC0000, SH7780_PCIMBMR0);
/* if use Operand Cache then enable PCICSCR Soonp bits. */
p4_out(0x08000000, SH7780_PCICSAR0);
p4_out(0x0000001B, SH7780_PCICSCR0); /* Snoop bit :On */
p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | SH7780_PCICR_ARBM
| SH7780_PCICR_FTO | SH7780_PCICR_PFCS | SH7780_PCICR_PFE),
SH7780_PCICR);
pci_sh4_init(hose);
return 0;
}

4
drivers/power/Makefile
View file

@ -4,10 +4,7 @@
# Tom Rix <Tom.Rix at windriver.com>
obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += acpi_pmc/
obj-y += battery/
obj-$(CONFIG_$(SPL_TPL_)POWER_DOMAIN) += domain/
obj-y += fuel_gauge/
obj-y += mfd/
obj-y += pmic/
obj-y += regulator/
@ -18,7 +15,6 @@ obj-$(CONFIG_AXP305_POWER) += axp305.o
obj-$(CONFIG_AXP809_POWER) += axp809.o
obj-$(CONFIG_AXP818_POWER) += axp818.o
obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o
obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o
obj-$(CONFIG_SY8106A_POWER) += sy8106a.o
obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o
obj-$(CONFIG_TWL4030_POWER) += twl4030.o

7
drivers/power/battery/Makefile
View file

@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2012 Samsung Electronics
# Lukasz Majewski <l.majewski@samsung.com>
obj-$(CONFIG_POWER_BATTERY_TRATS) += bat_trats.o
obj-$(CONFIG_POWER_BATTERY_TRATS2) += bat_trats2.o

91
drivers/power/battery/bat_trats.c
View file

@ -1,91 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2012 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*/
#include <common.h>
#include <console.h>
#include <log.h>
#include <linux/delay.h>
#include <power/pmic.h>
#include <power/battery.h>
#include <power/max8997_pmic.h>
#include <errno.h>
static struct battery battery_trats;
static int power_battery_charge(struct pmic *bat)
{
struct power_battery *p_bat = bat->pbat;
struct battery *battery = p_bat->bat;
int k;
if (bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_ENABLE, 450))
return -1;
for (k = 0; bat->chrg->chrg_bat_present(p_bat->chrg) &&
bat->chrg->chrg_type(p_bat->muic) &&
battery->state_of_chrg < 100; k++) {
udelay(2000000);
if (!(k % 5))
puts(".");
bat->fg->fg_battery_update(p_bat->fg, bat);
if (k == 200) {
debug(" %d [V]", battery->voltage_uV);
puts("\n");
k = 0;
}
if (ctrlc()) {
printf("\nCharging disabled on request.\n");
goto exit;
}
}
exit:
bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_DISABLE, 0);
return 0;
}
static int power_battery_init_trats(struct pmic *bat_,
struct pmic *fg_,
struct pmic *chrg_,
struct pmic *muic_)
{
bat_->pbat->fg = fg_;
bat_->pbat->chrg = chrg_;
bat_->pbat->muic = muic_;
bat_->fg = fg_->fg;
bat_->chrg = chrg_->chrg;
bat_->chrg->chrg_type = muic_->chrg->chrg_type;
return 0;
}
static struct power_battery power_bat_trats = {
.bat = &battery_trats,
.battery_init = power_battery_init_trats,
.battery_charge = power_battery_charge,
};
int power_bat_init(unsigned char bus)
{
static const char name[] = "BAT_TRATS";
struct pmic *p = pmic_alloc();
if (!p) {
printf("%s: POWER allocation error!\n", __func__);
return -ENOMEM;
}
debug("Board BAT init\n");
p->interface = PMIC_NONE;
p->name = name;
p->bus = bus;
p->pbat = &power_bat_trats;
return 0;
}

65
drivers/power/battery/bat_trats2.c
View file

@ -1,65 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2013 Samsung Electronics
* Piotr Wilczek <p.wilczek@samsung.com>
*/
#include <common.h>
#include <log.h>
#include <power/pmic.h>
#include <power/battery.h>
#include <power/max77693_pmic.h>
#include <errno.h>
static struct battery battery_trats;
static int power_battery_charge(struct pmic *bat)
{
struct power_battery *p_bat = bat->pbat;
if (bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_ENABLE, 450))
return -EINVAL;
return 0;
}
static int power_battery_init_trats2(struct pmic *bat_,
struct pmic *fg_,
struct pmic *chrg_,
struct pmic *muic_)
{
bat_->pbat->fg = fg_;
bat_->pbat->chrg = chrg_;
bat_->pbat->muic = muic_;
bat_->fg = fg_->fg;
bat_->chrg = chrg_->chrg;
bat_->chrg->chrg_type = muic_->chrg->chrg_type;
return 0;
}
static struct power_battery power_bat_trats2 = {
.bat = &battery_trats,
.battery_init = power_battery_init_trats2,
.battery_charge = power_battery_charge,
};
int power_bat_init(unsigned char bus)
{
static const char name[] = "BAT_TRATS2";
struct pmic *p = pmic_alloc();
if (!p) {
printf("%s: POWER allocation error!\n", __func__);
return -ENOMEM;
}
debug("Board BAT init\n");
p->interface = PMIC_NONE;
p->name = name;
p->bus = bus;
p->pbat = &power_bat_trats2;
return 0;
}

87
drivers/power/ftpmu010.c
View file

@ -1,87 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* Copyright (C) 2010 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*/
#include <common.h>
#include <asm/io.h>
#include <faraday/ftpmu010.h>
/* OSCC: OSC Control Register */
void ftpmu010_32768osc_enable(void)
{
static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int oscc;
/* enable the 32768Hz oscillator */
oscc = readl(&pmu->OSCC);
oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI);
writel(oscc, &pmu->OSCC);
/* wait until ready */
while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE))
;
/* select 32768Hz oscillator */
oscc = readl(&pmu->OSCC);
oscc |= FTPMU010_OSCC_OSCL_RTCLSEL;
writel(oscc, &pmu->OSCC);
}
/* MFPSR: Multi-Function Port Setting Register */
void ftpmu010_mfpsr_select_dev(unsigned int dev)
{
static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int mfpsr;
mfpsr = readl(&pmu->MFPSR);
mfpsr |= dev;
writel(mfpsr, &pmu->MFPSR);
}
void ftpmu010_mfpsr_diselect_dev(unsigned int dev)
{
static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int mfpsr;
mfpsr = readl(&pmu->MFPSR);
mfpsr &= ~dev;
writel(mfpsr, &pmu->MFPSR);
}
/* PDLLCR0: PLL/DLL Control Register 0 */
void ftpmu010_dlldis_disable(void)
{
static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int pdllcr0;
pdllcr0 = readl(&pmu->PDLLCR0);
pdllcr0 |= FTPMU010_PDLLCR0_DLLDIS;
writel(pdllcr0, &pmu->PDLLCR0);
}
void ftpmu010_sdram_clk_disable(unsigned int cr0)
{
static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int pdllcr0;
pdllcr0 = readl(&pmu->PDLLCR0);
pdllcr0 |= FTPMU010_PDLLCR0_HCLKOUTDIS(cr0);
writel(pdllcr0, &pmu->PDLLCR0);
}
/* SDRAMHTC: SDRAM Signal Hold Time Control */
void ftpmu010_sdramhtc_set(unsigned int val)
{
static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int sdramhtc;
sdramhtc = readl(&pmu->SDRAMHTC);
sdramhtc |= val;
writel(sdramhtc, &pmu->SDRAMHTC);
}

6
drivers/power/fuel_gauge/Makefile
View file

@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2012 Samsung Electronics
# Lukasz Majewski <l.majewski@samsung.com>
obj-$(CONFIG_POWER_FG_MAX17042) += fg_max17042.o

287
drivers/power/fuel_gauge/fg_max17042.c
View file

@ -1,287 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2012 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*/
#include <common.h>
#include <log.h>
#include <linux/delay.h>
#include <power/pmic.h>
#include <power/max17042_fg.h>
#include <i2c.h>
#include <power/max8997_pmic.h>
#include <power/power_chrg.h>
#include <power/battery.h>
#include <power/fg_battery_cell_params.h>
#include <errno.h>
static int fg_write_regs(struct pmic *p, u8 addr, u16 *data, int num)
{
int ret = 0;
int i;
for (i = 0; i < num; i++, addr++) {
ret = pmic_reg_write(p, addr, *(data + i));
if (ret)
return ret;
}
return 0;
}
static int fg_read_regs(struct pmic *p, u8 addr, u16 *data, int num)
{
unsigned int dat;
int ret = 0;
int i;
for (i = 0; i < num; i++, addr++) {
ret = pmic_reg_read(p, addr, &dat);
if (ret)
return ret;
*(data + i) = (u16)dat;
}
return 0;
}
static int fg_write_and_verify(struct pmic *p, u8 addr, u16 data)
{
unsigned int val = data;
int ret = 0;
ret |= pmic_reg_write(p, addr, val);
ret |= pmic_reg_read(p, addr, &val);
if (ret)
return ret;
if (((u16) val) == data)
return 0;
return -1;
}
static void por_fuelgauge_init(struct pmic *p)
{
u16 r_data0[16], r_data1[16], r_data2[16];
u32 rewrite_count = 5;
u32 check_count;
u32 lock_count;
u32 i = 0;
u32 val;
s32 ret = 0;
char *status_msg;
/* Delay 500 ms */
mdelay(500);
/* Initilize Configuration */
pmic_reg_write(p, MAX17042_CONFIG, 0x2310);
rewrite_model:
check_count = 5;
lock_count = 5;
if (!rewrite_count--) {
status_msg = "init failed!";
goto error;
}
/* Unlock Model Access */
pmic_reg_write(p, MAX17042_MLOCKReg1, MODEL_UNLOCK1);
pmic_reg_write(p, MAX17042_MLOCKReg2, MODEL_UNLOCK2);
/* Write/Read/Verify the Custom Model */
ret = fg_write_regs(p, MAX17042_MODEL1, cell_character0,
ARRAY_SIZE(cell_character0));
if (ret)
goto rewrite_model;
ret = fg_write_regs(p, MAX17042_MODEL2, cell_character1,
ARRAY_SIZE(cell_character1));
if (ret)
goto rewrite_model;
ret = fg_write_regs(p, MAX17042_MODEL3, cell_character2,
ARRAY_SIZE(cell_character2));
if (ret)
goto rewrite_model;
check_model:
if (!check_count--) {
if (rewrite_count)
goto rewrite_model;
else
status_msg = "check failed!";
goto error;
}
ret = fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0));
if (ret)
goto check_model;
ret = fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1));
if (ret)
goto check_model;
ret = fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2));
if (ret)
goto check_model;
for (i = 0; i < 16; i++) {
if ((cell_character0[i] != r_data0[i])
|| (cell_character1[i] != r_data1[i])
|| (cell_character2[i] != r_data2[i]))
goto rewrite_model;
}
lock_model:
if (!lock_count--) {
if (rewrite_count)
goto rewrite_model;
else
status_msg = "lock failed!";
goto error;
}
/* Lock model access */
pmic_reg_write(p, MAX17042_MLOCKReg1, MODEL_LOCK1);
pmic_reg_write(p, MAX17042_MLOCKReg2, MODEL_LOCK2);
/* Verify the model access is locked */
ret = fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0));
if (ret)
goto lock_model;
ret = fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1));
if (ret)
goto lock_model;
ret = fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2));
if (ret)
goto lock_model;
for (i = 0; i < ARRAY_SIZE(r_data0); i++) {
/* Check if model locked */
if (r_data0[i] || r_data1[i] || r_data2[i])
goto lock_model;
}
/* Write Custom Parameters */
fg_write_and_verify(p, MAX17042_RCOMP0, RCOMP0);
fg_write_and_verify(p, MAX17042_TEMPCO, TempCo);
/* Delay at least 350mS */
mdelay(350);
/* Initialization Complete */
pmic_reg_read(p, MAX17042_STATUS, &val);
/* Write and Verify Status with POR bit Cleared */
fg_write_and_verify(p, MAX17042_STATUS, val & ~MAX17042_POR);
/* Delay at least 350 ms */
mdelay(350);
status_msg = "OK!";
error:
debug("%s: model init status: %s\n", p->name, status_msg);
return;
}
static int power_update_battery(struct pmic *p, struct pmic *bat)
{
struct power_battery *pb = bat->pbat;
unsigned int val;
int ret = 0;
if (pmic_probe(p)) {
puts("Can't find max17042 fuel gauge\n");
return -ENODEV;
}
ret |= pmic_reg_read(p, MAX17042_VFSOC, &val);
pb->bat->state_of_chrg = (val >> 8);
pmic_reg_read(p, MAX17042_VCELL, &val);
debug("vfsoc: 0x%x\n", val);
pb->bat->voltage_uV = ((val & 0xFFUL) >> 3) + ((val & 0xFF00) >> 3);
pb->bat->voltage_uV = (pb->bat->voltage_uV * 625);
pmic_reg_read(p, 0x05, &val);
pb->bat->capacity = val >> 2;
return ret;
}
static int power_check_battery(struct pmic *p, struct pmic *bat)
{
struct power_battery *pb = bat->pbat;
unsigned int val;
int ret = 0;
if (pmic_probe(p)) {
puts("Can't find max17042 fuel gauge\n");
return -ENODEV;
}
ret |= pmic_reg_read(p, MAX17042_STATUS, &val);
debug("fg status: 0x%x\n", val);
if (val & MAX17042_POR)
por_fuelgauge_init(p);
ret |= pmic_reg_read(p, MAX17042_VERSION, &val);
pb->bat->version = val;
power_update_battery(p, bat);
debug("fg ver: 0x%x\n", pb->bat->version);
printf("BAT: state_of_charge(SOC):%d%%\n",
pb->bat->state_of_chrg);
printf(" voltage: %d.%6.6d [V] (expected to be %d [mAh])\n",
pb->bat->voltage_uV / 1000000,
pb->bat->voltage_uV % 1000000,
pb->bat->capacity);
if (pb->bat->voltage_uV > 3850000)
pb->bat->state = EXT_SOURCE;
else if (pb->bat->voltage_uV < 3600000 || pb->bat->state_of_chrg < 5)
pb->bat->state = CHARGE;
else
pb->bat->state = NORMAL;
return ret;
}
static struct power_fg power_fg_ops = {
.fg_battery_check = power_check_battery,
.fg_battery_update = power_update_battery,
};
int power_fg_init(unsigned char bus)
{
static const char name[] = "MAX17042_FG";
struct pmic *p = pmic_alloc();
if (!p) {
printf("%s: POWER allocation error!\n", __func__);
return -ENOMEM;
}
debug("Board Fuel Gauge init\n");
p->name = name;
p->interface = PMIC_I2C;
p->number_of_regs = FG_NUM_OF_REGS;
p->hw.i2c.addr = MAX17042_I2C_ADDR;
p->hw.i2c.tx_num = 2;
p->sensor_byte_order = PMIC_SENSOR_BYTE_ORDER_BIG;
p->bus = bus;
p->fg = &power_fg_ops;
return 0;
}

8
drivers/power/mfd/Makefile
View file

@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2013 Samsung Electronics
# Piotr Wilczek <p.wilczek@samsung.com>
obj-$(CONFIG_POWER_PMIC_MAX77693) += pmic_max77693.o
obj-$(CONFIG_POWER_MUIC_MAX77693) += muic_max77693.o
obj-$(CONFIG_POWER_FG_MAX77693) += fg_max77693.o

137
drivers/power/mfd/fg_max77693.c
View file

@ -1,137 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2013 Samsung Electronics
* Piotr Wilczek <p.wilczek@samsung.com>
*/
#include <common.h>
#include <log.h>
#include <power/pmic.h>
#include <power/max77693_fg.h>
#include <i2c.h>
#include <power/power_chrg.h>
#include <power/battery.h>
#include <power/fg_battery_cell_params.h>
#include <errno.h>
static int max77693_get_vcell(u32 *vcell)
{
u16 value;
u8 ret;
ret = i2c_read(MAX77693_FUEL_I2C_ADDR, MAX77693_VCELL, 1,
(u8 *)&value, 2);
if (ret)
return ret;
*vcell = (u32)(value >> 3);
*vcell = *vcell * 625;
return 0;
}
static int max77693_get_soc(u32 *soc)
{
u16 value;
u8 ret;
ret = i2c_read(MAX77693_FUEL_I2C_ADDR, MAX77693_VFSOC, 1,
(u8 *)&value, 2);
if (ret)
return ret;
*soc = (u32)(value >> 8);
return 0;
}
static int power_update_battery(struct pmic *p, struct pmic *bat)
{
struct power_battery *pb = bat->pbat;
int ret;
if (pmic_probe(p)) {
puts("Can't find max77693 fuel gauge\n");
return -ENODEV;
}
ret = max77693_get_soc(&pb->bat->state_of_chrg);
if (ret)
return ret;
max77693_get_vcell(&pb->bat->voltage_uV);
return 0;
}
static int power_check_battery(struct pmic *p, struct pmic *bat)
{
struct power_battery *pb = bat->pbat;
unsigned int val;
int ret = 0;
if (pmic_probe(p)) {
puts("Can't find max77693 fuel gauge\n");
return -ENODEV;
}
ret = pmic_reg_read(p, MAX77693_STATUS, &val);
if (ret)
return ret;
debug("fg status: 0x%x\n", val);
ret = pmic_reg_read(p, MAX77693_VERSION, &pb->bat->version);
if (ret)
return ret;
ret = power_update_battery(p, bat);
if (ret)
return ret;
debug("fg ver: 0x%x\n", pb->bat->version);
printf("BAT: state_of_charge(SOC):%d%%\n",
pb->bat->state_of_chrg);
printf(" voltage: %d.%6.6d [V] (expected to be %d [mAh])\n",
pb->bat->voltage_uV / 1000000,
pb->bat->voltage_uV % 1000000,
pb->bat->capacity);
if (pb->bat->voltage_uV > 3850000)
pb->bat->state = EXT_SOURCE;
else if (pb->bat->voltage_uV < 3600000 || pb->bat->state_of_chrg < 5)
pb->bat->state = CHARGE;
else
pb->bat->state = NORMAL;
return 0;
}
static struct power_fg power_fg_ops = {
.fg_battery_check = power_check_battery,
.fg_battery_update = power_update_battery,
};
int power_fg_init(unsigned char bus)
{
static const char name[] = "MAX77693_FG";
struct pmic *p = pmic_alloc();
if (!p) {
printf("%s: POWER allocation error!\n", __func__);
return -ENOMEM;
}
debug("Board Fuel Gauge init\n");
p->name = name;
p->interface = PMIC_I2C;
p->number_of_regs = FG_NUM_OF_REGS;
p->hw.i2c.addr = MAX77693_FUEL_I2C_ADDR;
p->hw.i2c.tx_num = 2;
p->sensor_byte_order = PMIC_SENSOR_BYTE_ORDER_BIG;
p->bus = bus;
p->fg = &power_fg_ops;
return 0;
}

77
drivers/power/mfd/muic_max77693.c
View file

@ -1,77 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2013 Samsung Electronics
* Piotr Wilczek <p.wilczek@samsung.com>
*/
#include <common.h>
#include <log.h>
#include <power/pmic.h>
#include <power/power_chrg.h>
#include <power/max77693_muic.h>
#include <i2c.h>
#include <errno.h>
static int power_chrg_get_type(struct pmic *p)
{
unsigned int val;
unsigned int charge_type, charger;
/* if probe failed, return cable none */
if (pmic_probe(p))
return CHARGER_NO;
pmic_reg_read(p, MAX77693_MUIC_STATUS2, &val);
charge_type = val & MAX77693_MUIC_CHG_MASK;
switch (charge_type) {
case MAX77693_MUIC_CHG_NO:
charger = CHARGER_NO;
break;
case MAX77693_MUIC_CHG_USB:
case MAX77693_MUIC_CHG_USB_D:
charger = CHARGER_USB;
break;
case MAX77693_MUIC_CHG_TA:
case MAX77693_MUIC_CHG_TA_1A:
charger = CHARGER_TA;
break;
case MAX77693_MUIC_CHG_TA_500:
charger = CHARGER_TA_500;
break;
default:
charger = CHARGER_UNKNOWN;
break;
}
return charger;
}
static struct power_chrg power_chrg_muic_ops = {
.chrg_type = power_chrg_get_type,
};
int power_muic_init(unsigned int bus)
{
static const char name[] = "MAX77693_MUIC";
struct pmic *p = pmic_alloc();
if (!p) {
printf("%s: POWER allocation error!\n", __func__);
return -ENOMEM;
}
debug("Board Micro USB Interface Controller init\n");
p->name = name;
p->interface = PMIC_I2C;
p->number_of_regs = MUIC_NUM_OF_REGS;
p->hw.i2c.addr = MAX77693_MUIC_I2C_ADDR;
p->hw.i2c.tx_num = 1;
p->bus = bus;
p->chrg = &power_chrg_muic_ops;
return 0;
}

96
drivers/power/mfd/pmic_max77693.c
View file

@ -1,96 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2013 Samsung Electronics
* Piotr Wilczek <p.wilczek@samsung.com>
*/
#include <common.h>
#include <log.h>
#include <power/pmic.h>
#include <power/max77693_pmic.h>
#include <i2c.h>
#include <errno.h>
static int max77693_charger_state(struct pmic *p, int state, int current)
{
unsigned int val;
if (pmic_probe(p))
return -ENODEV;
/* unlock write capability */
val = MAX77693_CHG_UNLOCK;
pmic_reg_write(p, MAX77693_CHG_CNFG_06, val);
if (state == PMIC_CHARGER_DISABLE) {
puts("Disable the charger.\n");
pmic_reg_read(p, MAX77693_CHG_CNFG_00, &val);
val &= ~0x01;
pmic_reg_write(p, MAX77693_CHG_CNFG_00, val);
return -ENOTSUPP;
}
if (current < CHARGER_MIN_CURRENT || current > CHARGER_MAX_CURRENT) {
printf("%s: Wrong charge current: %d [mA]\n",
__func__, current);
return -EINVAL;
}
/* set charging current */
pmic_reg_read(p, MAX77693_CHG_CNFG_02, &val);
val &= ~MAX77693_CHG_CC;
val |= current * 10 / 333; /* 0.1A/3 steps */
pmic_reg_write(p, MAX77693_CHG_CNFG_02, val);
/* enable charging */
val = MAX77693_CHG_MODE_ON;
pmic_reg_write(p, MAX77693_CHG_CNFG_00, val);
/* check charging current */
pmic_reg_read(p, MAX77693_CHG_CNFG_02, &val);
val &= 0x3f;
printf("Enable the charger @ %d [mA]\n", val * 333 / 10);
return 0;
}
static int max77693_charger_bat_present(struct pmic *p)
{
unsigned int val;
if (pmic_probe(p))
return -ENODEV;
pmic_reg_read(p, MAX77693_CHG_INT_OK, &val);
return !(val & MAX77693_CHG_DETBAT);
}
static struct power_chrg power_chrg_pmic_ops = {
.chrg_bat_present = max77693_charger_bat_present,
.chrg_state = max77693_charger_state,
};
int pmic_init_max77693(unsigned char bus)
{
static const char name[] = "MAX77693_PMIC";
struct pmic *p = pmic_alloc();
if (!p) {
printf("%s: POWER allocation error!\n", __func__);
return -ENOMEM;
}
debug("Board PMIC init\n");
p->name = name;
p->interface = PMIC_I2C;
p->number_of_regs = PMIC_NUM_OF_REGS;
p->hw.i2c.addr = MAX77693_PMIC_I2C_ADDR;
p->hw.i2c.tx_num = 1;
p->bus = bus;
p->chrg = &power_chrg_pmic_ops;
return 0;
}

1
drivers/power/pmic/Makefile
View file

@ -37,7 +37,6 @@ obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y)
obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
obj-$(CONFIG_POWER_PCA9450) += pmic_pca9450.o
obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o

74
drivers/power/pmic/muic_max8997.c
View file

@ -1,74 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2012 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*/
#include <common.h>
#include <log.h>
#include <power/pmic.h>
#include <power/power_chrg.h>
#include <power/max8997_muic.h>
#include <i2c.h>
#include <errno.h>
static int power_chrg_get_type(struct pmic *p)
{
unsigned int val;
unsigned char charge_type, charger;
if (pmic_probe(p))
return CHARGER_NO;
pmic_reg_read(p, MAX8997_MUIC_STATUS2, &val);
charge_type = val & MAX8997_MUIC_CHG_MASK;
switch (charge_type) {
case MAX8997_MUIC_CHG_NO:
charger = CHARGER_NO;
break;
case MAX8997_MUIC_CHG_USB:
case MAX8997_MUIC_CHG_USB_D:
charger = CHARGER_USB;
break;
case MAX8997_MUIC_CHG_TA:
case MAX8997_MUIC_CHG_TA_1A:
charger = CHARGER_TA;
break;
case MAX8997_MUIC_CHG_TA_500:
charger = CHARGER_TA_500;
break;
default:
charger = CHARGER_UNKNOWN;
break;
}
return charger;
}
static struct power_chrg power_chrg_muic_ops = {
.chrg_type = power_chrg_get_type,
};
int power_muic_init(unsigned int bus)
{
static const char name[] = "MAX8997_MUIC";
struct pmic *p = pmic_alloc();
if (!p) {
printf("%s: POWER allocation error!\n", __func__);
return -ENOMEM;
}
debug("Board Micro USB Interface Controller init\n");
p->name = name;
p->interface = PMIC_I2C;
p->number_of_regs = MUIC_NUM_OF_REGS;
p->hw.i2c.addr = MAX8997_MUIC_I2C_ADDR;
p->hw.i2c.tx_num = 1;
p->bus = bus;
p->chrg = &power_chrg_muic_ops;
return 0;
}

14
drivers/rtc/Makefile
View file

@ -6,49 +6,35 @@
obj-$(CONFIG_$(SPL_TPL_)DM_RTC) += rtc-uclass.o
obj-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o
obj-$(CONFIG_RTC_ARMADA38X) += armada38x.o
obj-$(CONFIG_RTC_DAVINCI) += davinci.o
obj-$(CONFIG_RTC_DS1302) += ds1302.o
obj-$(CONFIG_RTC_DS1306) += ds1306.o
obj-$(CONFIG_RTC_DS1307) += ds1307.o
obj-$(CONFIG_RTC_DS1338) += ds1307.o
obj-$(CONFIG_RTC_DS1339) += ds1307.o
obj-$(CONFIG_RTC_DS1337) += ds1337.o
obj-$(CONFIG_RTC_DS1374) += ds1374.o
obj-$(CONFIG_RTC_DS1388) += ds1337.o
obj-$(CONFIG_RTC_DS3231) += ds3231.o
obj-$(CONFIG_RTC_DS3232) += ds3232.o
obj-$(CONFIG_RTC_EMULATION) += emul_rtc.o
obj-$(CONFIG_RTC_FTRTC010) += ftrtc010.o
obj-$(CONFIG_RTC_HT1380) += ht1380.o
obj-$(CONFIG_SANDBOX) += i2c_rtc_emul.o
obj-$(CONFIG_RTC_IMXDI) += imxdi.o
obj-$(CONFIG_RTC_ISL1208) += isl1208.o
obj-$(CONFIG_RTC_M41T62) += m41t62.o
obj-$(CONFIG_RTC_MAX6900) += max6900.o
obj-$(CONFIG_RTC_MC13XXX) += mc13xxx-rtc.o
obj-$(CONFIG_RTC_MC146818) += mc146818.o
obj-$(CONFIG_RTC_MCP79411) += ds1307.o
obj-$(CONFIG_MCFRTC) += mcfrtc.o
obj-$(CONFIG_RTC_MK48T59) += mk48t59.o
obj-$(CONFIG_RTC_MV) += mvrtc.o
obj-$(CONFIG_RTC_MX27) += mx27rtc.o
obj-$(CONFIG_RTC_MXS) += mxsrtc.o
obj-$(CONFIG_RTC_PCF8563) += pcf8563.o
obj-$(CONFIG_RTC_PCF2127) += pcf2127.o
obj-$(CONFIG_RTC_PL031) += pl031.o
obj-$(CONFIG_RTC_PT7C4338) += pt7c4338.o
obj-$(CONFIG_RTC_RS5C372A) += rs5c372.o
obj-$(CONFIG_RTC_RV3028) += rv3028.o
obj-$(CONFIG_RTC_RV3029) += rv3029.o
obj-$(CONFIG_RTC_RV8803) += rv8803.o
obj-$(CONFIG_RTC_RX8025) += rx8025.o
obj-$(CONFIG_RTC_RX8010SJ) += rx8010sj.o
obj-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o
obj-$(CONFIG_RTC_S35392A) += s35392a.o
obj-$(CONFIG_RTC_STM32) += stm32_rtc.o
obj-$(CONFIG_SANDBOX) += sandbox_rtc.o
obj-$(CONFIG_RTC_X1205) += x1205.o
obj-$(CONFIG_RTC_ABX80X) += abx80x.o
obj-$(CONFIG_RTC_ZYNQMP) += zynqmp_rtc.o

78
drivers/rtc/at91sam9_rtt.c
View file

@ -1,78 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Reinhard Meyer, reinhard.meyer@emk-elektronik.de
*/
/*
* Date & Time support for the internal Real-time Timer
* of AT91SAM9260 and compatibles.
* Compatible with the LinuX rtc driver workaround:
* The RTT cannot be written to, but only reset.
* The actual time is the sum of RTT and one of
* the four GPBR registers.
*
* The at91sam9260 has 4 GPBR (0-3).
* For their typical use see at91_gpbr.h !
*
* make sure u-boot and kernel use the same GPBR !
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_rtt.h>
#include <asm/arch/at91_gpbr.h>
int rtc_get (struct rtc_time *tmp)
{
at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT;
at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR;
ulong tim;
ulong tim2;
ulong off;
do {
tim = readl(&rtt->vr);
tim2 = readl(&rtt->vr);
} while (tim!=tim2);
off = readl(&gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]);
/* off==0 means time is invalid, but we ignore that */
rtc_to_tm(tim+off, tmp);
return 0;
}
int rtc_set (struct rtc_time *tmp)
{
at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT;
at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR;
ulong tim;
tim = rtc_mktime(tmp);
/* clear alarm, set prescaler to 32768, clear counter */
writel(32768+AT91_RTT_RTTRST, &rtt->mr);
writel(~0, &rtt->ar);
writel(tim, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]);
/* wait for counter clear to happen, takes less than a 1/32768th second */
while (readl(&rtt->vr) != 0)
;
return 0;
}
void rtc_reset (void)
{
at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT;
at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR;
/* clear alarm, set prescaler to 32768, clear counter */
writel(32768+AT91_RTT_RTTRST, &rtt->mr);
writel(~0, &rtt->ar);
writel(0, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]);
/* wait for counter clear to happen, takes less than a 1/32768th second */
while (readl(&rtt->vr) != 0)
;
}

329
drivers/rtc/ds1302.c
View file

@ -1,329 +0,0 @@
/*
* ds1302.c - Support for the Dallas Semiconductor DS1302 Timekeeping Chip
*
* Rex G. Feany <rfeany@zumanetworks.com>
*
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <linux/delay.h>
/* GPP Pins */
#define DATA 0x200
#define SCLK 0x400
#define RST 0x800
/* Happy Fun Defines(tm) */
#define RESET rtc_go_low(RST), rtc_go_low(SCLK)
#define N_RESET rtc_go_high(RST), rtc_go_low(SCLK)
#define CLOCK_HIGH rtc_go_high(SCLK)
#define CLOCK_LOW rtc_go_low(SCLK)
#define DATA_HIGH rtc_go_high(DATA)
#define DATA_LOW rtc_go_low(DATA)
#define DATA_READ (GTREGREAD(GPP_VALUE) & DATA)
#undef RTC_DEBUG
#ifdef RTC_DEBUG
# define DPRINTF(x,args...) printf("ds1302: " x , ##args)
static inline void DUMP(const char *ptr, int num)
{
while (num--) printf("%x ", *ptr++);
printf("]\n");
}
#else
# define DPRINTF(x,args...)
# define DUMP(ptr, num)
#endif
/* time data format for DS1302 */
struct ds1302_st
{
unsigned char CH:1; /* clock halt 1=stop 0=start */
unsigned char sec10:3;
unsigned char sec:4;
unsigned char zero0:1;
unsigned char min10:3;
unsigned char min:4;
unsigned char fmt:1; /* 1=12 hour 0=24 hour */
unsigned char zero1:1;
unsigned char hr10:2; /* 10 (0-2) or am/pm (am/pm, 0-1) */
unsigned char hr:4;
unsigned char zero2:2;
unsigned char date10:2;
unsigned char date:4;
unsigned char zero3:3;
unsigned char month10:1;
unsigned char month:4;
unsigned char zero4:5;
unsigned char day:3; /* day of week */
unsigned char year10:4;
unsigned char year:4;
unsigned char WP:1; /* write protect 1=protect 0=unprot */
unsigned char zero5:7;
};
static int ds1302_initted=0;
/* Pin control */
static inline void
rtc_go_high(unsigned int mask)
{
unsigned int f = GTREGREAD(GPP_VALUE) | mask;
GT_REG_WRITE(GPP_VALUE, f);
}
static inline void
rtc_go_low(unsigned int mask)
{
unsigned int f = GTREGREAD(GPP_VALUE) & ~mask;
GT_REG_WRITE(GPP_VALUE, f);
}
static inline void
rtc_go_input(unsigned int mask)
{
unsigned int f = GTREGREAD(GPP_IO_CONTROL) & ~mask;
GT_REG_WRITE(GPP_IO_CONTROL, f);
}
static inline void
rtc_go_output(unsigned int mask)
{
unsigned int f = GTREGREAD(GPP_IO_CONTROL) | mask;
GT_REG_WRITE(GPP_IO_CONTROL, f);
}
/* Access data in RTC */
static void
write_byte(unsigned char b)
{
int i;
unsigned char mask=1;
for(i=0;i<8;i++) {
CLOCK_LOW; /* Lower clock */
(b&mask)?DATA_HIGH:DATA_LOW; /* set data */
udelay(1);
CLOCK_HIGH; /* latch data with rising clock */
udelay(1);
mask=mask<<1;
}
}
static unsigned char
read_byte(void)
{
int i;
unsigned char mask=1;
unsigned char b=0;
for(i=0;i<8;i++) {
CLOCK_LOW;
udelay(1);
if (DATA_READ) b|=mask; /* if this bit is high, set in b */
CLOCK_HIGH; /* clock out next bit */
udelay(1);
mask=mask<<1;
}
return b;
}
static void
read_ser_drv(unsigned char addr, unsigned char *buf, int count)
{
int i;
#ifdef RTC_DEBUG
char *foo = buf;
#endif
DPRINTF("READ 0x%x bytes @ 0x%x [ ", count, addr);
addr|=1; /* READ */
N_RESET;
udelay(4);
write_byte(addr);
rtc_go_input(DATA); /* Put gpp pin into input mode */
udelay(1);
for(i=0;i<count;i++) *(buf++)=read_byte();
RESET;
rtc_go_output(DATA);/* Reset gpp for output */
udelay(4);
DUMP(foo, count);
}
static void
write_ser_drv(unsigned char addr, unsigned char *buf, int count)
{
int i;
DPRINTF("WRITE 0x%x bytes @ 0x%x [ ", count, addr);
DUMP(buf, count);
addr&=~1; /* WRITE */
N_RESET;
udelay(4);
write_byte(addr);
for(i=0;i<count;i++) write_byte(*(buf++));
RESET;
udelay(4);
}
void
rtc_init(void)
{
struct ds1302_st bbclk;
unsigned char b;
int mod;
DPRINTF("init\n");
rtc_go_output(DATA|SCLK|RST);
/* disable write protect */
b = 0;
write_ser_drv(0x8e,&b,1);
/* enable trickle */
b = 0xa5; /* 1010.0101 */
write_ser_drv(0x90,&b,1);
/* read burst */
read_ser_drv(0xbe, (unsigned char *)&bbclk, 8);
/* Sanity checks */
mod = 0;
if (bbclk.CH) {
printf("ds1302: Clock was halted, starting clock\n");
bbclk.CH=0;
mod=1;
}
if (bbclk.fmt) {
printf("ds1302: Clock was in 12 hour mode, fixing\n");
bbclk.fmt=0;
mod=1;
}
if (bbclk.year>9) {
printf("ds1302: Year was corrupted, fixing\n");
bbclk.year10=100/10; /* 2000 - why not? ;) */
bbclk.year=0;
mod=1;
}
/* Write out the changes if needed */
if (mod) {
/* enable write protect */
bbclk.WP = 1;
write_ser_drv(0xbe,(unsigned char *)&bbclk,8);
} else {
/* Else just turn write protect on */
b = 0x80;
write_ser_drv(0x8e,&b,1);
}
DPRINTF("init done\n");
ds1302_initted=1;
}
void
rtc_reset(void)
{
if(!ds1302_initted) rtc_init();
/* TODO */
}
int
rtc_get(struct rtc_time *tmp)
{
int rel = 0;
struct ds1302_st bbclk;
if(!ds1302_initted) rtc_init();
read_ser_drv(0xbe,(unsigned char *)&bbclk, 8); /* read burst */
if (bbclk.CH) {
printf("ds1302: rtc_get: Clock was halted, clock probably "
"corrupt\n");
rel = -1;
}
tmp->tm_sec=10*bbclk.sec10+bbclk.sec;
tmp->tm_min=10*bbclk.min10+bbclk.min;
tmp->tm_hour=10*bbclk.hr10+bbclk.hr;
tmp->tm_wday=bbclk.day;
tmp->tm_mday=10*bbclk.date10+bbclk.date;
tmp->tm_mon=10*bbclk.month10+bbclk.month;
tmp->tm_year=10*bbclk.year10+bbclk.year + 1900;
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
DPRINTF("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
return rel;
}
int rtc_set(struct rtc_time *tmp)
{
struct ds1302_st bbclk;
unsigned char b=0;
if(!ds1302_initted) rtc_init();
DPRINTF("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
memset(&bbclk,0,sizeof(bbclk));
bbclk.CH=0; /* dont halt */
bbclk.WP=1; /* write protect when we're done */
bbclk.sec10=tmp->tm_sec/10;
bbclk.sec=tmp->tm_sec%10;
bbclk.min10=tmp->tm_min/10;
bbclk.min=tmp->tm_min%10;
bbclk.hr10=tmp->tm_hour/10;
bbclk.hr=tmp->tm_hour%10;
bbclk.day=tmp->tm_wday;
bbclk.date10=tmp->tm_mday/10;
bbclk.date=tmp->tm_mday%10;
bbclk.month10=tmp->tm_mon/10;
bbclk.month=tmp->tm_mon%10;
tmp->tm_year -= 1900;
bbclk.year10=tmp->tm_year/10;
bbclk.year=tmp->tm_year%10;
write_ser_drv(0x8e,&b,1); /* disable write protect */
write_ser_drv(0xbe,(unsigned char *)&bbclk, 8); /* write burst */
return 0;
}

438
drivers/rtc/ds1306.c
View file

@ -1,438 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002 SIXNET, dge@sixnetio.com.
*
* (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
* Stephan Linz <linz@li-pro.net>
*/
/*
* Date & Time support for DS1306 RTC using SPI:
*
* - SXNI855T: it uses its own soft SPI here in this file
* - all other: use the external spi_xfer() function
* (see include/spi.h)
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <spi.h>
#include <linux/delay.h>
#define RTC_SECONDS 0x00
#define RTC_MINUTES 0x01
#define RTC_HOURS 0x02
#define RTC_DAY_OF_WEEK 0x03
#define RTC_DATE_OF_MONTH 0x04
#define RTC_MONTH 0x05
#define RTC_YEAR 0x06
#define RTC_SECONDS_ALARM0 0x07
#define RTC_MINUTES_ALARM0 0x08
#define RTC_HOURS_ALARM0 0x09
#define RTC_DAY_OF_WEEK_ALARM0 0x0a
#define RTC_SECONDS_ALARM1 0x0b
#define RTC_MINUTES_ALARM1 0x0c
#define RTC_HOURS_ALARM1 0x0d
#define RTC_DAY_OF_WEEK_ALARM1 0x0e
#define RTC_CONTROL 0x0f
#define RTC_STATUS 0x10
#define RTC_TRICKLE_CHARGER 0x11
#define RTC_USER_RAM_BASE 0x20
/* ************************************************************************* */
#ifdef CONFIG_SXNI855T /* !!! SHOULD BE CHANGED TO NEW CODE !!! */
static void soft_spi_send (unsigned char n);
static unsigned char soft_spi_read (void);
static void init_spi (void);
/*-----------------------------------------------------------------------
* Definitions
*/
#define PB_SPISCK 0x00000002 /* PB 30 */
#define PB_SPIMOSI 0x00000004 /* PB 29 */
#define PB_SPIMISO 0x00000008 /* PB 28 */
#define PB_SPI_CE 0x00010000 /* PB 15 */
/* ------------------------------------------------------------------------- */
/* read clock time from DS1306 and return it in *tmp */
int rtc_get (struct rtc_time *tmp)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
unsigned char spi_byte; /* Data Byte */
init_spi (); /* set port B for software SPI */
/* Now we can enable the DS1306 RTC */
immap->im_cpm.cp_pbdat |= PB_SPI_CE;
udelay(10);
/* Shift out the address (0) of the time in the Clock Chip */
soft_spi_send (0);
/* Put the clock readings into the rtc_time structure */
tmp->tm_sec = bcd2bin (soft_spi_read ()); /* Read seconds */
tmp->tm_min = bcd2bin (soft_spi_read ()); /* Read minutes */
/* Hours are trickier */
spi_byte = soft_spi_read (); /* Read Hours into temporary value */
if (spi_byte & 0x40) {
/* 12 hour mode bit is set (time is in 1-12 format) */
if (spi_byte & 0x20) {
/* since PM we add 11 to get 0-23 for hours */
tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) + 11;
} else {
/* since AM we subtract 1 to get 0-23 for hours */
tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) - 1;
}
} else {
/* Otherwise, 0-23 hour format */
tmp->tm_hour = (bcd2bin (spi_byte & 0x3F));
}
soft_spi_read (); /* Read and discard Day of week */
tmp->tm_mday = bcd2bin (soft_spi_read ()); /* Read Day of the Month */
tmp->tm_mon = bcd2bin (soft_spi_read ()); /* Read Month */
/* Read Year and convert to this century */
tmp->tm_year = bcd2bin (soft_spi_read ()) + 2000;
/* Now we can disable the DS1306 RTC */
immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
udelay(10);
rtc_calc_weekday(tmp); /* Determine the day of week */
debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return 0;
}
/* ------------------------------------------------------------------------- */
/* set clock time in DS1306 RTC and in MPC8xx RTC */
int rtc_set (struct rtc_time *tmp)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
init_spi (); /* set port B for software SPI */
/* Now we can enable the DS1306 RTC */
immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */
udelay(10);
/* First disable write protect in the clock chip control register */
soft_spi_send (0x8F); /* send address of the control register */
soft_spi_send (0x00); /* send control register contents */
/* Now disable the DS1306 to terminate the write */
immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;
udelay(10);
/* Now enable the DS1306 to initiate a new write */
immap->im_cpm.cp_pbdat |= PB_SPI_CE;
udelay(10);
/* Next, send the address of the clock time write registers */
soft_spi_send (0x80); /* send address of the first time register */
/* Use Burst Mode to send all of the time data to the clock */
bin2bcd (tmp->tm_sec);
soft_spi_send (bin2bcd (tmp->tm_sec)); /* Send Seconds */
soft_spi_send (bin2bcd (tmp->tm_min)); /* Send Minutes */
soft_spi_send (bin2bcd (tmp->tm_hour)); /* Send Hour */
soft_spi_send (bin2bcd (tmp->tm_wday)); /* Send Day of the Week */
soft_spi_send (bin2bcd (tmp->tm_mday)); /* Send Day of Month */
soft_spi_send (bin2bcd (tmp->tm_mon)); /* Send Month */
soft_spi_send (bin2bcd (tmp->tm_year - 2000)); /* Send Year */
/* Now we can disable the Clock chip to terminate the burst write */
immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
udelay(10);
/* Now we can enable the Clock chip to initiate a new write */
immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */
udelay(10);
/* First we Enable write protect in the clock chip control register */
soft_spi_send (0x8F); /* send address of the control register */
soft_spi_send (0x40); /* send out Control Register contents */
/* Now disable the DS1306 */
immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
udelay(10);
/* Set standard MPC8xx clock to the same time so Linux will
* see the time even if it doesn't have a DS1306 clock driver.
* This helps with experimenting with standard kernels.
*/
{
ulong tim;
tim = rtc_mktime(tmp);
immap->im_sitk.sitk_rtck = KAPWR_KEY;
immap->im_sit.sit_rtc = tim;
}
debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return 0;
}
/* ------------------------------------------------------------------------- */
/* Initialize Port B for software SPI */
static void init_spi (void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
/* Force output pins to begin at logic 0 */
immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE | PB_SPIMOSI | PB_SPISCK);
/* Set these 3 signals as outputs */
immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK);
immap->im_cpm.cp_pbdir &= ~PB_SPIMISO; /* Make MISO pin an input */
udelay(10);
}
/* ------------------------------------------------------------------------- */
/* NOTE: soft_spi_send() assumes that the I/O lines are configured already */
static void soft_spi_send (unsigned char n)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
unsigned char bitpos; /* bit position to receive */
unsigned char i; /* Loop Control */
/* bit position to send, start with most significant bit */
bitpos = 0x80;
/* Send 8 bits to software SPI */
for (i = 0; i < 8; i++) { /* Loop for 8 bits */
immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */
if (n & bitpos)
immap->im_cpm.cp_pbdat |= PB_SPIMOSI; /* Set MOSI to 1 */
else
immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI; /* Set MOSI to 0 */
udelay(10);
immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */
udelay(10);
bitpos >>= 1; /* Shift for next bit position */
}
}
/* ------------------------------------------------------------------------- */
/* NOTE: soft_spi_read() assumes that the I/O lines are configured already */
static unsigned char soft_spi_read (void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
unsigned char spi_byte = 0; /* Return value, assume success */
unsigned char bitpos; /* bit position to receive */
unsigned char i; /* Loop Control */
/* bit position to receive, start with most significant bit */
bitpos = 0x80;
/* Read 8 bits here */
for (i = 0; i < 8; i++) { /* Do 8 bits in loop */
immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */
udelay(10);
if (immap->im_cpm.cp_pbdat & PB_SPIMISO) /* Get a bit of data */
spi_byte |= bitpos; /* Set data accordingly */
immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */
udelay(10);
bitpos >>= 1; /* Shift for next bit position */
}
return spi_byte; /* Return the byte read */
}
/* ------------------------------------------------------------------------- */
void rtc_reset (void)
{
return; /* nothing to do */
}
#else /* not CONFIG_SXNI855T */
/* ************************************************************************* */
static unsigned char rtc_read (unsigned char reg);
static void rtc_write (unsigned char reg, unsigned char val);
static struct spi_slave *slave;
/* read clock time from DS1306 and return it in *tmp */
int rtc_get (struct rtc_time *tmp)
{
unsigned char sec, min, hour, mday, wday, mon, year;
/*
* Assuming Vcc = 2.0V (lowest speed)
*
* REVISIT: If we add an rtc_init() function we can do this
* step just once.
*/
if (!slave) {
slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
SPI_MODE_3 | SPI_CS_HIGH);
if (!slave)
return;
}
if (spi_claim_bus(slave))
return;
sec = rtc_read (RTC_SECONDS);
min = rtc_read (RTC_MINUTES);
hour = rtc_read (RTC_HOURS);
mday = rtc_read (RTC_DATE_OF_MONTH);
wday = rtc_read (RTC_DAY_OF_WEEK);
mon = rtc_read (RTC_MONTH);
year = rtc_read (RTC_YEAR);
spi_release_bus(slave);
debug ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x\n",
year, mon, mday, wday, hour, min, sec);
debug ("Alarms[0]: wday: %02x hour: %02x min: %02x sec: %02x\n",
rtc_read (RTC_DAY_OF_WEEK_ALARM0),
rtc_read (RTC_HOURS_ALARM0),
rtc_read (RTC_MINUTES_ALARM0), rtc_read (RTC_SECONDS_ALARM0));
debug ("Alarms[1]: wday: %02x hour: %02x min: %02x sec: %02x\n",
rtc_read (RTC_DAY_OF_WEEK_ALARM1),
rtc_read (RTC_HOURS_ALARM1),
rtc_read (RTC_MINUTES_ALARM1), rtc_read (RTC_SECONDS_ALARM1));
tmp->tm_sec = bcd2bin (sec & 0x7F); /* convert Seconds */
tmp->tm_min = bcd2bin (min & 0x7F); /* convert Minutes */
/* convert Hours */
tmp->tm_hour = (hour & 0x40)
? ((hour & 0x20) /* 12 hour mode */
? bcd2bin (hour & 0x1F) + 11 /* PM */
: bcd2bin (hour & 0x1F) - 1 /* AM */
)
: bcd2bin (hour & 0x3F); /* 24 hour mode */
tmp->tm_mday = bcd2bin (mday & 0x3F); /* convert Day of the Month */
tmp->tm_mon = bcd2bin (mon & 0x1F); /* convert Month */
tmp->tm_year = bcd2bin (year) + 2000; /* convert Year */
tmp->tm_wday = bcd2bin (wday & 0x07) - 1; /* convert Day of the Week */
tmp->tm_yday = 0;
tmp->tm_isdst = 0;
debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return 0;
}
/* ------------------------------------------------------------------------- */
/* set clock time from *tmp in DS1306 RTC */
int rtc_set (struct rtc_time *tmp)
{
/* Assuming Vcc = 2.0V (lowest speed) */
if (!slave) {
slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
SPI_MODE_3 | SPI_CS_HIGH);
if (!slave)
return;
}
if (spi_claim_bus(slave))
return;
debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec));
rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min));
rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour));
rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1));
rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday));
rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon));
rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000));
spi_release_bus(slave);
}
/* ------------------------------------------------------------------------- */
/* reset the DS1306 */
void rtc_reset (void)
{
/* Assuming Vcc = 2.0V (lowest speed) */
if (!slave) {
slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
SPI_MODE_3 | SPI_CS_HIGH);
if (!slave)
return;
}
if (spi_claim_bus(slave))
return;
/* clear the control register */
rtc_write (RTC_CONTROL, 0x00); /* 1st step: reset WP */
rtc_write (RTC_CONTROL, 0x00); /* 2nd step: reset 1Hz, AIE1, AIE0 */
/* reset all alarms */
rtc_write (RTC_SECONDS_ALARM0, 0x00);
rtc_write (RTC_SECONDS_ALARM1, 0x00);
rtc_write (RTC_MINUTES_ALARM0, 0x00);
rtc_write (RTC_MINUTES_ALARM1, 0x00);
rtc_write (RTC_HOURS_ALARM0, 0x00);
rtc_write (RTC_HOURS_ALARM1, 0x00);
rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00);
rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00);
spi_release_bus(slave);
}
/* ------------------------------------------------------------------------- */
static unsigned char rtc_read (unsigned char reg)
{
int ret;
ret = spi_w8r8(slave, reg);
return ret < 0 ? 0 : ret;
}
/* ------------------------------------------------------------------------- */
static void rtc_write (unsigned char reg, unsigned char val)
{
unsigned char dout[2]; /* SPI Output Data Bytes */
unsigned char din[2]; /* SPI Input Data Bytes */
dout[0] = 0x80 | reg;
dout[1] = val;
spi_xfer (slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END);
}
#endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */

122
drivers/rtc/ftrtc010.c
View file

@ -1,122 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Faraday FTRTC010 Real Time Clock
*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*/
#include <config.h>
#include <common.h>
#include <log.h>
#include <rtc.h>
#include <asm/io.h>
struct ftrtc010 {
unsigned int sec; /* 0x00 */
unsigned int min; /* 0x04 */
unsigned int hour; /* 0x08 */
unsigned int day; /* 0x0c */
unsigned int alarm_sec; /* 0x10 */
unsigned int alarm_min; /* 0x14 */
unsigned int alarm_hour; /* 0x18 */
unsigned int record; /* 0x1c */
unsigned int cr; /* 0x20 */
unsigned int wsec; /* 0x24 */
unsigned int wmin; /* 0x28 */
unsigned int whour; /* 0x2c */
unsigned int wday; /* 0x30 */
unsigned int intr; /* 0x34 */
unsigned int div; /* 0x38 */
unsigned int rev; /* 0x3c */
};
/*
* RTC Control Register
*/
#define FTRTC010_CR_ENABLE (1 << 0)
#define FTRTC010_CR_INTERRUPT_SEC (1 << 1) /* per second irq */
#define FTRTC010_CR_INTERRUPT_MIN (1 << 2) /* per minute irq */
#define FTRTC010_CR_INTERRUPT_HR (1 << 3) /* per hour irq */
#define FTRTC010_CR_INTERRUPT_DAY (1 << 4) /* per day irq */
static struct ftrtc010 *rtc = (struct ftrtc010 *)CONFIG_FTRTC010_BASE;
static void ftrtc010_enable(void)
{
writel(FTRTC010_CR_ENABLE, &rtc->cr);
}
/*
* return current time in seconds
*/
static unsigned long ftrtc010_time(void)
{
unsigned long day;
unsigned long hour;
unsigned long minute;
unsigned long second;
unsigned long second2;
do {
second = readl(&rtc->sec);
day = readl(&rtc->day);
hour = readl(&rtc->hour);
minute = readl(&rtc->min);
second2 = readl(&rtc->sec);
} while (second != second2);
return day * 24 * 60 * 60 + hour * 60 * 60 + minute * 60 + second;
}
/*
* Get the current time from the RTC
*/
int rtc_get(struct rtc_time *tmp)
{
unsigned long now;
debug("%s(): record register: %x\n",
__func__, readl(&rtc->record));
#ifdef CFG_FTRTC010_PCLK
now = (ftrtc010_time() + readl(&rtc->record)) / RTC_DIV_COUNT;
#else /* CFG_FTRTC010_EXTCLK */
now = ftrtc010_time() + readl(&rtc->record);
#endif
rtc_to_tm(now, tmp);
return 0;
}
/*
* Set the RTC
*/
int rtc_set(struct rtc_time *tmp)
{
unsigned long new;
unsigned long now;
debug("%s(): DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
__func__,
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
new = rtc_mktime(tmp);
now = ftrtc010_time();
debug("%s(): write %lx to record register\n", __func__, new - now);
writel(new - now, &rtc->record);
return 0;
}
void rtc_reset(void)
{
debug("%s()\n", __func__);
ftrtc010_enable();
}

223
drivers/rtc/imxdi.c
View file

@ -1,223 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2009-2012 ADVANSEE
* Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
*
* Based on the Linux rtc-imxdi.c driver, which is:
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2010 Orex Computed Radiography
*/
/*
* Date & Time support for Freescale i.MX DryIce RTC
*/
#include <common.h>
#include <command.h>
#include <linux/compat.h>
#include <rtc.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
/* DryIce Register Definitions */
struct imxdi_regs {
u32 dtcmr; /* Time Counter MSB Reg */
u32 dtclr; /* Time Counter LSB Reg */
u32 dcamr; /* Clock Alarm MSB Reg */
u32 dcalr; /* Clock Alarm LSB Reg */
u32 dcr; /* Control Reg */
u32 dsr; /* Status Reg */
u32 dier; /* Interrupt Enable Reg */
};
#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
#define DCR_TCE (1 << 3) /* Time Counter Enable */
#define DSR_WBF (1 << 10) /* Write Busy Flag */
#define DSR_WNF (1 << 9) /* Write Next Flag */
#define DSR_WCF (1 << 8) /* Write Complete Flag */
#define DSR_WEF (1 << 7) /* Write Error Flag */
#define DSR_CAF (1 << 4) /* Clock Alarm Flag */
#define DSR_NVF (1 << 1) /* Non-Valid Flag */
#define DSR_SVF (1 << 0) /* Security Violation Flag */
#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */
#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */
#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */
#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */
/* Driver Private Data */
struct imxdi_data {
struct imxdi_regs __iomem *regs;
int init_done;
};
static struct imxdi_data data;
/*
* This function attempts to clear the dryice write-error flag.
*
* A dryice write error is similar to a bus fault and should not occur in
* normal operation. Clearing the flag requires another write, so the root
* cause of the problem may need to be fixed before the flag can be cleared.
*/
static void clear_write_error(void)
{
int cnt;
puts("### Warning: RTC - Register write error!\n");
/* clear the write error flag */
__raw_writel(DSR_WEF, &data.regs->dsr);
/* wait for it to take effect */
for (cnt = 0; cnt < 1000; cnt++) {
if ((__raw_readl(&data.regs->dsr) & DSR_WEF) == 0)
return;
udelay(10);
}
puts("### Error: RTC - Cannot clear write-error flag!\n");
}
/*
* Write a dryice register and wait until it completes.
*
* Use interrupt flags to determine when the write has completed.
*/
#define DI_WRITE_WAIT(val, reg) \
( \
/* do the register write */ \
__raw_writel((val), &data.regs->reg), \
\
di_write_wait((val), #reg) \
)
static int di_write_wait(u32 val, const char *reg)
{
int cnt;
int ret = 0;
int rc = 0;
/* wait for the write to finish */
for (cnt = 0; cnt < 100; cnt++) {
if ((__raw_readl(&data.regs->dsr) & (DSR_WCF | DSR_WEF)) != 0) {
ret = 1;
break;
}
udelay(10);
}
if (ret == 0)
printf("### Warning: RTC - Write-wait timeout "
"val = 0x%.8x reg = %s\n", val, reg);
/* check for write error */
if (__raw_readl(&data.regs->dsr) & DSR_WEF) {
clear_write_error();
rc = -1;
}
return rc;
}
/*
* Initialize dryice hardware
*/
static int di_init(void)
{
int rc = 0;
data.regs = (struct imxdi_regs __iomem *)IMX_DRYICE_BASE;
/* mask all interrupts */
__raw_writel(0, &data.regs->dier);
/* put dryice into valid state */
if (__raw_readl(&data.regs->dsr) & DSR_NVF) {
rc = DI_WRITE_WAIT(DSR_NVF | DSR_SVF, dsr);
if (rc)
goto err;
}
/* initialize alarm */
rc = DI_WRITE_WAIT(DCAMR_UNSET, dcamr);
if (rc)
goto err;
rc = DI_WRITE_WAIT(0, dcalr);
if (rc)
goto err;
/* clear alarm flag */
if (__raw_readl(&data.regs->dsr) & DSR_CAF) {
rc = DI_WRITE_WAIT(DSR_CAF, dsr);
if (rc)
goto err;
}
/* the timer won't count if it has never been written to */
if (__raw_readl(&data.regs->dtcmr) == 0) {
rc = DI_WRITE_WAIT(0, dtcmr);
if (rc)
goto err;
}
/* start keeping time */
if (!(__raw_readl(&data.regs->dcr) & DCR_TCE)) {
rc = DI_WRITE_WAIT(__raw_readl(&data.regs->dcr) | DCR_TCE, dcr);
if (rc)
goto err;
}
data.init_done = 1;
return 0;
err:
return rc;
}
int rtc_get(struct rtc_time *tmp)
{
unsigned long now;
int rc = 0;
if (!data.init_done) {
rc = di_init();
if (rc)
goto err;
}
now = __raw_readl(&data.regs->dtcmr);
rtc_to_tm(now, tmp);
err:
return rc;
}
int rtc_set(struct rtc_time *tmp)
{
unsigned long now;
int rc;
if (!data.init_done) {
rc = di_init();
if (rc)
goto err;
}
now = rtc_mktime(tmp);
/* zero the fractional part first */
rc = DI_WRITE_WAIT(0, dtclr);
if (rc == 0)
rc = DI_WRITE_WAIT(now, dtcmr);
err:
return rc;
}
void rtc_reset(void)
{
di_init();
}

105
drivers/rtc/max6900.c
View file

@ -1,105 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
/*
* Date & Time support for MAXIM MAX6900 RTC
*/
/* #define DEBUG */
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <i2c.h>
#include <linux/delay.h>
#ifndef CFG_SYS_I2C_RTC_ADDR
#define CFG_SYS_I2C_RTC_ADDR 0x50
#endif
/* ------------------------------------------------------------------------- */
static uchar rtc_read (uchar reg)
{
return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write (uchar reg, uchar val)
{
i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
udelay(2500);
}
/* ------------------------------------------------------------------------- */
int rtc_get (struct rtc_time *tmp)
{
uchar sec, min, hour, mday, wday, mon, cent, year;
int retry = 1;
do {
sec = rtc_read (0x80);
min = rtc_read (0x82);
hour = rtc_read (0x84);
mday = rtc_read (0x86);
mon = rtc_read (0x88);
wday = rtc_read (0x8a);
year = rtc_read (0x8c);
cent = rtc_read (0x92);
/*
* Check for seconds rollover
*/
if ((sec != 59) || (rtc_read(0x80) == sec)){
retry = 0;
}
} while (retry);
debug ( "Get RTC year: %02x mon: %02x cent: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x\n",
year, mon, cent, mday, wday,
hour, min, sec );
tmp->tm_sec = bcd2bin (sec & 0x7F);
tmp->tm_min = bcd2bin (min & 0x7F);
tmp->tm_hour = bcd2bin (hour & 0x3F);
tmp->tm_mday = bcd2bin (mday & 0x3F);
tmp->tm_mon = bcd2bin (mon & 0x1F);
tmp->tm_year = bcd2bin (year) + bcd2bin(cent) * 100;
tmp->tm_wday = bcd2bin (wday & 0x07);
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return 0;
}
int rtc_set (struct rtc_time *tmp)
{
debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
rtc_write (0x9E, 0x00);
rtc_write (0x80, 0); /* Clear seconds to ensure no rollover */
rtc_write (0x92, bin2bcd(tmp->tm_year / 100));
rtc_write (0x8c, bin2bcd(tmp->tm_year % 100));
rtc_write (0x8a, bin2bcd(tmp->tm_wday));
rtc_write (0x88, bin2bcd(tmp->tm_mon));
rtc_write (0x86, bin2bcd(tmp->tm_mday));
rtc_write (0x84, bin2bcd(tmp->tm_hour));
rtc_write (0x82, bin2bcd(tmp->tm_min ));
rtc_write (0x80, bin2bcd(tmp->tm_sec ));
return 0;
}
void rtc_reset (void)
{
}

175
drivers/rtc/mk48t59.c
View file

@ -1,175 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Andreas Heppel <aheppel@sysgo.de>
*/
/*
* Date & Time support for the MK48T59 RTC
*/
#undef RTC_DEBUG
#include <common.h>
#include <command.h>
#include <config.h>
#include <rtc.h>
#include <mk48t59.h>
#if defined(CONFIG_BAB7xx)
static uchar rtc_read (short reg)
{
out8(RTC_PORT_ADDR0, reg & 0xFF);
out8(RTC_PORT_ADDR1, (reg>>8) & 0xFF);
return in8(RTC_PORT_DATA);
}
static void rtc_write (short reg, uchar val)
{
out8(RTC_PORT_ADDR0, reg & 0xFF);
out8(RTC_PORT_ADDR1, (reg>>8) & 0xFF);
out8(RTC_PORT_DATA, val);
}
#elif defined(CONFIG_EVAL5200)
static uchar rtc_read (short reg)
{
return in8(RTC(reg));
}
static void rtc_write (short reg, uchar val)
{
out8(RTC(reg),val);
}
#else
# error Board specific rtc access functions should be supplied
#endif
/* ------------------------------------------------------------------------- */
void *nvram_read(void *dest, const short src, size_t count)
{
uchar *d = (uchar *) dest;
short s = src;
while (count--)
*d++ = rtc_read(s++);
return dest;
}
void nvram_write(short dest, const void *src, size_t count)
{
short d = dest;
uchar *s = (uchar *) src;
while (count--)
rtc_write(d++, *s++);
}
/* ------------------------------------------------------------------------- */
int rtc_get (struct rtc_time *tmp)
{
uchar save_ctrl_a;
uchar sec, min, hour, mday, wday, mon, year;
/* Simple: freeze the clock, read it and allow updates again */
save_ctrl_a = rtc_read(RTC_CONTROLA);
/* Set the register to read the value. */
save_ctrl_a |= RTC_CA_READ;
rtc_write(RTC_CONTROLA, save_ctrl_a);
sec = rtc_read (RTC_SECONDS);
min = rtc_read (RTC_MINUTES);
hour = rtc_read (RTC_HOURS);
mday = rtc_read (RTC_DAY_OF_MONTH);
wday = rtc_read (RTC_DAY_OF_WEEK);
mon = rtc_read (RTC_MONTH);
year = rtc_read (RTC_YEAR);
/* re-enable update */
save_ctrl_a &= ~RTC_CA_READ;
rtc_write(RTC_CONTROLA, save_ctrl_a);
#ifdef RTC_DEBUG
printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x\n",
year, mon, mday, wday,
hour, min, sec );
#endif
tmp->tm_sec = bcd2bin (sec & 0x7F);
tmp->tm_min = bcd2bin (min & 0x7F);
tmp->tm_hour = bcd2bin (hour & 0x3F);
tmp->tm_mday = bcd2bin (mday & 0x3F);
tmp->tm_mon = bcd2bin (mon & 0x1F);
tmp->tm_year = bcd2bin (year);
tmp->tm_wday = bcd2bin (wday & 0x07);
if(tmp->tm_year<70)
tmp->tm_year+=2000;
else
tmp->tm_year+=1900;
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
#ifdef RTC_DEBUG
printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
return 0;
}
int rtc_set (struct rtc_time *tmp)
{
uchar save_ctrl_a;
#ifdef RTC_DEBUG
printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
save_ctrl_a = rtc_read(RTC_CONTROLA);
save_ctrl_a |= RTC_CA_WRITE;
rtc_write(RTC_CONTROLA, save_ctrl_a); /* disables the RTC to update the regs */
rtc_write (RTC_YEAR, bin2bcd(tmp->tm_year % 100));
rtc_write (RTC_MONTH, bin2bcd(tmp->tm_mon));
rtc_write (RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday));
rtc_write (RTC_DAY_OF_MONTH, bin2bcd(tmp->tm_mday));
rtc_write (RTC_HOURS, bin2bcd(tmp->tm_hour));
rtc_write (RTC_MINUTES, bin2bcd(tmp->tm_min ));
rtc_write (RTC_SECONDS, bin2bcd(tmp->tm_sec ));
save_ctrl_a &= ~RTC_CA_WRITE;
rtc_write(RTC_CONTROLA, save_ctrl_a); /* enables the RTC to update the regs */
return 0;
}
void rtc_reset (void)
{
uchar control_b;
/*
* Start oscillator here.
*/
control_b = rtc_read(RTC_CONTROLB);
control_b &= ~RTC_CB_STOP;
rtc_write(RTC_CONTROLB, control_b);
}
void rtc_set_watchdog(short multi, short res)
{
uchar wd_value;
wd_value = RTC_WDS | ((multi & 0x1F) << 2) | (res & 0x3);
rtc_write(RTC_WATCHDOG, wd_value);
}

64
drivers/rtc/mx27rtc.c
View file

@ -1,64 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Freescale i.MX27 RTC Driver
*
* Copyright (C) 2012 Philippe Reynes <tremyfr@yahoo.fr>
*/
#include <common.h>
#include <rtc.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#define HOUR_SHIFT 8
#define HOUR_MASK 0x1f
#define MIN_SHIFT 0
#define MIN_MASK 0x3f
int rtc_get(struct rtc_time *time)
{
struct rtc_regs *rtc_regs = (struct rtc_regs *)IMX_RTC_BASE;
uint32_t day, hour, min, sec;
day = readl(&rtc_regs->dayr);
hour = readl(&rtc_regs->hourmin);
sec = readl(&rtc_regs->seconds);
min = (hour >> MIN_SHIFT) & MIN_MASK;
hour = (hour >> HOUR_SHIFT) & HOUR_MASK;
sec += min * 60 + hour * 3600 + day * 24 * 3600;
rtc_to_tm(sec, time);
return 0;
}
int rtc_set(struct rtc_time *time)
{
struct rtc_regs *rtc_regs = (struct rtc_regs *)IMX_RTC_BASE;
uint32_t day, hour, min, sec;
sec = rtc_mktime(time);
day = sec / (24 * 3600);
sec = sec % (24 * 3600);
hour = sec / 3600;
sec = sec % 3600;
min = sec / 60;
sec = sec % 60;
hour = (hour & HOUR_MASK) << HOUR_SHIFT;
hour |= (min & MIN_MASK) << MIN_SHIFT;
writel(day, &rtc_regs->dayr);
writel(hour, &rtc_regs->hourmin);
writel(sec, &rtc_regs->seconds);
return 0;
}
void rtc_reset(void)
{
/* nothing to do */
}

256
drivers/rtc/rs5c372.c
View file

@ -1,256 +0,0 @@
/*
* rs5c372.c
*
* Device driver for Ricoh's Real Time Controller RS5C372A.
*
* Copyright (C) 2004 Gary Jennejohn garyj@denx.de
*
* Based in part in ds1307.c -
* (C) Copyright 2001, 2002, 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* Keith Outwater, keith_outwater@mvis.com`
* Steven Scholz, steven.scholz@imc-berlin.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <i2c.h>
/*
* Reads are always done starting with register 15, which requires some
* jumping-through-hoops to access the data correctly.
*
* Writes are always done starting with register 0.
*/
#define DEBUG 0
#if DEBUG
static unsigned int rtc_debug = DEBUG;
#else
#define rtc_debug 0 /* gcc will remove all the debug code for us */
#endif
#ifndef CFG_SYS_I2C_RTC_ADDR
#define CFG_SYS_I2C_RTC_ADDR 0x32
#endif
#define RS5C372_RAM_SIZE 0x10
#define RATE_32000HZ 0x80 /* Rate Select 32.000KHz */
#define RATE_32768HZ 0x00 /* Rate Select 32.768KHz */
#define STATUS_XPT 0x10 /* data invalid because voltage was 0 */
#define USE_24HOUR_MODE 0x20
#define TWELVE_HOUR_MODE(n) ((((n) >> 5) & 1) == 0)
#define HOURS_AP(n) (((n) >> 5) & 1)
#define HOURS_12(n) bcd2bin((n) & 0x1F)
#define HOURS_24(n) bcd2bin((n) & 0x3F)
static int setup_done = 0;
static int
rs5c372_readram(unsigned char *buf, int len)
{
int ret;
ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, len);
if (ret != 0) {
printf("%s: failed to read\n", __FUNCTION__);
return ret;
}
if (buf[0] & STATUS_XPT)
printf("### Warning: RTC lost power\n");
return ret;
}
static void
rs5c372_enable(void)
{
unsigned char buf[RS5C372_RAM_SIZE + 1];
int ret;
/* note that this returns reg. 15 in buf[1] */
ret = rs5c372_readram(&buf[1], RS5C372_RAM_SIZE);
if (ret != 0) {
printf("%s: failed\n", __FUNCTION__);
return;
}
buf[0] = 0;
/* we want to start writing at register 0 so we have to copy the */
/* register contents up one slot */
for (ret = 2; ret < 9; ret++)
buf[ret - 1] = buf[ret];
/* registers 0 to 6 (time values) are not touched */
buf[8] = RATE_32768HZ; /* reg. 7 */
buf[9] = 0; /* reg. 8 */
buf[10] = 0; /* reg. 9 */
buf[11] = 0; /* reg. 10 */
buf[12] = 0; /* reg. 11 */
buf[13] = 0; /* reg. 12 */
buf[14] = 0; /* reg. 13 */
buf[15] = 0; /* reg. 14 */
buf[16] = USE_24HOUR_MODE; /* reg. 15 */
ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1);
if (ret != 0) {
printf("%s: failed\n", __FUNCTION__);
return;
}
setup_done = 1;
return;
}
static void
rs5c372_convert_to_time(struct rtc_time *dt, unsigned char *buf)
{
/* buf[0] is register 15 */
dt->tm_sec = bcd2bin(buf[1]);
dt->tm_min = bcd2bin(buf[2]);
if (TWELVE_HOUR_MODE(buf[0])) {
dt->tm_hour = HOURS_12(buf[3]);
if (HOURS_AP(buf[3])) /* PM */
dt->tm_hour += 12;
} else /* 24-hour-mode */
dt->tm_hour = HOURS_24(buf[3]);
dt->tm_mday = bcd2bin(buf[5]);
dt->tm_mon = bcd2bin(buf[6]);
dt->tm_year = bcd2bin(buf[7]);
if (dt->tm_year >= 70)
dt->tm_year += 1900;
else
dt->tm_year += 2000;
/* 0 is Sunday */
dt->tm_wday = bcd2bin(buf[4] & 0x07);
dt->tm_yday = 0;
dt->tm_isdst= 0;
if(rtc_debug > 2) {
printf("rs5c372_convert_to_time: year = %d\n", dt->tm_year);
printf("rs5c372_convert_to_time: mon = %d\n", dt->tm_mon);
printf("rs5c372_convert_to_time: mday = %d\n", dt->tm_mday);
printf("rs5c372_convert_to_time: hour = %d\n", dt->tm_hour);
printf("rs5c372_convert_to_time: min = %d\n", dt->tm_min);
printf("rs5c372_convert_to_time: sec = %d\n", dt->tm_sec);
}
}
/*
* Get the current time from the RTC
*/
int
rtc_get (struct rtc_time *tmp)
{
unsigned char buf[RS5C372_RAM_SIZE];
int ret;
if (!setup_done)
rs5c372_enable();
if (!setup_done)
return -1;
memset(buf, 0, sizeof(buf));
/* note that this returns reg. 15 in buf[0] */
ret = rs5c372_readram(buf, RS5C372_RAM_SIZE);
if (ret != 0) {
printf("%s: failed\n", __FUNCTION__);
return -1;
}
rs5c372_convert_to_time(tmp, buf);
return 0;
}
/*
* Set the RTC
*/
int rtc_set (struct rtc_time *tmp)
{
unsigned char buf[8], reg15;
int ret;
if (!setup_done)
rs5c372_enable();
if (!setup_done)
return -1;
if(rtc_debug > 2) {
printf("rtc_set: tm_year = %d\n", tmp->tm_year);
printf("rtc_set: tm_mon = %d\n", tmp->tm_mon);
printf("rtc_set: tm_mday = %d\n", tmp->tm_mday);
printf("rtc_set: tm_hour = %d\n", tmp->tm_hour);
printf("rtc_set: tm_min = %d\n", tmp->tm_min);
printf("rtc_set: tm_sec = %d\n", tmp->tm_sec);
}
memset(buf, 0, sizeof(buf));
/* only read register 15 */
ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1);
if (ret == 0) {
/* need to save register 15 */
reg15 = buf[0];
buf[0] = 0; /* register address on RS5C372 */
buf[1] = bin2bcd(tmp->tm_sec);
buf[2] = bin2bcd(tmp->tm_min);
/* need to handle 12 hour mode */
if (TWELVE_HOUR_MODE(reg15)) {
if (tmp->tm_hour >= 12) { /* PM */
/* 12 PM is a special case */
if (tmp->tm_hour == 12)
buf[3] = bin2bcd(tmp->tm_hour);
else
buf[3] = bin2bcd(tmp->tm_hour - 12);
buf[3] |= 0x20;
}
} else {
buf[3] = bin2bcd(tmp->tm_hour);
}
buf[4] = bin2bcd(tmp->tm_wday);
buf[5] = bin2bcd(tmp->tm_mday);
buf[6] = bin2bcd(tmp->tm_mon);
if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
printf("WARNING: year should be between 1970 and 2069!\n");
buf[7] = bin2bcd(tmp->tm_year % 100);
ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8);
if (ret != 0) {
printf("rs5c372_set_datetime(), i2c_master_send() returned %d\n",ret);
return -1;
}
} else {
return -1;
}
return 0;
}
/*
* Reset the RTC.
*/
void
rtc_reset (void)
{
if (!setup_done)
rs5c372_enable();
}

149
drivers/rtc/s3c24x0_rtc.c
View file

@ -1,149 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2003
* David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
*/
/*
* Date & Time support for the built-in Samsung S3C24X0 RTC
*/
#include <common.h>
#include <command.h>
#include <asm/arch/s3c24x0_cpu.h>
#include <rtc.h>
#include <asm/io.h>
#include <linux/compiler.h>
typedef enum {
RTC_ENABLE,
RTC_DISABLE
} RTC_ACCESS;
static inline void SetRTC_Access(RTC_ACCESS a)
{
struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc();
switch (a) {
case RTC_ENABLE:
writeb(readb(&rtc->rtccon) | 0x01, &rtc->rtccon);
break;
case RTC_DISABLE:
writeb(readb(&rtc->rtccon) & ~0x01, &rtc->rtccon);
break;
}
}
/* ------------------------------------------------------------------------- */
int rtc_get(struct rtc_time *tmp)
{
struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc();
uchar sec, min, hour, mday, wday, mon, year;
__maybe_unused uchar a_sec, a_min, a_hour, a_date,
a_mon, a_year, a_armed;
/* enable access to RTC registers */
SetRTC_Access(RTC_ENABLE);
/* read RTC registers */
do {
sec = readb(&rtc->bcdsec);
min = readb(&rtc->bcdmin);
hour = readb(&rtc->bcdhour);
mday = readb(&rtc->bcddate);
wday = readb(&rtc->bcdday);
mon = readb(&rtc->bcdmon);
year = readb(&rtc->bcdyear);
} while (sec != readb(&rtc->bcdsec));
/* read ALARM registers */
a_sec = readb(&rtc->almsec);
a_min = readb(&rtc->almmin);
a_hour = readb(&rtc->almhour);
a_date = readb(&rtc->almdate);
a_mon = readb(&rtc->almmon);
a_year = readb(&rtc->almyear);
a_armed = readb(&rtc->rtcalm);
/* disable access to RTC registers */
SetRTC_Access(RTC_DISABLE);
#ifdef RTC_DEBUG
printf("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x\n",
year, mon, mday, wday, hour, min, sec);
printf("Alarms: %02x: year: %02x month: %02x date: %02x hour: "
"%02x min: %02x sec: %02x\n",
a_armed, a_year, a_mon, a_date, a_hour, a_min, a_sec);
#endif
tmp->tm_sec = bcd2bin(sec & 0x7F);
tmp->tm_min = bcd2bin(min & 0x7F);
tmp->tm_hour = bcd2bin(hour & 0x3F);
tmp->tm_mday = bcd2bin(mday & 0x3F);
tmp->tm_mon = bcd2bin(mon & 0x1F);
tmp->tm_year = bcd2bin(year);
tmp->tm_wday = bcd2bin(wday & 0x07);
if (tmp->tm_year < 70)
tmp->tm_year += 2000;
else
tmp->tm_year += 1900;
tmp->tm_yday = 0;
tmp->tm_isdst = 0;
#ifdef RTC_DEBUG
printf("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
return 0;
}
int rtc_set(struct rtc_time *tmp)
{
struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc();
uchar sec, min, hour, mday, wday, mon, year;
#ifdef RTC_DEBUG
printf("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
year = bin2bcd(tmp->tm_year % 100);
mon = bin2bcd(tmp->tm_mon);
wday = bin2bcd(tmp->tm_wday);
mday = bin2bcd(tmp->tm_mday);
hour = bin2bcd(tmp->tm_hour);
min = bin2bcd(tmp->tm_min);
sec = bin2bcd(tmp->tm_sec);
/* enable access to RTC registers */
SetRTC_Access(RTC_ENABLE);
/* write RTC registers */
writeb(sec, &rtc->bcdsec);
writeb(min, &rtc->bcdmin);
writeb(hour, &rtc->bcdhour);
writeb(mday, &rtc->bcddate);
writeb(wday, &rtc->bcdday);
writeb(mon, &rtc->bcdmon);
writeb(year, &rtc->bcdyear);
/* disable access to RTC registers */
SetRTC_Access(RTC_DISABLE);
return 0;
}
void rtc_reset(void)
{
struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc();
writeb((readb(&rtc->rtccon) & ~0x06) | 0x08, &rtc->rtccon);
writeb(readb(&rtc->rtccon) & ~(0x08 | 0x01), &rtc->rtccon);
}

161
drivers/rtc/x1205.c
View file

@ -1,161 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* based on a the Linux rtc-x1207.c driver which is:
* Copyright 2004 Karen Spearel
* Copyright 2005 Alessandro Zummo
*
* Information and datasheet:
* http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
*/
/*
* Date & Time support for Xicor/Intersil X1205 RTC
*/
/* #define DEBUG */
#include <common.h>
#include <command.h>
#include <log.h>
#include <rtc.h>
#include <i2c.h>
#define CCR_SEC 0
#define CCR_MIN 1
#define CCR_HOUR 2
#define CCR_MDAY 3
#define CCR_MONTH 4
#define CCR_YEAR 5
#define CCR_WDAY 6
#define CCR_Y2K 7
#define X1205_REG_SR 0x3F /* status register */
#define X1205_REG_Y2K 0x37
#define X1205_REG_DW 0x36
#define X1205_REG_YR 0x35
#define X1205_REG_MO 0x34
#define X1205_REG_DT 0x33
#define X1205_REG_HR 0x32
#define X1205_REG_MN 0x31
#define X1205_REG_SC 0x30
#define X1205_REG_DTR 0x13
#define X1205_REG_ATR 0x12
#define X1205_REG_INT 0x11
#define X1205_REG_0 0x10
#define X1205_REG_Y2K1 0x0F
#define X1205_REG_DWA1 0x0E
#define X1205_REG_YRA1 0x0D
#define X1205_REG_MOA1 0x0C
#define X1205_REG_DTA1 0x0B
#define X1205_REG_HRA1 0x0A
#define X1205_REG_MNA1 0x09
#define X1205_REG_SCA1 0x08
#define X1205_REG_Y2K0 0x07
#define X1205_REG_DWA0 0x06
#define X1205_REG_YRA0 0x05
#define X1205_REG_MOA0 0x04
#define X1205_REG_DTA0 0x03
#define X1205_REG_HRA0 0x02
#define X1205_REG_MNA0 0x01
#define X1205_REG_SCA0 0x00
#define X1205_CCR_BASE 0x30 /* Base address of CCR */
#define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */
#define X1205_SR_RTCF 0x01 /* Clock failure */
#define X1205_SR_WEL 0x02 /* Write Enable Latch */
#define X1205_SR_RWEL 0x04 /* Register Write Enable */
#define X1205_DTR_DTR0 0x01
#define X1205_DTR_DTR1 0x02
#define X1205_DTR_DTR2 0x04
#define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */
static void rtc_write(int reg, u8 val)
{
i2c_write(CFG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1);
}
/*
* In the routines that deal directly with the x1205 hardware, we use
* rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
* Epoch is initialized as 2000. Time is set to UTC.
*/
int rtc_get(struct rtc_time *tm)
{
u8 buf[8];
i2c_read(CFG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8);
debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
__FUNCTION__,
buf[0], buf[1], buf[2], buf[3],
buf[4], buf[5], buf[6], buf[7]);
tm->tm_sec = bcd2bin(buf[CCR_SEC]);
tm->tm_min = bcd2bin(buf[CCR_MIN]);
tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
tm->tm_mday = bcd2bin(buf[CCR_MDAY]);
tm->tm_mon = bcd2bin(buf[CCR_MONTH]); /* mon is 0-11 */
tm->tm_year = bcd2bin(buf[CCR_YEAR])
+ (bcd2bin(buf[CCR_Y2K]) * 100);
tm->tm_wday = buf[CCR_WDAY];
debug("%s: tm is secs=%d, mins=%d, hours=%d, "
"mday=%d, mon=%d, year=%d, wday=%d\n",
__FUNCTION__,
tm->tm_sec, tm->tm_min, tm->tm_hour,
tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
return 0;
}
int rtc_set(struct rtc_time *tm)
{
int i;
u8 buf[8];
debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
tm->tm_hour, tm->tm_min, tm->tm_sec);
buf[CCR_SEC] = bin2bcd(tm->tm_sec);
buf[CCR_MIN] = bin2bcd(tm->tm_min);
/* set hour and 24hr bit */
buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL;
buf[CCR_MDAY] = bin2bcd(tm->tm_mday);
/* month, 1 - 12 */
buf[CCR_MONTH] = bin2bcd(tm->tm_mon);
/* year, since the rtc epoch*/
buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100);
buf[CCR_WDAY] = tm->tm_wday & 0x07;
buf[CCR_Y2K] = bin2bcd(tm->tm_year / 100);
/* this sequence is required to unlock the chip */
rtc_write(X1205_REG_SR, X1205_SR_WEL);
rtc_write(X1205_REG_SR, X1205_SR_WEL | X1205_SR_RWEL);
/* write register's data */
for (i = 0; i < 8; i++)
rtc_write(X1205_CCR_BASE + i, buf[i]);
rtc_write(X1205_REG_SR, 0);
return 0;
}
void rtc_reset(void)
{
/*
* Nothing to do
*/
}

10
drivers/serial/serial_sh.h
View file

@ -13,7 +13,6 @@ struct uart_port {
};
#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
# define PORT_PTCR 0xA405011EUL
@ -149,7 +148,6 @@ struct uart_port {
#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
# define SCIF_ORER 0x0200
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
@ -197,7 +195,6 @@ struct uart_port {
(((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
@ -278,8 +275,7 @@ static inline void sci_##name##_out(struct uart_port *port,\
SCI_OUT(sci_size, sci_offset, value);\
}
#if defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
#if defined(CONFIG_R8A7740)
#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0)
#define SCIF_FNS(name, scif_offset, scif_size) \
@ -323,8 +319,7 @@ static inline void sci_##name##_out(struct uart_port *port,\
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
#endif
#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0)
#if defined(CONFIG_CPU_SH7721)
SCIF_FNS(SCSMR, 0x00, 16)
SCIF_FNS(SCBRR, 0x04, 8)
@ -477,7 +472,6 @@ static inline int sci_rxd_in(struct uart_port *port)
#if defined(CONFIG_CPU_SH7780)
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
#elif defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
#elif defined(CONFIG_CPU_SH7723)

2
drivers/sysreset/Makefile
View file

@ -20,6 +20,6 @@ obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o
obj-$(CONFIG_SYSRESET_$(SPL_TPL_)AT91) += sysreset_at91.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_AT91) += sysreset_at91.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o

3
drivers/usb/gadget/Makefile
View file

@ -19,8 +19,7 @@ obj-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o
obj-$(CONFIG_USB_GADGET_BCM_UDC_OTG_PHY) += bcm_udc_otg_phy.o
obj-$(CONFIG_USB_GADGET_DWC2_OTG) += dwc2_udc_otg.o
obj-$(CONFIG_USB_GADGET_DWC2_OTG_PHY) += dwc2_udc_otg_phy.o
obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o
obj-$(CONFIG_USB_GADGET_MAX3420) += max3420_udc.o
0obj-$(CONFIG_USB_GADGET_MAX3420) += max3420_udc.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_GADGET_DOWNLOAD) += g_dnl.o
obj-$(CONFIG_USB_FUNCTION_THOR) += f_thor.o

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