mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
Merge branch '2022-03-28-critical-fixes'
- A zstd, two Apple M1 and an MXS NAND critical bugfix - Clean up another file that wasn't being removed and update some external documentation links.
This commit is contained in:
Tom Rini
commit
94e836f7dd
9 changed files with 82 additions and 36 deletions
3
Makefile
3
Makefile
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@ -2186,7 +2186,8 @@ CLEAN_DIRS += $(MODVERDIR) \
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$(foreach d, spl tpl, $(patsubst %,$d/%, \
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$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
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CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h tools/version.h \
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CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
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drivers/video/u_boot_logo.S tools/version.h \
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u-boot* MLO* SPL System.map fit-dtb.blob* \
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u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \
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lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \
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@ -6,6 +6,7 @@
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#include <common.h>
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#include <dm.h>
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#include <efi_loader.h>
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#include <lmb.h>
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#include <asm/armv8/mmu.h>
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#include <asm/global_data.h>
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@ -266,32 +267,27 @@ u64 get_page_table_size(void)
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return SZ_256K;
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}
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#define KERNEL_COMP_SIZE SZ_128M
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int board_late_init(void)
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{
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unsigned long base;
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unsigned long top;
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struct lmb lmb;
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u32 status = 0;
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/* Reserve 4M each for scriptaddr and pxefile_addr_r at the top of RAM
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* at least 1M below the stack.
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*/
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top = gd->start_addr_sp - CONFIG_STACK_SIZE - SZ_8M - SZ_1M;
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top = ALIGN_DOWN(top, SZ_8M);
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status |= env_set_hex("scriptaddr", top + SZ_4M);
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status |= env_set_hex("pxefile_addr_r", top);
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lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
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/* somewhat based on the Linux Kernel boot requirements:
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* align by 2M and maximal FDT size 2M
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*/
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base = ALIGN(gd->ram_base, SZ_2M);
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status |= env_set_hex("fdt_addr_r", base);
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status |= env_set_hex("kernel_addr_r", base + SZ_2M);
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status |= env_set_hex("ramdisk_addr_r", base + SZ_128M);
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status |= env_set_hex("loadaddr", base + SZ_2G);
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status |= env_set_hex("kernel_comp_addr_r", base + SZ_2G - SZ_128M);
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status |= env_set_hex("kernel_comp_size", SZ_128M);
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status |= env_set_hex("loadaddr", lmb_alloc(&lmb, SZ_1G, SZ_2M));
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status |= env_set_hex("fdt_addr_r", lmb_alloc(&lmb, SZ_2M, SZ_2M));
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status |= env_set_hex("kernel_addr_r", lmb_alloc(&lmb, SZ_128M, SZ_2M));
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status |= env_set_hex("ramdisk_addr_r", lmb_alloc(&lmb, SZ_1G, SZ_2M));
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status |= env_set_hex("kernel_comp_addr_r",
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lmb_alloc(&lmb, KERNEL_COMP_SIZE, SZ_2M));
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status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE);
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status |= env_set_hex("scriptaddr", lmb_alloc(&lmb, SZ_4M, SZ_2M));
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status |= env_set_hex("pxefile_addr_r", lmb_alloc(&lmb, SZ_4M, SZ_2M));
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if (status)
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log_warning("late_init: Failed to set run time variables\n");
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@ -170,7 +170,7 @@ wait_epmap:
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pwrstate = APPLE_RTKIT_PWR_STATE_SLEEP;
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while (pwrstate != APPLE_RTKIT_PWR_STATE_ON) {
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ret = mbox_recv(chan, &msg, 100000);
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ret = mbox_recv(chan, &msg, 1000000);
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if (ret < 0)
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return ret;
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@ -500,7 +500,7 @@ int image_decomp(int comp, ulong load, ulong image_start, int type,
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struct abuf in, out;
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abuf_init_set(&in, image_buf, image_len);
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abuf_init_set(&in, load_buf, unc_len);
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abuf_init_set(&out, load_buf, unc_len);
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ret = zstd_decompress(&in, &out);
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if (ret >= 0) {
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image_len = ret;
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@ -14,7 +14,7 @@ Where to get boot_format:
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========================
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you can browse it online at:
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http://git.freescale.com/git/cgit.cgi/ppc/sdk/boot-format.git/
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https://source.codeaurora.org/external/qoriq/qoriq-yocto-sdk/boot-format
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Building
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========
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@ -6,7 +6,7 @@
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* Based on Dirk Behme's
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* https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
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* which is based on Freescale's
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* http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
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* https://source.codeaurora.org/external/imx/uboot-imx/tree/drivers/misc/imx_otp.c?id=9aa74e6,
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* which is:
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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*/
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@ -195,6 +195,7 @@ static inline int mxs_nand_legacy_calc_ecc_layout(struct bch_geometry *geo,
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
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unsigned int block_mark_bit_offset;
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int corr, ds_corr;
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/* The default for the length of Galois Field. */
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geo->gf_len = 13;
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@ -225,6 +226,17 @@ static inline int mxs_nand_legacy_calc_ecc_layout(struct bch_geometry *geo,
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geo->ecc_strength = min(round_down(geo->ecc_strength, 2),
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nand_info->max_ecc_strength_supported);
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/* check ecc strength, same as nand_ecc_is_strong_enough() did*/
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if (chip->ecc_step_ds) {
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corr = mtd->writesize * geo->ecc_strength /
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geo->ecc_chunkn_size;
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ds_corr = mtd->writesize * chip->ecc_strength_ds /
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chip->ecc_step_ds;
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if (corr < ds_corr ||
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geo->ecc_strength < chip->ecc_strength_ds)
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return -EINVAL;
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}
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block_mark_bit_offset = mtd->writesize * 8 -
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(geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - 1)
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+ MXS_NAND_METADATA_SIZE * 8);
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@ -1111,6 +1123,7 @@ static int mxs_nand_set_geometry(struct mtd_info *mtd, struct bch_geometry *geo)
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct nand_chip *nand = mtd_to_nand(mtd);
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struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
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int err;
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if (chip->ecc_strength_ds > nand_info->max_ecc_strength_supported) {
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printf("unsupported NAND chip, minimum ecc required %d\n"
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@ -1118,19 +1131,57 @@ static int mxs_nand_set_geometry(struct mtd_info *mtd, struct bch_geometry *geo)
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return -EINVAL;
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}
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if ((!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0) &&
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mtd->oobsize < 1024) || nand_info->legacy_bch_geometry) {
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dev_warn(mtd->dev, "use legacy bch geometry\n");
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return mxs_nand_legacy_calc_ecc_layout(geo, mtd);
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/* use the legacy bch setting by default */
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if ((!nand_info->use_minimum_ecc && mtd->oobsize < 1024) ||
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!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0)) {
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dev_dbg(mtd->dev, "use legacy bch geometry\n");
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err = mxs_nand_legacy_calc_ecc_layout(geo, mtd);
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if (!err)
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return 0;
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}
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if (mtd->oobsize > 1024 || chip->ecc_step_ds < mtd->oobsize)
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return mxs_nand_calc_ecc_for_large_oob(geo, mtd);
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/* for large oob nand */
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if (mtd->oobsize > 1024) {
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dev_dbg(mtd->dev, "use large oob bch geometry\n");
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err = mxs_nand_calc_ecc_for_large_oob(geo, mtd);
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if (!err)
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return 0;
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}
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return mxs_nand_calc_ecc_layout_by_info(geo, mtd,
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chip->ecc_strength_ds, chip->ecc_step_ds);
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/* otherwise use the minimum ecc nand chips required */
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dev_dbg(mtd->dev, "use minimum ecc bch geometry\n");
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err = mxs_nand_calc_ecc_layout_by_info(geo, mtd, chip->ecc_strength_ds,
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chip->ecc_step_ds);
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return 0;
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if (err)
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dev_err(mtd->dev, "none of the bch geometry setting works\n");
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return err;
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}
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void mxs_nand_dump_geo(struct mtd_info *mtd)
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{
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struct nand_chip *nand = mtd_to_nand(mtd);
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struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
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struct bch_geometry *geo = &nand_info->bch_geometry;
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dev_dbg(mtd->dev, "BCH Geometry :\n"
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"GF Length\t\t: %u\n"
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"ECC Strength\t\t: %u\n"
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"ECC for Meta\t\t: %u\n"
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"ECC Chunk0 Size\t\t: %u\n"
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"ECC Chunkn Size\t\t: %u\n"
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"ECC Chunk Count\t\t: %u\n"
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"Block Mark Byte Offset\t: %u\n"
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"Block Mark Bit Offset\t: %u\n",
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geo->gf_len,
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geo->ecc_strength,
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geo->ecc_for_meta,
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geo->ecc_chunk0_size,
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geo->ecc_chunkn_size,
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geo->ecc_chunk_count,
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geo->block_mark_byte_offset,
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geo->block_mark_bit_offset);
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}
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/*
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@ -1159,6 +1210,8 @@ int mxs_nand_setup_ecc(struct mtd_info *mtd)
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if (ret)
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return ret;
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mxs_nand_dump_geo(mtd);
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/* Configure BCH and set NFC geometry */
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mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
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@ -92,8 +92,6 @@ static int mxs_nand_dt_probe(struct udevice *dev)
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info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc");
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info->legacy_bch_geometry = dev_read_bool(dev, "fsl,legacy-bch-geometry");
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if (IS_ENABLED(CONFIG_CLK) && IS_ENABLED(CONFIG_IMX8)) {
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/* Assigned clock already set clock */
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struct clk gpmi_clk;
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@ -44,8 +44,6 @@ struct mxs_nand_info {
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struct udevice *dev;
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unsigned int max_ecc_strength_supported;
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bool use_minimum_ecc;
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/* legacy bch geometry flag */
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bool legacy_bch_geometry;
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int cur_chip;
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uint32_t cmd_queue_len;
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