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riscv: Clear pending interrupts before enabling IPIs

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On some platforms (k210), the previous stage bootloader may have not
cleared pending IPIs before transferring control to U-Boot. This can cause
race conditions, as multiple harts all attempt to initialize the IPI
controller at once. This patch clears IPIs before enabling them, ensuring
that only one hart modifies shared memory at once.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Sean Anderson 2020-06-24 06:41:17 -04:00 committed by Andes
parent 309c79f3de
commit 9472630337
1 changed files with 2 additions and 0 deletions
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2
arch/riscv/cpu/start.S
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@ -65,6 +65,8 @@ _start:
#else
li t0, SIE_SSIE
#endif
/* Clear any pending IPIs */
csrc MODE_PREFIX(ip), t0
csrs MODE_PREFIX(ie), t0
#endif