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https://github.com/AsahiLinux/u-boot
synced 2024-11-14 00:47:26 +00:00
ARM: keystone2: Cleanup init_pll definition
This is just a cosmetic change that makes the calling of pll init code looks much cleaner. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
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74af583e9f
commit
94069301ba
5 changed files with 84 additions and 46 deletions
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@ -211,12 +211,16 @@ void init_pll(const struct pll_init_data *data)
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sdelay(210000);
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sdelay(210000);
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}
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}
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void init_plls(int num_pll, struct pll_init_data *config)
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void init_plls(void)
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{
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{
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int i;
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struct pll_init_data *data;
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int pll;
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for (i = 0; i < num_pll; i++)
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for (pll = MAIN_PLL; pll < MAX_PLL_COUNT; pll++) {
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init_pll(&config[i]);
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data = get_pll_init_data(pll);
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if (data)
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init_pll(data);
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}
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}
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}
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static int get_max_speed(u32 val, u32 speed_supported)
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static int get_max_speed(u32 val, u32 speed_supported)
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@ -76,8 +76,9 @@ extern const struct keystone_pll_regs keystone_pll_regs[];
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extern s16 divn_val[];
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extern s16 divn_val[];
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extern int speeds[];
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extern int speeds[];
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void init_plls(int num_pll, struct pll_init_data *config);
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void init_plls(void);
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void init_pll(const struct pll_init_data *data);
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void init_pll(const struct pll_init_data *data);
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struct pll_init_data *get_pll_init_data(int pll);
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unsigned long clk_get_rate(unsigned int clk);
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unsigned long clk_get_rate(unsigned int clk);
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unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
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unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
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int clk_set_rate(unsigned int clk, unsigned long hz);
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int clk_set_rate(unsigned int clk, unsigned long hz);
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@ -59,6 +59,26 @@ s16 divn_val[16] = {
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static struct pll_init_data pa_pll_config =
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static struct pll_init_data pa_pll_config =
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PASS_PLL_1000;
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PASS_PLL_1000;
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struct pll_init_data *get_pll_init_data(int pll)
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{
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int speed;
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struct pll_init_data *data;
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switch (pll) {
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case MAIN_PLL:
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speed = get_max_dev_speed();
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data = &core_pll_config[speed];
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break;
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case PASS_PLL:
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data = &pa_pll_config;
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break;
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default:
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data = NULL;
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}
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return data;
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}
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#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
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#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
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struct eth_priv_t eth_priv_cfg[] = {
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struct eth_priv_t eth_priv_cfg[] = {
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{
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{
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@ -128,24 +148,15 @@ int get_num_eth_ports(void)
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#if defined(CONFIG_BOARD_EARLY_INIT_F)
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#if defined(CONFIG_BOARD_EARLY_INIT_F)
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int board_early_init_f(void)
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int board_early_init_f(void)
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{
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{
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int speed;
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init_plls();
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speed = get_max_dev_speed();
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init_pll(&core_pll_config[speed]);
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init_pll(&pa_pll_config);
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return 0;
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return 0;
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}
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}
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#endif
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#endif
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#ifdef CONFIG_SPL_BUILD
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#ifdef CONFIG_SPL_BUILD
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static struct pll_init_data spl_pll_config[] = {
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CORE_PLL_800,
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};
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void spl_init_keystone_plls(void)
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void spl_init_keystone_plls(void)
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{
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{
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init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
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init_plls();
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}
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}
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#endif
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#endif
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@ -50,6 +50,30 @@ static struct pll_init_data tetris_pll_config[] = {
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static struct pll_init_data pa_pll_config =
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static struct pll_init_data pa_pll_config =
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PASS_PLL_983;
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PASS_PLL_983;
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struct pll_init_data *get_pll_init_data(int pll)
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{
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int speed;
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struct pll_init_data *data;
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switch (pll) {
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case MAIN_PLL:
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speed = get_max_dev_speed();
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data = &core_pll_config[speed];
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break;
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case TETRIS_PLL:
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speed = get_max_arm_speed();
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data = &tetris_pll_config[speed];
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break;
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case PASS_PLL:
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data = &pa_pll_config;
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break;
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default:
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data = NULL;
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}
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return data;
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}
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#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
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#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
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struct eth_priv_t eth_priv_cfg[] = {
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struct eth_priv_t eth_priv_cfg[] = {
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{
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{
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@ -91,28 +115,15 @@ int get_num_eth_ports(void)
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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int board_early_init_f(void)
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{
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{
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int speed;
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init_plls();
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speed = get_max_dev_speed();
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init_pll(&core_pll_config[speed]);
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init_pll(&pa_pll_config);
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speed = get_max_arm_speed();
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init_pll(&tetris_pll_config[speed]);
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return 0;
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return 0;
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}
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}
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#endif
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#endif
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#ifdef CONFIG_SPL_BUILD
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#ifdef CONFIG_SPL_BUILD
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static struct pll_init_data spl_pll_config[] = {
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CORE_PLL_799,
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TETRIS_PLL_500,
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};
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void spl_init_keystone_plls(void)
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void spl_init_keystone_plls(void)
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{
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{
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init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
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init_plls();
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}
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}
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#endif
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#endif
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@ -46,6 +46,30 @@ static struct pll_init_data tetris_pll_config[] = {
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static struct pll_init_data pa_pll_config =
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static struct pll_init_data pa_pll_config =
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PASS_PLL_983;
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PASS_PLL_983;
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struct pll_init_data *get_pll_init_data(int pll)
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{
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int speed;
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struct pll_init_data *data;
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switch (pll) {
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case MAIN_PLL:
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speed = get_max_dev_speed();
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data = &core_pll_config[speed];
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break;
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case TETRIS_PLL:
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speed = get_max_arm_speed();
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data = &tetris_pll_config[speed];
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break;
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case PASS_PLL:
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data = &pa_pll_config;
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break;
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default:
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data = NULL;
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}
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return data;
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}
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#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
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#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
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struct eth_priv_t eth_priv_cfg[] = {
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struct eth_priv_t eth_priv_cfg[] = {
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{
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{
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@ -87,28 +111,15 @@ int get_num_eth_ports(void)
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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int board_early_init_f(void)
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{
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{
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int speed;
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init_plls();
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speed = get_max_dev_speed();
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init_pll(&core_pll_config[speed]);
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init_pll(&pa_pll_config);
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speed = get_max_arm_speed();
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init_pll(&tetris_pll_config[speed]);
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return 0;
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return 0;
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}
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}
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#endif
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#endif
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#ifdef CONFIG_SPL_BUILD
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#ifdef CONFIG_SPL_BUILD
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static struct pll_init_data spl_pll_config[] = {
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CORE_PLL_799,
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TETRIS_PLL_491,
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};
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void spl_init_keystone_plls(void)
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void spl_init_keystone_plls(void)
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{
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{
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init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
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init_plls();
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}
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}
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#endif
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#endif
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