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Tom Rini 2024-01-08 12:00:18 -05:00
commit 93d91e9485
2238 changed files with 62867 additions and 19687 deletions
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3
.azure-pipelines.yml
View file

@ -287,9 +287,6 @@ stages:
sandbox64_clang:
TEST_PY_BD: "sandbox64"
OVERRIDE: "-O clang-16"
sandbox_nolto:
TEST_PY_BD: "sandbox"
BUILD_ENV: "NO_LTO=1"
sandbox_spl:
TEST_PY_BD: "sandbox_spl"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"

12
.gitlab-ci.yml
View file

@ -258,12 +258,6 @@ sandbox with clang test.py:
OVERRIDE: "-O clang-16"
<<: *buildman_and_testpy_dfn
sandbox without LTO test.py:
variables:
TEST_PY_BD: "sandbox"
BUILD_ENV: "NO_LTO=1"
<<: *buildman_and_testpy_dfn
sandbox64 test.py:
variables:
TEST_PY_BD: "sandbox64"
@ -275,12 +269,6 @@ sandbox64 with clang test.py:
OVERRIDE: "-O clang-16"
<<: *buildman_and_testpy_dfn
sandbox64 without LTO test.py:
variables:
TEST_PY_BD: "sandbox64"
BUILD_ENV: "NO_LTO=1"
<<: *buildman_and_testpy_dfn
sandbox_spl test.py:
variables:
TEST_PY_BD: "sandbox_spl"

10
MAINTAINERS
View file

@ -53,6 +53,7 @@ Maintainers List (try to look for most precise areas first)
ACPI:
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: board/emulation/configs/acpi.config
F: cmd/acpi.c
F: lib/acpi/
@ -411,6 +412,8 @@ F: drivers/watchdog/mtk_wdt.c
F: drivers/net/mtk_eth.c
F: drivers/net/mtk_eth.h
F: drivers/reset/reset-mediatek.c
F: include/dt-bindings/clock/mediatek,*
F: include/dt-bindings/power/mediatek,*
F: tools/mtk_image.c
F: tools/mtk_image.h
F: tools/mtk_nand_headers.c
@ -982,7 +985,7 @@ EFI APP
M: Simon Glass <sjg@chromium.org>
M: Heinrich Schuchardt <xypron.glpk@gmx.de>
S: Maintained
W: https://u-boot.readthedocs.io/en/latest/develop/uefi/u-boot_on_efi.html
W: https://docs.u-boot.org/en/latest/develop/uefi/u-boot_on_efi.html
F: board/efi/efi-x86_app
F: configs/efi-x86_app*
F: doc/develop/uefi/u-boot_on_efi.rst
@ -1555,6 +1558,11 @@ M: Liviu Dudau <liviu.dudau@foss.arm.com>
S: Maintained
F: drivers/video/tda19988.c
TI LP5562 LED DRIVER
M: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
S: Supported
F: drivers/led/led_lp5562.c
TI SYSTEM SECURITY
M: Andrew F. Davis <afd@ti.com>
S: Supported

5
Makefile
View file

@ -750,6 +750,7 @@ endif
ifeq ($(CONFIG_STACKPROTECTOR),y)
KBUILD_CFLAGS += $(call cc-option,-fstack-protector-strong)
KBUILD_CFLAGS += $(call cc-option,-mstack-protector-guard=global)
CFLAGS_EFI += $(call cc-option,-fno-stack-protector)
else
KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
@ -851,7 +852,7 @@ HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makef
libs-$(CONFIG_API) += api/
libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
libs-y += boot/
libs-y += cmd/
libs-$(CONFIG_CMDLINE) += cmd/
libs-y += common/
libs-$(CONFIG_OF_EMBED) += dts/
libs-y += env/
@ -1153,7 +1154,6 @@ endif
@# is enable to tell 'deprecated' that one of these symbols exists
$(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CFG_SYS_TIMER_RATE)$(CFG_SYS_TIMER_COUNTER)),x))
$(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL))
$(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI))
@# Check that this build does not override OF_HAS_PRIOR_STAGE by
@# disabling OF_BOARD.
$(call cmd,ofcheck,$(KCONFIG_CONFIG))
@ -1349,6 +1349,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
$(foreach f,$(BINMAN_INDIRS),-I $(f)) \
-a atf-bl31-path=${BL31} \
-a tee-os-path=${TEE} \
-a ti-dm-path=${TI_DM} \
-a opensbi-path=${OPENSBI} \
-a default-dt=$(default_dt) \
-a scp-path=$(SCP) \

44
README
View file

@ -300,13 +300,6 @@ The following options need to be configured:
different from COUNTER_FREQUENCY, and can only be determined
at run time.
- Tegra SoC options:
CONFIG_TEGRA_SUPPORT_NON_SECURE
Support executing U-Boot in non-secure (NS) mode. Certain
impossible actions will be skipped if the CPU is in NS mode,
such as ARM architectural timer initialization.
- Linux Kernel Interface:
CONFIG_OF_LIBFDT
@ -1191,11 +1184,10 @@ The following options need to be configured:
Support for a lightweight UBI (fastmap) scanner and
loader
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
CFG_SYS_NAND_ECCPOS, CFG_SYS_NAND_ECCSIZE,
CFG_SYS_NAND_ECCBYTES
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_SIZE,
CONFIG_SYS_NAND_OOBSIZE, CONFIG_SYS_NAND_BLOCK_SIZE,
CONFIG_SYS_NAND_BAD_BLOCK_POS, CFG_SYS_NAND_ECCPOS,
CFG_SYS_NAND_ECCSIZE, CFG_SYS_NAND_ECCBYTES
Defines the size and behavior of the NAND that SPL uses
to read U-Boot
@ -1545,16 +1537,26 @@ Low Level (hardware related) configuration options:
globally (CONFIG_CMD_MEMORY).
- CONFIG_SPL_BUILD
Set when the currently-running compilation is for an artifact
that will end up in the SPL (as opposed to the TPL or U-Boot
proper). Code that needs stage-specific behavior should check
this.
Set when the currently running compilation is for an artifact
that will end up in one of the 'xPL' builds, i.e. SPL, TPL or
VPL. Code that needs phase-specific behaviour can check this,
or (where possible) use spl_phase() instead.
Note that CONFIG_SPL_BUILD *is* always defined when either
of CONFIG_TPL_BUILD / CONFIG_VPL_BUILD is defined. This can be
counter-intuitive and should perhaps be changed.
- CONFIG_TPL_BUILD
Set when the currently-running compilation is for an artifact
that will end up in the TPL (as opposed to the SPL or U-Boot
proper). Code that needs stage-specific behavior should check
this.
Set when the currently running compilation is for an artifact
that will end up in the TPL build (as opposed to SPL, VPL or
U-Boot proper). Code that needs phase-specific behaviour can
check this, or (where possible) use spl_phase() instead.
- CONFIG_VPL_BUILD
Set when the currently running compilation is for an artifact
that will end up in the VPL build (as opposed to the SPL, TPL
or U-Boot proper). Code that needs phase-specific behaviour can
check this, or (where possible) use spl_phase() instead.
- CONFIG_ARCH_MAP_SYSMEM
Generally U-Boot (and in particular the md command) uses
@ -2650,5 +2652,5 @@ Contributing
The U-Boot projects depends on contributions from the user community.
If you want to participate, please, have a look at the 'General'
section of https://u-boot.readthedocs.io/en/latest/develop/index.html
section of https://docs.u-boot.org/en/latest/develop/index.html
where we describe coding standards and the patch submission process.

7
api/api_storage.c
View file

@ -67,13 +67,6 @@ void dev_stor_init(void)
specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA;
specs[ENUM_SATA].name = "sata";
#endif
#if defined(CONFIG_SCSI)
specs[ENUM_SCSI].max_dev = SCSI_MAX_DEVICE;
specs[ENUM_SCSI].enum_started = 0;
specs[ENUM_SCSI].enum_ended = 0;
specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI;
specs[ENUM_SCSI].name = "scsi";
#endif
#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
specs[ENUM_USB].max_dev = USB_MAX_STOR_DEV;
specs[ENUM_USB].enum_started = 0;

12
arch/Kconfig
View file

@ -108,6 +108,7 @@ config PPC
config RISCV
bool "RISC-V architecture"
select CREATE_ARCH_SYMLINK
select SUPPORT_ACPI
select SUPPORT_OF_CONTROL
select OF_CONTROL
select DM
@ -134,7 +135,7 @@ config SANDBOX
select ARCH_SUPPORTS_LTO
select BOARD_LATE_INIT
select BZIP2
select CMD_POWEROFF
select CMD_POWEROFF if CMDLINE
select DM
select DM_EVENT
select DM_FUZZING_ENGINE
@ -152,10 +153,10 @@ config SANDBOX
select PCI_ENDPOINT
select SPI
select SUPPORT_OF_CONTROL
select SYSRESET_CMD_POWEROFF
select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
select SYS_CACHE_SHIFT_4
select IRQ
select SUPPORT_EXTENSION_SCAN
select SUPPORT_EXTENSION_SCAN if CMDLINE
select SUPPORT_ACPI
imply BITREVERSE
select BLOBLIST
@ -210,6 +211,9 @@ config SANDBOX
imply BINMAN
imply CMD_MBR
imply CMD_MMC
imply BOOTSTD_DEFAULTS if BOOTSTD_FULL && CMDLINE
imply BOOTMETH_DISTRO if BOOTSTD_FULL && CMDLINE
imply CMD_SYSBOOT if BOOTSTD_FULL
config SH
bool "SuperH architecture"
@ -248,7 +252,7 @@ config X86
imply DM_KEYBOARD
imply DM_MMC
imply DM_RTC
imply DM_SCSI
imply SCSI
imply DM_SERIAL
imply DM_SPI
imply DM_SPI_FLASH

2
arch/arc/include/asm/arc-bcr.h
View file

@ -13,8 +13,6 @@
#define __ARC_BCR_H
#ifndef __ASSEMBLY__
#include <config.h>
union bcr_di_cache {
struct {
#ifdef CONFIG_CPU_BIG_ENDIAN

1
arch/arc/include/asm/arcregs.h
View file

@ -7,7 +7,6 @@
#define _ASM_ARC_ARCREGS_H
#include <asm/cache.h>
#include <config.h>
/*
* ARC architecture has additional address space - auxiliary registers.

2
arch/arc/include/asm/cache.h
View file

@ -6,8 +6,6 @@
#ifndef __ASM_ARC_CACHE_H
#define __ASM_ARC_CACHE_H
#include <config.h>
/*
* As of today we may handle any L1 cache line length right in software.
* For that essentially cache line length is a variable not constant.

5
arch/arc/lib/bootm.c
View file

@ -3,6 +3,7 @@
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*/
#include <bootm.h>
#include <bootstage.h>
#include <env.h>
#include <image.h>
@ -78,8 +79,10 @@ static void boot_jump_linux(struct bootm_headers *images, int flag)
board_jump_and_run(kernel_entry, r0, 0, r2);
}
int do_bootm_linux(int flag, int argc, char *argv[], struct bootm_headers *images)
int do_bootm_linux(int flag, struct bootm_info *bmi)
{
struct bootm_headers *images = bmi->images;
/* No need for those on ARC */
if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE))
return -1;

1
arch/arc/lib/cpu.c
View file

@ -3,6 +3,7 @@
* Copyright (C) 2013-2014, 2018 Synopsys, Inc. All rights reserved.
*/
#include <config.h>
#include <clock_legacy.h>
#include <init.h>
#include <malloc.h>

7
arch/arm/Kconfig
View file

@ -568,6 +568,7 @@ config ARCH_AT91
select GPIO_EXTRA_HEADER
select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
select SPL_SEPARATE_BSS if SPL
imply SYS_THUMB_BUILD
config ARCH_DAVINCI
bool "TI DaVinci"
@ -1133,7 +1134,6 @@ config ARCH_SUNXI
select DM_SPI_FLASH if SPI
select DM_KEYBOARD
select DM_MMC if MMC
select DM_SCSI if SCSI
select DM_SERIAL
select OF_BOARD_SETUP
select OF_CONTROL
@ -1838,7 +1838,7 @@ config TARGET_SL28
select PCI
select DM_RNG
select DM_RTC
select DM_SCSI
select SCSI
select DM_SERIAL
select DM_SPI
select GPIO_EXTRA_HEADER
@ -1945,7 +1945,7 @@ config ARCH_STM32MP
select REGMAP
select SYSCON
select SYSRESET
select SYS_THUMB_BUILD
select SYS_THUMB_BUILD if !ARM64
imply SPL_SYSRESET
imply CMD_DM
imply CMD_POWEROFF
@ -2053,7 +2053,6 @@ config TARGET_POMELO
select PCI
select DM_PCI
select SCSI
select DM_SCSI
select DM_SERIAL
imply CMD_PCI
help

4
arch/arm/cpu/arm926ejs/mxs/mxs.c
View file

@ -71,6 +71,7 @@ void reset_cpu(void)
* actually 0x20, this the associated <destination address>. Loading the PC
* register with an address performs a jump to that address.
*/
noinline __attribute__((target("arm")))
void mx28_fixup_vt(uint32_t start_addr)
{
/* ldr pc, [pc, #0x18] */
@ -85,6 +86,9 @@ void mx28_fixup_vt(uint32_t start_addr)
/* cppcheck-suppress nullPointer */
vt[i + 8] = start_addr + (4 * i);
}
/* Make sure ARM core points to low vectors */
set_cr(get_cr() & ~CR_V);
}
#ifdef CONFIG_ARCH_MISC_INIT

8
arch/arm/cpu/arm926ejs/mxs/spl_boot.c
View file

@ -17,6 +17,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/sections.h>
#include <asm/system.h>
#include <linux/compiler.h>
#include "mxs_init.h"
@ -93,7 +94,9 @@ static uint8_t mxs_get_bootmode_index(void)
return i;
}
static void mxs_spl_fixup_vectors(void)
static noinline
__attribute__((target("arm")))
void mxs_spl_fixup_vectors(void)
{
/*
* Copy our vector table to 0x0, since due to HAB, we cannot
@ -104,6 +107,9 @@ static void mxs_spl_fixup_vectors(void)
/* cppcheck-suppress nullPointer */
memcpy(0x0, _start, 0x60);
/* Make sure ARM core points to low vectors */
set_cr(get_cr() & ~CR_V);
}
static void mxs_spl_console_init(void)

8
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
View file

@ -1177,8 +1177,9 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
if (adjust_up && cfg->bo_irq) {
if (powered_by_linreg) {
bo_int = readl(cfg->reg);
clrbits_le32(cfg->reg, cfg->bo_enirq);
bo_int = readl(&power_regs->hw_power_ctrl);
clrbits_le32(&power_regs->hw_power_ctrl,
cfg->bo_enirq);
}
setbits_le32(cfg->reg, cfg->bo_offset_mask);
}
@ -1220,7 +1221,8 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
if (adjust_up && powered_by_linreg) {
writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
if (bo_int & cfg->bo_enirq)
setbits_le32(cfg->reg, cfg->bo_enirq);
setbits_le32(&power_regs->hw_power_ctrl,
cfg->bo_enirq);
}
clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,

3
arch/arm/cpu/u-boot.lds
View file

@ -14,9 +14,6 @@ OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
#ifndef CONFIG_CMDLINE
/DISCARD/ : { *(__u_boot_list_2_cmd_*) }
#endif
#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC)
/*
* If CONFIG_ARMV7_SECURE_BASE is true, secure code will not

11
arch/arm/dts/Makefile
View file

@ -1075,6 +1075,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-kontron-bl-osm-s.dtb \
imx8mm-mx8menlo.dtb \
imx8mm-phg.dtb \
imx8mm-phyboard-polis-rdk.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \
@ -1085,7 +1086,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-venice-gw7904.dtb \
imx8mm-venice-gw7905-0x.dtb \
imx8mm-verdin-wifi-dev.dtb \
phycore-imx8mm.dtb \
imx8mn-bsh-smm-s2.dtb \
imx8mn-bsh-smm-s2pro.dtb \
imx8mn-ddr4-evk.dtb \
@ -1105,6 +1105,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-dhcom-som-overlay-eth1xfast.dtbo \
imx8mp-dhcom-som-overlay-eth2xfast.dtbo \
imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \
imx8mp-debix-model-a.dtb \
imx8mp-dhcom-pdk2.dtb \
imx8mp-dhcom-pdk3.dtb \
imx8mp-dhcom-pdk3-overlay-rev100.dtbo \
@ -1382,6 +1383,9 @@ dtb-$(CONFIG_STM32MP15x) += \
stm32mp15xx-dhcor-drc-compact.dtb \
stm32mp15xx-dhcor-testbench.dtb
dtb-$(CONFIG_STM32MP25X) += \
stm32mp257f-ev1.dtb
dtb-$(CONFIG_SOC_K3_AM654) += \
k3-am654-base-board.dtb \
k3-am654-r5-base-board.dtb \
@ -1398,7 +1402,10 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \
k3-j7200-r5-common-proc-board.dtb \
k3-j721e-sk.dtb \
k3-j721e-r5-sk.dtb
k3-j721e-r5-sk.dtb \
k3-j721e-beagleboneai64.dtb \
k3-j721e-r5-beagleboneai64.dtb
dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\
k3-am68-sk-r5-base-board.dtb\
k3-j721s2-common-proc-board.dtb\

1
arch/arm/dts/fsl-imx8qm-apalis.dts
View file

@ -9,7 +9,6 @@
/memreserve/ 0x80000000 0x00020000;
#include "fsl-imx8qm.dtsi"
#include "fsl-imx8qm-apalis-u-boot.dtsi"
/ {
model = "Toradex Apalis iMX8";

15
arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
View file

@ -84,6 +84,21 @@
bootph-some-ram;
};
&gpio_expander_43 {
usb-bypass-n-hog {
gpio-hog;
gpios = <5 GPIO_ACTIVE_LOW>;
line-name = "usb-bypass-n";
output-high;
};
usb-reset-n-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_LOW>;
line-name = "usb-reset-n";
output-low;
};
};
&gpio0 {
bootph-some-ram;
};

3
arch/arm/dts/fsl-imx8qxp-colibri.dts
View file

@ -6,7 +6,6 @@
/dts-v1/;
#include "fsl-imx8qxp.dtsi"
#include "fsl-imx8qxp-colibri-u-boot.dtsi"
/ {
model = "Toradex Colibri iMX8X";
@ -320,8 +319,6 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x43>;
initial_io_dir = <0xff>;
initial_output = <0x05>;
};
};

11
arch/arm/dts/imx7d-pico-pi-u-boot.dtsi
View file

@ -1,11 +1,12 @@
#include "imx7s-u-boot.dtsi"
/{
aliases {
mmc0 = &usdhc3;
usb0 = &usbotg1;
display0 = &lcdif;
};
aliases {
mmc0 = &usdhc3;
mmc1 = &usdhc1;
usb0 = &usbotg1;
display0 = &lcdif;
};
wdt-reboot {
compatible = "wdt-reboot";

51
arch/arm/dts/imx7d-sdb-u-boot.dtsi
View file

@ -18,57 +18,6 @@
dr_mode = "peripheral";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
};
&pinctrl_usdhc1 {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
>;
};
&iomuxc {
pinctrl_usdhc1_gpio: usdhc1gpiogrp {
fsl,pins = <
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
>;
};
pinctrl_usdhc1_100mhz: usdhc1100mhzgrp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
>;
};
pinctrl_usdhc1_200mhz: usdhc1200mhzgrp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
>;
};
};
&wdog1 {
bootph-pre-ram;
};

73
arch/arm/dts/imx7d-sdb.dts
View file

@ -24,14 +24,14 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
volume-up {
key-volume-up {
label = "Volume Up";
gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
wakeup-source;
};
volume-down {
key-volume-down {
label = "Volume Down";
gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
@ -39,12 +39,12 @@
};
};
spi4 {
spi-4 {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi4>;
gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
sck-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
num-chipselects = <1>;
#address-cells = <1>;
@ -60,6 +60,17 @@
};
};
reg_sd1_vmmc: regulator-sd1-vmmc {
compatible = "regulator-fixed";
regulator-name = "VDD_SD1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <200000>;
off-on-delay-us = <20000>;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
@ -205,13 +216,8 @@
pinctrl-0 = <&pinctrl_tsc2046_pendown>;
interrupt-parent = <&gpio2>;
interrupts = <29 0>;
pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
ti,x-min = /bits/ 16 <0>;
ti,x-max = /bits/ 16 <0>;
ti,y-min = /bits/ 16 <0>;
ti,y-max = /bits/ 16 <0>;
ti,pressure-max = /bits/ 16 <0>;
ti,x-plate-ohms = /bits/ 16 <400>;
pendown-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>;
touchscreen-max-pressure = <255>;
wakeup-source;
};
};
@ -269,7 +275,7 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze3000@8 {
pmic: pmic@8 {
compatible = "fsl,pfuze3000";
reg = <0x08>;
@ -478,10 +484,13 @@
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_sd1_vmmc>;
wakeup-source;
keep-power-in-suspend;
status = "okay";
@ -736,6 +745,15 @@
>;
};
pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
fsl,pins = <
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
@ -744,9 +762,28 @@
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
>;
};

0
arch/arm/dts/phycore-imx8mm-u-boot.dtsi → arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
View file

460
arch/arm/dts/imx8mm-phyboard-polis-rdk.dts Normal file
View file

@ -0,0 +1,460 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 PHYTEC Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm-phycore-som.dtsi"
/ {
model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK";
compatible = "phytec,imx8mm-phyboard-polis-rdk",
"phytec,imx8mm-phycore-som", "fsl,imx8mm";
chosen {
stdout-path = &uart3;
};
bt_osc_32k: bt-lp-clock {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "bt_osc_32k";
#clock-cells = <0>;
};
can_osc_40m: can-clock {
compatible = "fixed-clock";
clock-frequency = <40000000>;
clock-output-names = "can_osc_40m";
#clock-cells = <0>;
};
fan {
compatible = "gpio-fan";
gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = <0 0
13000 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fan>;
#cooling-cells = <2>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
led-0 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_DISK;
gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc2";
};
led-1 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_DISK;
gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc1";
};
led-2 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_CPU;
gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
usdhc1_pwrseq: pwr-seq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <60>;
reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
};
reg_can_en: regulator-can-en {
compatible = "regulator-fixed";
gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_en>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "CAN_EN";
startup-delay-us = <20>;
};
reg_usb_otg1_vbus: regulator-usb-otg1 {
compatible = "regulator-fixed";
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1pwrgrp>;
regulator-name = "usb_otg1_vbus";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <20000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VSD_3V3";
};
reg_vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VCC_3V3";
};
};
/* SPI - CAN MCP251XFD */
&ecspi1 {
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
can0: can@0 {
compatible = "microchip,mcp251xfd";
clocks = <&can_osc_40m>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_int>;
reg = <0>;
spi-max-frequency = <20000000>;
xceiver-supply = <&reg_can_en>;
};
};
&gpio1 {
gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT",
"", "", "", "RESET_ETHPHY",
"CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "",
"USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE";
};
&gpio2 {
gpio-line-names = "", "", "", "",
"", "", "BT_REG_ON", "WL_REG_ON",
"BT_DEV_WAKE", "BT_HOST_WAKE", "", "",
"X_SD2_CD_B", "", "", "",
"", "", "", "SD2_RESET_B";
};
&gpio4 {
gpio-line-names = "", "", "", "",
"", "", "", "",
"FAN", "miniPCIe_nPERST", "", "",
"COEX1", "COEX2";
};
&gpio5 {
gpio-line-names = "", "", "", "",
"", "", "", "",
"", "ECSPI1_SS0";
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
};
/* PCIe */
&pcie0 {
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
assigned-clock-rates = <10000000>, <250000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcie_phy {
clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
fsl,tx-deemph-gen1 = <0x2d>;
fsl,tx-deemph-gen2 = <0xf>;
status = "okay";
};
&rv3028 {
trickle-resistor-ohms = <3000>;
};
&snvs_pwrkey {
status = "okay";
};
/* UART - RS232/RS485 */
&uart1 {
assigned-clocks = <&clk IMX8MM_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
status = "okay";
};
/* UART - Sterling-LWB Bluetooth */
&uart2 {
assigned-clocks = <&clk IMX8MM_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
fsl,dte-mode;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_bt>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&bt_osc_32k>;
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wakeup";
interrupt-parent = <&gpio2>;
interrupts = <9 IRQ_TYPE_EDGE_BOTH>;
max-speed = <2000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bt>;
shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
vddio-supply = <&reg_vcc_3v3>;
};
};
/* UART - console */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
/* USB */
&usbotg1 {
adp-disable;
dr_mode = "otg";
over-current-active-low;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
srp-disable;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
};
/* SDIO - Sterling-LWB Wifi */
&usdhc1 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
assigned-clock-rates = <200000000>;
bus-width = <4>;
mmc-pwrseq = <&usdhc1_pwrseq>;
non-removable;
no-1-8-v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};
/* SD-Card */
&usdhc2 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
vmmc-supply = <&reg_usdhc2_vmmc>;
vqmmc-supply = <&reg_nvcc_sd2>;
status = "okay";
};
&iomuxc {
pinctrl_bt: btgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00
MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00
MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00
>;
};
pinctrl_can_en: can-engrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
>;
};
pinctrl_can_int: can-intgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
>;
};
pinctrl_fan: fan0grp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
>;
};
pinctrl_leds: leds1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16
MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00
>;
};
pinctrl_uart2_bt: uart2btgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00
MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00
MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00
MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40
>;
};
pinctrl_usbotg1pwrgrp: usbotg1pwrgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
};
pinctrl_wlan: wlangrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00
>;
};
};

440
arch/arm/dts/imx8mm-phycore-som.dtsi Normal file
View file

@ -0,0 +1,440 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 PHYTEC Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*/
#include "imx8mm.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
model = "PHYTEC phyCORE-i.MX8MM";
compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";
aliases {
rtc0 = &rv3028;
rtc1 = &snvs_rtc;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
reg_vdd_3v3_s: regulator-vdd-3v3-s {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VDD_3V3_S";
};
};
&A53_0 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_1 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_2 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_3 {
cpu-supply = <&reg_vdd_arm>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
};
/* Ethernet */
&fec1 {
fsl,magic-packet;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
enet-phy-lane-no-swap;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
reg = <0>;
reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
};
};
};
/* SPI Flash */
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
som_flash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&gpio1 {
gpio-line-names = "nINT_ETHPHY", "", "WDOG_INT", "X_RTC_INT",
"", "", "", "RESET_ETHPHY",
"", "", "nENABLE_FLATLINK";
};
/* I2C1 */
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default","gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic@8 {
compatible = "nxp,pf8121a";
reg = <0x08>;
regulators {
reg_nvcc_sd1: ldo1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "NVCC_SD1 (LDO1)";
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_nvcc_sd2: ldo2 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
regulator-name = "NVCC_SD2 (LDO2)";
vselect-en;
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_vcc_enet: ldo3 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <2500000>;
regulator-min-microvolt = <1500000>;
regulator-name = "VCC_ENET_2V5 (LDO3)";
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_vdda_1v8: ldo4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1500000>;
regulator-name = "VDDA_1V8 (LDO4)";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-min-microvolt = <1500000>;
regulator-suspend-max-microvolt = <1500000>;
};
};
reg_soc_vdda_phy: buck1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <900000>;
regulator-min-microvolt = <400000>;
regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-min-microvolt = <400000>;
regulator-suspend-max-microvolt = <400000>;
};
};
reg_vdd_gpu_dram: buck2 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1000000>;
regulator-min-microvolt = <1000000>;
regulator-name = "VDD_GPU_DRAM (BUCK2)";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-max-microvolt = <1000000>;
regulator-suspend-min-microvolt = <1000000>;
};
};
reg_vdd_gpu: buck3 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1000000>;
regulator-min-microvolt = <400000>;
regulator-name = "VDD_VPU (BUCK3)";
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_vdd_mipi: buck4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1050000>;
regulator-min-microvolt = <900000>;
regulator-name = "VDD_MIPI_0P9 (BUCK4)";
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_vdd_arm: buck5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1050000>;
regulator-min-microvolt = <400000>;
regulator-name = "VDD_ARM (BUCK5)";
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_vdd_1v8: buck6 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "VDD_1V8 (BUCK6)";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-max-microvolt = <1800000>;
regulator-suspend-min-microvolt = <1800000>;
};
};
reg_nvcc_dram: buck7 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1100000>;
regulator-min-microvolt = <1100000>;
regulator-name = "NVCC_DRAM_1P1V (BUCK7)";
};
reg_vsnvs: vsnvs {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "NVCC_SNVS_1P8 (VSNVS)";
};
};
};
sn65dsi83: bridge@2d {
compatible = "ti,sn65dsi83";
enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sn65dsi83>;
reg = <0x2d>;
status = "disabled";
};
eeprom@51 {
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x51>;
vcc-supply = <&reg_vdd_3v3_s>;
};
rv3028: rtc@52 {
compatible = "microcrystal,rv3028";
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
reg = <0x52>;
};
};
/* EMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
bus-width = <8>;
keep-power-in-suspend;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
non-removable;
status = "okay";
};
/* Watchdog */
&wdog1 {
fsl,ext-reset-output;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
status = "okay";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
>;
};
pinctrl_sn65dsi83: sn65dsi83grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26
>;
};
};

7
arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi
View file

@ -39,6 +39,13 @@
gpios = <9 GPIO_ACTIVE_HIGH>;
line-name = "dio1";
};
tpm_rst {
gpio-hog;
output-high;
gpios = <11 GPIO_ACTIVE_HIGH>;
line-name = "tpm_rst#";
};
};
&gpio4 {

10
arch/arm/dts/imx8mm-venice-gw72xx.dtsi
View file

@ -84,8 +84,15 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
<&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@1 {
compatible = "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};
};
&gpio1 {
@ -314,6 +321,7 @@
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
>;
};

7
arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi
View file

@ -39,6 +39,13 @@
gpios = <9 GPIO_ACTIVE_HIGH>;
line-name = "dio1";
};
tpm_rst {
gpio-hog;
output-high;
gpios = <11 GPIO_ACTIVE_HIGH>;
line-name = "tpm_rst#";
};
};
&gpio4 {

10
arch/arm/dts/imx8mm-venice-gw73xx.dtsi
View file

@ -104,8 +104,15 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
<&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@1 {
compatible = "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};
};
&gpio1 {
@ -364,6 +371,7 @@
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
>;
};

153
arch/arm/dts/imx8mm.dtsi
View file

@ -139,6 +139,7 @@
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
@ -276,6 +277,7 @@
assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
clock-names = "main_clk";
power-domains = <&pgc_otg1>;
};
usbphynop2: usbphynop2 {
@ -285,6 +287,7 @@
assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
clock-names = "main_clk";
power-domains = <&pgc_otg2>;
};
soc: soc@0 {
@ -396,6 +399,7 @@
"pll8k", "pll11k", "clkext3";
dmas = <&sdma2 24 25 0x80000000>;
dma-names = "rx";
#sound-dai-cells = <0>;
status = "disabled";
};
@ -493,6 +497,8 @@
compatible = "fsl,imx8mm-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
nvmem-cells = <&tmu_calib>;
nvmem-cell-names = "calib";
#thermal-sensor-cells = <0>;
};
@ -547,8 +553,8 @@
reg = <0x30330000 0x10000>;
};
gpr: iomuxc-gpr@30340000 {
compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
gpr: syscon@30340000 {
compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
@ -560,22 +566,40 @@
#address-cells = <1>;
#size-cells = <1>;
imx8mm_uid: unique-id@410 {
/*
* The register address below maps to the MX8M
* Fusemap Description Table entries this way.
* Assuming
* reg = <ADDR SIZE>;
* then
* Fuse Address = (ADDR * 4) + 0x400
* Note that if SIZE is greater than 4, then
* each subsequent fuse is located at offset
* +0x10 in Fusemap Description Table (e.g.
* reg = <0x4 0x8> describes fuses 0x410 and
* 0x420).
*/
imx8mm_uid: unique-id@4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
fec_mac_address: mac-address@90 {
tmu_calib: calib@3c { /* 0x4f0 */
reg = <0x3c 4>;
};
fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
};
anatop: anatop@30360000 {
compatible = "fsl,imx8mm-anatop", "syscon";
anatop: clock-controller@30360000 {
compatible = "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
#clock-cells = <1>;
};
snvs: snvs@30370000 {
@ -674,13 +698,11 @@
pgc_otg1: power-domain@2 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_OTG1>;
power-domains = <&pgc_hsiomix>;
};
pgc_otg2: power-domain@3 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_OTG2>;
power-domains = <&pgc_hsiomix>;
};
pgc_gpumix: power-domain@4 {
@ -1098,6 +1120,61 @@
#size-cells = <1>;
ranges = <0x32c00000 0x32c00000 0x400000>;
lcdif: lcdif@32e00000 {
compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif";
reg = <0x32e00000 0x10000>;
clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
<&clk IMX8MM_CLK_DISP_APB_ROOT>,
<&clk IMX8MM_CLK_DISP_AXI_ROOT>;
clock-names = "pix", "axi", "disp_axi";
assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
<&clk IMX8MM_CLK_DISP_AXI>,
<&clk IMX8MM_CLK_DISP_APB>;
assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
<&clk IMX8MM_SYS_PLL2_1000M>,
<&clk IMX8MM_SYS_PLL1_800M>;
assigned-clock-rates = <594000000>, <500000000>, <200000000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
status = "disabled";
port {
lcdif_to_dsim: endpoint {
remote-endpoint = <&dsim_from_lcdif>;
};
};
};
mipi_dsi: dsi@32e10000 {
compatible = "fsl,imx8mm-mipi-dsim";
reg = <0x32e10000 0x400>;
clocks = <&clk IMX8MM_CLK_DSI_CORE>,
<&clk IMX8MM_CLK_DSI_PHY_REF>;
clock-names = "bus_clk", "sclk_mipi";
assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
<&clk IMX8MM_CLK_DSI_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
<&clk IMX8MM_CLK_24M>;
assigned-clock-rates = <266000000>, <24000000>;
samsung,pll-clock-frequency = <24000000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsim_from_lcdif: endpoint {
remote-endpoint = <&lcdif_to_dsim>;
};
};
};
};
csi: csi@32e20000 {
compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
reg = <0x32e20000 0x1000>;
@ -1145,10 +1222,9 @@
compatible = "fsl,imx8mm-mipi-csi2";
reg = <0x32e30000 0x1000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
<&clk IMX8MM_CLK_CSI1_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
<&clk IMX8MM_SYS_PLL2_1000M>;
assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>;
clock-frequency = <333000000>;
clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
<&clk IMX8MM_CLK_CSI1_ROOT>,
@ -1177,7 +1253,7 @@
};
usbotg1: usb@32e40000 {
compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x32e40000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
@ -1186,18 +1262,19 @@
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
phys = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
power-domains = <&pgc_otg1>;
power-domains = <&pgc_hsiomix>;
status = "disabled";
};
usbmisc1: usbmisc@32e40200 {
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
"fsl,imx6q-usbmisc";
#index-cells = <1>;
reg = <0x32e40200 0x200>;
};
usbotg2: usb@32e50000 {
compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x32e50000 0x200>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
@ -1206,12 +1283,13 @@
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
phys = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
power-domains = <&pgc_otg2>;
power-domains = <&pgc_hsiomix>;
status = "disabled";
};
usbmisc2: usbmisc@32e50200 {
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
"fsl,imx6q-usbmisc";
#index-cells = <1>;
reg = <0x32e50200 0x200>;
};
@ -1238,16 +1316,15 @@
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <4>;
clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
};
gpmi: nand-controller@33002000{
gpmi: nand-controller@33002000 {
compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <0>;
reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
reg-names = "gpmi-nand", "bch";
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
@ -1268,8 +1345,8 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
<0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
@ -1282,6 +1359,10 @@
<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <2>;
linux,pci-domain = <0>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
clock-names = "pcie", "pcie_bus", "pcie_aux";
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
@ -1291,6 +1372,30 @@
status = "disabled";
};
pcie0_ep: pcie-ep@33800000 {
compatible = "fsl,imx8mm-pcie-ep";
reg = <0x33800000 0x400000>,
<0x18000000 0x8000000>;
reg-names = "dbi", "addr_space";
num-lanes = <1>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dma";
fsl,max-link-speed = <2>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
clock-names = "pcie", "pcie_bus", "pcie_aux";
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "apps", "turnoff";
phys = <&pcie_phy>;
phy-names = "pcie-phy";
num-ib-windows = <4>;
num-ob-windows = <4>;
status = "disabled";
};
gpu_3d: gpu@38000000 {
compatible = "vivante,gc";
reg = <0x38000000 0x8000>;

167
arch/arm/dts/imx8mn.dtsi
View file

@ -139,6 +139,7 @@
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
@ -295,6 +296,7 @@
sai2: sai@30020000 {
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30020000 0x10000>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
<&clk IMX8MN_CLK_DUMMY>,
@ -309,6 +311,7 @@
sai3: sai@30030000 {
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30030000 0x10000>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
<&clk IMX8MN_CLK_DUMMY>,
@ -323,6 +326,7 @@
sai5: sai@30050000 {
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30050000 0x10000>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
<&clk IMX8MN_CLK_DUMMY>,
@ -339,6 +343,7 @@
sai6: sai@30060000 {
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30060000 0x10000>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
<&clk IMX8MN_CLK_DUMMY>,
@ -366,6 +371,7 @@
"pll8k", "pll11k", "clkext3";
dmas = <&sdma2 24 25 0x80000000>;
dma-names = "rx";
#sound-dai-cells = <0>;
status = "disabled";
};
@ -396,6 +402,7 @@
sai7: sai@300b0000 {
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x300b0000 0x10000>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
<&clk IMX8MN_CLK_DUMMY>,
@ -497,6 +504,8 @@
compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
nvmem-cells = <&tmu_calib>;
nvmem-cell-names = "calib";
#thermal-sensor-cells = <0>;
};
@ -551,7 +560,7 @@
reg = <0x30330000 0x10000>;
};
gpr: iomuxc-gpr@30340000 {
gpr: syscon@30340000 {
compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
@ -563,23 +572,40 @@
#address-cells = <1>;
#size-cells = <1>;
imx8mn_uid: unique-id@410 {
/*
* The register address below maps to the MX8M
* Fusemap Description Table entries this way.
* Assuming
* reg = <ADDR SIZE>;
* then
* Fuse Address = (ADDR * 4) + 0x400
* Note that if SIZE is greater than 4, then
* each subsequent fuse is located at offset
* +0x10 in Fusemap Description Table (e.g.
* reg = <0x4 0x8> describes fuses 0x410 and
* 0x420).
*/
imx8mn_uid: unique-id@4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
fec_mac_address: mac-address@90 {
tmu_calib: calib@3c { /* 0x4f0 */
reg = <0x3c 4>;
};
fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
};
anatop: anatop@30360000 {
compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
"syscon";
anatop: clock-controller@30360000 {
compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
#clock-cells = <1>;
};
snvs: snvs@30370000 {
@ -662,7 +688,6 @@
pgc_otg1: power-domain@1 {
#power-domain-cells = <0>;
reg = <IMX8MN_POWER_DOMAIN_OTG1>;
power-domains = <&pgc_hsiomix>;
};
pgc_gpumix: power-domain@2 {
@ -1038,6 +1063,72 @@
#size-cells = <1>;
ranges;
lcdif: lcdif@32e00000 {
compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif";
reg = <0x32e00000 0x10000>;
clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
<&clk IMX8MN_CLK_DISP_APB_ROOT>,
<&clk IMX8MN_CLK_DISP_AXI_ROOT>;
clock-names = "pix", "axi", "disp_axi";
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>;
status = "disabled";
port {
lcdif_to_dsim: endpoint {
remote-endpoint = <&dsim_from_lcdif>;
};
};
};
mipi_dsi: dsi@32e10000 {
compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim";
reg = <0x32e10000 0x400>;
clocks = <&clk IMX8MN_CLK_DSI_CORE>,
<&clk IMX8MN_CLK_DSI_PHY_REF>;
clock-names = "bus_clk", "sclk_mipi";
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsim_from_lcdif: endpoint {
remote-endpoint = <&lcdif_to_dsim>;
};
};
};
};
isi: isi@32e20000 {
compatible = "fsl,imx8mn-isi";
reg = <0x32e20000 0x8000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
<&clk IMX8MN_CLK_DISP_APB_ROOT>;
clock-names = "axi", "apb";
fsl,blk-ctrl = <&disp_blk_ctrl>;
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
isi_in: endpoint {
remote-endpoint = <&mipi_csi_out>;
};
};
};
};
disp_blk_ctrl: blk-ctrl@32e28000 {
compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
reg = <0x32e28000 0x100>;
@ -1063,11 +1154,60 @@
"lcdif-axi", "lcdif-apb", "lcdif-pix",
"dsi-pclk", "dsi-ref",
"csi-aclk", "csi-pclk";
assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
<&clk IMX8MN_CLK_DSI_PHY_REF>,
<&clk IMX8MN_CLK_DISP_PIXEL>,
<&clk IMX8MN_CLK_DISP_AXI>,
<&clk IMX8MN_CLK_DISP_APB>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
<&clk IMX8MN_CLK_24M>,
<&clk IMX8MN_VIDEO_PLL1_OUT>,
<&clk IMX8MN_SYS_PLL2_1000M>,
<&clk IMX8MN_SYS_PLL1_800M>;
assigned-clock-rates = <266000000>,
<24000000>,
<594000000>,
<500000000>,
<200000000>;
#power-domain-cells = <1>;
};
mipi_csi: mipi-csi@32e30000 {
compatible = "fsl,imx8mm-mipi-csi2";
reg = <0x32e30000 0x1000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>;
assigned-clock-rates = <333000000>;
clock-frequency = <333000000>;
clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>,
<&clk IMX8MN_CLK_CAMERA_PIXEL>,
<&clk IMX8MN_CLK_CSI1_PHY_REF>,
<&clk IMX8MN_CLK_DISP_AXI_ROOT>;
clock-names = "pclk", "wrap", "phy", "axi";
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
mipi_csi_out: endpoint {
remote-endpoint = <&isi_in>;
};
};
};
};
usbotg1: usb@32e40000 {
compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x32e40000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
@ -1076,12 +1216,13 @@
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
phys = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
power-domains = <&pgc_otg1>;
power-domains = <&pgc_hsiomix>;
status = "disabled";
};
usbmisc1: usbmisc@32e40200 {
compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc",
"fsl,imx6q-usbmisc";
#index-cells = <1>;
reg = <0x32e40200 0x200>;
};
@ -1094,7 +1235,6 @@
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <4>;
clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
@ -1103,7 +1243,7 @@
gpmi: nand-controller@33002000 {
compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <0>;
reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
reg-names = "gpmi-nand", "bch";
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
@ -1175,5 +1315,6 @@
assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
clock-names = "main_clk";
power-domains = <&pgc_otg1>;
};
};

141
arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi Normal file
View file

@ -0,0 +1,141 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019, 2021 NXP
* Copyright 2023 Gilles Talis <gilles.talis@gmail.com>
*/
#include "imx8mp-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
bootph-pre-ram;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
&crypto {
bootph-pre-ram;
};
&ethphy0 {
reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
reset-delay-us = <15000>;
reset-post-delay-us = <100000>;
};
&fec {
phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
phy-reset-duration = <15>;
phy-reset-post-delay = <100>;
};
&gpio1 {
bootph-pre-ram;
};
&gpio2 {
bootph-pre-ram;
};
&gpio3 {
bootph-pre-ram;
};
&gpio4 {
bootph-pre-ram;
};
&gpio5 {
bootph-pre-ram;
};
&i2c1 {
bootph-pre-ram;
};
&pinctrl_i2c1 {
bootph-pre-ram;
};
&pinctrl_pmic {
bootph-pre-ram;
};
&pinctrl_uart2 {
bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
bootph-pre-ram;
};
&pinctrl_usdhc2 {
bootph-pre-ram;
};
&pinctrl_usdhc3 {
bootph-pre-ram;
};
&pinctrl_wdog {
bootph-pre-ram;
};
&pmic {
bootph-pre-ram;
regulators {
bootph-pre-ram;
};
};
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
&reg_usdhc2_vmmc {
bootph-pre-ram;
};
&uart2 {
bootph-pre-ram;
};
&sec_jr0 {
bootph-pre-ram;
};
&sec_jr1 {
bootph-pre-ram;
};
&sec_jr2 {
bootph-pre-ram;
};
&usdhc1 {
bootph-pre-ram;
};
&usdhc2 {
bootph-pre-ram;
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&usdhc3 {
bootph-pre-ram;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
};
&wdog1 {
bootph-pre-ram;
};

507
arch/arm/dts/imx8mp-debix-model-a.dts Normal file
View file

@ -0,0 +1,507 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
* Copyright 2022 Ideas on Board Oy
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/usb/pd.h>
#include "imx8mp.dtsi"
/ {
model = "Polyhex Debix Model A i.MX8MPlus board";
compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp";
chosen {
stdout-path = &uart2;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
led-0 {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-connection-type = "rgmii-id";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 { /* RTL8211E */
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
reset-assert-us = <20>;
reset-deassert-us = <200000>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_EDGE_RISING>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
buck4: BUCK4{
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5{
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xin32k";
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc_int>;
};
};
&i2c6 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c6>;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart2 {
/* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
/* SD Card */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
/* eMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f
MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1f
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x1f
MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f
MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
>;
};
pinctrl_i2c6: i2c6grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3
MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
>;
};
pinctrl_rtc_int: rtcintgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49
MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>;
};
};

32
arch/arm/dts/imx8mp-evk-u-boot.dtsi
View file

@ -13,6 +13,22 @@
};
};
&pinctrl_i2c1 {
bootph-all;
};
&pinctrl_pmic {
bootph-all;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
bootph-all;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
bootph-all;
};
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
@ -66,7 +82,7 @@
};
&i2c1 {
bootph-pre-ram;
bootph-all;
};
&i2c2 {
@ -121,17 +137,3 @@
&wdog1 {
bootph-pre-ram;
};
&ethphy0 {
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-delay-us = <15000>;
reset-post-delay-us = <100000>;
};
&fec {
phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
phy-reset-duration = <15>;
phy-reset-post-delay = <100>;
};

9
arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi
View file

@ -4,6 +4,15 @@
*/
#include "imx8mp-venice-gw702x-u-boot.dtsi"
&gpio1 {
tpm_rst {
gpio-hog;
output-high;
gpios = <11 GPIO_ACTIVE_HIGH>;
line-name = "tpm_rst#";
};
};
&gpio4 {
dio_1 {
gpio-hog;

9
arch/arm/dts/imx8mp-venice-gw72xx.dtsi
View file

@ -83,8 +83,14 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
<&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@1 {
compatible = "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};
};
&gpio4 {
@ -286,6 +292,7 @@
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
>;
};

9
arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi
View file

@ -10,6 +10,15 @@
reset-post-delay-us = <300000>;
};
&gpio1 {
tpm_rst {
gpio-hog;
output-high;
gpios = <11 GPIO_ACTIVE_HIGH>;
line-name = "tpm_rst#";
};
};
&gpio4 {
dio_1 {
gpio-hog;

9
arch/arm/dts/imx8mp-venice-gw73xx.dtsi
View file

@ -95,8 +95,14 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
<&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@1 {
compatible = "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};
};
&gpio4 {
@ -327,6 +333,7 @@
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
>;
};

542
arch/arm/dts/imx8mp.dtsi
View file

@ -202,6 +202,60 @@
clock-output-names = "clk_ext4";
};
funnel {
/*
* non-configurable funnel don't show up on the AMBA
* bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-funnel";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ca_funnel_in_port0: endpoint {
remote-endpoint = <&etm0_out_port>;
};
};
port@1 {
reg = <1>;
ca_funnel_in_port1: endpoint {
remote-endpoint = <&etm1_out_port>;
};
};
port@2 {
reg = <2>;
ca_funnel_in_port2: endpoint {
remote-endpoint = <&etm2_out_port>;
};
};
port@3 {
reg = <3>;
ca_funnel_in_port3: endpoint {
remote-endpoint = <&etm3_out_port>;
};
};
};
out-ports {
port {
ca_funnel_out_port0: endpoint {
remote-endpoint = <&hugo_funnel_in_port0>;
};
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -304,6 +358,153 @@
nvmem-cells = <&imx8mp_uid>;
nvmem-cell-names = "soc_unique_id";
etm0: etm@28440000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x28440000 0x1000>;
cpu = <&A53_0>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
out-ports {
port {
etm0_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port0>;
};
};
};
};
etm1: etm@28540000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x28540000 0x1000>;
cpu = <&A53_1>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
out-ports {
port {
etm1_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port1>;
};
};
};
};
etm2: etm@28640000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x28640000 0x1000>;
cpu = <&A53_2>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
out-ports {
port {
etm2_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port2>;
};
};
};
};
etm3: etm@28740000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x28740000 0x1000>;
cpu = <&A53_3>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
out-ports {
port {
etm3_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port3>;
};
};
};
};
funnel@28c03000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x28c03000 0x1000>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hugo_funnel_in_port0: endpoint {
remote-endpoint = <&ca_funnel_out_port0>;
};
};
port@1 {
reg = <1>;
hugo_funnel_in_port1: endpoint {
/* M7 input */
};
};
port@2 {
reg = <2>;
hugo_funnel_in_port2: endpoint {
/* DSP input */
};
};
/* the other input ports are not connect to anything */
};
out-ports {
port {
hugo_funnel_out_port0: endpoint {
remote-endpoint = <&etf_in_port>;
};
};
};
};
etf@28c04000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x28c04000 0x1000>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
in-ports {
port {
etf_in_port: endpoint {
remote-endpoint = <&hugo_funnel_out_port0>;
};
};
};
out-ports {
port {
etf_out_port: endpoint {
remote-endpoint = <&etr_in_port>;
};
};
};
};
etr@28c06000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x28c06000 0x1000>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
in-ports {
port {
etr_in_port: endpoint {
remote-endpoint = <&etf_out_port>;
};
};
};
};
aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30000000 0x400000>;
@ -497,7 +698,7 @@
snvs_rtc: snvs-rtc-lp {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
regmap =<&snvs>;
regmap = <&snvs>;
offset = <0x34>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
@ -534,26 +735,16 @@
<&clk IMX8MP_CLK_A53_CORE>,
<&clk IMX8MP_CLK_NOC>,
<&clk IMX8MP_CLK_NOC_IO>,
<&clk IMX8MP_CLK_GIC>,
<&clk IMX8MP_CLK_AUDIO_AHB>,
<&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
<&clk IMX8MP_AUDIO_PLL1>,
<&clk IMX8MP_AUDIO_PLL2>;
<&clk IMX8MP_CLK_GIC>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_ARM_PLL_OUT>,
<&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL2_500M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>;
<&clk IMX8MP_SYS_PLL2_500M>;
assigned-clock-rates = <0>, <0>,
<1000000000>,
<800000000>,
<500000000>,
<400000000>,
<800000000>,
<393216000>,
<361267200>;
<500000000>;
};
src: reset-controller@30390000 {
@ -595,6 +786,19 @@
reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
};
pgc_audio: power-domain@5 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
<&clk IMX8MP_CLK_AUDIO_AXI>;
assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
<&clk IMX8MP_CLK_AUDIO_AXI_SRC>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <400000000>,
<600000000>;
};
pgc_gpu2d: power-domain@6 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
@ -653,7 +857,7 @@
pgc_vpumix: power-domain@19 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
clocks =<&clk IMX8MP_CLK_VPU_ROOT>;
clocks = <&clk IMX8MP_CLK_VPU_ROOT>;
};
pgc_vpu_g1: power-domain@20 {
@ -1147,6 +1351,198 @@
};
};
aips5: bus@30c00000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30c00000 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
spba-bus@30c00000 {
compatible = "fsl,spba-bus", "simple-bus";
reg = <0x30c00000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
sai1: sai@30c10000 {
compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
reg = <0x30c10000 0x10000>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
dma-names = "rx", "tx";
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sai2: sai@30c20000 {
compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
reg = <0x30c20000 0x10000>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
dma-names = "rx", "tx";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sai3: sai@30c30000 {
compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
reg = <0x30c30000 0x10000>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
dma-names = "rx", "tx";
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sai5: sai@30c50000 {
compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
reg = <0x30c50000 0x10000>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
dma-names = "rx", "tx";
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sai6: sai@30c60000 {
compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
reg = <0x30c60000 0x10000>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
dma-names = "rx", "tx";
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sai7: sai@30c80000 {
compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
reg = <0x30c80000 0x10000>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
dma-names = "rx", "tx";
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
easrc: easrc@30c90000 {
compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc";
reg = <0x30c90000 0x10000>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_ASRC_IPG>;
clock-names = "mem";
dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
<&sdma2 18 23 0> , <&sdma2 19 23 0>,
<&sdma2 20 23 0> , <&sdma2 21 23 0>,
<&sdma2 22 23 0> , <&sdma2 23 23 0>;
dma-names = "ctx0_rx", "ctx0_tx",
"ctx1_rx", "ctx1_tx",
"ctx2_rx", "ctx2_tx",
"ctx3_rx", "ctx3_tx";
firmware-name = "imx/easrc/easrc-imx8mn.bin";
fsl,asrc-rate = <8000>;
fsl,asrc-format = <2>;
status = "disabled";
};
micfil: audio-controller@30ca0000 {
compatible = "fsl,imx8mp-micfil";
reg = <0x30ca0000 0x10000>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_IPG>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_SEL>,
<&clk IMX8MP_AUDIO_PLL1_OUT>,
<&clk IMX8MP_AUDIO_PLL2_OUT>,
<&clk IMX8MP_CLK_EXT3>;
clock-names = "ipg_clk", "ipg_clk_app",
"pll8k", "pll11k", "clkext3";
dmas = <&sdma2 24 25 0x80000000>;
dma-names = "rx";
status = "disabled";
};
};
sdma3: dma-controller@30e00000 {
compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
reg = <0x30e00000 0x10000>;
#dma-cells = <3>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>,
<&clk IMX8MP_CLK_AUDIO_ROOT>;
clock-names = "ipg", "ahb";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
sdma2: dma-controller@30e10000 {
compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
reg = <0x30e10000 0x10000>;
#dma-cells = <3>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>,
<&clk IMX8MP_CLK_AUDIO_ROOT>;
clock-names = "ipg", "ahb";
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
audio_blk_ctrl: clock-controller@30e20000 {
compatible = "fsl,imx8mp-audio-blk-ctrl";
reg = <0x30e20000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
<&clk IMX8MP_CLK_SAI1>,
<&clk IMX8MP_CLK_SAI2>,
<&clk IMX8MP_CLK_SAI3>,
<&clk IMX8MP_CLK_SAI5>,
<&clk IMX8MP_CLK_SAI6>,
<&clk IMX8MP_CLK_SAI7>;
clock-names = "ahb",
"sai1", "sai2", "sai3",
"sai5", "sai6", "sai7";
power-domains = <&pgc_audio>;
};
};
noc: interconnect@32700000 {
compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
reg = <0x32700000 0x100000>;
@ -1174,6 +1570,118 @@
#size-cells = <1>;
ranges;
isi_0: isi@32e00000 {
compatible = "fsl,imx8mp-isi";
reg = <0x32e00000 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "axi", "apb";
fsl,blk-ctrl = <&media_blk_ctrl>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
isi_in_0: endpoint {
remote-endpoint = <&mipi_csi_0_out>;
};
};
port@1 {
reg = <1>;
isi_in_1: endpoint {
remote-endpoint = <&mipi_csi_1_out>;
};
};
};
};
dewarp: dwe@32e30000 {
compatible = "nxp,imx8mp-dw100";
reg = <0x32e30000 0x10000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "axi", "ahb";
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
};
mipi_csi_0: csi@32e40000 {
compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
reg = <0x32e40000 0x10000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pclk", "wrap", "phy", "axi";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
assigned-clock-rates = <500000000>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
mipi_csi_0_out: endpoint {
remote-endpoint = <&isi_in_0>;
};
};
};
};
mipi_csi_1: csi@32e50000 {
compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
reg = <0x32e50000 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <266000000>;
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pclk", "wrap", "phy", "axi";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
assigned-clock-rates = <266000000>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
mipi_csi_1_out: endpoint {
remote-endpoint = <&isi_in_1>;
};
};
};
};
mipi_dsi: dsi@32e60000 {
compatible = "fsl,imx8mp-mipi-dsim";
reg = <0x32e60000 0x400>;
@ -1382,8 +1890,8 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
<0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
<0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;

4
arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
View file

@ -131,10 +131,6 @@
phy-reset-post-delay = <100>;
};
&eqos {
compatible = "fsl,imx-eqos";
};
&ethphy1 {
reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;

12
arch/arm/dts/k3-am62-main.dtsi
View file

@ -81,7 +81,8 @@
};
dmss: bus@48000000 {
compatible = "simple-mfd";
bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges;
@ -90,6 +91,7 @@
ti,sci-dev-id = <25>;
secure_proxy_main: mailbox@4d000000 {
bootph-all;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
@ -165,6 +167,7 @@
};
dmsc: system-controller@44043000 {
bootph-all;
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
@ -174,16 +177,19 @@
reg = <0x00 0x44043000 0x00 0xfe0>;
k3_pds: power-controller {
bootph-all;
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clock-controller {
bootph-all;
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
k3_reset: reset-controller {
bootph-all;
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
@ -202,6 +208,7 @@
};
secure_proxy_sa3: mailbox@43600000 {
bootph-pre-ram;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
@ -217,6 +224,7 @@
};
main_pmx0: pinctrl@f4000 {
bootph-all;
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2ac>;
#pinctrl-cells = <1>;
@ -225,12 +233,14 @@
};
main_esm: esm@420000 {
bootph-pre-ram;
compatible = "ti,j721e-esm";
reg = <0x00 0x420000 0x00 0x1000>;
ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
};
main_timer0: timer@2400000 {
bootph-all;
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm/dts/k3-am62-mcu.dtsi
View file

@ -7,6 +7,7 @@
&cbass_mcu {
mcu_pmx0: pinctrl@4084000 {
bootph-all;
compatible = "pinctrl-single";
reg = <0x00 0x04084000 0x00 0x88>;
#pinctrl-cells = <1>;
@ -15,6 +16,7 @@
};
mcu_esm: esm@4100000 {
bootph-pre-ram;
compatible = "ti,j721e-esm";
reg = <0x00 0x4100000 0x00 0x1000>;
ti,esm-pins = <0>, <1>, <2>, <85>;

6
arch/arm/dts/k3-am62-verdin-wifi.dtsi
View file

@ -35,5 +35,11 @@
&main_uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
fw-init-baudrate = <3000000>;
};
};

1
arch/arm/dts/k3-am62-verdin.dtsi
View file

@ -1061,6 +1061,7 @@
vddc-supply = <&reg_1v2_dsi>;
vddmipi-supply = <&reg_1v2_dsi>;
vddio-supply = <&reg_1v8_dsi>;
status = "disabled";
dsi_bridge_ports: ports {
#address-cells = <1>;

2
arch/arm/dts/k3-am62-wakeup.dtsi
View file

@ -7,6 +7,7 @@
&cbass_wakeup {
wkup_conf: syscon@43000000 {
bootph-all;
compatible = "syscon", "simple-mfd";
reg = <0x00 0x43000000 0x00 0x20000>;
#address-cells = <1>;
@ -14,6 +15,7 @@
ranges = <0x0 0x00 0x43000000 0x20000>;
chipid: chipid@14 {
bootph-all;
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
};

3
arch/arm/dts/k3-am62.dtsi
View file

@ -47,6 +47,7 @@
};
cbass_main: bus@f0000 {
bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@ -86,6 +87,7 @@
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
cbass_mcu: bus@4000000 {
bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@ -93,6 +95,7 @@
};
cbass_wakeup: bus@b00000 {
bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;

268
arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
View file

@ -6,151 +6,49 @@
* Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
*/
#include "k3-am625-sk-binman.dtsi"
#include "k3-binman.dtsi"
/ {
chosen {
tick-timer = &main_timer0;
};
memory@80000000 {
bootph-all;
};
/* Keep the LEDs on by default to indicate life */
leds {
bootph-all;
led-0 {
default-state = "on";
bootph-all;
};
led-1 {
default-state = "on";
bootph-all;
};
led-2 {
default-state = "on";
bootph-all;
};
led-3 {
default-state = "on";
bootph-all;
};
led-4 {
default-state = "on";
bootph-all;
};
};
};
&cbass_main {
bootph-all;
};
&main_timer0 {
clock-frequency = <25000000>;
bootph-all;
};
&dmss {
bootph-all;
};
&secure_proxy_main {
bootph-all;
};
&dmsc {
bootph-all;
};
&k3_pds {
bootph-all;
};
&k3_clks {
bootph-all;
};
&k3_reset {
bootph-all;
};
&dmsc {
bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-all;
};
};
&wkup_conf {
bootph-all;
};
&chipid {
bootph-all;
};
&main_pmx0 {
bootph-all;
};
&main_uart0 {
bootph-all;
};
&console_pins_default {
bootph-all;
};
&cbass_mcu {
bootph-all;
};
&cbass_wakeup {
bootph-all;
};
&mcu_pmx0 {
bootph-all;
};
&main_i2c0 {
bootph-all;
};
&local_i2c_pins_default {
bootph-all;
};
&gpio0_pins_default {
bootph-all;
};
&main_gpio0 {
bootph-all;
};
&main_gpio1 {
bootph-all;
};
&sdhci0 {
/* EMMC */
bootph-all;
};
&emmc_pins_default {
bootph-all;
};
&sd_pins_default {
bootph-all;
/* Force to use SDCD card detect pin */
pinctrl-single,pins = <
AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
@ -163,33 +61,155 @@
>;
};
&tps65219 {
bootph-all;
};
&sdhci1 {
bootph-all;
};
#ifdef CONFIG_TARGET_AM625_A53_EVM
#ifdef CONFIG_TARGET_AM625_A53_BEAGLEPLAY
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM625_BEAGLEPLAY_DTB "spl/dts/k3-am625-beagleplay.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM625_BEAGLEPLAY_DTB "arch/arm/dts/k3-am625-beagleplay.dtb"
&spl_am625_sk_dtb {
filename = SPL_AM625_BEAGLEPLAY_DTB;
};
&binman {
ti-dm {
filename = "ti-dm.bin";
blob-ext {
filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
};
};
&am625_sk_dtb {
filename = AM625_BEAGLEPLAY_DTB;
};
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
&spl_am625_sk_dtb_unsigned {
filename = SPL_AM625_BEAGLEPLAY_DTB;
};
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
&am625_sk_dtb_unsigned {
filename = AM625_BEAGLEPLAY_DTB;
};
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob {
filename = "spl/u-boot-spl-nodtb.bin";
};
};
fdt-0 {
description = "k3-am625-beagleplay";
type = "flat_dt";
arch = "arm";
compression = "none";
spl_am625_bp_dtb_unsigned: blob {
filename = SPL_AM625_BEAGLEPLAY_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am625-beagleplay";
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
};
};
};
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM625 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
};
fdt-0 {
description = "k3-am625-beagleplay";
type = "flat_dt";
arch = "arm";
compression = "none";
am625_bp_dtb_unsigned: blob {
filename = AM625_BEAGLEPLAY_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am625-beagleplay";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
#endif

34
arch/arm/dts/k3-am625-beagleplay.dts
View file

@ -46,6 +46,7 @@
};
memory@80000000 {
bootph-pre-ram;
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
@ -58,7 +59,7 @@
ramoops: ramoops@9ca00000 {
compatible = "ramoops";
reg = <0x00 0x9c700000 0x00 0x00100000>;
reg = <0x00 0x9ca00000 0x00 0x00100000>;
record-size = <0x8000>;
console-size = <0x8000>;
ftrace-size = <0x00>;
@ -83,6 +84,7 @@
};
vsys_5v0: regulator-1 {
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-min-microvolt = <5000000>;
@ -93,6 +95,7 @@
vdd_3v3: regulator-2 {
/* output of TLV62595DMQR-U12 */
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
regulator-min-microvolt = <3300000>;
@ -118,6 +121,7 @@
vdd_3v3_sd: regulator-4 {
/* output of TPS22918DBVR-U21 */
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&vdd_3v3_sd_pins_default>;
@ -132,6 +136,7 @@
};
vdd_sd_dv: regulator-5 {
bootph-all;
compatible = "regulator-gpio";
regulator-name = "sd_hs200_switch";
pinctrl-names = "default";
@ -146,9 +151,11 @@
};
leds {
bootph-all;
compatible = "gpio-leds";
led-0 {
bootph-all;
gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
function = LED_FUNCTION_HEARTBEAT;
@ -156,6 +163,7 @@
};
led-1 {
bootph-all;
gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "disk-activity";
function = LED_FUNCTION_DISK_ACTIVITY;
@ -163,16 +171,19 @@
};
led-2 {
bootph-all;
gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_CPU;
};
led-3 {
bootph-all;
gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_LAN;
};
led-4 {
bootph-all;
gpios = <&main_gpio0 9 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_WLAN;
};
@ -245,6 +256,7 @@
&main_pmx0 {
gpio0_pins_default: gpio0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */
AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */
@ -264,6 +276,7 @@
};
vdd_sd_dv_pins_default: vdd-sd-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
>;
@ -283,6 +296,7 @@
};
local_i2c_pins_default: local-i2c-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
@ -321,6 +335,7 @@
};
emmc_pins_default: emmc-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
@ -336,12 +351,14 @@
};
vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */
>;
};
sd_pins_default: sd-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
@ -418,6 +435,7 @@
};
mikrobus_gpio_pins_default: mikrobus-gpio-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */
AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */
@ -426,6 +444,7 @@
};
console_pins_default: console-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
@ -597,6 +616,7 @@
};
&main_gpio0 {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&gpio0_pins_default>;
gpio-line-names = "BL_EN_3V3", "SPE_PO_EN", "RTC_INT", /* 0-2 */
@ -616,6 +636,7 @@
};
&main_gpio1 {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&mikrobus_gpio_pins_default>;
gpio-line-names = "", "", "", "", "", /* 0-4 */
@ -633,6 +654,7 @@
};
&main_i2c0 {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&local_i2c_pins_default>;
clock-frequency = <400000>;
@ -651,6 +673,7 @@
};
tps65219: pmic@30 {
bootph-all;
compatible = "ti,tps65219";
reg = <0x30>;
buck1-supply = <&vsys_5v0>;
@ -801,6 +824,7 @@
};
&sdhci0 {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&emmc_pins_default>;
ti,driver-strength-ohm = <50>;
@ -810,6 +834,7 @@
&sdhci1 {
/* SD/MMC */
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&sd_pins_default>;
@ -850,6 +875,7 @@
};
&main_uart0 {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&console_pins_default>;
status = "okay";
@ -870,6 +896,12 @@
pinctrl-names = "default";
pinctrl-0 = <&wifi_debug_uart_pins_default>;
status = "okay";
mcu {
compatible = "ti,cc1352p7";
reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_LOW>;
vdds-supply = <&vdd_3v3>;
};
};
&dss {

48
arch/arm/dts/k3-am625-r5-beagleplay.dts
View file

@ -54,12 +54,7 @@
ti,secure-host;
};
&mcu_esm {
bootph-pre-ram;
};
&secure_proxy_sa3 {
bootph-pre-ram;
/* We require this for boot handshake */
status = "okay";
};
@ -73,10 +68,6 @@
};
};
&main_esm {
bootph-pre-ram;
};
&main_pktdma {
ti,sci = <&dm_tifs>;
};
@ -84,3 +75,42 @@
&main_bcdma {
ti,sci = <&dm_tifs>;
};
&binman {
tiboot3-am62x-gp-evm.bin {
filename = "tiboot3-am62x-gp-evm.bin";
ti-secure-rom {
content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
combined;
dm-data;
content-sbl = <&u_boot_spl_unsigned>;
load = <0x43c00000>;
content-sysfw = <&ti_fs_gp>;
load-sysfw = <0x40000>;
content-sysfw-data = <&combined_tifs_cfg_gp>;
load-sysfw-data = <0x67000>;
content-dm-data = <&combined_dm_cfg_gp>;
load-dm-data = <0x43c3a800>;
sw-rev = <1>;
keyfile = "ti-degenerate-key.pem";
};
u_boot_spl_unsigned: u-boot-spl {
no-expanded;
};
ti_fs_gp: ti-fs-gp.bin {
filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
filename = "combined-tifs-cfg.bin";
type = "blob-ext";
};
combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
filename = "combined-dm-cfg.bin";
type = "blob-ext";
};
};
};

21
arch/arm/dts/k3-am625-r5-sk.dts
View file

@ -55,20 +55,11 @@
ti,secure-host;
};
&mcu_esm {
bootph-pre-ram;
};
&secure_proxy_sa3 {
bootph-pre-ram;
/* We require this for boot handshake */
status = "okay";
};
&main_esm {
bootph-pre-ram;
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
@ -78,22 +69,14 @@
};
};
&wkup_uart0_pins_default {
bootph-pre-ram;
};
&main_uart1_pins_default {
bootph-pre-ram;
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
bootph-pre-ram;
status = "okay";
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
bootph-pre-ram;
status = "okay";
};
&ospi0 {

161
arch/arm/dts/k3-am625-sk-binman.dtsi
View file

@ -141,10 +141,7 @@
#ifdef CONFIG_TARGET_AM625_A53_EVM
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM625_SK_DTB "spl/dts/k3-am625-sk.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM625_SK_DTB "u-boot.dtb"
&binman {
@ -155,81 +152,20 @@
};
};
ti-spl {
filename = "tispl.bin";
pad-byte = <0xff>;
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
content = <&atf>;
keyfile = "custMpk.pem";
};
atf: atf-bl31 {
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
};
tee: tee-os {
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
};
dm: blob-ext {
dm: ti-dm {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
ti-secure {
content = <&u_boot_spl_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_spl_nodtb: blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-am625-sk";
type = "flat_dt";
@ -263,29 +199,12 @@
&binman {
u-boot {
filename = "u-boot.img";
pad-byte = <0xff>;
insert-template = <&u_boot_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM625 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
ti-secure {
content = <&u_boot_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_nodtb: u-boot-nodtb {
};
hash {
algo = "crc32";
};
description = "U-Boot for AM625 Board";
};
fdt-0 {
@ -323,67 +242,17 @@
&binman {
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
insert-template = <&ti_spl_unsigned_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
ti-dm {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob {
filename = "spl/u-boot-spl-nodtb.bin";
};
};
fdt-0 {
description = "k3-am625-sk";
type = "flat_dt";
@ -411,26 +280,12 @@
&binman {
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
insert-template = <&u_boot_unsigned_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM625 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
description = "U-Boot for AM625 Board";
};
fdt-0 {

145
arch/arm/dts/k3-am625-sk-u-boot.dtsi
View file

@ -8,122 +8,12 @@
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &main_timer0;
};
aliases {
mmc1 = &sdhci1;
};
memory@80000000 {
bootph-all;
};
};
&main_conf {
bootph-all;
};
&cbass_main {
bootph-all;
};
&main_timer0 {
clock-frequency = <25000000>;
bootph-all;
};
&dmss {
bootph-all;
};
&secure_proxy_main {
bootph-all;
};
&dmsc {
bootph-all;
};
&k3_pds {
bootph-all;
};
&k3_clks {
bootph-all;
};
&k3_reset {
bootph-all;
};
&wkup_conf {
bootph-all;
};
&chipid {
bootph-all;
};
&main_pmx0 {
bootph-all;
};
&main_uart0 {
bootph-all;
};
&main_uart0_pins_default {
bootph-all;
};
&cbass_mcu {
bootph-all;
};
&cbass_wakeup {
bootph-all;
};
&mcu_pmx0 {
bootph-all;
};
&sdhci1 {
bootph-all;
};
&main_mmc1_pins_default {
bootph-all;
};
&fss {
bootph-all;
};
&ospi0_pins_default {
bootph-all;
};
&ospi0 {
bootph-all;
flash@0 {
bootph-all;
partitions {
bootph-all;
partition@3fc0000 {
bootph-all;
};
};
};
};
&inta_main_dmss {
bootph-all;
};
&main_bcdma {
@ -153,41 +43,6 @@
bootph-all;
};
&cpsw3g_mdio {
bootph-all;
};
&cpsw3g_phy0 {
bootph-all;
};
&cpsw3g_phy1 {
bootph-all;
};
&main_rgmii1_pins_default {
bootph-all;
};
&main_rgmii2_pins_default {
bootph-all;
};
&phy_gmii_sel {
bootph-all;
};
&cpsw3g {
bootph-all;
ethernet-ports {
bootph-all;
};
};
&cpsw_port1 {
bootph-all;
};
&cpsw_port2 {
status = "disabled";
};

27
arch/arm/dts/k3-am625-sk.dts
View file

@ -31,6 +31,7 @@
vmain_pd: regulator-0 {
/* TPS65988 PD CONTROLLER OUTPUT */
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vmain_pd";
regulator-min-microvolt = <5000000>;
@ -41,6 +42,7 @@
vcc_5v0: regulator-1 {
/* Output of LM34936 */
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vcc_5v0";
regulator-min-microvolt = <5000000>;
@ -52,6 +54,7 @@
vcc_3v3_sys: regulator-2 {
/* output of LM61460-Q1 */
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
regulator-min-microvolt = <3300000>;
@ -63,6 +66,7 @@
vdd_mmc1: regulator-3 {
/* TPS22918DBVR */
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
@ -75,6 +79,7 @@
vdd_sd_dv: regulator-4 {
/* Output of TLV71033 */
bootph-all;
compatible = "regulator-gpio";
regulator-name = "tlv71033";
pinctrl-names = "default";
@ -102,6 +107,7 @@
&main_pmx0 {
main_rgmii2_pins_default: main-rgmii2-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
@ -119,6 +125,7 @@
};
ospi0_pins_default: ospi0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
@ -135,20 +142,32 @@
};
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
>;
};
main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
>;
};
};
&main_gpio0 {
bootph-all;
};
&main_gpio1 {
bootph-all;
};
&main_i2c1 {
bootph-all;
exp1: gpio@22 {
bootph-all;
compatible = "ti,tca6424";
reg = <0x22>;
gpio-controller;
@ -207,12 +226,18 @@
};
};
&fss {
bootph-all;
};
&ospi0 {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
flash@0 {
bootph-all;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
@ -225,6 +250,7 @@
cdns,read-delay = <4>;
partitions {
bootph-all;
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
@ -260,6 +286,7 @@
};
partition@3fc0000 {
bootph-pre-ram;
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
};

9
arch/arm/dts/k3-am625-verdin-r5.dts
View file

@ -69,16 +69,7 @@
ti,secure-host;
};
&main_esm {
bootph-pre-ram;
};
&mcu_esm {
bootph-pre-ram;
};
&secure_proxy_sa3 {
bootph-pre-ram;
/* We require this for boot handshake */
status = "okay";
};

233
arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
View file

@ -5,80 +5,6 @@
#include "k3-binman.dtsi"
&custmpk_pem {
filename = "../../ti/keys/custMpk.pem";
};
&dkey_pem {
filename = "../../ti/keys/ti-degenerate-key.pem";
};
#ifndef CONFIG_ARM64
&bcfg_yaml {
schema = "../../ti/common/schema.yaml";
};
&pcfg_yaml {
schema = "../../ti/common/schema.yaml";
};
&rcfg_yaml {
schema = "../../ti/common/schema.yaml";
};
&scfg_yaml {
schema = "../../ti/common/schema.yaml";
};
/* combined-tifs-cfg */
&bcfg_yaml_tifs {
schema = "../../ti/common/schema.yaml";
};
&pcfg_yaml_tifs {
schema = "../../ti/common/schema.yaml";
};
&rcfg_yaml_tifs {
schema = "../../ti/common/schema.yaml";
};
&scfg_yaml_tifs {
schema = "../../ti/common/schema.yaml";
};
/* combined-dm-cfg */
&pcfg_yaml_dm {
schema = "../../ti/common/schema.yaml";
};
&rcfg_yaml_dm {
schema = "../../ti/common/schema.yaml";
};
/* combined-sysfw-cfg */
&bcfg_yaml_sysfw {
schema = "../../ti/common/schema.yaml";
};
&pcfg_yaml_sysfw {
schema = "../../ti/common/schema.yaml";
};
&rcfg_yaml_sysfw {
schema = "../../ti/common/schema.yaml";
};
&scfg_yaml_sysfw {
schema = "../../ti/common/schema.yaml";
};
#endif /* CONFIG_ARM64 */
#ifdef CONFIG_TARGET_VERDIN_AM62_R5
&binman {
@ -214,10 +140,7 @@
#ifdef CONFIG_TARGET_VERDIN_AM62_A53
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_VERDIN_AM62_DTB "spl/dts/k3-am625-verdin-wifi-dev.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define VERDIN_AM62_DTB "u-boot.dtb"
&binman {
@ -228,80 +151,21 @@
};
};
ti-spl {
filename = "tispl.bin";
pad-byte = <0xff>;
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
content = <&atf>;
keyfile = "custMpk.pem";
};
atf: atf-bl31 {
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
};
tee: tee-os {
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
};
dm: blob-ext {
dm: ti-dm {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
ti-secure {
content = <&u_boot_spl_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_spl_nodtb: blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-am625-verdin-wifi-dev";
type = "flat_dt";
@ -333,29 +197,12 @@
&binman {
u-boot {
filename = "u-boot.img";
pad-byte = <0xff>;
insert-template = <&u_boot_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM625 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
ti-secure {
content = <&u_boot_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_nodtb: u-boot-nodtb {
};
hash {
algo = "crc32";
};
description = "U-Boot fot AM625 Verdin Board";
};
fdt-0 {
@ -392,66 +239,16 @@
&binman {
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
insert-template = <&ti_spl_unsigned_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
ti-dm {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob {
filename = "spl/u-boot-spl-nodtb.bin";
};
};
fdt-0 {
description = "k3-am625-verdin-wifi-dev";
type = "flat_dt";
@ -479,26 +276,12 @@
&binman {
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
insert-template = <&u_boot_unsigned_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM625 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
description = "U-Boot for AM625 Verdin Board";
};
fdt-0 {

56
arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
View file

@ -21,25 +21,8 @@
};
};
&cbass_main {
bootph-all;
timer@2400000 {
clock-frequency = <25000000>;
bootph-all;
};
};
&cbass_mcu {
bootph-all;
};
&cbass_wakeup {
bootph-all;
};
&chipid {
bootph-all;
&main_timer0 {
clock-frequency = <25000000>;
};
&main_bcdma {
@ -53,6 +36,7 @@
<0x00 0x484c2000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
"ringrt" , "cfg", "tchan", "rchan";
bootph-all;
};
&main_pktdma {
@ -98,34 +82,16 @@
};
&dmsc {
bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-all;
};
};
&dmss {
bootph-all;
};
&fss {
bootph-all;
};
&k3_clks {
bootph-all;
};
&k3_pds {
bootph-all;
};
&k3_reset {
bootph-all;
};
&main_gpio0 {
bootph-all;
};
@ -156,10 +122,6 @@
};
};
&main_pmx0 {
bootph-all;
};
/* Verdin UART_3, used as the Linux console */
&main_uart0 {
bootph-all;
@ -170,10 +132,6 @@
bootph-all;
};
&mcu_pmx0 {
bootph-all;
};
&pinctrl_ctrl_sleep_moci {
bootph-all;
};
@ -210,18 +168,10 @@
status = "disabled";
};
&secure_proxy_main {
bootph-all;
};
&verdin_ctrl_sleep_moci {
bootph-all;
};
&wkup_conf {
bootph-all;
};
/* Verdin UART_2 */
&wkup_uart0 {
bootph-all;

162
arch/arm/dts/k3-am62a-sk-binman.dtsi
View file

@ -144,10 +144,7 @@
#ifdef CONFIG_TARGET_AM62A7_A53_EVM
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM62A7_SK_DTB "spl/dts/k3-am62a7-sk.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM62A7_SK_DTB "u-boot.dtb"
&binman {
@ -158,81 +155,20 @@
};
};
ti-spl {
filename = "tispl.bin";
pad-byte = <0xff>;
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
content = <&atf>;
keyfile = "custMpk.pem";
};
atf: atf-bl31 {
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
};
tee: tee-os {
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
};
dm: blob-ext {
dm: ti-dm {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
ti-secure {
content = <&u_boot_spl_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_spl_nodtb: blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-am62a7-sk";
type = "flat_dt";
@ -266,29 +202,12 @@
&binman {
u-boot {
filename = "u-boot.img";
pad-byte = <0xff>;
insert-template = <&u_boot_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM62Ax board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
ti-secure {
content = <&u_boot_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_nodtb: u-boot-nodtb {
};
hash {
algo = "crc32";
};
description = "U-Boot for AM62Ax Board";
};
fdt-0 {
@ -326,67 +245,16 @@
&binman {
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
insert-template = <&ti_spl_unsigned_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
ti-dm {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob {
filename = "spl/u-boot-spl-nodtb.bin";
};
};
fdt-0 {
description = "k3-am62a7-sk";
type = "flat_dt";
@ -414,26 +282,12 @@
&binman {
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
insert-template = <&u_boot_unsigned_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM62Ax board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
description = "U-Boot for AM62Ax Board";
};
fdt-0 {

109
arch/arm/dts/k3-am62x-sk-common.dtsi
View file

@ -28,6 +28,7 @@
};
memory@80000000 {
bootph-pre-ram;
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
@ -114,11 +115,23 @@
clocks = <&tlv320_mclk>;
};
};
hdmi0: connector-hdmi {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&sii9022_out>;
};
};
};
};
&main_pmx0 {
/* First pad number is ALW package and second is AMC package */
main_uart0_pins_default: main-uart0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */
AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */
@ -126,6 +139,7 @@
};
main_uart1_pins_default: main-uart1-default-pins {
bootph-pre-ram;
pinctrl-single,pins = <
AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19/B18) MCASP0_AXR3.UART1_CTSn */
AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19/B17) MCASP0_AXR2.UART1_RTSn */
@ -156,6 +170,7 @@
};
main_mmc0_pins_default: main-mmc0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */
AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */
@ -171,6 +186,7 @@
};
main_mmc1_pins_default: main-mmc1-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */
AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */
@ -196,6 +212,7 @@
};
main_rgmii1_pins_default: main-rgmii1-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */
AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17/Y16) RGMII1_RD1 */
@ -226,10 +243,44 @@
AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */
>;
};
main_dss0_pins_default: main-dss0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */
AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */
AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */
AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */
AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */
AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */
AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */
AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */
AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */
AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */
AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */
AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */
AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */
AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */
AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */
AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */
AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */
AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */
AM62X_IOPAD(0x05c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */
AM62X_IOPAD(0x060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */
AM62X_IOPAD(0x064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */
AM62X_IOPAD(0x068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */
AM62X_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */
AM62X_IOPAD(0x070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */
AM62X_IOPAD(0x074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */
AM62X_IOPAD(0x078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */
>;
};
};
&mcu_pmx0 {
wkup_uart0_pins_default: wkup-uart0-default-pins {
bootph-pre-ram;
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6/A7) WKUP_UART0_CTSn */
AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4/B4) WKUP_UART0_RTSn */
@ -241,12 +292,14 @@
&wkup_uart0 {
/* WKUP UART0 is used by DM firmware */
bootph-pre-ram;
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};
&main_uart0 {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
@ -254,6 +307,7 @@
&main_uart1 {
/* Main UART1 is used by TIFS firmware */
bootph-pre-ram;
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
@ -300,7 +354,7 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
clock-frequency = <100000>;
tlv320aic3106: audio-codec@1b {
#sound-dai-cells = <0>;
@ -313,9 +367,40 @@
IOVDD-supply = <&vcc_3v3_sys>;
DRVDD-supply = <&vcc_3v3_sys>;
};
sii9022: bridge-hdmi@3b {
compatible = "sil,sii9022";
reg = <0x3b>;
interrupt-parent = <&exp1>;
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
#sound-dai-cells = <0>;
sil,i2s-data-lanes = < 0 >;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sii9022_in: endpoint {
remote-endpoint = <&dpi1_out>;
};
};
port@1 {
reg = <1>;
sii9022_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
};
&sdhci0 {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
@ -325,6 +410,7 @@
&sdhci1 {
/* SD/MMC */
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
@ -333,21 +419,25 @@
};
&cpsw3g {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&main_rgmii1_pins_default>;
};
&cpsw_port1 {
bootph-all;
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw3g_mdio {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mdio1_pins_default>;
cpsw3g_phy0: ethernet-phy@0 {
bootph-all;
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
@ -410,3 +500,20 @@
tx-num-evt = <32>;
rx-num-evt = <32>;
};
&dss {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_dss0_pins_default>;
};
&dss_ports {
/* VP2: DPI Output */
port@1 {
reg = <1>;
dpi1_out: endpoint {
remote-endpoint = <&sii9022_in>;
};
};
};

151
arch/arm/dts/k3-am64x-binman.dtsi
View file

@ -118,87 +118,27 @@
#ifdef CONFIG_TARGET_AM642_A53_EVM
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM642_EVM_DTB "spl/dts/k3-am642-evm.dtb"
#define SPL_AM642_SK_DTB "spl/dts/k3-am642-sk.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM642_EVM_DTB "u-boot.dtb"
#define AM642_SK_DTB "arch/arm/dts/k3-am642-sk.dtb"
&binman {
ti-spl {
filename = "tispl.bin";
pad-byte = <0xff>;
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
content = <&atf>;
keyfile = "custMpk.pem";
};
atf: atf-bl31 {
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
};
tee: tee-os {
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
filename = "/dev/null";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
ti-secure {
content = <&u_boot_spl_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_spl_nodtb: blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-am642-evm";
@ -254,29 +194,12 @@
&binman {
u-boot {
filename = "u-boot.img";
pad-byte = <0xff>;
insert-template = <&u_boot_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM64 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
ti-secure {
content = <&u_boot_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_nodtb: u-boot-nodtb {
};
hash {
algo = "crc32";
};
description = "U-Boot for AM64 Board";
};
fdt-0 {
@ -340,65 +263,17 @@
&binman {
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
insert-template = <&ti_spl_unsigned_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
filename = "/dev/null";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob {
filename = "spl/u-boot-spl-nodtb.bin";
};
};
fdt-0 {
description = "k3-am642-evm";
type = "flat_dt";
@ -443,26 +318,12 @@
&binman {
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
insert-template = <&u_boot_unsigned_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM64 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
description = "U-Boot for AM64 Board";
};
fdt-0 {

273
arch/arm/dts/k3-am65x-binman.dtsi
View file

@ -42,77 +42,7 @@
};
itb {
filename = "sysfw-am65x_sr2-hs-evm.itb";
fit {
description = "SYSFW and Config fragments";
#address-cells = <1>;
images {
sysfw.bin {
description = "sysfw";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sysfw.bin";
};
};
board-cfg.bin {
description = "board-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&board_cfg>;
keyfile = "custMpk.pem";
};
board_cfg: board-cfg {
filename = "board-cfg.bin";
type = "blob-ext";
};
};
pm-cfg.bin {
description = "pm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&pm_cfg>;
keyfile = "custMpk.pem";
};
pm_cfg: pm-cfg {
filename = "pm-cfg.bin";
type = "blob-ext";
};
};
rm-cfg.bin {
description = "rm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&rm_cfg>;
keyfile = "custMpk.pem";\
};
rm_cfg: rm-cfg {
filename = "rm-cfg.bin";
type = "blob-ext";
};
};
sec-cfg.bin {
description = "sec-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&sec_cfg>;
keyfile = "custMpk.pem";
};
sec_cfg: sec-cfg {
filename = "sec-cfg.bin";
type = "blob-ext";
};
};
};
};
insert-template = <&itb_template>;
};
};
@ -149,55 +79,14 @@
itb_gp {
filename = "sysfw-am65x_sr2-gp-evm.itb";
symlink = "sysfw.itb";
insert-template = <&itb_unsigned_template>;
fit {
description = "SYSFW and Config fragments";
#address-cells = <1>;
images {
sysfw.bin {
description = "sysfw";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sysfw.bin_gp";
};
};
board-cfg.bin {
description = "board-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "board-cfg.bin";
};
};
pm-cfg.bin {
description = "pm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "pm-cfg.bin";
};
};
rm-cfg.bin {
description = "rm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "rm-cfg.bin";
};
};
sec-cfg.bin {
description = "sec-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sec-cfg.bin";
};
};
};
};
};
@ -206,86 +95,22 @@
#ifdef CONFIG_TARGET_AM654_A53_EVM
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM654_EVM_DTB "spl/dts/k3-am654-base-board.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM654_EVM_DTB "u-boot.dtb"
&binman {
ti-spl {
filename = "tispl.bin";
pad-byte = <0xff>;
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
content = <&atf>;
keyfile = "custMpk.pem";
};
atf: atf-bl31 {
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
};
tee: tee-os {
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
filename = "/dev/null";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
ti-secure {
content = <&u_boot_spl_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_spl_nodtb: blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-am654-base-board";
type = "flat_dt";
@ -317,29 +142,12 @@
&binman {
u-boot {
filename = "u-boot.img";
pad-byte = <0xff>;
insert-template = <&u_boot_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM65 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
ti-secure {
content = <&u_boot_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_nodtb: u-boot-nodtb {
};
hash {
algo = "crc32";
};
description = "U-Boot for AM65 Board";
};
fdt-0 {
@ -378,67 +186,16 @@
&binman {
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
insert-template = <&ti_spl_unsigned_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
filename = "/dev/null";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-j721e-common-proc-board";
type = "flat_dt";
@ -466,26 +223,12 @@
&binman {
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
insert-template = <&u_boot_unsigned_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM65 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
description = "U-Boot for AM65 Board";
};
fdt-0 {

56
arch/arm/dts/k3-am68-sk-base-board.dts
View file

@ -553,3 +553,59 @@
};
};
};
&serdes_ln_ctrl {
idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_PCIE1_LANE1>,
<J721S2_SERDES0_LANE2_USB_SWAP>, <J721S2_SERDES0_LANE3_USB>;
};
&serdes_refclk {
clock-frequency = <100000000>;
};
&serdes0 {
status = "okay";
serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
};
serdes0_usb_link: phy@2 {
status = "okay";
reg = <2>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_USB3>;
resets = <&serdes_wiz0 3>;
};
};
&pcie1_rc {
status = "okay";
reset-gpios = <&exp1 10 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
};
&usb_serdes_mux {
idle-states = <0>; /* USB0 to SERDES lane 2 */
};
&usbss0 {
status = "okay";
pinctrl-0 = <&main_usbss0_pins_default>;
pinctrl-names = "default";
ti,vbus-divider;
};
&usb0 {
dr_mode = "host";
maximum-speed = "super-speed";
phys = <&serdes0_usb_link>;
phy-names = "cdns3,usb3-phy";
};

208
arch/arm/dts/k3-am68-sk-som.dtsi
View file

@ -25,6 +25,108 @@
reg = <0x00 0x9e800000 0x00 0x01800000>;
no-map;
};
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa5000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa5100000 0x00 0xf00000>;
no-map;
};
c71_0_dma_memory_region: c71-dma-memory@a6000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6000000 0x00 0x100000>;
no-map;
};
c71_0_memory_region: c71-memory@a6100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6100000 0x00 0xf00000>;
no-map;
};
c71_1_dma_memory_region: c71-dma-memory@a7000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7000000 0x00 0x100000>;
no-map;
};
c71_1_memory_region: c71-memory@a7100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a8000000 {
reg = <0x00 0xa8000000 0x00 0x01c00000>;
alignment = <0x1000>;
no-map;
};
};
};
@ -49,3 +151,109 @@
reg = <0x51>;
};
};
&mailbox0_cluster0 {
status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster1 {
status = "okay";
interrupts = <432>;
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster2 {
status = "okay";
interrupts = <428>;
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster4 {
status = "okay";
interrupts = <420>;
mbox_c71_0: mbox-c71-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_c71_1: mbox-c71-1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mcu_r5fss0_core0 {
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&c71_0 {
status = "okay";
mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};
&c71_1 {
status = "okay";
mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
memory-region = <&c71_1_dma_memory_region>,
<&c71_1_memory_region>;
};

408
arch/arm/dts/k3-binman.dtsi
View file

@ -3,6 +3,8 @@
* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-security.h"
/ {
binman: binman {
multiple-images;
@ -13,14 +15,14 @@
custMpk {
filename = "custMpk.pem";
custmpk_pem: blob-ext {
filename = "../keys/custMpk.pem";
filename = "arch/arm/mach-k3/keys/custMpk.pem";
};
};
ti-degenerate-key {
filename = "ti-degenerate-key.pem";
dkey_pem: blob-ext {
filename = "../keys/ti-degenerate-key.pem";
filename = "arch/arm/mach-k3/keys/ti-degenerate-key.pem";
};
};
};
@ -32,28 +34,28 @@
filename = "board-cfg.bin";
bcfg_yaml: ti-board-config {
config = "board-cfg.yaml";
schema = "../common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
};
pm-cfg {
filename = "pm-cfg.bin";
pcfg_yaml: ti-board-config {
config = "pm-cfg.yaml";
schema = "../common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
};
rm-cfg {
filename = "rm-cfg.bin";
rcfg_yaml: ti-board-config {
config = "rm-cfg.yaml";
schema = "../common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
};
sec-cfg {
filename = "sec-cfg.bin";
scfg_yaml: ti-board-config {
config = "sec-cfg.yaml";
schema = "../common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
};
combined-tifs-cfg {
@ -61,19 +63,19 @@
ti-board-config {
bcfg_yaml_tifs: board-cfg {
config = "board-cfg.yaml";
schema = "../common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
scfg_yaml_tifs: sec-cfg {
config = "sec-cfg.yaml";
schema = "../common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
pcfg_yaml_tifs: pm-cfg {
config = "pm-cfg.yaml";
schema = "../common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
rcfg_yaml_tifs: rm-cfg {
config = "rm-cfg.yaml";
schema = "../common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
};
};
@ -82,11 +84,11 @@
ti-board-config {
pcfg_yaml_dm: pm-cfg {
config = "pm-cfg.yaml";
schema = "../common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
rcfg_yaml_dm: rm-cfg {
config = "rm-cfg.yaml";
schema = "../common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
};
};
@ -95,22 +97,396 @@
ti-board-config {
bcfg_yaml_sysfw: board-cfg {
config = "board-cfg.yaml";
schema = "../common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
scfg_yaml_sysfw: sec-cfg {
config = "sec-cfg.yaml";
schema = "../common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
pcfg_yaml_sysfw: pm-cfg {
config = "pm-cfg.yaml";
schema = "../common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
rcfg_yaml_sysfw: rm-cfg {
config = "rm-cfg.yaml";
schema = "../common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
};
};
};
&binman {
itb_template: template-5 {
fit {
description = "SYSFW and Config fragments";
#address-cells = <1>;
images {
sysfw.bin {
description = "sysfw";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sysfw.bin";
};
};
board-cfg.bin {
description = "board-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&board_cfg>;
keyfile = "custMpk.pem";
};
board_cfg: board-cfg {
filename = "board-cfg.bin";
type = "blob-ext";
};
};
pm-cfg.bin {
description = "pm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&pm_cfg>;
keyfile = "custMpk.pem";
};
pm_cfg: pm-cfg {
filename = "pm-cfg.bin";
type = "blob-ext";
};
};
rm-cfg.bin {
description = "rm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&rm_cfg>;
keyfile = "custMpk.pem";
};
rm_cfg: rm-cfg {
filename = "rm-cfg.bin";
type = "blob-ext";
};
};
sec-cfg.bin {
description = "sec-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&sec_cfg>;
keyfile = "custMpk.pem";
};
sec_cfg: sec-cfg {
filename = "sec-cfg.bin";
type = "blob-ext";
};
};
};
};
};
itb_unsigned_template: template-6 {
fit {
description = "SYSFW and Config fragments";
#address-cells = <1>;
images {
sysfw.bin {
description = "sysfw";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sysfw.bin_fs";
};
};
board-cfg.bin {
description = "board-cfg";
type = "firmware";
arch = "arm";
compression = "none";
board-cfg {
filename = "board-cfg.bin";
type = "blob-ext";
};
};
pm-cfg.bin {
description = "pm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
pm-cfg {
filename = "pm-cfg.bin";
type = "blob-ext";
};
};
rm-cfg.bin {
description = "rm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
rm-cfg {
filename = "rm-cfg.bin";
type = "blob-ext";
};
};
sec-cfg.bin {
description = "sec-cfg";
type = "firmware";
arch = "arm";
compression = "none";
sec-cfg {
filename = "sec-cfg.bin";
type = "blob-ext";
};
};
};
};
};
};
#else
&binman {
ti_spl_template: template-1 {
filename = "tispl.bin";
pad-byte = <0xff>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
content = <&atf>;
keyfile = "custMpk.pem";
};
atf: atf-bl31 {
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
};
tee: tee-os {
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
ti-secure {
content = <&u_boot_spl_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_spl_nodtb: blob-ext {
filename = "spl/u-boot-spl-nodtb.bin";
};
};
};
};
};
ti_spl_unsigned_template: template-2 {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob-ext {
filename = "spl/u-boot-spl-nodtb.bin";
};
};
};
};
};
u_boot_template: template-3 {
filename = "u-boot.img";
pad-byte = <0xff>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
ti-secure {
content = <&u_boot_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_nodtb: u-boot-nodtb {
};
hash {
algo = "crc32";
};
};
};
};
};
u_boot_unsigned_template: template-4 {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = "u-boot-nodtb.bin";
};
hash {
algo = "crc32";
};
};
};
};
};
firewall_bg_1: template-5 {
control = <(FWCTRL_EN | FWCTRL_LOCK |
FWCTRL_BG | FWCTRL_CACHE)>;
permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) |
FWPERM_SECURE_PRIV_RWCD |
FWPERM_SECURE_USER_RWCD |
FWPERM_NON_SECURE_PRIV_RWCD |
FWPERM_NON_SECURE_USER_RWCD)>;
start_address = <0x0 0x0>;
end_address = <0xff 0xffffffff>;
};
firewall_bg_3: template-6 {
insert-template = <&firewall_bg_1>;
permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) |
FWPERM_SECURE_PRIV_RWCD |
FWPERM_SECURE_USER_RWCD |
FWPERM_NON_SECURE_PRIV_RWCD |
FWPERM_NON_SECURE_USER_RWCD)>,
<((FWPRIVID_ALL << FWPRIVID_SHIFT) |
FWPERM_SECURE_PRIV_RWCD |
FWPERM_SECURE_USER_RWCD |
FWPERM_NON_SECURE_PRIV_RWCD |
FWPERM_NON_SECURE_USER_RWCD)>,
<((FWPRIVID_ALL << FWPRIVID_SHIFT) |
FWPERM_SECURE_PRIV_RWCD |
FWPERM_SECURE_USER_RWCD |
FWPERM_NON_SECURE_PRIV_RWCD |
FWPERM_NON_SECURE_USER_RWCD)>;
};
firewall_armv8_atf_fg: template-7 {
control = <(FWCTRL_EN | FWCTRL_LOCK |
FWCTRL_CACHE)>;
permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) |
FWPERM_SECURE_PRIV_RWCD |
FWPERM_SECURE_USER_RWCD)>;
start_address = <0x0 0x70000000>;
end_address = <0x0 0x7001ffff>;
};
firewall_armv8_optee_fg: template-8 {
control = <(FWCTRL_EN | FWCTRL_LOCK |
FWCTRL_CACHE)>;
permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) |
FWPERM_SECURE_PRIV_RWCD |
FWPERM_SECURE_USER_RWCD)>;
start_address = <0x0 0x9e800000>;
end_address = <0x0 0x9fffffff>;
};
};
#endif

235
arch/arm/dts/k3-j7200-binman.dtsi
View file

@ -180,10 +180,7 @@
#ifdef CONFIG_TARGET_J7200_A72_EVM
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_J7200_EVM_DTB "spl/dts/k3-j7200-common-proc-board.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define J7200_EVM_DTB "u-boot.dtb"
&binman {
@ -194,82 +191,110 @@
};
};
ti-spl {
filename = "tispl.bin";
pad-byte = <0xff>;
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
content = <&atf>;
keyfile = "custMpk.pem";
};
atf: atf-bl31 {
auth-in-place = <0xa02>;
firewall-257-0 {
/* cpu_0_cpu_0_msmc Background Firewall */
insert-template = <&firewall_bg_1>;
id = <257>;
region = <0>;
};
firewall-257-1 {
/* cpu_0_cpu_0_msmc Foreground Firewall */
insert-template = <&firewall_armv8_atf_fg>;
id = <257>;
region = <1>;
};
/* firewall-4760-0 {
* nb_slv0__mem0 Background Firewall
* Already configured by the secure entity
* };
*/
firewall-4760-1 {
/* nb_slv0__mem0 Foreground Firewall */
insert-template = <&firewall_armv8_atf_fg>;
id = <4760>;
region = <1>;
};
/* firewall-4761-0 {
* nb_slv1__mem0 Background Firewall
* Already configured by the secure entity
* };
*/
firewall-4761-1 {
/* nb_slv1__mem0 Foreground Firewall */
insert-template = <&firewall_armv8_atf_fg>;
id = <4761>;
region = <1>;
};
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
};
tee: tee-os {
auth-in-place = <0xa02>;
/* cpu_0_cpu_0_msmc region 0 and 1 configured
* during ATF Firewalling
*/
firewall-257-2 {
/* cpu_0_cpu_0_msmc Foreground Firewall */
insert-template = <&firewall_armv8_optee_fg>;
id = <257>;
region = <2>;
};
firewall-4762-0 {
/* nb_slv2__mem0 Background Firewall - 0 */
insert-template = <&firewall_bg_3>;
id = <4762>;
region = <0>;
};
firewall-4762-1 {
/* nb_slv2__mem0 Foreground Firewall */
insert-template = <&firewall_armv8_optee_fg>;
id = <4762>;
region = <1>;
};
firewall-4763-0 {
/* nb_slv3__mem0 Background Firewall - 0 */
insert-template = <&firewall_bg_3>;
id = <4763>;
region = <0>;
};
firewall-4763-1 {
/* nb_slv3__mem0 Foreground Firewall */
insert-template = <&firewall_armv8_optee_fg>;
id = <4763>;
region = <1>;
};
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
};
dm: blob-ext {
dm: ti-dm {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
ti-secure {
content = <&u_boot_spl_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_spl_nodtb: blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-j7200-common-proc-board";
type = "flat_dt";
@ -302,29 +327,12 @@
&binman {
u-boot {
filename = "u-boot.img";
pad-byte = <0xff>;
insert-template = <&u_boot_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for J7200 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
ti-secure {
content = <&u_boot_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_nodtb: u-boot-nodtb {
};
hash {
algo = "crc32";
};
description = "U-Boot for J7200 Board";
};
fdt-0 {
@ -362,67 +370,16 @@
&binman {
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
insert-template = <&ti_spl_unsigned_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
ti-dm {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob {
filename = SPL_NODTB;
};
};
fdt-1 {
description = "k3-j7200-common-proc-board";
type = "flat_dt";
@ -450,26 +407,12 @@
&binman {
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
insert-template = <&u_boot_unsigned_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for J7200 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
description = "U-Boot for J7200 Board";
};
fdt-1 {

2
arch/arm/dts/k3-j7200-main.dtsi
View file

@ -91,7 +91,7 @@
};
main_navss: bus@30000000 {
compatible = "simple-mfd";
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;

9
arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
View file

@ -318,7 +318,7 @@
};
mcu_navss: bus@28380000 {
compatible = "simple-mfd";
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
@ -637,4 +637,11 @@
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
mcu_esm: esm@40800000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x40800000 0x00 0x1000>;
ti,esm-pins = <95>;
bootph-pre-ram;
};
};

3
arch/arm/dts/k3-j7200-r5-common-proc-board.dts
View file

@ -24,7 +24,8 @@
<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 1>;
assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 323 0>;
assigned-clock-parents= <0>, <0>, <&k3_clks 323 2>;
assigned-clock-rates = <2000000000>, <200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;

358
arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi Normal file
View file

@ -0,0 +1,358 @@
// SPDX-License-Identifier: GPL-2.0
/*
* https://beagleboard.org/ai-64
*
* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation
* Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
*/
#include "k3-binman.dtsi"
/ {
memory@80000000 {
bootph-all;
};
/* Keep the LEDs on by default to indicate life */
leds {
bootph-all;
led-0 {
default-state = "on";
bootph-all;
};
led-1 {
default-state = "on";
bootph-all;
};
led-2 {
default-state = "on";
bootph-all;
};
led-3 {
default-state = "on";
bootph-all;
};
led-4 {
default-state = "on";
bootph-all;
};
};
};
&cbass_main {
bootph-all;
};
&main_navss {
bootph-all;
};
&cbass_mcu_wakeup {
bootph-all;
chipid@43000014 {
bootph-all;
};
};
&mcu_navss {
bootph-all;
};
&mcu_ringacc {
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
bootph-all;
};
&mcu_udmap {
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x284c0000 0x0 0x4000>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x284a0000 0x0 0x4000>,
<0x0 0x2aa00000 0x0 0x40000>,
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
bootph-all;
};
&secure_proxy_main {
bootph-all;
};
&dmsc {
bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-all;
};
};
&k3_pds {
bootph-all;
};
&k3_clks {
bootph-all;
};
&k3_reset {
bootph-all;
};
&wkup_pmx0 {
bootph-all;
};
&main_pmx0 {
bootph-all;
};
&main_uart0 {
bootph-all;
};
&main_gpio0 {
bootph-all;
};
&main_uart0_pins_default {
bootph-all;
};
&main_sdhci0 {
bootph-all;
};
&main_sdhci1 {
bootph-all;
sdhci-caps-mask = <0x00000007 0x00000000>;
/delete-property/ cd-gpios;
/delete-property/ cd-debounce-delay-ms;
/delete-property/ ti,fails-without-test-cd;
/delete-property/ no-1-8-v;
};
&main_mmc1_pins_default {
bootph-all;
};
&mcu_cpsw {
bootph-all;
};
&davinci_mdio {
bootph-all;
};
&phy0 {
bootph-all;
};
&serdes2 {
bootph-all;
};
&serdes_ln_ctrl {
bootph-all;
};
&serdes2_usb_link {
bootph-all;
};
&usb_serdes_mux {
bootph-all;
};
&serdes_wiz2 {
bootph-all;
};
&main_usbss1_pins_default {
bootph-all;
};
&mcu_usbss1_pins_default {
bootph-all;
};
&usbss1 {
bootph-all;
};
&usb1 {
bootph-all;
};
&wkup_i2c0_pins_default {
bootph-all;
};
&wkup_i2c0 {
bootph-all;
};
#ifdef CONFIG_TARGET_J721E_A72_BEAGLEBONEAI64
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_J721E_BBAI64_DTB "spl/dts/k3-j721e-beagleboneai64.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define J721E_BBAI64_DTB "arch/arm/dts/k3-j721e-beagleboneai64.dtb"
&binman {
ti-dm {
filename = "ti-dm.bin";
blob-ext {
filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f";
};
};
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-j721e-beagleboneai64";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = SPL_J721E_BBAI64_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-j721e-beagleboneai64";
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
};
};
};
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for j721e board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
};
fdt-0 {
description = "k3-j721e-beagleboneai64";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = J721E_BBAI64_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-j721e-beagleboneai64";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
#endif

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arch/arm/dts/k3-j721e-beagleboneai64.dts Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* https://beagleboard.org/ai-64
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation
* Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation
*/
/dts-v1/;
#include "k3-j721e.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-cadence.h>
/ {
compatible = "beagle,j721e-beagleboneai64", "ti,j721e";
model = "BeagleBoard.org BeagleBone AI-64";
aliases {
serial0 = &wkup_uart0;
serial2 = &main_uart0;
mmc0 = &main_sdhci0;
mmc1 = &main_sdhci1;
i2c0 = &wkup_i2c0;
i2c1 = &main_i2c6;
i2c2 = &main_i2c2;
i2c3 = &main_i2c4;
};
chosen {
stdout-path = "serial2:115200n8";
};
memory@80000000 {
device_type = "memory";
/* 4G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
<0x00000008 0x80000000 0x00000000 0x80000000>;
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>;
no-map;
};
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa5000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa5100000 0x00 0xf00000>;
no-map;
};
c66_1_dma_memory_region: c66-dma-memory@a6000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6000000 0x00 0x100000>;
no-map;
};
c66_0_memory_region: c66-memory@a6100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6100000 0x00 0xf00000>;
no-map;
};
c66_0_dma_memory_region: c66-dma-memory@a7000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7000000 0x00 0x100000>;
no-map;
};
c66_1_memory_region: c66-memory@a7100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7100000 0x00 0xf00000>;
no-map;
};
c71_0_dma_memory_region: c71-dma-memory@a8000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa8000000 0x00 0x100000>;
no-map;
};
c71_0_memory_region: c71-memory@a8100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa8100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@aa000000 {
reg = <0x00 0xaa000000 0x00 0x01c00000>;
alignment = <0x1000>;
no-map;
};
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&sw_pwr_pins_default>;
button-1 {
label = "BOOT";
linux,code = <BTN_0>;
gpios = <&wkup_gpio0 0 GPIO_ACTIVE_LOW>;
};
button-2 {
label = "POWER";
linux,code = <KEY_POWER>;
gpios = <&wkup_gpio0 4 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins_default>;
led-0 {
gpios = <&main_gpio0 96 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_HEARTBEAT;
linux,default-trigger = "heartbeat";
};
led-1 {
gpios = <&main_gpio0 95 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_DISK_ACTIVITY;
linux,default-trigger = "mmc0";
};
led-2 {
gpios = <&main_gpio0 97 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_CPU;
linux,default-trigger = "cpu";
};
led-3 {
gpios = <&main_gpio0 110 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_DISK_ACTIVITY;
linux,default-trigger = "mmc1";
};
led-4 {
gpios = <&main_gpio0 109 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_WLAN;
default-state = "off";
};
};
evm_12v0: regulator-0 {
/* main supply */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
vsys_3v3: regulator-1 {
/* Output of LMS140 */
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vsys_5v0: regulator-2 {
/* Output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vdd_mmc1: regulator-3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&sd_pwr_en_pins_default>;
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
vin-supply = <&vsys_3v3>;
gpio = <&main_gpio0 82 GPIO_ACTIVE_HIGH>;
};
vdd_sd_dv_alt: regulator-4 {
compatible = "regulator-gpio";
pinctrl-names = "default";
pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
regulator-name = "tlv71033";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
vin-supply = <&vsys_5v0>;
gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
states = <1800000 0x0>,
<3300000 0x1>;
};
dp_pwr_3v3: regulator-5 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&dp0_3v3_en_pins_default>;
regulator-name = "dp-pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; /* DP0_PWR_SW_EN */
enable-active-high;
};
dp0: connector {
compatible = "dp-connector";
label = "DP0";
type = "full-size";
dp-pwr-supply = <&dp_pwr_3v3>;
port {
dp_connector_in: endpoint {
remote-endpoint = <&dp0_out>;
};
};
};
};
&main_pmx0 {
led_pins_default: led-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */
J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */
J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
J721E_IOPAD(0x1bc, PIN_INPUT, 7) /* (V24) MDIO0_MDC.GPIO0_110 */
J721E_IOPAD(0x1b8, PIN_INPUT, 7) /* (V26) MDIO0_MDIO.GPIO0_109 */
>;
};
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
>;
};
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
>;
};
sd_pwr_en_pins_default: sd-pwr-en-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
>;
};
vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
>;
};
main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */
>;
};
main_usbss1_pins_default: main-usbss1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */
>;
};
dp0_3v3_en_pins_default:dp0-3v3-en-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */
>;
};
dp0_pins_default: dp0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */
>;
};
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
>;
};
main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x208, PIN_INPUT_PULLUP, 4) /* (W5) MCAN0_RX.I2C2_SCL */
J721E_IOPAD(0x20c, PIN_INPUT_PULLUP, 4) /* (W6) MCAN0_TX.I2C2_SDA */
J721E_IOPAD(0x138, PIN_INPUT, 7) /* (AE25) PRG0_PRU1_GPO14.GPIO0_77 */
J721E_IOPAD(0x13c, PIN_INPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */
>;
};
main_i2c3_pins_default: main-i2c3-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
>;
};
main_i2c4_pins_default: main-i2c4-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1e0, PIN_INPUT_PULLUP, 2) /* (Y5) SPI1_D0.I2C4_SCL */
J721E_IOPAD(0x1dc, PIN_INPUT_PULLUP, 2) /* (Y1) SPI1_CLK.I2C4_SDA */
J721E_IOPAD(0x30, PIN_INPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */
J721E_IOPAD(0x34, PIN_INPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */
>;
};
main_i2c5_pins_default: main-i2c5-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
>;
};
main_i2c6_pins_default: main-i2c6-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
J721E_IOPAD(0x74, PIN_INPUT, 7) /* (AC21) PRG1_PRU1_GPO7.GPIO0_28 */
J721E_IOPAD(0xa4, PIN_INPUT, 7) /* (AH22) PRG1_PRU1_GPO19.GPIO0_40 */
>;
};
csi0_gpio_pins_default: csi0-gpio-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
>;
};
csi1_gpio_pins_default: csi1-gpio-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
J721E_IOPAD(0x1b0, PIN_INPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
>;
};
pcie1_rst_pins_default: pcie1-rst-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */
>;
};
};
&wkup_pmx0 {
eeprom_wp_pins_default: eeprom-wp-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */
>;
};
mcu_adc0_pins_default: mcu-adc0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */
J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */
J721E_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K28) MCU_ADC0_AIN2 */
J721E_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (L28) MCU_ADC0_AIN3 */
J721E_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN4 */
J721E_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (K27) MCU_ADC0_AIN5 */
J721E_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K29) MCU_ADC0_AIN6 */
>;
};
mcu_adc1_pins_default: mcu-adc1-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */
>;
};
mikro_bus_pins_default: mikro-bus-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */
J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */
J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 7) /* SDA (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */
J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* SCL (G27) WKUP_GPIO0_8.MCU_I2C1_SCL */
J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 7) /* SCL (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */
J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* MOSI (F28) WKUP_GPIO0_2.MCU_SPI1_D1 */
J721E_WKUP_IOPAD(0xb4, PIN_INPUT, 7) /* MISO (F25) WKUP_GPIO0_1.MCU_SPI1_D0 */
J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* CLK (F26) WKUP_GPIO0_0.MCU_SPI1_CLK */
J721E_WKUP_IOPAD(0xbc, PIN_INPUT, 7) /* CS (F27) WKUP_GPIO0_3.MCU_SPI1_CS0 */
J721E_WKUP_IOPAD(0x44, PIN_INPUT, 7) /* RX (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */
J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* TX (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */
J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* INT (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */
J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /* RST (E22) MCU_OSPI1_CSn1.WKUP_GPIO0_37 */
J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* PWM (H27) WKUP_GPIO0_11 */
J721E_WKUP_IOPAD(0xac, PIN_INPUT, 7) /* AN (C29) MCU_MCAN0_RX.WKUP_GPIO0_59 */
>;
};
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
>;
};
mcu_mdio_pins_default: mcu-mdio1-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
>;
};
sw_pwr_pins_default: sw-pwr-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */
>;
};
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
>;
};
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
>;
};
mcu_usbss1_pins_default: mcu-usbss1-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */
>;
};
};
&wkup_uart0 {
/* Wakeup UART is used by TIFS firmware. */
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};
&main_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
/* Shared with ATF on this platform */
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
&main_sdhci0 {
/* eMMC */
status = "okay";
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&main_sdhci1 {
/* SD Card */
status = "okay";
vmmc-supply = <&vdd_mmc1>;
vqmmc-supply = <&vdd_sd_dv_alt>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&main_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
};
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
};
&main_i2c2 {
/* BBB Header: P9.19 and P9.20 */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c2_pins_default>;
clock-frequency = <100000>;
};
&main_i2c3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c3_pins_default>;
clock-frequency = <400000>;
};
&main_i2c4 {
/* BBB Header: P9.24 and P9.26 */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c4_pins_default>;
clock-frequency = <100000>;
};
&main_i2c5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c5_pins_default>;
clock-frequency = <400000>;
};
&main_i2c6 {
/* BBB Header: P9.17 and P9.18 */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c6_pins_default>;
clock-frequency = <100000>;
status = "okay";
};
&wkup_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@50 {
compatible = "atmel,24c04";
reg = <0x50>;
pinctrl-names = "default";
pinctrl-0 = <&eeprom_wp_pins_default>;
};
};
&wkup_gpio0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>,
<&mikro_bus_pins_default>;
};
&main_gpio0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>;
};
&main_gpio1 {
status = "okay";
};
&usb_serdes_mux {
idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
};
&serdes_ln_ctrl {
idle-states = <J721E_SERDES0_LANE0_IP4_UNUSED>, <J721E_SERDES0_LANE1_IP4_UNUSED>,
<J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
<J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>,
<J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
<J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
<J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};
&serdes_wiz3 {
typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_LOW>;
typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
};
&serdes3 {
serdes3_usb_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_USB3>;
resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
};
};
&serdes4 {
torrent_phy_dp: phy@0 {
reg = <0>;
resets = <&serdes_wiz4 1>;
cdns,phy-type = <PHY_TYPE_DP>;
cdns,num-lanes = <4>;
cdns,max-bit-rate = <5400>;
#phy-cells = <0>;
};
};
&mhdp {
phys = <&torrent_phy_dp>;
phy-names = "dpphy";
pinctrl-names = "default";
pinctrl-0 = <&dp0_pins_default>;
};
&usbss0 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss0_pins_default>;
ti,vbus-divider;
};
&usb0 {
dr_mode = "peripheral";
maximum-speed = "super-speed";
phys = <&serdes3_usb_link>;
phy-names = "cdns3,usb3-phy";
};
&serdes2 {
serdes2_usb_link: phy@1 {
reg = <1>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_USB3>;
resets = <&serdes_wiz2 2>;
};
};
&usbss1 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss1_pins_default>, <&mcu_usbss1_pins_default>;
ti,vbus-divider;
};
&usb1 {
dr_mode = "host";
maximum-speed = "super-speed";
phys = <&serdes2_usb_link>;
phy-names = "cdns3,usb3-phy";
};
&tscadc0 {
status = "okay";
/* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */
adc {
ti,adc-channels = <0 1 2 3 4 5 6>;
};
};
&tscadc1 {
status = "okay";
/* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */
adc {
ti,adc-channels = <0>;
};
};
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default>;
};
&davinci_mdio {
pinctrl-names = "default";
pinctrl-0 = <&mcu_mdio_pins_default>;
phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&phy0>;
};
&dss {
/*
* These clock assignments are chosen to enable the following outputs:
*
* VP0 - DisplayPort SST
* VP1 - DPI0
* VP2 - DSI
* VP3 - DPI1
*/
assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */
<&k3_clks 152 4>, /* VP 2 pixel clock */
<&k3_clks 152 9>, /* VP 3 pixel clock */
<&k3_clks 152 13>; /* VP 4 pixel clock */
assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
<&k3_clks 152 6>, /* PLL19_HSDIV0 */
<&k3_clks 152 11>, /* PLL18_HSDIV0 */
<&k3_clks 152 18>; /* PLL23_HSDIV0 */
};
&dss_ports {
port {
dpi0_out: endpoint {
remote-endpoint = <&dp0_in>;
};
};
};
&dp0_ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dp0_in: endpoint {
remote-endpoint = <&dpi0_out>;
};
};
port@4 {
reg = <4>;
dp0_out: endpoint {
remote-endpoint = <&dp_connector_in>;
};
};
};
&serdes0 {
serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>;
};
};
&serdes1 {
serdes1_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
};
};
&pcie1_rc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pcie1_rst_pins_default>;
phys = <&serdes1_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
max-link-speed = <3>;
reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>;
};
&ufs_wrapper {
status = "disabled";
};
&mailbox0_cluster0 {
status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster1 {
status = "okay";
interrupts = <432>;
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster2 {
status = "okay";
interrupts = <428>;
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster3 {
status = "okay";
interrupts = <424>;
mbox_c66_0: mbox-c66-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_c66_1: mbox-c66-1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster4 {
status = "okay";
interrupts = <420>;
mbox_c71_0: mbox-c71-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
};
&mcu_r5fss0_core0 {
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&c66_0 {
status = "okay";
mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
memory-region = <&c66_0_dma_memory_region>,
<&c66_0_memory_region>;
};
&c66_1 {
status = "okay";
mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
memory-region = <&c66_1_dma_memory_region>,
<&c66_1_memory_region>;
};
&c71_0 {
status = "okay";
mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};

434
arch/arm/dts/k3-j721e-binman.dtsi
View file

@ -42,78 +42,7 @@
};
itb {
filename = "sysfw-j721e_sr1_1-hs-evm.itb";
fit {
description = "SYSFW and Config fragments";
#address-cells = <1>;
images {
sysfw.bin {
description = "sysfw";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sysfw.bin";
};
};
board-cfg.bin {
description = "board-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&board_cfg>;
keyfile = "custMpk.pem";
};
board_cfg: board-cfg {
filename = "board-cfg.bin";
type = "blob-ext";
};
};
pm-cfg.bin {
description = "pm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&pm_cfg>;
keyfile = "custMpk.pem";
};
pm_cfg: pm-cfg {
filename = "pm-cfg.bin";
type = "blob-ext";
};
};
rm-cfg.bin {
description = "rm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&rm_cfg>;
keyfile = "custMpk.pem";
};
rm_cfg: rm-cfg {
filename = "rm-cfg.bin";
type = "blob-ext";
};
};
sec-cfg.bin {
description = "sec-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&sec_cfg>;
keyfile = "custMpk.pem";
};
sec_cfg: sec-cfg {
filename = "sec-cfg.bin";
type = "blob-ext";
};
};
};
};
insert-template = <&itb_template>;
};
};
@ -145,62 +74,7 @@
};
itb_fs {
filename = "sysfw-j721e_sr2-hs-fs-evm.itb";
fit {
description = "SYSFW and Config fragments";
#address-cells = <1>;
images {
sysfw.bin {
description = "sysfw";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sysfw.bin_fs";
};
};
board-cfg.bin {
description = "board-cfg";
type = "firmware";
arch = "arm";
compression = "none";
board-cfg {
filename = "board-cfg.bin";
type = "blob-ext";
};
};
pm-cfg.bin {
description = "pm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
pm-cfg {
filename = "pm-cfg.bin";
type = "blob-ext";
};
};
rm-cfg.bin {
description = "rm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
rm-cfg {
filename = "rm-cfg.bin";
type = "blob-ext";
};
};
sec-cfg.bin {
description = "sec-cfg";
type = "firmware";
arch = "arm";
compression = "none";
sec-cfg {
filename = "sec-cfg.bin";
type = "blob-ext";
};
};
};
};
insert-template = <&itb_unsigned_template>;
};
};
@ -237,55 +111,15 @@
itb_gp {
filename = "sysfw-j721e-gp-evm.itb";
symlink = "sysfw.itb";
insert-template = <&itb_unsigned_template>;
fit {
description = "SYSFW and Config fragments";
#address-cells = <1>;
images {
sysfw.bin {
description = "sysfw";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sysfw.bin_gp";
};
};
board-cfg.bin {
description = "board-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "board-cfg.bin";
};
};
pm-cfg.bin {
description = "pm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "pm-cfg.bin";
};
};
rm-cfg.bin {
description = "rm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "rm-cfg.bin";
};
};
sec-cfg.bin {
description = "sec-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sec-cfg.bin";
};
};
};
};
};
@ -294,11 +128,9 @@
#ifdef CONFIG_TARGET_J721E_A72_EVM
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_J721E_EVM_DTB "spl/dts/k3-j721e-common-proc-board.dtb"
#define SPL_J721E_SK_DTB "spl/dts/k3-j721e-sk.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define J721E_EVM_DTB "u-boot.dtb"
#define J721E_SK_DTB "arch/arm/dts/k3-j721e-sk.dtb"
@ -310,82 +142,136 @@
};
};
ti-spl {
filename = "tispl.bin";
pad-byte = <0xff>;
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
content = <&atf>;
keyfile = "custMpk.pem";
};
atf: atf-bl31 {
auth-in-place = <0xa02>;
firewall-257-0 {
/* cpu_0_cpu_0_msmc Background Firewall */
insert-template = <&firewall_bg_1>;
id = <257>;
region = <0>;
};
firewall-257-1 {
/* cpu_0_cpu_0_msmc Foreground Firewall */
insert-template = <&firewall_armv8_atf_fg>;
id = <257>;
region = <1>;
};
firewall-284-0 {
/* dru_0_msmc Background Firewall */
insert-template = <&firewall_bg_3>;
id = <284>;
region = <0>;
};
firewall-284-1 {
/* dru_0_msmc Foreground Firewall */
insert-template = <&firewall_armv8_atf_fg>;
id = <284>;
region = <1>;
};
/* firewall-4760-0 {
* nb_slv0__mem0 Background Firewall
* Already configured by the secure entity
* };
*/
firewall-4760-1 {
/* nb_slv0__mem0 Foreground Firewall */
insert-template = <&firewall_armv8_atf_fg>;
id = <4760>;
region = <1>;
};
/* firewall-4761-0 {
* nb_slv1__mem0 Background Firewall
* Already configured by the secure entity
* };
*/
firewall-4761-1 {
/* nb_slv1__mem0 Foreground Firewall */
insert-template = <&firewall_armv8_atf_fg>;
id = <4761>;
region = <1>;
};
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
};
tee: tee-os {
auth-in-place = <0xa02>;
/* cpu_0_cpu_0_msmc region 0 and 1 configured
* during ATF Firewalling
*/
firewall-257-2 {
/* cpu_0_cpu_0_msmc Foreground Firewall */
insert-template = <&firewall_armv8_optee_fg>;
id = <257>;
region = <2>;
};
/* dru_0_msmc region 0 and 1 configured
* during ATF Firewalling
*/
firewall-284-2 {
/* dru_0_msmc Foreground Firewall */
insert-template = <&firewall_armv8_optee_fg>;
id = <284>;
region = <2>;
};
firewall-4762-0 {
/* nb_slv2__mem0 Background Firewall */
insert-template = <&firewall_bg_3>;
id = <4762>;
region = <0>;
};
firewall-4762-1 {
/* nb_slv2__mem0 Foreground Firewall */
insert-template = <&firewall_armv8_optee_fg>;
id = <4762>;
region = <1>;
};
firewall-4763-0 {
/* nb_slv3__mem0 Background Firewall */
insert-template = <&firewall_bg_3>;
id = <4763>;
region = <0>;
};
firewall-4763-1 {
/* nb_slv3__mem0 Foreground Firewall */
insert-template = <&firewall_armv8_optee_fg>;
id = <4763>;
region = <1>;
};
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
};
dm: blob-ext {
dm: ti-dm {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
ti-secure {
content = <&u_boot_spl_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_spl_nodtb: blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-j721e-common-proc-board";
type = "flat_dt";
@ -439,29 +325,12 @@
&binman {
u-boot {
filename = "u-boot.img";
pad-byte = <0xff>;
insert-template = <&u_boot_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for j721e board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
ti-secure {
content = <&u_boot_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_nodtb: u-boot-nodtb {
};
hash {
algo = "crc32";
};
description = "U-Boot for J721E Board";
};
fdt-0 {
@ -524,67 +393,16 @@
&binman {
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
insert-template = <&ti_spl_unsigned_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
ti-dm {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-j721e-common-proc-board";
type = "flat_dt";
@ -629,26 +447,12 @@
&binman {
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
insert-template = <&u_boot_unsigned_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for j721e board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
description = "U-Boot for J721E Board";
};
fdt-0 {

2200
arch/arm/dts/k3-j721e-ddr-beagleboneai64-lp4-3200.dtsi Normal file
View file

File diff suppressed because it is too large Load diff

2
arch/arm/dts/k3-j721e-main.dtsi
View file

@ -181,7 +181,7 @@
};
main_navss: bus@30000000 {
compatible = "simple-mfd";
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;

9
arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
View file

@ -440,7 +440,7 @@
};
mcu_navss: bus@28380000 {
compatible = "simple-mfd";
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
@ -671,4 +671,11 @@
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
mcu_esm: esm@40800000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x40800000 0x00 0x1000>;
ti,esm-pins = <95>;
bootph-pre-ram;
};
};

185
arch/arm/dts/k3-j721e-r5-beagleboneai64.dts Normal file
View file

@ -0,0 +1,185 @@
// SPDX-License-Identifier: GPL-2.0
/*
* https://beagleboard.org/ai-64
*
* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation
* Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
*/
#include "k3-j721e-beagleboneai64.dts"
#include "k3-j721e-ddr-beagleboneai64-lp4-3200.dtsi"
#include "k3-j721e-ddr.dtsi"
#include "k3-j721e-beagleboneai64-u-boot.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a72_0;
};
chosen {
tick-timer = &mcu_timer0;
};
a72_0: a72@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 1>;
assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
assigned-clock-rates = <2000000000>, <200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <3>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_mcu 21>,
<&secure_proxy_mcu 23>;
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_mcu 6>,
<&secure_proxy_mcu 8>,
<&secure_proxy_mcu 5>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <4>;
ti,secure-host;
};
&mcu_timer0 {
status = "okay";
bootph-pre-ram;
};
&secure_proxy_mcu {
bootph-pre-ram;
/* We require this for boot handshake */
status = "okay";
};
&cbass_mcu_wakeup {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx";
bootph-pre-ram;
};
};
&mcu_ringacc {
ti,sci = <&dm_tifs>;
};
&mcu_udmap {
ti,sci = <&dm_tifs>;
};
&wkup_uart0_pins_default {
bootph-pre-ram;
};
&wkup_i2c0 {
bootph-pre-ram;
};
&binman {
tiboot3-j721e-gp-evm.bin {
filename = "tiboot3-j721e-gp-evm.bin";
symlink = "tiboot3.bin";
ti-secure-rom {
content = <&u_boot_spl_unsigned>;
core = "public";
load = <CONFIG_SPL_TEXT_BASE>;
sw-rev = <CONFIG_K3_X509_SWRV>;
keyfile = "ti-degenerate-key.pem";
};
u_boot_spl_unsigned: u-boot-spl {
no-expanded;
};
};
sysfw_gp {
filename = "sysfw.bin_gp";
ti-secure-rom {
content = <&ti_fs>;
core = "secure";
load = <0x40000>;
sw-rev = <CONFIG_K3_X509_SWRV>;
keyfile = "ti-degenerate-key.pem";
};
ti_fs: ti-fs.bin {
filename = "ti-sysfw/ti-fs-firmware-j721e-gp.bin";
type = "blob-ext";
optional;
};
};
itb_gp {
filename = "sysfw-j721e-gp-evm.itb";
symlink = "sysfw.itb";
fit {
description = "SYSFW and Config fragments";
#address-cells = <1>;
images {
sysfw.bin {
description = "sysfw";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sysfw.bin_gp";
};
};
board-cfg.bin {
description = "board-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "board-cfg.bin";
};
};
pm-cfg.bin {
description = "pm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "pm-cfg.bin";
};
};
rm-cfg.bin {
description = "rm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "rm-cfg.bin";
};
};
sec-cfg.bin {
description = "sec-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sec-cfg.bin";
};
};
};
};
};
};

266
arch/arm/dts/k3-j721s2-binman.dtsi
View file

@ -141,11 +141,9 @@
#ifdef CONFIG_TARGET_J721S2_A72_EVM
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_J721S2_EVM_DTB "spl/dts/k3-j721s2-common-proc-board.dtb"
#define SPL_AM68_SK_DTB "spl/dts/k3-am68-sk-base-board.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define J721S2_EVM_DTB "u-boot.dtb"
#define AM68_SK_DTB "arch/arm/dts/k3-am68-sk-base-board.dtb"
@ -157,81 +155,143 @@
};
};
ti-spl {
filename = "tispl.bin";
pad-byte = <0xff>;
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
content = <&atf>;
keyfile = "custMpk.pem";
};
atf: atf-bl31 {
auth-in-place = <0xa02>;
firewall-257-0 {
/* cpu_0_cpu_0_msmc Background Firewall */
insert-template = <&firewall_bg_1>;
id = <257>;
region = <0>;
};
firewall-257-1 {
/* cpu_0_cpu_0_msmc Foreground Firewall */
insert-template = <&firewall_armv8_atf_fg>;
id = <257>;
region = <1>;
};
firewall-284-0 {
/* dru_0_msmc Background Firewall */
insert-template = <&firewall_bg_3>;
id = <284>;
region = <0>;
};
firewall-284-1 {
/* dru_0_msmc Foreground Firewall */
insert-template = <&firewall_armv8_atf_fg>;
id = <284>;
region = <1>;
};
/* firewall-5140-0 {
* nb_slv0__mem0 Background Firewall
* Already configured by the secure entity
* };
*/
firewall-5140-1 {
/* nb_slv0__mem0 Foreground Firewall */
insert-template = <&firewall_armv8_atf_fg>;
id = <5140>;
region = <1>;
};
/* firewall-5140-0 {
* nb_slv1__mem0 Background Firewall
* Already configured by the secure entity
* };
*/
firewall-5141-1 {
/* nb_slv1__mem0 Foreground Firewall */
insert-template = <&firewall_armv8_atf_fg>;
id = <5141>;
region = <1>;
};
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
};
tee: tee-os {
auth-in-place = <0xa02>;
firewall-257-2 {
/* cpu_0_cpu_0_msmc Foreground Firewall */
insert-template = <&firewall_armv8_optee_fg>;
id = <257>;
region = <2>;
};
firewall-284-2 {
/* dru_0_msmc Foreground Firewall */
insert-template = <&firewall_armv8_optee_fg>;
id = <284>;
region = <2>;
};
firewall-5142-0 {
/* nb_slv2__mem0 Background Firewall - 0 */
insert-template = <&firewall_bg_3>;
id = <5142>;
region = <0>;
};
firewall-5142-1 {
/* nb_slv2__mem0 Foreground Firewall */
insert-template = <&firewall_armv8_optee_fg>;
id = <5142>;
region = <1>;
};
firewall-5143-0 {
/* nb_slv3__mem0 Background Firewall - 0 */
insert-template = <&firewall_bg_3>;
id = <5143>;
region = <0>;
};
firewall-5143-1 {
/* nb_slv3__mem0 Foreground Firewall */
insert-template = <&firewall_armv8_optee_fg>;
id = <5143>;
region = <1>;
};
firewall-5144-0 {
/* nb_slv4__mem0 Background Firewall - 0 */
insert-template = <&firewall_bg_3>;
id = <5144>;
region = <0>;
};
firewall-5144-1 {
/* nb_slv4__mem0 Foreground Firewall */
insert-template = <&firewall_armv8_optee_fg>;
id = <5144>;
region = <1>;
};
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
};
dm: blob-ext {
dm: ti-dm {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
ti-secure {
content = <&u_boot_spl_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_spl_nodtb: blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-j721s2-common-proc-board";
type = "flat_dt";
@ -285,29 +345,12 @@
&binman {
u-boot {
filename = "u-boot.img";
pad-byte = <0xff>;
insert-template = <&u_boot_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for J721S2 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
ti-secure {
content = <&u_boot_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_nodtb: u-boot-nodtb {
};
hash {
algo = "crc32";
};
description = "U-Boot for J721S2 Board";
};
fdt-0 {
@ -371,67 +414,16 @@
&binman {
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
insert-template = <&ti_spl_unsigned_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
ti-dm {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob {
filename = "spl/u-boot-spl-nodtb.bin";
};
};
fdt-0 {
description = "k3-j721s2-common-proc-board";
type = "flat_dt";
@ -475,26 +467,12 @@
&binman {
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
insert-template = <&u_boot_unsigned_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for J721S2 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
description = "U-Boot for J721S2 Board";
};
fdt-0 {

232
arch/arm/dts/k3-j721s2-main.dtsi
View file

@ -775,7 +775,7 @@
};
main_navss: bus@30000000 {
compatible = "simple-mfd";
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
@ -807,6 +807,7 @@
ti,sci = <&sms>;
ti,sci-dev-id = <265>;
ti,interrupt-ranges = <0 0 256>;
ti,unmapped-event-sources = <&main_bcdma_csi>;
};
secure_proxy_main: mailbox@32c00000 {
@ -1103,6 +1104,22 @@
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
};
main_bcdma_csi: dma-controller@311a0000 {
compatible = "ti,j721s2-dmss-bcdma-csi";
reg = <0x00 0x311a0000 0x00 0x100>,
<0x00 0x35d00000 0x00 0x20000>,
<0x00 0x35c00000 0x00 0x10000>,
<0x00 0x35e00000 0x00 0x80000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
msi-parent = <&main_udmass_inta>;
#dma-cells = <3>;
ti,sci = <&sms>;
ti,sci-dev-id = <225>;
ti,sci-rm-range-rchan = <0x21>;
ti,sci-rm-range-tchan = <0x22>;
status = "disabled";
};
cpts@310d0000 {
compatible = "ti,j721e-cpts";
reg = <0x0 0x310d0000 0x0 0x400>;
@ -1695,4 +1712,217 @@
dss_ports: ports {
};
};
main_r5fss0: r5fss@5c00000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
<0x5d00000 0x00 0x5d00000 0x20000>;
power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
main_r5fss0_core0: r5f@5c00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5c00000 0x00010000>,
<0x5c10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <279>;
ti,sci-proc-ids = <0x06 0xff>;
resets = <&k3_reset 279 1>;
firmware-name = "j721s2-main-r5f0_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
main_r5fss0_core1: r5f@5d00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5d00000 0x00010000>,
<0x5d10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <280>;
ti,sci-proc-ids = <0x07 0xff>;
resets = <&k3_reset 280 1>;
firmware-name = "j721s2-main-r5f0_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
main_r5fss1: r5fss@5e00000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
<0x5f00000 0x00 0x5f00000 0x20000>;
power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
main_r5fss1_core0: r5f@5e00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5e00000 0x00010000>,
<0x5e10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <281>;
ti,sci-proc-ids = <0x08 0xff>;
resets = <&k3_reset 281 1>;
firmware-name = "j721s2-main-r5f1_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
main_r5fss1_core1: r5f@5f00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5f00000 0x00010000>,
<0x5f10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <282>;
ti,sci-proc-ids = <0x09 0xff>;
resets = <&k3_reset 282 1>;
firmware-name = "j721s2-main-r5f1_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
c71_0: dsp@64800000 {
compatible = "ti,j721s2-c71-dsp";
reg = <0x00 0x64800000 0x00 0x00080000>,
<0x00 0x64e00000 0x00 0x0000c000>;
reg-names = "l2sram", "l1dram";
ti,sci = <&sms>;
ti,sci-dev-id = <8>;
ti,sci-proc-ids = <0x30 0xff>;
resets = <&k3_reset 8 1>;
firmware-name = "j721s2-c71_0-fw";
status = "disabled";
};
c71_1: dsp@65800000 {
compatible = "ti,j721s2-c71-dsp";
reg = <0x00 0x65800000 0x00 0x00080000>,
<0x00 0x65e00000 0x00 0x0000c000>;
reg-names = "l2sram", "l1dram";
ti,sci = <&sms>;
ti,sci-dev-id = <11>;
ti,sci-proc-ids = <0x31 0xff>;
resets = <&k3_reset 11 1>;
firmware-name = "j721s2-c71_1-fw";
status = "disabled";
};
main_esm: esm@700000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x700000 0x00 0x1000>;
ti,esm-pins = <688>, <689>;
bootph-pre-ram;
};
watchdog0: watchdog@2200000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2200000 0x00 0x100>;
clocks = <&k3_clks 286 1>;
power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 286 1>;
assigned-clock-parents = <&k3_clks 286 5>;
};
watchdog1: watchdog@2210000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2210000 0x00 0x100>;
clocks = <&k3_clks 287 1>;
power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 287 1>;
assigned-clock-parents = <&k3_clks 287 5>;
};
/*
* The following RTI instances are coupled with MCU R5Fs, c7x and
* GPU so keeping them reserved as these will be used by their
* respective firmware
*/
watchdog2: watchdog@22f0000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x22f0000 0x00 0x100>;
clocks = <&k3_clks 290 1>;
power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 290 1>;
assigned-clock-parents = <&k3_clks 290 5>;
/* reserved for GPU */
status = "reserved";
};
watchdog3: watchdog@2300000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2300000 0x00 0x100>;
clocks = <&k3_clks 288 1>;
power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 288 1>;
assigned-clock-parents = <&k3_clks 288 5>;
/* reserved for C7X_0 */
status = "reserved";
};
watchdog4: watchdog@2310000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2310000 0x00 0x100>;
clocks = <&k3_clks 289 1>;
power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 289 1>;
assigned-clock-parents = <&k3_clks 289 5>;
/* reserved for C7X_1 */
status = "reserved";
};
watchdog5: watchdog@23c0000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x23c0000 0x00 0x100>;
clocks = <&k3_clks 291 1>;
power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 291 1>;
assigned-clock-parents = <&k3_clks 291 5>;
/* reserved for MAIN_R5F0_0 */
status = "reserved";
};
watchdog6: watchdog@23d0000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x23d0000 0x00 0x100>;
clocks = <&k3_clks 292 1>;
power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 292 1>;
assigned-clock-parents = <&k3_clks 292 5>;
/* reserved for MAIN_R5F0_1 */
status = "reserved";
};
watchdog7: watchdog@23e0000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x23e0000 0x00 0x100>;
clocks = <&k3_clks 293 1>;
power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 293 1>;
assigned-clock-parents = <&k3_clks 293 5>;
/* reserved for MAIN_R5F1_0 */
status = "reserved";
};
watchdog8: watchdog@23f0000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x23f0000 0x00 0x100>;
clocks = <&k3_clks 294 1>;
power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 294 1>;
assigned-clock-parents = <&k3_clks 294 5>;
/* reserved for MAIN_R5F1_1 */
status = "reserved";
};
};

82
arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
View file

@ -443,7 +443,7 @@
};
mcu_navss: bus@28380000 {
compatible = "simple-mfd";
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
@ -655,4 +655,84 @@
power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
#thermal-sensor-cells = <1>;
};
mcu_r5fss0: r5fss@41000000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x41000000 0x00 0x41000000 0x20000>,
<0x41400000 0x00 0x41400000 0x20000>;
power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
mcu_r5fss0_core0: r5f@41000000 {
compatible = "ti,j721s2-r5f";
reg = <0x41000000 0x00010000>,
<0x41010000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <284>;
ti,sci-proc-ids = <0x01 0xff>;
resets = <&k3_reset 284 1>;
firmware-name = "j721s2-mcu-r5f0_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
mcu_r5fss0_core1: r5f@41400000 {
compatible = "ti,j721s2-r5f";
reg = <0x41400000 0x00010000>,
<0x41410000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <285>;
ti,sci-proc-ids = <0x02 0xff>;
resets = <&k3_reset 285 1>;
firmware-name = "j721s2-mcu-r5f0_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
mcu_esm: esm@40800000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x40800000 0x00 0x1000>;
ti,esm-pins = <95>;
bootph-pre-ram;
};
wkup_esm: esm@42080000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x42080000 0x00 0x1000>;
ti,esm-pins = <63>;
bootph-pre-ram;
};
/*
* The 2 RTI instances are couple with MCU R5Fs so keeping them
* reserved as these will be used by their respective firmware
*/
mcu_watchdog0: watchdog@40600000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x40600000 0x00 0x100>;
clocks = <&k3_clks 295 1>;
power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 295 1>;
assigned-clock-parents = <&k3_clks 295 5>;
/* reserved for MCU_R5F0_0 */
status = "reserved";
};
mcu_watchdog1: watchdog@40610000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x40610000 0x00 0x100>;
clocks = <&k3_clks 296 1>;
power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 296 1>;
assigned-clock-parents = <&k3_clks 296 5>;
/* reserved for MCU_R5F0_1 */
status = "reserved";
};
};

208
arch/arm/dts/k3-j721s2-som-p0.dtsi
View file

@ -29,6 +29,108 @@
alignment = <0x1000>;
no-map;
};
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa5000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa5100000 0x00 0xf00000>;
no-map;
};
c71_0_dma_memory_region: c71-dma-memory@a6000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6000000 0x00 0x100000>;
no-map;
};
c71_0_memory_region: c71-memory@a6100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6100000 0x00 0xf00000>;
no-map;
};
c71_1_dma_memory_region: c71-dma-memory@a7000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7000000 0x00 0x100000>;
no-map;
};
c71_1_memory_region: c71-memory@a7100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a8000000 {
reg = <0x00 0xa8000000 0x00 0x01c00000>;
alignment = <0x1000>;
no-map;
};
};
mux0: mux-controller {
@ -151,3 +253,109 @@
cdns,read-delay = <4>;
};
};
&mailbox0_cluster0 {
status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster1 {
status = "okay";
interrupts = <432>;
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster2 {
status = "okay";
interrupts = <428>;
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster4 {
status = "okay";
interrupts = <420>;
mbox_c71_0: mbox-c71-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_c71_1: mbox-c71-1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mcu_r5fss0_core0 {
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&c71_0 {
status = "okay";
mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};
&c71_1 {
status = "okay";
mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
memory-region = <&c71_1_dma_memory_region>,
<&c71_1_memory_region>;
};

58
arch/arm/dts/k3-security.h Normal file
View file

@ -0,0 +1,58 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef DTS_ARM64_TI_K3_FIREWALL_H
#define DTS_ARM64_TI_K3_FIREWALL_H
#define FWPRIVID_ALL 0xc3
#define FWPRIVID_ARMV8 1
#define FWPRIVID_SHIFT 16
#define FWCTRL_EN 0xA
#define FWCTRL_LOCK (1 << 4)
#define FWCTRL_BG (1 << 8)
#define FWCTRL_CACHE (1 << 9)
#define FWPERM_SECURE_PRIV_WRITE (1 << 0)
#define FWPERM_SECURE_PRIV_READ (1 << 1)
#define FWPERM_SECURE_PRIV_CACHEABLE (1 << 2)
#define FWPERM_SECURE_PRIV_DEBUG (1 << 3)
#define FWPERM_SECURE_PRIV_RWCD (FWPERM_SECURE_PRIV_READ | \
FWPERM_SECURE_PRIV_WRITE | \
FWPERM_SECURE_PRIV_CACHEABLE | \
FWPERM_SECURE_PRIV_DEBUG)
#define FWPERM_SECURE_USER_WRITE (1 << 4)
#define FWPERM_SECURE_USER_READ (1 << 5)
#define FWPERM_SECURE_USER_CACHEABLE (1 << 6)
#define FWPERM_SECURE_USER_DEBUG (1 << 7)
#define FWPERM_SECURE_USER_RWCD (FWPERM_SECURE_USER_READ | \
FWPERM_SECURE_USER_WRITE | \
FWPERM_SECURE_USER_CACHEABLE | \
FWPERM_SECURE_USER_DEBUG)
#define FWPERM_NON_SECURE_PRIV_WRITE (1 << 8)
#define FWPERM_NON_SECURE_PRIV_READ (1 << 9)
#define FWPERM_NON_SECURE_PRIV_CACHEABLE (1 << 10)
#define FWPERM_NON_SECURE_PRIV_DEBUG (1 << 11)
#define FWPERM_NON_SECURE_PRIV_RWCD (FWPERM_NON_SECURE_PRIV_READ | \
FWPERM_NON_SECURE_PRIV_WRITE | \
FWPERM_NON_SECURE_PRIV_CACHEABLE | \
FWPERM_NON_SECURE_PRIV_DEBUG)
#define FWPERM_NON_SECURE_USER_WRITE (1 << 12)
#define FWPERM_NON_SECURE_USER_READ (1 << 13)
#define FWPERM_NON_SECURE_USER_CACHEABLE (1 << 14)
#define FWPERM_NON_SECURE_USER_DEBUG (1 << 15)
#define FWPERM_NON_SECURE_USER_RWCD (FWPERM_NON_SECURE_USER_READ | \
FWPERM_NON_SECURE_USER_WRITE | \
FWPERM_NON_SECURE_USER_CACHEABLE | \
FWPERM_NON_SECURE_USER_DEBUG)
#endif

2
arch/arm/dts/k3-serdes.h
View file

@ -111,7 +111,7 @@
#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0
#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1
#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2
#define J721S2_SERDES0_LANE2_USB_SWAP 0x2
#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3
#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0

4
arch/arm/dts/meson-gx-libretech-pc.dtsi
View file

@ -17,7 +17,7 @@
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
update-button {
button-update {
label = "update";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <1300000>;
@ -416,7 +416,7 @@
pinctrl-names = "default";
status = "okay";
gd25lq128: spi-flash@0 {
gd25lq128: flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;

21
arch/arm/dts/meson-gx.dtsi
View file

@ -49,6 +49,12 @@
no-map;
};
/* 32 MiB reserved for ARM Trusted Firmware (BL32) */
secmon_reserved_bl32: secmon@5300000 {
reg = <0x0 0x05300000 0x0 0x2000000>;
no-map;
};
linux,cma {
compatible = "shared-dma-pool";
reusable;
@ -126,6 +132,7 @@
l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};
@ -226,7 +233,7 @@
reg = <0x14 0x10>;
};
eth_mac: eth_mac@34 {
eth_mac: eth-mac@34 {
reg = <0x34 0x10>;
};
@ -243,7 +250,7 @@
scpi_clocks: clocks {
compatible = "arm,scpi-clocks";
scpi_dvfs: scpi_clocks@0 {
scpi_dvfs: clocks-0 {
compatible = "arm,scpi-dvfs-clocks";
#clock-cells = <1>;
clock-indices = <0>;
@ -444,7 +451,7 @@
sysctrl_AO: sys-ctrl@0 {
compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
reg = <0x0 0x0 0x0 0x100>;
reg = <0x0 0x0 0x0 0x100>;
clkc_AO: clock-controller {
compatible = "amlogic,meson-gx-aoclkc";
@ -525,7 +532,7 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
hwrng: rng {
hwrng: rng@0 {
compatible = "amlogic,meson-rng";
reg = <0x0 0x0 0x0 0x4>;
};
@ -596,21 +603,21 @@
sd_emmc_a: mmc@70000 {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x70000 0x0 0x800>;
interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sd_emmc_b: mmc@72000 {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x72000 0x0 0x800>;
interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sd_emmc_c: mmc@74000 {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x74000 0x0 0x800>;
interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};

13
arch/arm/dts/meson-gxbb-nanopi-k2.dts
View file

@ -385,9 +385,20 @@
/* Bluetooth on AP6212 */
&uart_A {
status = "disabled";
status = "okay";
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
pinctrl-names = "default";
uart-has-rtscts;
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&wifi_32k>;
clock-names = "lpo";
vbat-supply = <&vddio_ao3v3>;
vddio-supply = <&vddio_ao18>;
host-wakeup-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>;
};
};
/* 40-pin CON1 */

26
arch/arm/dts/meson-gxbb-odroidc2.dts
View file

@ -250,21 +250,6 @@
};
};
&gpio_ao {
/*
* WARNING: The USB Hub on the Odroid-C2 needs a reset signal
* to be turned high in order to be detected by the USB Controller
* This signal should be handled by a USB specific power sequence
* in order to reset the Hub when USB bus is powered down.
*/
hog-0 {
gpio-hog;
gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb-hub-reset";
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
@ -414,5 +399,16 @@
};
&usb1 {
dr_mode = "host";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
hub@1 {
/* Genesys Logic GL852G USB 2.0 hub */
compatible = "usb5e3,610";
reg = <1>;
vdd-supply = <&p5v0>;
reset-gpio = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
};
};

18
arch/arm/dts/meson-gxbb.dtsi
View file

@ -300,8 +300,8 @@
};
&gpio_intc {
compatible = "amlogic,meson-gpio-intc",
"amlogic,meson-gxbb-gpio-intc";
compatible = "amlogic,meson-gxbb-gpio-intc",
"amlogic,meson-gpio-intc";
status = "okay";
};
@ -427,6 +427,20 @@
};
};
spi_idle_high_pins: spi-idle-high-pins {
mux {
groups = "spi_sclk";
bias-pull-up;
};
};
spi_idle_low_pins: spi-idle-low-pins {
mux {
groups = "spi_sclk";
bias-pull-down;
};
};
spi_ss0_pins: spi-ss0 {
mux {
groups = "spi_ss0";

2
arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
View file

@ -298,7 +298,7 @@
pinctrl-0 = <&nor_pins>;
pinctrl-names = "default";
w25q32: spi-flash@0 {
w25q32: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";

12
arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts
View file

@ -86,11 +86,11 @@
};
&efuse {
bt_mac: bt_mac@6 {
bt_mac: bt-mac@6 {
reg = <0x6 0x6>;
};
wifi_mac: wifi_mac@C {
wifi_mac: wifi-mac@c {
reg = <0xc 0x6>;
};
};
@ -213,6 +213,12 @@
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
pinctrl-names = "default";
uart-has-rtscts;
bluetooth {
compatible = "realtek,rtl8822cs-bt";
enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
host-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
};
};
&uart_C {
@ -233,7 +239,7 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c_b_pins>;
pcf8563: pcf8563@51 {
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
status = "okay";

16
arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
View file

@ -140,7 +140,6 @@
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xin32k";
};
};
@ -218,20 +217,7 @@
};
&sd_emmc_a {
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
&uart_A {
bluetooth {
compatible = "brcm,bcm43438-bt";
shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
max-speed = <2000000>;
clocks = <&wifi32k>;
clock-names = "lpo";
};
max-frequency = <100000000>;
};
/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */

3
arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts
View file

@ -284,7 +284,7 @@
pinctrl-0 = <&nor_pins>;
pinctrl-names = "default";
nor_4u1: spi-flash@0 {
nor_4u1: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@ -305,7 +305,6 @@
};
&usb2_phy0 {
pinctrl-names = "default";
phy-supply = <&vcc5v>;
};

68
arch/arm/dts/meson-gxl-s905x-p212.dts
View file

@ -7,11 +7,19 @@
/dts-v1/;
#include "meson-gxl-s905x-p212.dtsi"
#include <dt-bindings/sound/meson-aiu.h>
/ {
compatible = "amlogic,p212", "amlogic,s905x", "amlogic,meson-gxl";
model = "Amlogic Meson GXL (S905X) P212 Development Board";
dio2133: analog-amplifier {
compatible = "simple-audio-amplifier";
sound-name-prefix = "AU2";
VCC-supply = <&hdmi_5v>;
enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
};
cvbs-connector {
compatible = "composite-video-connector";
@ -32,6 +40,66 @@
};
};
};
sound {
compatible = "amlogic,gx-sound-card";
model = "S905X-P212";
audio-aux-devs = <&dio2133>;
audio-widgets = "Line", "Lineout";
audio-routing = "AU2 INL", "ACODEC LOLN",
"AU2 INR", "ACODEC LORN",
"Lineout", "AU2 OUTL",
"Lineout", "AU2 OUTR";
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
dai-link-0 {
sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
};
dai-link-1 {
sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
dai-format = "i2s";
mclk-fs = <256>;
codec-0 {
sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
};
codec-1 {
sound-dai = <&aiu AIU_ACODEC CTRL_I2S>;
};
};
dai-link-2 {
sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
codec-0 {
sound-dai = <&hdmi_tx>;
};
};
dai-link-3 {
sound-dai = <&aiu AIU_ACODEC CTRL_OUT>;
codec-0 {
sound-dai = <&acodec>;
};
};
};
};
&acodec {
AVDD-supply = <&vddio_ao18>;
status = "okay";
};
&aiu {
status = "okay";
};
&cec_AO {

21
arch/arm/dts/meson-gxl-s905x-p212.dtsi
View file

@ -97,6 +97,14 @@
pinctrl-names = "default";
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
&saradc {
status = "okay";
vref-supply = <&vddio_ao18>;
@ -125,6 +133,11 @@
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SD card */
@ -165,14 +178,6 @@
vqmmc-supply = <&vddio_boot>;
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
/* This is connected to the Bluetooth module: */
&uart_A {
status = "okay";

43
arch/arm/dts/meson-gxl.dtsi
View file

@ -312,8 +312,8 @@
};
&gpio_intc {
compatible = "amlogic,meson-gpio-intc",
"amlogic,meson-gxl-gpio-intc";
compatible = "amlogic,meson-gxl-gpio-intc",
"amlogic,meson-gpio-intc";
status = "okay";
};
@ -429,6 +429,20 @@
};
};
spi_idle_high_pins: spi-idle-high-pins {
mux {
groups = "spi_sclk";
bias-pull-up;
};
};
spi_idle_low_pins: spi-idle-low-pins {
mux {
groups = "spi_sclk";
bias-pull-down;
};
};
spi_ss0_pins: spi-ss0 {
mux {
groups = "spi_ss0";
@ -759,16 +773,23 @@
};
};
eth-phy-mux {
compatible = "mdio-mux-mmioreg", "mdio-mux";
eth_phy_mux: mdio@558 {
reg = <0x0 0x558 0x0 0xc>;
compatible = "amlogic,gxl-mdio-mux";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x55c 0x0 0x4>;
mux-mask = <0xffffffff>;
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "ref";
mdio-parent-bus = <&mdio0>;
internal_mdio: mdio@e40908ff {
reg = <0xe40908ff>;
external_mdio: mdio@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
};
internal_mdio: mdio@1 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
@ -779,12 +800,6 @@
max-speed = <100>;
};
};
external_mdio: mdio@2009087f {
reg = <0x2009087f>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};

15
arch/arm/dts/meson-gxm-khadas-vim2.dts
View file

@ -52,10 +52,11 @@
gpios = <&gpio GPIODV_14 GPIO_ACTIVE_HIGH
&gpio GPIODV_15 GPIO_ACTIVE_HIGH>;
/* Dummy RPM values since fan is optional */
gpio-fan,speed-map = <0 0
1 1
2 2
3 3>;
gpio-fan,speed-map =
<0 0>,
<1 1>,
<2 2>,
<3 3>;
#cooling-cells = <2>;
};
@ -270,7 +271,6 @@
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xin32k";
};
};
@ -307,7 +307,8 @@
#size-cells = <0>;
bus-width = <4>;
max-frequency = <60000000>;
cap-sd-highspeed;
max-frequency = <100000000>;
non-removable;
disable-wp;
@ -373,7 +374,7 @@
pinctrl-0 = <&nor_pins>;
pinctrl-names = "default";
w25q32: spi-flash@0 {
w25q32: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q16", "jedec,spi-nor";

2
arch/arm/dts/meson-gxm-wetek-core2.dts
View file

@ -45,8 +45,6 @@
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
button-power {

282
arch/arm/dts/mt6357.dtsi Normal file
View file

@ -0,0 +1,282 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (c) 2020 MediaTek Inc.
* Copyright (c) 2023 BayLibre Inc.
*/
#include <dt-bindings/input/input.h>
&pwrap {
mt6357_pmic: pmic {
compatible = "mediatek,mt6357";
regulators {
mt6357_vproc_reg: buck-vproc {
regulator-name = "vproc";
regulator-min-microvolt = <518750>;
regulator-max-microvolt = <1312500>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <220>;
regulator-always-on;
};
mt6357_vcore_reg: buck-vcore {
regulator-name = "vcore";
regulator-min-microvolt = <518750>;
regulator-max-microvolt = <1312500>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <220>;
regulator-always-on;
};
mt6357_vmodem_reg: buck-vmodem {
regulator-name = "vmodem";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1193750>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <220>;
};
mt6357_vs1_reg: buck-vs1 {
regulator-name = "vs1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <2200000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <220>;
regulator-always-on;
};
mt6357_vpa_reg: buck-vpa {
regulator-name = "vpa";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3650000>;
regulator-ramp-delay = <50000>;
regulator-enable-ramp-delay = <220>;
};
mt6357_vfe28_reg: ldo-vfe28 {
compatible = "regulator-fixed";
regulator-name = "vfe28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vxo22_reg: ldo-vxo22 {
regulator-name = "vxo22";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <2400000>;
regulator-enable-ramp-delay = <110>;
};
mt6357_vrf18_reg: ldo-vrf18 {
compatible = "regulator-fixed";
regulator-name = "vrf18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <110>;
};
mt6357_vrf12_reg: ldo-vrf12 {
compatible = "regulator-fixed";
regulator-name = "vrf12";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-enable-ramp-delay = <110>;
};
mt6357_vefuse_reg: ldo-vefuse {
regulator-name = "vefuse";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vcn33_bt_reg: ldo-vcn33-bt {
regulator-name = "vcn33-bt";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3500000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vcn33_wifi_reg: ldo-vcn33-wifi {
regulator-name = "vcn33-wifi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3500000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vcn28_reg: ldo-vcn28 {
compatible = "regulator-fixed";
regulator-name = "vcn28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vcn18_reg: ldo-vcn18 {
compatible = "regulator-fixed";
regulator-name = "vcn18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vcama_reg: ldo-vcama {
regulator-name = "vcama";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vcamd_reg: ldo-vcamd {
regulator-name = "vcamd";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vcamio_reg: ldo-vcamio18 {
compatible = "regulator-fixed";
regulator-name = "vcamio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vldo28_reg: ldo-vldo28 {
regulator-name = "vldo28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vsram_others_reg: ldo-vsram-others {
regulator-name = "vsram-others";
regulator-min-microvolt = <518750>;
regulator-max-microvolt = <1312500>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <110>;
regulator-always-on;
};
mt6357_vsram_proc_reg: ldo-vsram-proc {
regulator-name = "vsram-proc";
regulator-min-microvolt = <518750>;
regulator-max-microvolt = <1312500>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <110>;
regulator-always-on;
};
mt6357_vaux18_reg: ldo-vaux18 {
compatible = "regulator-fixed";
regulator-name = "vaux18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vaud28_reg: ldo-vaud28 {
compatible = "regulator-fixed";
regulator-name = "vaud28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vio28_reg: ldo-vio28 {
compatible = "regulator-fixed";
regulator-name = "vio28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vio18_reg: ldo-vio18 {
compatible = "regulator-fixed";
regulator-name = "vio18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <264>;
regulator-always-on;
};
mt6357_vdram_reg: ldo-vdram {
regulator-name = "vdram";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1200000>;
regulator-enable-ramp-delay = <3300>;
};
mt6357_vmc_reg: ldo-vmc {
regulator-name = "vmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <44>;
};
mt6357_vmch_reg: ldo-vmch {
regulator-name = "vmch";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <44>;
};
mt6357_vemc_reg: ldo-vemc {
regulator-name = "vemc";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <44>;
regulator-always-on;
};
mt6357_vsim1_reg: ldo-vsim1 {
regulator-name = "vsim1";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <3100000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vsim2_reg: ldo-vsim2 {
regulator-name = "vsim2";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <3100000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vibr_reg: ldo-vibr {
regulator-name = "vibr";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <44>;
};
mt6357_vusb33_reg: ldo-vusb33 {
regulator-name = "vusb33";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3100000>;
regulator-enable-ramp-delay = <264>;
};
};
rtc {
compatible = "mediatek,mt6357-rtc";
};
keys {
compatible = "mediatek,mt6357-keys";
key-power {
linux,keycodes = <KEY_POWER>;
wakeup-source;
};
key-home {
linux,keycodes = <KEY_HOME>;
wakeup-source;
};
};
};
};

418
arch/arm/dts/mt8365-evk.dts Normal file
View file

@ -0,0 +1,418 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021-2022 BayLibre, SAS.
* Authors:
* Fabien Parent <fparent@baylibre.com>
* Bernhard Rosenkränzer <bero@baylibre.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
#include "mt8365.dtsi"
#include "mt6357.dtsi"
/ {
model = "MediaTek MT8365 Open Platform EVK";
compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:921600n8";
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys>;
key-volume-up {
gpios = <&pio 24 GPIO_ACTIVE_LOW>;
label = "volume_up";
linux,code = <KEY_VOLUMEUP>;
wakeup-source;
debounce-interval = <15>;
};
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0xc0000000>;
};
usb_otg_vbus: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
bl31_secmon_reserved: secmon@43000000 {
no-map;
reg = <0 0x43000000 0 0x30000>;
};
/* 12 MiB reserved for OP-TEE (BL32)
* +-----------------------+ 0x43e0_0000
* | SHMEM 2MiB |
* +-----------------------+ 0x43c0_0000
* | | TA_RAM 8MiB |
* + TZDRAM +--------------+ 0x4340_0000
* | | TEE_RAM 2MiB |
* +-----------------------+ 0x4320_0000
*/
optee_reserved: optee@43200000 {
no-map;
reg = <0 0x43200000 0 0x00c00000>;
};
};
};
&cpu0 {
proc-supply = <&mt6357_vproc_reg>;
sram-supply = <&mt6357_vsram_proc_reg>;
};
&cpu1 {
proc-supply = <&mt6357_vproc_reg>;
sram-supply = <&mt6357_vsram_proc_reg>;
};
&cpu2 {
proc-supply = <&mt6357_vproc_reg>;
sram-supply = <&mt6357_vsram_proc_reg>;
};
&cpu3 {
proc-supply = <&mt6357_vproc_reg>;
sram-supply = <&mt6357_vsram_proc_reg>;
};
&ethernet {
pinctrl-0 = <&ethernet_pins>;
pinctrl-names = "default";
phy-handle = <&eth_phy>;
phy-mode = "rmii";
/*
* Ethernet and HDMI (DSI0) are sharing pins.
* Only one can be enabled at a time and require the physical switch
* SW2101 to be set on LAN position
* mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet
*/
status = "disabled";
mdio {
#address-cells = <1>;
#size-cells = <0>;
eth_phy: ethernet-phy@0 {
reg = <0>;
};
};
};
&i2c0 {
clock-frequency = <100000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
};
&mmc0 {
assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
bus-width = <8>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
hs400-ds-delay = <0x12012>;
max-frequency = <200000000>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
no-sd;
no-sdio;
non-removable;
pinctrl-0 = <&mmc0_default_pins>;
pinctrl-1 = <&mmc0_uhs_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&mt6357_vemc_reg>;
vqmmc-supply = <&mt6357_vio18_reg>;
status = "okay";
};
&mmc1 {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
max-frequency = <200000000>;
pinctrl-0 = <&mmc1_default_pins>;
pinctrl-1 = <&mmc1_uhs_pins>;
pinctrl-names = "default", "state_uhs";
sd-uhs-sdr104;
sd-uhs-sdr50;
vmmc-supply = <&mt6357_vmch_reg>;
vqmmc-supply = <&mt6357_vmc_reg>;
status = "okay";
};
&mt6357_pmic {
interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
};
&pio {
ethernet_pins: ethernet-pins {
phy_reset_pins {
pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
};
rmii_pins {
pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>,
<MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1>,
<MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2>,
<MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3>,
<MT8365_PIN_4_GPIO4__FUNC_EXT_TXC>,
<MT8365_PIN_5_GPIO5__FUNC_EXT_RXER>,
<MT8365_PIN_6_GPIO6__FUNC_EXT_RXC>,
<MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV>,
<MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0>,
<MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1>,
<MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2>,
<MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3>,
<MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN>,
<MT8365_PIN_13_GPIO13__FUNC_EXT_COL>,
<MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO>,
<MT8365_PIN_15_GPIO15__FUNC_EXT_MDC>;
};
};
gpio_keys: gpio-keys-pins {
pins {
pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
bias-pull-up;
input-enable;
};
};
i2c0_pins: i2c0-pins {
pins {
pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>,
<MT8365_PIN_58_SCL0__FUNC_SCL0_0>;
bias-pull-up;
};
};
mmc0_default_pins: mmc0-default-pins {
clk-pins {
pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
bias-pull-down;
};
cmd-dat-pins {
pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
<MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
<MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
<MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
<MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
<MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
<MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
<MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
<MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
input-enable;
bias-pull-up;
};
rst-pins {
pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
bias-pull-up;
};
};
mmc0_uhs_pins: mmc0-uhs-pins {
clk-pins {
pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_10mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
cmd-dat-pins {
pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
<MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
<MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
<MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
<MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
<MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
<MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
<MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
<MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_10mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
ds-pins {
pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
drive-strength = <MTK_DRIVE_10mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
rst-pins {
pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_10mA>;
bias-pull-up;
};
};
mmc1_default_pins: mmc1-default-pins {
cd-pins {
pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
bias-pull-up;
};
clk-pins {
pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
cmd-dat-pins {
pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
<MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
<MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
<MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
<MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
input-enable;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
mmc1_uhs_pins: mmc1-uhs-pins {
clk-pins {
pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
cmd-dat-pins {
pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
<MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
<MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
<MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
<MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
uart0_pins: uart0-pins {
pins {
pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
<MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
};
};
uart1_pins: uart1-pins {
pins {
pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
<MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
};
};
uart2_pins: uart2-pins {
pins {
pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
<MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
};
};
usb_pins: usb-pins {
id-pins {
pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
input-enable;
bias-pull-up;
};
usb0-vbus-pins {
pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
output-high;
};
usb1-vbus-pins {
pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
output-high;
};
};
pwm_pins: pwm-pins {
pins {
pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
<MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
};
};
};
&pwm {
pinctrl-0 = <&pwm_pins>;
pinctrl-names = "default";
status = "okay";
};
&ssusb {
dr_mode = "otg";
maximum-speed = "high-speed";
pinctrl-0 = <&usb_pins>;
pinctrl-names = "default";
usb-role-switch;
vusb33-supply = <&mt6357_vusb33_reg>;
status = "okay";
connector {
compatible = "gpio-usb-b-connector", "usb-b-connector";
id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
type = "micro";
vbus-supply = <&usb_otg_vbus>;
};
};
&usb_host {
vusb33-supply = <&mt6357_vusb33_reg>;
status = "okay";
};
&uart0 {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
status = "okay";
};
&uart1 {
pinctrl-0 = <&uart1_pins>;
pinctrl-names = "default";
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
status = "okay";
};

840
arch/arm/dts/mt8365.dtsi Normal file
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@ -0,0 +1,840 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* (C) 2018 MediaTek Inc.
* Copyright (C) 2022 BayLibre SAS
* Fabien Parent <fparent@baylibre.com>
* Bernhard Rosenkränzer <bero@baylibre.com>
*/
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mediatek,mt8365-power.h>
/ {
compatible = "mediatek,mt8365";
interrupt-parent = <&sysirq>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp-850000000 {
opp-hz = /bits/ 64 <850000000>;
opp-microvolt = <650000>;
};
opp-918000000 {
opp-hz = /bits/ 64 <918000000>;
opp-microvolt = <668750>;
};
opp-987000000 {
opp-hz = /bits/ 64 <987000000>;
opp-microvolt = <687500>;
};
opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
opp-microvolt = <706250>;
};
opp-1125000000 {
opp-hz = /bits/ 64 <1125000000>;
opp-microvolt = <725000>;
};
opp-1216000000 {
opp-hz = /bits/ 64 <1216000000>;
opp-microvolt = <750000>;
};
opp-1308000000 {
opp-hz = /bits/ 64 <1308000000>;
opp-microvolt = <775000>;
};
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-microvolt = <800000>;
};
opp-1466000000 {
opp-hz = /bits/ 64 <1466000000>;
opp-microvolt = <825000>;
};
opp-1533000000 {
opp-hz = /bits/ 64 <1533000000>;
opp-microvolt = <850000>;
};
opp-1633000000 {
opp-hz = /bits/ 64 <1633000000>;
opp-microvolt = <887500>;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <912500>;
};
opp-1767000000 {
opp-hz = /bits/ 64 <1767000000>;
opp-microvolt = <937500>;
};
opp-1834000000 {
opp-hz = /bits/ 64 <1834000000>;
opp-microvolt = <962500>;
};
opp-1917000000 {
opp-hz = /bits/ 64 <1917000000>;
opp-microvolt = <993750>;
};
opp-2001000000 {
opp-hz = /bits/ 64 <2001000000>;
opp-microvolt = <1025000>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
#cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
#cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate", "armpll";
operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
#cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate", "armpll";
operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
#cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate", "armpll";
operating-points-v2 = <&cluster0_opp>;
};
idle-states {
entry-method = "psci";
CPU_MCDI: cpu-mcdi {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x00010001>;
entry-latency-us = <300>;
exit-latency-us = <200>;
min-residency-us = <1000>;
};
CLUSTER_MCDI: cluster-mcdi {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x01010001>;
entry-latency-us = <350>;
exit-latency-us = <250>;
min-residency-us = <1200>;
};
CLUSTER_DPIDLE: cluster-dpidle {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x01010004>;
entry-latency-us = <300>;
exit-latency-us = <800>;
min-residency-us = <3300>;
};
};
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
};
};
clk26m: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x10000>, /* GICD */
<0 0x0c080000 0 0x80000>, /* GICR */
<0 0x0c400000 0 0x2000>, /* GICC */
<0 0x0c410000 0 0x1000>, /* GICH */
<0 0x0c420000 0 0x2000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
topckgen: syscon@10000000 {
compatible = "mediatek,mt8365-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infracfg: syscon@10001000 {
compatible = "mediatek,mt8365-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
};
pericfg: syscon@10003000 {
compatible = "mediatek,mt8365-pericfg", "syscon";
reg = <0 0x10003000 0 0x1000>;
#clock-cells = <1>;
};
syscfg_pctl: syscfg-pctl@10005000 {
compatible = "mediatek,mt8365-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
scpsys: syscon@10006000 {
compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
#power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
compatible = "mediatek,mt8365-power-controller";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
/* power domains of the SoC */
power-domain@MT8365_POWER_DOMAIN_MM {
reg = <MT8365_POWER_DOMAIN_MM>;
clocks = <&topckgen CLK_TOP_MM_SEL>,
<&mmsys CLK_MM_MM_SMI_COMMON>,
<&mmsys CLK_MM_MM_SMI_COMM0>,
<&mmsys CLK_MM_MM_SMI_COMM1>,
<&mmsys CLK_MM_MM_SMI_LARB0>;
clock-names = "mm", "mm-0", "mm-1",
"mm-2", "mm-3";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
mediatek,infracfg-nao = <&infracfg_nao>;
#address-cells = <1>;
#size-cells = <0>;
power-domain@MT8365_POWER_DOMAIN_CAM {
reg = <MT8365_POWER_DOMAIN_CAM>;
clocks = <&camsys CLK_CAM_LARB2>,
<&camsys CLK_CAM_SENIF>,
<&camsys CLK_CAMSV0>,
<&camsys CLK_CAMSV1>,
<&camsys CLK_CAM_FDVT>,
<&camsys CLK_CAM_WPE>;
clock-names = "cam-0", "cam-1",
"cam-2", "cam-3",
"cam-4", "cam-5";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
mediatek,smi = <&smi_common>;
};
power-domain@MT8365_POWER_DOMAIN_VDEC {
reg = <MT8365_POWER_DOMAIN_VDEC>;
#power-domain-cells = <0>;
mediatek,smi = <&smi_common>;
};
power-domain@MT8365_POWER_DOMAIN_VENC {
reg = <MT8365_POWER_DOMAIN_VENC>;
#power-domain-cells = <0>;
mediatek,smi = <&smi_common>;
};
power-domain@MT8365_POWER_DOMAIN_APU {
reg = <MT8365_POWER_DOMAIN_APU>;
clocks = <&infracfg CLK_IFR_APU_AXI>,
<&apu CLK_APU_IPU_CK>,
<&apu CLK_APU_AXI>,
<&apu CLK_APU_JTAG>,
<&apu CLK_APU_IF_CK>,
<&apu CLK_APU_EDMA>,
<&apu CLK_APU_AHB>;
clock-names = "apu", "apu-0",
"apu-1", "apu-2",
"apu-3", "apu-4",
"apu-5";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
mediatek,smi = <&smi_common>;
};
};
power-domain@MT8365_POWER_DOMAIN_CONN {
reg = <MT8365_POWER_DOMAIN_CONN>;
clocks = <&topckgen CLK_TOP_CONN_32K>,
<&topckgen CLK_TOP_CONN_26M>;
clock-names = "conn", "conn1";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8365_POWER_DOMAIN_MFG {
reg = <MT8365_POWER_DOMAIN_MFG>;
clocks = <&topckgen CLK_TOP_MFG_SEL>;
clock-names = "mfg";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8365_POWER_DOMAIN_AUDIO {
reg = <MT8365_POWER_DOMAIN_AUDIO>;
clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
<&infracfg CLK_IFR_AUDIO>,
<&infracfg CLK_IFR_AUD_26M_BK>;
clock-names = "audio", "audio1", "audio2";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8365_POWER_DOMAIN_DSP {
reg = <MT8365_POWER_DOMAIN_DSP>;
clocks = <&topckgen CLK_TOP_DSP_SEL>,
<&topckgen CLK_TOP_DSP_26M>;
clock-names = "dsp", "dsp1";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
};
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt";
reg = <0 0x10007000 0 0x100>;
#reset-cells = <1>;
};
pio: pinctrl@1000b000 {
compatible = "mediatek,mt8365-pinctrl";
reg = <0 0x1000b000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
};
apmixedsys: syscon@1000c000 {
compatible = "mediatek,mt8365-apmixedsys", "syscon";
reg = <0 0x1000c000 0 0x1000>;
#clock-cells = <1>;
};
pwrap: pwrap@1000d000 {
compatible = "mediatek,mt8365-pwrap";
reg = <0 0x1000d000 0 0x1000>;
reg-names = "pwrap";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_IFR_PWRAP_SPI>,
<&infracfg CLK_IFR_PMIC_AP>,
<&infracfg CLK_IFR_PWRAP_SYS>,
<&infracfg CLK_IFR_PWRAP_TMR>;
clock-names = "spi", "wrap", "sys", "tmr";
};
keypad: keypad@10010000 {
compatible = "mediatek,mt6779-keypad";
reg = <0 0x10010000 0 0x1000>;
wakeup-source;
interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>;
clocks = <&clk26m>;
clock-names = "kpd";
status = "disabled";
};
mcucfg: syscon@10200000 {
compatible = "mediatek,mt8365-mcucfg", "syscon";
reg = <0 0x10200000 0 0x2000>;
#clock-cells = <1>;
};
sysirq: interrupt-controller@10200a80 {
compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10200a80 0 0x20>;
};
iommu: iommu@10205000 {
compatible = "mediatek,mt8365-m4u";
reg = <0 0x10205000 0 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>;
mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>;
#iommu-cells = <1>;
};
infracfg_nao: infracfg@1020e000 {
compatible = "mediatek,mt8365-infracfg", "syscon";
reg = <0 0x1020e000 0 0x1000>;
#clock-cells = <1>;
};
rng: rng@1020f000 {
compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng";
reg = <0 0x1020f000 0 0x100>;
clocks = <&infracfg CLK_IFR_TRNG>;
clock-names = "rng";
};
apdma: dma-controller@11000280 {
compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma";
reg = <0 0x11000280 0 0x80>,
<0 0x11000300 0 0x80>,
<0 0x11000380 0 0x80>,
<0 0x11000400 0 0x80>,
<0 0x11000580 0 0x80>,
<0 0x11000600 0 0x80>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
dma-requests = <6>;
clocks = <&infracfg CLK_IFR_AP_DMA>;
clock-names = "apdma";
#dma-cells = <1>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>;
clock-names = "baud", "bus";
dmas = <&apdma 0>, <&apdma 1>;
dma-names = "tx", "rx";
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>;
clock-names = "baud", "bus";
dmas = <&apdma 2>, <&apdma 3>;
dma-names = "tx", "rx";
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>;
clock-names = "baud", "bus";
dmas = <&apdma 4>, <&apdma 5>;
dma-names = "tx", "rx";
status = "disabled";
};
pwm: pwm@11006000 {
compatible = "mediatek,mt8365-pwm";
reg = <0 0x11006000 0 0x1000>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_IFR_PWM_HCLK>,
<&infracfg CLK_IFR_PWM>,
<&infracfg CLK_IFR_PWM1>,
<&infracfg CLK_IFR_PWM2>,
<&infracfg CLK_IFR_PWM3>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
};
i2c0: i2c@11007000 {
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
clock-div = <1>;
clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@11008000 {
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>;
clock-div = <1>;
clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@11009000 {
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>;
clock-div = <1>;
clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi: spi@1100a000 {
compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi";
reg = <0 0x1100a000 0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_IFR_SPI0>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
i2c3: i2c@1100f000 {
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
clock-div = <1>;
clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ssusb: usb@11201000 {
compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>;
phys = <&u2port0 PHY_TYPE_USB2>,
<&u2port1 PHY_TYPE_USB2>;
clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
<&infracfg CLK_IFR_SSUSB_REF>,
<&infracfg CLK_IFR_SSUSB_SYS>,
<&infracfg CLK_IFR_ICUSB>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usb_host: usb@11200000 {
compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci";
reg = <0 0x11200000 0 0x1000>;
reg-names = "mac";
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
<&infracfg CLK_IFR_SSUSB_REF>,
<&infracfg CLK_IFR_SSUSB_SYS>,
<&infracfg CLK_IFR_ICUSB>,
<&infracfg CLK_IFR_SSUSB_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck",
"dma_ck", "xhci_ck";
status = "disabled";
};
};
mmc0: mmc@11230000 {
compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11230000 0 0x1000>,
<0 0x11cd0000 0 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
<&infracfg CLK_IFR_MSDC0_HCLK>,
<&infracfg CLK_IFR_MSDC0_SRC>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
mmc1: mmc@11240000 {
compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11240000 0 0x1000>,
<0 0x11c90000 0 0x1000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
<&infracfg CLK_IFR_MSDC1_HCLK>,
<&infracfg CLK_IFR_MSDC1_SRC>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
mmc2: mmc@11250000 {
compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11250000 0 0x1000>,
<0 0x11c60000 0 0x1000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>,
<&infracfg CLK_IFR_MSDC2_HCLK>,
<&infracfg CLK_IFR_MSDC2_SRC>,
<&infracfg CLK_IFR_MSDC2_BK>,
<&infracfg CLK_IFR_AP_MSDC0>;
clock-names = "source", "hclk", "source_cg",
"bus_clk", "sys_cg";
status = "disabled";
};
ethernet: ethernet@112a0000 {
compatible = "mediatek,mt8365-eth";
reg = <0 0x112a0000 0 0x1000>;
mediatek,pericfg = <&infracfg>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_ETH_SEL>,
<&infracfg CLK_IFR_NIC_AXI>,
<&infracfg CLK_IFR_NIC_SLV_AXI>;
clock-names = "core", "reg", "trans";
status = "disabled";
};
u3phy: t-phy@11cc0000 {
compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x11cc0000 0x9000>;
u2port0: usb-phy@0 {
reg = <0x0 0x400>;
clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
<&topckgen CLK_TOP_USB20_48M_EN>;
clock-names = "ref", "da_ref";
#phy-cells = <1>;
};
u2port1: usb-phy@1000 {
reg = <0x1000 0x400>;
clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
<&topckgen CLK_TOP_USB20_48M_EN>;
clock-names = "ref", "da_ref";
#phy-cells = <1>;
};
};
mmsys: syscon@14000000 {
compatible = "mediatek,mt8365-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};
smi_common: smi@14002000 {
compatible = "mediatek,mt8365-smi-common";
reg = <0 0x14002000 0 0x1000>;
clocks = <&mmsys CLK_MM_MM_SMI_COMMON>,
<&mmsys CLK_MM_MM_SMI_COMMON>,
<&mmsys CLK_MM_MM_SMI_COMM0>,
<&mmsys CLK_MM_MM_SMI_COMM1>;
clock-names = "apb", "smi", "gals0", "gals1";
power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
};
larb0: larb@14003000 {
compatible = "mediatek,mt8365-smi-larb",
"mediatek,mt8186-smi-larb";
reg = <0 0x14003000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&mmsys CLK_MM_MM_SMI_LARB0>,
<&mmsys CLK_MM_MM_SMI_LARB0>;
clock-names = "apb", "smi";
power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
mediatek,larb-id = <0>;
};
camsys: syscon@15000000 {
compatible = "mediatek,mt8365-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
};
larb2: larb@15001000 {
compatible = "mediatek,mt8365-smi-larb",
"mediatek,mt8186-smi-larb";
reg = <0 0x15001000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&mmsys CLK_MM_MM_SMI_IMG>,
<&camsys CLK_CAM_LARB2>;
clock-names = "apb", "smi";
power-domains = <&spm MT8365_POWER_DOMAIN_CAM>;
mediatek,larb-id = <2>;
};
vdecsys: syscon@16000000 {
compatible = "mediatek,mt8365-vdecsys", "syscon";
reg = <0 0x16000000 0 0x1000>;
#clock-cells = <1>;
};
larb3: larb@16010000 {
compatible = "mediatek,mt8365-smi-larb",
"mediatek,mt8186-smi-larb";
reg = <0 0x16010000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&vdecsys CLK_VDEC_LARB1>,
<&vdecsys CLK_VDEC_LARB1>;
clock-names = "apb", "smi";
power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>;
mediatek,larb-id = <3>;
};
vencsys: syscon@17000000 {
compatible = "mediatek,mt8365-vencsys", "syscon";
reg = <0 0x17000000 0 0x1000>;
#clock-cells = <1>;
};
larb1: larb@17010000 {
compatible = "mediatek,mt8365-smi-larb",
"mediatek,mt8186-smi-larb";
reg = <0 0x17010000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&vencsys CLK_VENC>, <&vencsys CLK_VENC>;
clock-names = "apb", "smi";
power-domains = <&spm MT8365_POWER_DOMAIN_VENC>;
mediatek,larb-id = <1>;
};
apu: syscon@19020000 {
compatible = "mediatek,mt8365-apu", "syscon";
reg = <0 0x19020000 0 0x1000>;
#clock-cells = <1>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
system_clk: dummy13m {
compatible = "fixed-clock";
clock-frequency = <13000000>;
#clock-cells = <0>;
};
systimer: timer@10017000 {
compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer";
reg = <0 0x10017000 0 0x100>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&system_clk>;
clock-names = "clk13m";
};
};

11
arch/arm/dts/nuvoton-common-npcm8xx.dtsi
View file

@ -133,7 +133,16 @@
ranges = <0x0 0x0 0xf0000000 0x00300000>,
<0xfff00000 0x0 0xfff00000 0x00016000>;
spi1: spi@201000 {
host_intf: host_intf@9f000 {
compatible = "nuvoton,npcm845-host-intf";
reg = <0x9f000 0x1000>;
type = "espi";
ioaddr = <0x4e>;
channel-support = <0xf>;
syscon = <&gcr>;
};
pspi: spi@201000 {
compatible = "nuvoton,npcm845-pspi";
reg = <0x201000 0x1000>;
pinctrl-names = "default";

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