From 3194c3cddf7bbb7d2d74097e54f587953d0bb35f Mon Sep 17 00:00:00 2001
From: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Date: Mon, 16 Oct 2017 16:21:32 +0300
Subject: [PATCH 1/3] ARC: HSDK: introduce CREG GPIO driver
The HSDK can manage some pins via CREG registers block.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
---
MAINTAINERS | 6 ++
drivers/gpio/Kconfig | 7 +++
drivers/gpio/Makefile | 1 +
drivers/gpio/hsdk-creg-gpio.c | 110 ++++++++++++++++++++++++++++++++++
4 files changed, 124 insertions(+)
create mode 100644 drivers/gpio/hsdk-creg-gpio.c
diff --git a/MAINTAINERS b/MAINTAINERS
index b167b028ec..2a20b940c3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -59,6 +59,12 @@ S: Maintained
T: git git://git.denx.de/u-boot-arc.git
F: arch/arc/
+ARC HSDK CREG GPIO
+M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+S: Maintained
+L: uboot-snps-arc@synopsys.com
+F: drivers/gpio/hsdk-creg-gpio.c
+
ARM
M: Albert Aribaud <albert.u.boot@aribaud.net>
S: Maintained
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 6240c39539..2acb33bb51 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -80,6 +80,13 @@ config IMX_RGPIO2P
help
This driver supports i.MX7ULP Rapid GPIO2P controller.
+config HSDK_CREG_GPIO
+ bool "HSDK CREG GPIO griver"
+ depends on DM
+ default n
+ help
+ This driver supports CREG GPIOs on Synopsys HSDK SOC.
+
config LPC32XX_GPIO
bool "LPC32XX GPIO driver"
depends on DM
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 81f55a576b..201d7bfff9 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o
obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o
obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o
obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o
+obj-$(CONFIG_HSDK_CREG_GPIO) += hsdk-creg-gpio.o
obj-$(CONFIG_IMX_RGPIO2P) += imx_rgpio2p.o
obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o
obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o
diff --git a/drivers/gpio/hsdk-creg-gpio.c b/drivers/gpio/hsdk-creg-gpio.c
new file mode 100644
index 0000000000..8ca807a18f
--- /dev/null
+++ b/drivers/gpio/hsdk-creg-gpio.c
@@ -0,0 +1,110 @@
+/*
+ * Synopsys HSDK SDP Generic PLL clock driver
+ *
+ * Copyright (C) 2017 Synopsys
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm-generic/gpio.h>
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <linux/printk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define HSDK_CREG_MAX_GPIO 8
+
+#define GPIO_ACTIVATE 0x2
+#define GPIO_DEACTIVATE 0x3
+#define GPIO_PIN_MASK 0x3
+#define BIT_PER_GPIO 2
+
+struct hsdk_creg_gpio {
+ uint32_t *regs;
+};
+
+static int hsdk_creg_gpio_set_value(struct udevice *dev, unsigned oft, int val)
+{
+ struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
+ uint32_t reg = readl(hcg->regs);
+ uint32_t cmd = val ? GPIO_DEACTIVATE : GPIO_ACTIVATE;
+
+ reg &= ~(GPIO_PIN_MASK << (oft * BIT_PER_GPIO));
+ reg |= (cmd << (oft * BIT_PER_GPIO));
+
+ writel(reg, hcg->regs);
+
+ return 0;
+}
+
+static int hsdk_creg_gpio_direction_output(struct udevice *dev, unsigned oft,
+ int val)
+{
+ hsdk_creg_gpio_set_value(dev, oft, val);
+
+ return 0;
+}
+
+static int hsdk_creg_gpio_direction_input(struct udevice *dev, unsigned oft)
+{
+ pr_err("hsdk-creg-gpio can't be used as input!\n");
+
+ return -ENOTSUPP;
+}
+
+static int hsdk_creg_gpio_get_value(struct udevice *dev, unsigned int oft)
+{
+ struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
+ uint32_t val = readl(hcg->regs);
+
+ val = (val >> (oft * BIT_PER_GPIO)) & GPIO_PIN_MASK;
+ return (val == GPIO_DEACTIVATE) ? 1 : 0;
+}
+
+static const struct dm_gpio_ops hsdk_creg_gpio_ops = {
+ .direction_output = hsdk_creg_gpio_direction_output,
+ .direction_input = hsdk_creg_gpio_direction_input,
+ .set_value = hsdk_creg_gpio_set_value,
+ .get_value = hsdk_creg_gpio_get_value,
+};
+
+static int hsdk_creg_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
+
+ hcg->regs = (uint32_t *)devfdt_get_addr_ptr(dev);
+
+ uc_priv->gpio_count = dev_read_u32_default(dev, "gpio-count", 1);
+ if (uc_priv->gpio_count > HSDK_CREG_MAX_GPIO)
+ uc_priv->gpio_count = HSDK_CREG_MAX_GPIO;
+
+ uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
+ if (!uc_priv->bank_name)
+ uc_priv->bank_name = dev_read_name(dev);
+
+ pr_debug("%s GPIO [0x%p] controller with %d gpios probed\n",
+ uc_priv->bank_name, hcg->regs, uc_priv->gpio_count);
+
+ return 0;
+}
+
+static const struct udevice_id hsdk_creg_gpio_ids[] = {
+ { .compatible = "snps,hsdk-creg-gpio" },
+ { }
+};
+
+U_BOOT_DRIVER(gpio_hsdk_creg) = {
+ .name = "gpio_hsdk_creg",
+ .id = UCLASS_GPIO,
+ .ops = &hsdk_creg_gpio_ops,
+ .probe = hsdk_creg_gpio_probe,
+ .of_match = hsdk_creg_gpio_ids,
+ .platdata_auto_alloc_size = sizeof(struct hsdk_creg_gpio),
+};
From d764a20f2bcab2e76bce0751ed125b0c32f9d82f Mon Sep 17 00:00:00 2001
From: Alexey Brodkin <abrodkin@synopsys.com>
Date: Fri, 17 Nov 2017 15:53:20 +0300
Subject: [PATCH 2/3] arc: bootm: Move slave cores kick-starting under !fake
Currently slave cores will be kick-started even if we want
to dry run bootm which is not what we really want.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Eugeniy Paltsev <paltsev@synopsys.com>
---
arch/arc/lib/bootm.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c
index a498ce5b29..9eef7070cf 100644
--- a/arch/arc/lib/bootm.c
+++ b/arch/arc/lib/bootm.c
@@ -88,11 +88,11 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
r2 = (unsigned int)env_get("bootargs");
}
- smp_set_core_boot_addr((unsigned long)kernel_entry, -1);
- smp_kick_all_cpus();
-
- if (!fake)
+ if (!fake) {
+ smp_set_core_boot_addr((unsigned long)kernel_entry, -1);
+ smp_kick_all_cpus();
kernel_entry(r0, 0, r2);
+ }
}
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
From f2a226780fa0e4055bec636b8108bf7e80951174 Mon Sep 17 00:00:00 2001
From: Alexey Brodkin <abrodkin@synopsys.com>
Date: Fri, 17 Nov 2017 16:02:17 +0300
Subject: [PATCH 3/3] arc: cache: Add required NOPs after invalidation of
instruction cache
As per ARC HS databook (see chapter 5.3.3.2) it is required to add
3 NOPs after each write to IC_IVIC which we do from now on.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Eugeniy Paltsev <paltsev@synopsys.com>
---
arch/arc/lib/cache.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index cbae27e9fc..d8741fe959 100644
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -278,6 +278,13 @@ void invalidate_icache_all(void)
/* Any write to IC_IVIC register triggers invalidation of entire I$ */
if (icache_status()) {
write_aux_reg(ARC_AUX_IC_IVIC, 1);
+ /*
+ * As per ARC HS databook (see chapter 5.3.3.2)
+ * it is required to add 3 NOPs after each write to IC_IVIC.
+ */
+ __builtin_arc_nop();
+ __builtin_arc_nop();
+ __builtin_arc_nop();
read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
}
}