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sunxi: dram: Derive write recovery delay from DRAM clock speed

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The write recovery time is 15ns for all JEDEC DDR3 speed bins. And
instead of hardcoding it to 10 cycles, it is possible to set tighter
timings based on accurate calculations. For example, DRAM clock
frequencies up to 533MHz need only 8 cycles for write recovery.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Siarhei Siamashka 2014-08-03 05:32:53 +03:00 committed by Hans de Goede
parent b5c71f5f9c
commit 935758b1d5
1 changed files with 16 additions and 1 deletions
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17
arch/arm/cpu/armv7/sunxi/dram.c
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@ -451,6 +451,21 @@ static void dramc_set_autorefresh_cycle(u32 clk, u32 density)
writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr); writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr);
} }
/* Calculate the value for A11, A10, A9 bits in MR0 (write recovery) */
static u32 ddr3_write_recovery(u32 clk)
{
u32 twr_ns = 15; /* DDR3 spec says that it is 15ns for all speed bins */
u32 twr_ck = (twr_ns * clk + 999) / 1000;
if (twr_ck < 5)
return 1;
else if (twr_ck <= 8)
return twr_ck - 4;
else if (twr_ck <= 10)
return 5;
else
return 6;
}
/* /*
* If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this * If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this
* means that DRAM is currently in self-refresh mode and retaining the old * means that DRAM is currently in self-refresh mode and retaining the old
@ -647,7 +662,7 @@ unsigned long dramc_init(struct dram_para *para)
reg_val |= DRAM_MR_POWER_DOWN; reg_val |= DRAM_MR_POWER_DOWN;
#endif #endif
reg_val |= DRAM_MR_CAS_LAT(para->cas - 4); reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
reg_val |= DRAM_MR_WRITE_RECOVERY(0x5); reg_val |= DRAM_MR_WRITE_RECOVERY(ddr3_write_recovery(para->clock));
writel(reg_val, &dram->mr); writel(reg_val, &dram->mr);
writel(para->emr1, &dram->emr); writel(para->emr1, &dram->emr);