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rockchip: pinebook-pro: default to SPI bus 1 for SPI-flash
SPI flash on this machine is located on bus 1, default to using bus 1
for SPI flash and stop aliasing it to bus 0.
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Fixes: c4cea2bb
("rockchip: Enable building a SPI ROM image on bob")
This commit is contained in:
parent
b8c725e736
commit
92cb207af1
2 changed files with 2 additions and 4 deletions
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@ -7,10 +7,6 @@
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#include "rk3399-sdram-lpddr4-100.dtsi"
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/ {
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aliases {
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spi0 = &spi1;
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};
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chosen {
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u-boot,spl-boot-order = "same-as-spl", &sdhci, &spiflash, &sdmmc;
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};
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@ -37,6 +37,7 @@ CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_DM_KEYBOARD=y
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@ -49,6 +50,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_SDMA=y
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CONFIG_MMC_SDHCI_ROCKCHIP=y
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_SF_DEFAULT_SPEED=20000000
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_WINBOND=y
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