mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
Merge branch 'mpc85xx'
Conflicts: include/ft_build.h include/pci.h Resolved, though.
This commit is contained in:
Jon Loeliger
commit
92c427b189
32 changed files with 801 additions and 490 deletions
54
README
54
README
|
|
@ -447,6 +447,11 @@ The following options need to be configured:
|
|||
Board code has addition modification that it wants to make
|
||||
to the flat device tree before handing it off to the kernel
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||||
|
||||
CONFIG_OF_BOOT_CPU
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||||
|
||||
This define fills in the correct boot cpu in the boot
|
||||
param header, the default value is zero if undefined.
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||||
|
||||
- Serial Ports:
|
||||
CFG_PL010_SERIAL
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||||
|
||||
|
|
@ -3019,6 +3024,55 @@ format!) to the "bootm" command:
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|||
|
||||
bash#
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||||
|
||||
Boot Linux and pass a flat device tree:
|
||||
-----------
|
||||
|
||||
First, U-Boot must be compiled with the appropriate defines. See the section
|
||||
titled "Linux Kernel Interface" above for a more in depth explanation. The
|
||||
following is an example of how to start a kernel and pass an updated
|
||||
flat device tree:
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||||
|
||||
=> print oftaddr
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||||
oftaddr=0x300000
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||||
=> print oft
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||||
oft=oftrees/mpc8540ads.dtb
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||||
=> tftp $oftaddr $oft
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||||
Speed: 1000, full duplex
|
||||
Using TSEC0 device
|
||||
TFTP from server 192.168.1.1; our IP address is 192.168.1.101
|
||||
Filename 'oftrees/mpc8540ads.dtb'.
|
||||
Load address: 0x300000
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||||
Loading: #
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||||
done
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||||
Bytes transferred = 4106 (100a hex)
|
||||
=> tftp $loadaddr $bootfile
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||||
Speed: 1000, full duplex
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||||
Using TSEC0 device
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||||
TFTP from server 192.168.1.1; our IP address is 192.168.1.2
|
||||
Filename 'uImage'.
|
||||
Load address: 0x200000
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||||
Loading:############
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||||
done
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||||
Bytes transferred = 1029407 (fb51f hex)
|
||||
=> print loadaddr
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loadaddr=200000
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||||
=> print oftaddr
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||||
oftaddr=0x300000
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=> bootm $loadaddr - $oftaddr
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||||
## Booting image at 00200000 ...
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||||
Image Name: Linux-2.6.17-dirty
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||||
Image Type: PowerPC Linux Kernel Image (gzip compressed)
|
||||
Data Size: 1029343 Bytes = 1005.2 kB
|
||||
Load Address: 00000000
|
||||
Entry Point: 00000000
|
||||
Verifying Checksum ... OK
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||||
Uncompressing Kernel Image ... OK
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Booting using flat device tree at 0x300000
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||||
Using MPC85xx ADS machine description
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Memory CAM mapping: CAM0=256Mb, CAM1=256Mb, CAM2=0Mb residual: 0Mb
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||||
[snip]
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||||
|
||||
|
||||
More About U-Boot Image Types:
|
||||
------------------------------
|
||||
|
||||
|
|
|
|||
49
board/cds/common/ft_board.c
Normal file
49
board/cds/common/ft_board.c
Normal file
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|
@ -0,0 +1,49 @@
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|||
/*
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||||
* Copyright 2004 Freescale Semiconductor.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
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||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
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||||
#include <ft_build.h>
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||||
extern void ft_cpu_setup(void *blob, bd_t *bd);
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||||
#endif
|
||||
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
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||||
{
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||||
u32 *p;
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||||
int len;
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
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||||
#endif
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
p = ft_get_prop(blob, "/memory/reg", &len);
|
||||
if (p != NULL) {
|
||||
*p++ = cpu_to_be32(bd->bi_memstart);
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||||
*p = cpu_to_be32(bd->bi_memsize);
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||||
}
|
||||
}
|
||||
#endif
|
||||
99
board/cds/common/via.c
Normal file
99
board/cds/common/via.c
Normal file
|
|
@ -0,0 +1,99 @@
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|||
/*
|
||||
* Copyright 2006 Freescale Semiconductor.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
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||||
|
||||
#include <common.h>
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||||
#include <pci.h>
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||||
/* Config the VIA chip */
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||||
void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
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{
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pci_dev_t bridge;
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/* Enable USB and IDE functions */
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pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
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pciauto_config_device(hose, dev);
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/*
|
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* Force the backplane P2P bridge to have a window
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||||
* open from 0x00000000-0x00001fff in PCI I/O space.
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* This allows legacy I/O (i8259, etc) on the VIA
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* southbridge to be accessed.
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*/
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bridge = PCI_BDF(0,17,0);
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pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
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pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
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pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
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pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
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}
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||||
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||||
/* Function 1, IDE */
|
||||
void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
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||||
{
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pciauto_config_device(hose, dev);
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||||
/*
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* Since the P2P window was forced to cover the fixed
|
||||
* legacy I/O addresses, it is necessary to manually
|
||||
* place the base addresses for the IDE and USB functions
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||||
* within this window.
|
||||
*/
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
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||||
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
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||||
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
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||||
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
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}
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||||
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||||
/* Function 2, USB ports 0-1 */
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||||
void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
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||||
{
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||||
pciauto_config_device(hose, dev);
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||||
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||||
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
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||||
}
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||||
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||||
/* Function 3, USB ports 2-3 */
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||||
void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
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{
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pciauto_config_device(hose, dev);
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||||
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
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}
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/* Function 5, Power Management */
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||||
void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
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||||
{
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pciauto_config_device(hose, dev);
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||||
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||||
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
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}
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||||
/* Function 6, AC97 Interface */
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void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
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||||
{
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pciauto_config_device(hose, dev);
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||||
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||||
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
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||||
}
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||||
|
||||
18
board/cds/common/via.h
Normal file
18
board/cds/common/via.h
Normal file
|
|
@ -0,0 +1,18 @@
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|||
#ifndef _MPC85xx_VIA_H
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void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
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/* Function 1, IDE */
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void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
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/* Function 2, USB ports 0-1 */
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void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
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/* Function 3, USB ports 2-3 */
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void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
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/* Function 5, Power Management */
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void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
|
||||
|
||||
/* Function 6, AC97 Interface */
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||||
void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
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#endif /* _MPC85xx_VIA_H */
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|
|
@ -28,7 +28,9 @@ LIB = lib$(BOARD).a
|
|||
|
||||
OBJS := $(BOARD).o \
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||||
../common/cadmus.o \
|
||||
../common/eeprom.o
|
||||
../common/eeprom.o \
|
||||
../common/ft_board.o \
|
||||
../common/via.o
|
||||
|
||||
SOBJS := init.o
|
||||
|
||||
|
|
|
|||
|
|
@ -210,8 +210,8 @@ tlb1_entry:
|
|||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
|
||||
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
|
||||
* 0xe000_0000 0xe000_ffff CCSR 1M
|
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
|
||||
* 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
|
||||
* 0xe200_0000 0xe20f_ffff PCI1 IO 1M
|
||||
* 0xe210_0000 0xe21f_ffff PCI2 IO 1M
|
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M
|
||||
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
|
||||
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
|
||||
|
|
@ -234,11 +234,11 @@ tlb1_entry:
|
|||
#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
|
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
||||
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
|
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
|
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
|
||||
|
||||
#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
|
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
|
||||
#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
|
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
|
||||
|
||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
|
||||
#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@
|
|||
|
||||
#include "../common/cadmus.h"
|
||||
#include "../common/eeprom.h"
|
||||
#include "../common/via.h"
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||
extern void ddr_enable_ecc(unsigned int dram_size);
|
||||
|
|
@ -468,26 +469,25 @@ testdram(void)
|
|||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
/*
|
||||
* Initialize PCI Devices, report devices found.
|
||||
/* For some reason the Tundra PCI bridge shows up on itself as a
|
||||
* different device. Work around that by refusing to configure it.
|
||||
*/
|
||||
void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
|
||||
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
|
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
||||
PCI_IDSEL_NUMBER, PCI_ANY_ID,
|
||||
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
|
||||
PCI_ENET0_MEMADDR,
|
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
|
||||
} },
|
||||
{ }
|
||||
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
|
||||
{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
|
||||
{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
|
||||
{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
|
||||
{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
|
||||
{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
|
||||
{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct pci_controller hose = {
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
config_table: pci_mpc85xxcds_config_table,
|
||||
static struct pci_controller hose[] = {
|
||||
{ config_table: pci_mpc85xxcds_config_table,},
|
||||
#ifdef CONFIG_MPC85XX_PCI2
|
||||
{},
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
@ -497,7 +497,7 @@ void
|
|||
pci_init_board(void)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
extern void pci_mpc85xx_init(struct pci_controller *hose);
|
||||
extern void pci_mpc85xx_init(struct pci_controller **hose);
|
||||
|
||||
pci_mpc85xx_init(&hose);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -28,7 +28,9 @@ LIB = lib$(BOARD).a
|
|||
|
||||
OBJS := $(BOARD).o \
|
||||
../common/cadmus.o \
|
||||
../common/eeprom.o
|
||||
../common/eeprom.o \
|
||||
../common/ft_board.o \
|
||||
../common/via.o
|
||||
|
||||
SOBJS := init.o
|
||||
|
||||
|
|
|
|||
|
|
@ -210,8 +210,8 @@ tlb1_entry:
|
|||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
|
||||
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
|
||||
* 0xe000_0000 0xe000_ffff CCSR 1M
|
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
|
||||
* 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
|
||||
* 0xe200_0000 0xe20f_ffff PCI1 IO 1M
|
||||
* 0xe210_0000 0xe21f_ffff PCI2 IO 1M
|
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M
|
||||
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
|
||||
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
|
||||
|
|
@ -234,11 +234,11 @@ tlb1_entry:
|
|||
#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
|
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
||||
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
|
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
|
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
|
||||
|
||||
#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
|
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
|
||||
#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
|
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
|
||||
|
||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
|
||||
#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@
|
|||
|
||||
#include "../common/cadmus.h"
|
||||
#include "../common/eeprom.h"
|
||||
#include "../common/via.h"
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||
extern void ddr_enable_ecc(unsigned int dram_size);
|
||||
|
|
@ -293,26 +294,25 @@ testdram(void)
|
|||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
/*
|
||||
* Initialize PCI Devices, report devices found.
|
||||
/* For some reason the Tundra PCI bridge shows up on itself as a
|
||||
* different device. Work around that by refusing to configure it.
|
||||
*/
|
||||
void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
|
||||
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
|
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
||||
PCI_IDSEL_NUMBER, PCI_ANY_ID,
|
||||
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
|
||||
PCI_ENET0_MEMADDR,
|
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
|
||||
} },
|
||||
{ }
|
||||
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
|
||||
{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
|
||||
{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
|
||||
{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
|
||||
{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
|
||||
{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
|
||||
{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct pci_controller hose = {
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
config_table: pci_mpc85xxcds_config_table,
|
||||
static struct pci_controller hose[] = {
|
||||
{ config_table: pci_mpc85xxcds_config_table,},
|
||||
#ifdef CONFIG_MPC85XX_PCI2
|
||||
{},
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
@ -322,7 +322,7 @@ void
|
|||
pci_init_board(void)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
extern void pci_mpc85xx_init(struct pci_controller *hose);
|
||||
extern void pci_mpc85xx_init(struct pci_controller **hose);
|
||||
|
||||
pci_mpc85xx_init(&hose);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -28,7 +28,9 @@ LIB = lib$(BOARD).a
|
|||
|
||||
OBJS := $(BOARD).o \
|
||||
../common/cadmus.o \
|
||||
../common/eeprom.o
|
||||
../common/eeprom.o \
|
||||
../common/ft_board.o \
|
||||
../common/via.o
|
||||
|
||||
SOBJS := init.o
|
||||
|
||||
|
|
|
|||
|
|
@ -210,8 +210,8 @@ tlb1_entry:
|
|||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
|
||||
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
|
||||
* 0xe000_0000 0xe000_ffff CCSR 1M
|
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
|
||||
* 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
|
||||
* 0xe200_0000 0xe20f_ffff PCI1 IO 1M
|
||||
* 0xe210_0000 0xe21f_ffff PCI2 IO 1M
|
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M
|
||||
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
|
||||
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
|
||||
|
|
@ -234,11 +234,11 @@ tlb1_entry:
|
|||
#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
|
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
||||
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
|
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
|
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
|
||||
|
||||
#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
|
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
|
||||
#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
|
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
|
||||
|
||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
|
||||
#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
|
||||
#include "../common/cadmus.h"
|
||||
#include "../common/eeprom.h"
|
||||
#include "../common/via.h"
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||
extern void ddr_enable_ecc(unsigned int dram_size);
|
||||
|
|
@ -464,31 +465,33 @@ testdram(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
/*
|
||||
* Initialize PCI Devices, report devices found.
|
||||
#ifdef CONFIG_PCI
|
||||
/* For some reason the Tundra PCI bridge shows up on itself as a
|
||||
* different device. Work around that by refusing to configure it
|
||||
*/
|
||||
void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
|
||||
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
|
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
||||
PCI_IDSEL_NUMBER, PCI_ANY_ID,
|
||||
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
|
||||
PCI_ENET0_MEMADDR,
|
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
|
||||
} },
|
||||
{ }
|
||||
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
|
||||
{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
|
||||
{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
|
||||
{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
|
||||
{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
|
||||
{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
|
||||
{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct pci_controller hose = {
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
|
||||
static struct pci_controller hose[] = {
|
||||
{
|
||||
config_table: pci_mpc85xxcds_config_table,
|
||||
},
|
||||
#ifdef CONFIG_MPC85XX_PCI2
|
||||
{ }
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
#endif
|
||||
|
||||
void
|
||||
pci_init_board(void)
|
||||
|
|
@ -496,6 +499,6 @@ pci_init_board(void)
|
|||
#ifdef CONFIG_PCI
|
||||
extern void pci_mpc85xx_init(struct pci_controller *hose);
|
||||
|
||||
pci_mpc85xx_init(&hose);
|
||||
pci_mpc85xx_init(hose);
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -31,6 +31,12 @@
|
|||
#include <asm/immap_85xx.h>
|
||||
#include <spd.h>
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
#include <ft_build.h>
|
||||
extern void ft_cpu_setup(void *blob, bd_t *bd);
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||
extern void ddr_enable_ecc(unsigned int dram_size);
|
||||
#endif
|
||||
|
|
@ -311,24 +317,8 @@ long int fixed_sdram (void)
|
|||
* Initialize PCI Devices, report devices found.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
static struct pci_config_table pci_mpc85xxads_config_table[] = {
|
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
||||
PCI_IDSEL_NUMBER, PCI_ANY_ID,
|
||||
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
|
||||
PCI_ENET0_MEMADDR,
|
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
|
||||
} },
|
||||
{ }
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
static struct pci_controller hose = {
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
config_table: pci_mpc85xxads_config_table,
|
||||
#endif
|
||||
};
|
||||
static struct pci_controller hose;
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
|
|
@ -342,3 +332,24 @@ pci_init_board(void)
|
|||
pci_mpc85xx_init(&hose);
|
||||
#endif /* CONFIG_PCI */
|
||||
}
|
||||
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
u32 *p;
|
||||
int len;
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
p = ft_get_prop(blob, "/memory/reg", &len);
|
||||
if (p != NULL) {
|
||||
*p++ = cpu_to_be32(bd->bi_memstart);
|
||||
*p = cpu_to_be32(bd->bi_memsize);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -544,3 +544,12 @@ pci_init_board(void)
|
|||
pci_mpc85xx_init(&hose);
|
||||
#endif /* CONFIG_PCI */
|
||||
}
|
||||
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
ft_cpu_setup(blob, bd);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -25,19 +25,11 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS = $(BOARD).o oftree.o
|
||||
OBJS = $(BOARD).o
|
||||
|
||||
$(LIB): .depend $(OBJS)
|
||||
$(AR) crv $@ $(OBJS)
|
||||
|
||||
%.dtb: %.dts
|
||||
dtc -f -V 0x10 -I dts -O dtb $< >$@
|
||||
|
||||
%.c: %.dtb
|
||||
xxd -i $< \
|
||||
| sed -e "s/^unsigned char/const unsigned char/g" \
|
||||
| sed -e "s/^unsigned int/const unsigned int/g" > $@
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
|
||||
|
|
|
|||
|
|
@ -1,52 +0,0 @@
|
|||
/ {
|
||||
model = "STXXTC V1";
|
||||
compatible = "STXXTC";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
linux,phandle = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
PowerPC,MPC870@0 {
|
||||
linux,phandle = <3>;
|
||||
name = "PowerPC,MPC870";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
clock-frequency = <0>; /* place-holder for runtime fillup */
|
||||
timebase-frequency = <0>; /* dido */
|
||||
linux,boot-cpu;
|
||||
i-cache-size = <2000>;
|
||||
d-cache-size = <2000>;
|
||||
32-bit;
|
||||
};
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <00000000 00000000 00000000 20000000>;
|
||||
};
|
||||
|
||||
/* copy of the bd_t information (place-holders) */
|
||||
bd_t {
|
||||
memstart = <0>;
|
||||
memsize = <0>;
|
||||
flashstart = <0>;
|
||||
flashsize = <0>;
|
||||
flashoffset = <0>;
|
||||
sramstart = <0>;
|
||||
sramsize = <0>;
|
||||
|
||||
immr_base = <0>;
|
||||
|
||||
bootflags = <0>;
|
||||
ip_addr = <0>;
|
||||
enetaddr = [ 00 00 00 00 00 00 ];
|
||||
ethspeed = <0>;
|
||||
intfreq = <0>;
|
||||
busfreq = <0>;
|
||||
|
||||
baudrate = <0>;
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -465,6 +465,13 @@ U_BOOT_CMD(
|
|||
"[addr [arg ...]]\n - boot application image stored in memory\n"
|
||||
"\tpassing arguments 'arg ...'; when booting a Linux kernel,\n"
|
||||
"\t'arg' can be the address of an initrd image\n"
|
||||
#ifdef CONFIG_OF_FLAT_TREE
|
||||
"\tWhen booting a Linux kernel which requires a flat device-tree\n"
|
||||
"\ta third argument is required which is the address of the of the\n"
|
||||
"\tdevice-tree blob. To boot that kernel without an initrd image,\n"
|
||||
"\tuse a '-' for the second argument. If you do not pass a third\n"
|
||||
"\ta bd_info struct will be passed instead\n"
|
||||
#endif
|
||||
);
|
||||
|
||||
#ifdef CONFIG_SILENT_CONSOLE
|
||||
|
|
@ -500,11 +507,6 @@ fixup_silent_linux ()
|
|||
}
|
||||
#endif /* CONFIG_SILENT_CONSOLE */
|
||||
|
||||
#ifdef CONFIG_OF_FLAT_TREE
|
||||
extern const unsigned char oftree_dtb[];
|
||||
extern const unsigned int oftree_dtb_len;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PPC
|
||||
static void
|
||||
do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
|
||||
|
|
@ -616,7 +618,17 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
|
|||
/*
|
||||
* Check if there is an initrd image
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_OF_FLAT_TREE
|
||||
/* Look for a '-' which indicates to ignore the ramdisk argument */
|
||||
if (argc >= 3 && strcmp(argv[2], "-") == 0) {
|
||||
debug ("Skipping initrd\n");
|
||||
data = 0;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
if (argc >= 3) {
|
||||
debug ("Not skipping initrd\n");
|
||||
SHOW_BOOT_PROGRESS (9);
|
||||
|
||||
addr = simple_strtoul(argv[2], NULL, 16);
|
||||
|
|
@ -724,6 +736,15 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
|
|||
len = data = 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_FLAT_TREE
|
||||
if (argc >= 3)
|
||||
{
|
||||
of_flat_tree = (char *) simple_strtoul(argv[3], NULL, 16);
|
||||
printf ("Booting using flat device tree at 0x%x\n",
|
||||
of_flat_tree);
|
||||
}
|
||||
#endif
|
||||
|
||||
if (!data) {
|
||||
debug ("No initrd\n");
|
||||
}
|
||||
|
|
@ -793,15 +814,6 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
|
|||
initrd_end = 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_FLAT_TREE
|
||||
if (initrd_start == 0)
|
||||
of_flat_tree = (char *)(((ulong)kbd - OF_FLAT_TREE_MAX_SIZE -
|
||||
sizeof(bd_t)) & ~0xF);
|
||||
else
|
||||
of_flat_tree = (char *)((initrd_start - OF_FLAT_TREE_MAX_SIZE -
|
||||
sizeof(bd_t)) & ~0xF);
|
||||
#endif
|
||||
|
||||
debug ("## Transferring control to Linux (at address %08lx) ...\n",
|
||||
(ulong)kernel);
|
||||
|
||||
|
|
@ -824,7 +836,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
|
|||
(*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
|
||||
|
||||
#else
|
||||
ft_setup(of_flat_tree, OF_FLAT_TREE_MAX_SIZE, kbd, initrd_start, initrd_end);
|
||||
ft_setup(of_flat_tree, kbd, initrd_start, initrd_end);
|
||||
/* ft_dump_blob(of_flat_tree); */
|
||||
|
||||
#if defined(CFG_INIT_RAM_LOCK) && (!defined(CONFIG_E500)||!defined(CONFIG_MPC86xx))
|
||||
|
|
|
|||
|
|
@ -1,5 +1,22 @@
|
|||
/*
|
||||
* OF flat tree builder
|
||||
* Written by: Pantelis Antoniou <pantelis.antoniou@gmail.com>
|
||||
* Updated by: Matthew McClintock <msm@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
|
@ -13,44 +30,39 @@
|
|||
|
||||
#include <ft_build.h>
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
/* align addr on a size boundary - adjust address up if needed -- Cort */
|
||||
#define _ALIGN(addr,size) (((addr)+(size)-1)&(~((size)-1)))
|
||||
#ifndef CONFIG_OF_BOOT_CPU
|
||||
#define CONFIG_OF_BOOT_CPU 0
|
||||
#endif
|
||||
#define SIZE_OF_RSVMAP_ENTRY (2*sizeof(u64))
|
||||
|
||||
static void ft_put_word(struct ft_cxt *cxt, u32 v)
|
||||
{
|
||||
if (cxt->overflow) /* do nothing */
|
||||
return;
|
||||
|
||||
/* check for overflow */
|
||||
if (cxt->p + 4 > cxt->pstr) {
|
||||
cxt->overflow = 1;
|
||||
return;
|
||||
}
|
||||
memmove(cxt->p + sizeof(u32), cxt->p, cxt->p_end - cxt->p);
|
||||
|
||||
*(u32 *) cxt->p = cpu_to_be32(v);
|
||||
cxt->p += 4;
|
||||
cxt->p += sizeof(u32);
|
||||
cxt->p_end += sizeof(u32);
|
||||
}
|
||||
|
||||
static inline void ft_put_bin(struct ft_cxt *cxt, const void *data, int sz)
|
||||
{
|
||||
u8 *p;
|
||||
int aligned_size = ((u8 *)_ALIGN((unsigned long)cxt->p + sz,
|
||||
sizeof(u32))) - cxt->p;
|
||||
|
||||
if (cxt->overflow) /* do nothing */
|
||||
return;
|
||||
memmove(cxt->p + aligned_size, cxt->p, cxt->p_end - cxt->p);
|
||||
|
||||
/* next pointer pos */
|
||||
p = (u8 *) _ALIGN((unsigned long)cxt->p + sz, 4);
|
||||
|
||||
/* check for overflow */
|
||||
if (p > cxt->pstr) {
|
||||
cxt->overflow = 1;
|
||||
return;
|
||||
}
|
||||
/* make sure the last bytes are zeroed */
|
||||
memset(cxt->p + aligned_size - (aligned_size % sizeof(u32)), 0,
|
||||
(aligned_size % sizeof(u32)));
|
||||
|
||||
memcpy(cxt->p, data, sz);
|
||||
if ((sz & 3) != 0)
|
||||
memset(cxt->p + sz, 0, 4 - (sz & 3));
|
||||
cxt->p = p;
|
||||
|
||||
cxt->p += aligned_size;
|
||||
cxt->p_end += aligned_size;
|
||||
}
|
||||
|
||||
void ft_begin_node(struct ft_cxt *cxt, const char *name)
|
||||
|
|
@ -73,10 +85,10 @@ static int lookup_string(struct ft_cxt *cxt, const char *name)
|
|||
{
|
||||
u8 *p;
|
||||
|
||||
p = cxt->pstr;
|
||||
while (p < cxt->pstr_begin) {
|
||||
p = cxt->p;
|
||||
while (p < cxt->p_end) {
|
||||
if (strcmp(p, name) == 0)
|
||||
return p - cxt->p_begin;
|
||||
return p - cxt->p;
|
||||
p += strlen(p) + 1;
|
||||
}
|
||||
|
||||
|
|
@ -85,24 +97,13 @@ static int lookup_string(struct ft_cxt *cxt, const char *name)
|
|||
|
||||
void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz)
|
||||
{
|
||||
int len, off;
|
||||
|
||||
if (cxt->overflow)
|
||||
return;
|
||||
|
||||
len = strlen(name) + 1;
|
||||
int off = 0;
|
||||
|
||||
off = lookup_string(cxt, name);
|
||||
if (off == -1) {
|
||||
/* check if we have space */
|
||||
if (cxt->p + 12 + sz + len > cxt->pstr) {
|
||||
cxt->overflow = 1;
|
||||
return;
|
||||
}
|
||||
|
||||
cxt->pstr -= len;
|
||||
memcpy(cxt->pstr, name, len);
|
||||
off = cxt->pstr - cxt->p_begin;
|
||||
memcpy(cxt->p_end, name, strlen(name) + 1);
|
||||
off = cxt->p_end - cxt->p;
|
||||
cxt->p_end += strlen(name) + 2;
|
||||
}
|
||||
|
||||
/* now put offset from beginning of *STRUCTURE* */
|
||||
|
|
@ -122,137 +123,62 @@ void ft_prop_int(struct ft_cxt *cxt, const char *name, int val)
|
|||
{
|
||||
u32 v = cpu_to_be32((u32) val);
|
||||
|
||||
ft_prop(cxt, name, &v, 4);
|
||||
ft_prop(cxt, name, &v, sizeof(u32));
|
||||
}
|
||||
|
||||
/* start construction of the flat OF tree */
|
||||
void ft_begin(struct ft_cxt *cxt, void *blob, int max_size)
|
||||
/* pick up and start working on a tree in place */
|
||||
void ft_init_cxt(struct ft_cxt *cxt, void *blob)
|
||||
{
|
||||
struct boot_param_header *bph = blob;
|
||||
u32 off;
|
||||
|
||||
/* clear the cxt */
|
||||
memset(cxt, 0, sizeof(*cxt));
|
||||
|
||||
cxt->bph = bph;
|
||||
cxt->max_size = max_size;
|
||||
bph->boot_cpuid_phys = CONFIG_OF_BOOT_CPU;
|
||||
|
||||
/* zero everything in the header area */
|
||||
memset(bph, 0, sizeof(*bph));
|
||||
/* find beginning and end of reserve map table (zeros in last entry) */
|
||||
cxt->p_rsvmap = (u8 *)bph + bph->off_mem_rsvmap;
|
||||
while ( ((uint64_t *)cxt->p_rsvmap)[0] != 0 &&
|
||||
((uint64_t *)cxt->p_rsvmap)[1] != 0 ) {
|
||||
cxt->p_rsvmap += SIZE_OF_RSVMAP_ENTRY;
|
||||
}
|
||||
|
||||
bph->magic = cpu_to_be32(OF_DT_HEADER);
|
||||
bph->version = cpu_to_be32(0x10);
|
||||
bph->last_comp_version = cpu_to_be32(0x10);
|
||||
|
||||
/* start pointers */
|
||||
cxt->pres_begin = (u8 *) _ALIGN((unsigned long)(bph + 1), 8);
|
||||
cxt->pres = cxt->pres_begin;
|
||||
|
||||
off = (unsigned long)cxt->pres_begin - (unsigned long)bph;
|
||||
bph->off_mem_rsvmap = cpu_to_be32(off);
|
||||
|
||||
((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */
|
||||
((u64 *) cxt->pres)[1] = 0;
|
||||
|
||||
cxt->p_anchor = cxt->pres + 16; /* over the terminator */
|
||||
cxt->p_start = (char*)bph + bph->off_dt_struct;
|
||||
cxt->p_end = (char *)bph + bph->totalsize;
|
||||
cxt->p = (char *)bph + bph->off_dt_strings;
|
||||
}
|
||||
|
||||
/* add a reserver physical area to the rsvmap */
|
||||
void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size)
|
||||
void ft_add_rsvmap(struct ft_cxt *cxt, u64 physstart, u64 physend)
|
||||
{
|
||||
((u64 *) cxt->pres)[0] = cpu_to_be64(physaddr); /* phys = 0, size = 0, terminate */
|
||||
((u64 *) cxt->pres)[1] = cpu_to_be64(size);
|
||||
memmove(cxt->p_rsvmap + SIZE_OF_RSVMAP_ENTRY, cxt->p_rsvmap,
|
||||
cxt->p_end - cxt->p_rsvmap);
|
||||
|
||||
cxt->pres += 16; /* advance */
|
||||
((u64 *)cxt->p_rsvmap)[0] = cpu_to_be64(physstart);
|
||||
((u64 *)cxt->p_rsvmap)[1] = cpu_to_be64(physend);
|
||||
((u64 *)cxt->p_rsvmap)[2] = 0;
|
||||
((u64 *)cxt->p_rsvmap)[3] = 0;
|
||||
|
||||
((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */
|
||||
((u64 *) cxt->pres)[1] = 0;
|
||||
|
||||
/* keep track of size */
|
||||
cxt->res_size = cxt->pres + 16 - cxt->pres_begin;
|
||||
|
||||
cxt->p_anchor = cxt->pres + 16; /* over the terminator */
|
||||
cxt->p_rsvmap += SIZE_OF_RSVMAP_ENTRY;
|
||||
cxt->p_start += SIZE_OF_RSVMAP_ENTRY;
|
||||
cxt->p += SIZE_OF_RSVMAP_ENTRY;
|
||||
cxt->p_end += SIZE_OF_RSVMAP_ENTRY;
|
||||
}
|
||||
|
||||
void ft_begin_tree(struct ft_cxt *cxt)
|
||||
void ft_end_tree(struct ft_cxt *cxt)
|
||||
{
|
||||
cxt->p_begin = cxt->p_anchor;
|
||||
cxt->pstr_begin = (char *)cxt->bph + cxt->max_size; /* point at the end */
|
||||
|
||||
cxt->p = cxt->p_begin;
|
||||
cxt->pstr = cxt->pstr_begin;
|
||||
}
|
||||
|
||||
int ft_end_tree(struct ft_cxt *cxt)
|
||||
{
|
||||
struct boot_param_header *bph = cxt->bph;
|
||||
int off, sz, sz1;
|
||||
u32 tag, v;
|
||||
u8 *p;
|
||||
|
||||
ft_put_word(cxt, OF_DT_END);
|
||||
|
||||
if (cxt->overflow)
|
||||
return -ENOMEM;
|
||||
|
||||
/* size of the areas */
|
||||
cxt->struct_size = cxt->p - cxt->p_begin;
|
||||
cxt->strings_size = cxt->pstr_begin - cxt->pstr;
|
||||
|
||||
/* the offset we must move */
|
||||
off = (cxt->pstr_begin - cxt->p_begin) - cxt->strings_size;
|
||||
|
||||
/* the new strings start */
|
||||
cxt->pstr_begin = cxt->p_begin + cxt->struct_size;
|
||||
|
||||
/* move the whole string area */
|
||||
memmove(cxt->pstr_begin, cxt->pstr, cxt->strings_size);
|
||||
|
||||
/* now perform the fixup of the strings */
|
||||
p = cxt->p_begin;
|
||||
while ((tag = be32_to_cpu(*(u32 *) p)) != OF_DT_END) {
|
||||
p += 4;
|
||||
|
||||
if (tag == OF_DT_BEGIN_NODE) {
|
||||
p = (u8 *) _ALIGN((unsigned long)p + strlen(p) + 1, 4);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (tag == OF_DT_END_NODE || tag == OF_DT_NOP)
|
||||
continue;
|
||||
|
||||
if (tag != OF_DT_PROP)
|
||||
return -EINVAL;
|
||||
|
||||
sz = be32_to_cpu(*(u32 *) p);
|
||||
p += 4;
|
||||
|
||||
v = be32_to_cpu(*(u32 *) p);
|
||||
v -= off;
|
||||
*(u32 *) p = cpu_to_be32(v); /* move down */
|
||||
p += 4;
|
||||
|
||||
p = (u8 *) _ALIGN((unsigned long)p + sz, 4);
|
||||
}
|
||||
|
||||
/* fix sizes */
|
||||
p = (char *)cxt->bph;
|
||||
sz = (cxt->pstr_begin + cxt->strings_size) - p;
|
||||
sz1 = _ALIGN(sz, 16); /* align at 16 bytes */
|
||||
if (sz != sz1)
|
||||
memset(p + sz, 0, sz1 - sz);
|
||||
bph->totalsize = cpu_to_be32(sz1);
|
||||
bph->off_dt_struct = cpu_to_be32(cxt->p_begin - p);
|
||||
bph->off_dt_strings = cpu_to_be32(cxt->pstr_begin - p);
|
||||
|
||||
/* the new strings start */
|
||||
cxt->pstr_begin = cxt->p_begin + cxt->struct_size;
|
||||
cxt->pstr = cxt->pstr_begin + cxt->strings_size;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**********************************************************************/
|
||||
/* update the boot param header with correct values */
|
||||
void ft_finalize_tree(struct ft_cxt *cxt) {
|
||||
struct boot_param_header *bph = cxt->bph;
|
||||
|
||||
bph->totalsize = cxt->p_end - (u8 *)bph;
|
||||
bph->off_dt_struct = cxt->p_start - (u8 *)bph;
|
||||
bph->off_dt_strings = cxt->p - (u8 *)bph;
|
||||
bph->dt_strings_size = cxt->p_end - cxt->p;
|
||||
}
|
||||
|
||||
static inline int isprint(int c)
|
||||
{
|
||||
|
|
@ -381,8 +307,8 @@ void ft_dump_blob(const void *bphp)
|
|||
}
|
||||
|
||||
if (tag != OF_DT_PROP) {
|
||||
fprintf(stderr, "%*s ** Unknown tag 0x%08x\n",
|
||||
depth * shift, "", tag);
|
||||
fprintf(stderr, "%*s ** Unknown tag 0x%08x at 0x%x\n",
|
||||
depth * shift, "", tag, --p);
|
||||
break;
|
||||
}
|
||||
sz = be32_to_cpu(*p++);
|
||||
|
|
@ -397,64 +323,15 @@ void ft_dump_blob(const void *bphp)
|
|||
|
||||
void ft_backtrack_node(struct ft_cxt *cxt)
|
||||
{
|
||||
if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE)
|
||||
return; /* XXX only for node */
|
||||
int i = 4;
|
||||
|
||||
cxt->p -= 4;
|
||||
}
|
||||
while (be32_to_cpu(*(u32 *) (cxt->p - i)) != OF_DT_END_NODE)
|
||||
i += 4;
|
||||
|
||||
/* note that the root node of the blob is "peeled" off */
|
||||
void ft_merge_blob(struct ft_cxt *cxt, void *blob)
|
||||
{
|
||||
struct boot_param_header *bph = (struct boot_param_header *)blob;
|
||||
u32 *p_struct = (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_struct));
|
||||
u32 *p_strings =
|
||||
(u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_strings));
|
||||
u32 tag, *p;
|
||||
char *s, *t;
|
||||
int depth, sz;
|
||||
memmove (cxt->p - i, cxt->p, cxt->p_end - cxt->p);
|
||||
|
||||
if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE)
|
||||
return; /* XXX only for node */
|
||||
|
||||
cxt->p -= 4;
|
||||
|
||||
depth = 0;
|
||||
p = p_struct;
|
||||
while ((tag = be32_to_cpu(*p++)) != OF_DT_END) {
|
||||
|
||||
/* printf("tag: 0x%08x (%d) - %d\n", tag, p - p_struct, depth); */
|
||||
|
||||
if (tag == OF_DT_BEGIN_NODE) {
|
||||
s = (char *)p;
|
||||
p = (u32 *) _ALIGN((unsigned long)p + strlen(s) + 1, 4);
|
||||
|
||||
if (depth++ > 0)
|
||||
ft_begin_node(cxt, s);
|
||||
|
||||
continue;
|
||||
}
|
||||
|
||||
if (tag == OF_DT_END_NODE) {
|
||||
ft_end_node(cxt);
|
||||
if (--depth == 0)
|
||||
break;
|
||||
continue;
|
||||
}
|
||||
|
||||
if (tag == OF_DT_NOP)
|
||||
continue;
|
||||
|
||||
if (tag != OF_DT_PROP)
|
||||
break;
|
||||
|
||||
sz = be32_to_cpu(*p++);
|
||||
s = (char *)p_strings + be32_to_cpu(*p++);
|
||||
t = (char *)p;
|
||||
p = (u32 *) _ALIGN((unsigned long)p + sz, 4);
|
||||
|
||||
ft_prop(cxt, s, t, sz);
|
||||
}
|
||||
cxt->p_end -= i;
|
||||
cxt->p -= i;
|
||||
}
|
||||
|
||||
void *ft_get_prop(void *bphp, const char *propname, int *szp)
|
||||
|
|
@ -521,9 +398,6 @@ void *ft_get_prop(void *bphp, const char *propname, int *szp)
|
|||
|
||||
/********************************************************************/
|
||||
|
||||
extern unsigned char oftree_dtb[];
|
||||
extern unsigned int oftree_dtb_len;
|
||||
|
||||
/* Function that returns a character from the environment */
|
||||
extern uchar(*env_get_char) (int);
|
||||
|
||||
|
|
@ -577,7 +451,7 @@ static const struct {
|
|||
};
|
||||
#endif
|
||||
|
||||
void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end)
|
||||
void ft_setup(void *blob, bd_t * bd, ulong initrd_start, ulong initrd_end)
|
||||
{
|
||||
u32 *p;
|
||||
int len;
|
||||
|
|
@ -600,20 +474,16 @@ void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_
|
|||
return;
|
||||
}
|
||||
|
||||
ft_begin(&cxt, blob, size);
|
||||
#ifdef DEBUG
|
||||
printf ("recieved oftree\n");
|
||||
ft_dump_blob(blob);
|
||||
#endif
|
||||
|
||||
ft_init_cxt(&cxt, blob);
|
||||
|
||||
if (initrd_start && initrd_end)
|
||||
ft_add_rsvmap(&cxt, initrd_start, initrd_end - initrd_start + 1);
|
||||
|
||||
ft_begin_tree(&cxt);
|
||||
|
||||
ft_begin_node(&cxt, "");
|
||||
|
||||
ft_end_node(&cxt);
|
||||
|
||||
/* copy RO tree */
|
||||
ft_merge_blob(&cxt, oftree_dtb);
|
||||
|
||||
/* back into root */
|
||||
ft_backtrack_node(&cxt);
|
||||
|
||||
|
|
@ -642,8 +512,8 @@ void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_
|
|||
#endif
|
||||
|
||||
ft_begin_node(&cxt, "chosen");
|
||||
|
||||
ft_prop_str(&cxt, "name", "chosen");
|
||||
|
||||
ft_prop_str(&cxt, "bootargs", getenv("bootargs"));
|
||||
ft_prop_int(&cxt, "linux,platform", 0x600); /* what is this? */
|
||||
if (initrd_start && initrd_end) {
|
||||
|
|
@ -659,11 +529,7 @@ void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_
|
|||
ft_end_node(&cxt); /* end root */
|
||||
|
||||
ft_end_tree(&cxt);
|
||||
|
||||
/*
|
||||
printf("merged OF-tree\n");
|
||||
ft_dump_blob(blob);
|
||||
*/
|
||||
ft_finalize_tree(&cxt);
|
||||
|
||||
#ifdef CONFIG_OF_HAS_BD_T
|
||||
/* paste the bd_t at the end of the flat tree */
|
||||
|
|
@ -712,11 +578,12 @@ void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_
|
|||
ft_board_setup(blob, bd);
|
||||
#endif
|
||||
|
||||
/*
|
||||
printf("final OF-tree\n");
|
||||
ft_dump_blob(blob);
|
||||
*/
|
||||
|
||||
}
|
||||
/* in case the size changed in the platform code */
|
||||
ft_finalize_tree(&cxt);
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("final OF-tree\n");
|
||||
ft_dump_blob(blob);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -30,7 +30,10 @@
|
|||
#include <command.h>
|
||||
#include <asm/cache.h>
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
#include <ft_build.h>
|
||||
#endif
|
||||
|
||||
|
||||
int checkcpu (void)
|
||||
{
|
||||
|
|
@ -227,3 +230,48 @@ int dma_xfer(void *dest, uint count, void *src) {
|
|||
return dma_check();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_OF_FLAT_TREE
|
||||
void
|
||||
ft_cpu_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
u32 *p;
|
||||
ulong clock;
|
||||
int len;
|
||||
|
||||
clock = bd->bi_busfreq;
|
||||
p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
|
||||
if (p != NULL)
|
||||
*p = cpu_to_be32(clock);
|
||||
|
||||
p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
|
||||
if (p != NULL)
|
||||
*p = cpu_to_be32(clock);
|
||||
|
||||
p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
|
||||
if (p != NULL)
|
||||
*p = cpu_to_be32(clock);
|
||||
|
||||
#if defined(CONFIG_MPC85XX_TSEC1)
|
||||
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
|
||||
memcpy(p, bd->bi_enetaddr, 6);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_HAS_ETH1)
|
||||
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
|
||||
memcpy(p, bd->bi_enet1addr, 6);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_HAS_ETH2)
|
||||
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
|
||||
memcpy(p, bd->bi_enet2addr, 6);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_HAS_ETH3)
|
||||
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
|
||||
memcpy(p, bd->bi_enet3addr, 6);
|
||||
#endif
|
||||
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
||||
#ifdef CONFIG_CPM2
|
||||
static void config_8560_ioports (volatile immap_t * immr)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -32,17 +32,78 @@
|
|||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
static struct pci_controller *pci_hose;
|
||||
|
||||
void
|
||||
pci_mpc85xx_init(struct pci_controller *hose)
|
||||
pci_mpc85xx_init(struct pci_controller *board_hose)
|
||||
{
|
||||
u16 reg16;
|
||||
u32 dev;
|
||||
|
||||
volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
|
||||
volatile ccsr_pcix_t *pcix = &immap->im_pcix;
|
||||
volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2;
|
||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
||||
struct pci_controller * hose;
|
||||
|
||||
u16 reg16;
|
||||
pci_hose = board_hose;
|
||||
|
||||
hose = &pci_hose[0];
|
||||
|
||||
hose->first_busno = 0;
|
||||
hose->last_busno = 0xff;
|
||||
|
||||
pci_setup_indirect(hose,
|
||||
(CFG_IMMR+0x8000),
|
||||
(CFG_IMMR+0x8004));
|
||||
|
||||
/*
|
||||
* Hose scan.
|
||||
*/
|
||||
dev = PCI_BDF(hose->first_busno, 0, 0);
|
||||
pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
|
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
||||
pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
|
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register.
|
||||
*/
|
||||
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
|
||||
|
||||
if (!(gur->pordevsr & PORDEVSR_PCI)) {
|
||||
/* PCI-X init */
|
||||
if (CONFIG_SYS_CLK_FREQ < 66000000)
|
||||
printf("PCI-X will only work at 66 MHz\n");
|
||||
|
||||
reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
|
||||
| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
|
||||
pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
|
||||
}
|
||||
|
||||
pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
|
||||
pcix->potear1 = 0x00000000;
|
||||
pcix->powbar1 = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff;
|
||||
pcix->powbear1 = 0x00000000;
|
||||
pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
|
||||
POWAR_MEM_WRITE | POWAR_MEM_512M);
|
||||
|
||||
pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
|
||||
pcix->potear2 = 0x00000000;
|
||||
pcix->powbar2 = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff;
|
||||
pcix->powbear2 = 0x00000000;
|
||||
pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
|
||||
POWAR_IO_WRITE | POWAR_IO_1M);
|
||||
|
||||
pcix->pitar1 = 0x00000000;
|
||||
pcix->piwbar1 = 0x00000000;
|
||||
pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
|
||||
PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
|
||||
|
||||
pcix->powar3 = 0;
|
||||
pcix->powar4 = 0;
|
||||
pcix->piwar2 = 0;
|
||||
pcix->piwar3 = 0;
|
||||
|
||||
pci_set_region(hose->regions + 0,
|
||||
CFG_PCI1_MEM_BASE,
|
||||
CFG_PCI1_MEM_PHYS,
|
||||
|
|
@ -57,42 +118,8 @@ pci_mpc85xx_init(struct pci_controller *hose)
|
|||
|
||||
hose->region_count = 2;
|
||||
|
||||
pci_setup_indirect(hose,
|
||||
(CFG_IMMR+0x8000),
|
||||
(CFG_IMMR+0x8004));
|
||||
|
||||
pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
|
||||
pcix->potear1 = 0x00000000;
|
||||
pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
|
||||
pcix->powbear1 = 0x00000000;
|
||||
pcix->powar1 = 0x8004401c; /* 512M MEM space */
|
||||
|
||||
pcix->potar2 = 0x00000000;
|
||||
pcix->potear2 = 0x00000000;
|
||||
pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
|
||||
pcix->powbear2 = 0x00000000;
|
||||
pcix->powar2 = 0x80088017; /* 16M IO space */
|
||||
|
||||
pcix->pitar1 = 0x00000000;
|
||||
pcix->piwbar1 = 0x00000000;
|
||||
pcix->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem,
|
||||
* Snoop R/W, 2G */
|
||||
|
||||
/*
|
||||
* Hose scan.
|
||||
*/
|
||||
pci_register_hose(hose);
|
||||
|
||||
pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
|
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
||||
pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
|
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register.
|
||||
*/
|
||||
pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
|
||||
pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
|
||||
|
||||
#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
|
||||
/*
|
||||
* This is a SW workaround for an apparent HW problem
|
||||
|
|
@ -117,6 +144,94 @@ pci_mpc85xx_init(struct pci_controller *hose)
|
|||
#endif
|
||||
|
||||
hose->last_busno = pci_hose_scan(hose);
|
||||
|
||||
#ifdef CONFIG_MPC85XX_PCI2
|
||||
hose = &pci_hose[1];
|
||||
|
||||
hose->first_busno = pci_hose[0].last_busno + 1;
|
||||
hose->last_busno = 0xff;
|
||||
|
||||
pci_setup_indirect(hose,
|
||||
(CFG_IMMR+0x9000),
|
||||
(CFG_IMMR+0x9004));
|
||||
|
||||
dev = PCI_BDF(hose->first_busno, 0, 0);
|
||||
pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
|
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
||||
pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
|
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register.
|
||||
*/
|
||||
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
|
||||
|
||||
pcix2->potar1 = (CFG_PCI2_MEM_BASE >> 12) & 0x000fffff;
|
||||
pcix2->potear1 = 0x00000000;
|
||||
pcix2->powbar1 = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff;
|
||||
pcix2->powbear1 = 0x00000000;
|
||||
pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
|
||||
POWAR_MEM_WRITE | POWAR_MEM_512M);
|
||||
|
||||
pcix2->potar2 = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff;
|
||||
pcix2->potear2 = 0x00000000;
|
||||
pcix2->powbar2 = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff;
|
||||
pcix2->powbear2 = 0x00000000;
|
||||
pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
|
||||
POWAR_IO_WRITE | POWAR_IO_1M);
|
||||
|
||||
pcix2->pitar1 = 0x00000000;
|
||||
pcix2->piwbar1 = 0x00000000;
|
||||
pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
|
||||
PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
|
||||
|
||||
pcix2->powar3 = 0;
|
||||
pcix2->powar4 = 0;
|
||||
pcix2->piwar2 = 0;
|
||||
pcix2->piwar3 = 0;
|
||||
|
||||
pci_set_region(hose->regions + 0,
|
||||
CFG_PCI2_MEM_BASE,
|
||||
CFG_PCI2_MEM_PHYS,
|
||||
CFG_PCI2_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
pci_set_region(hose->regions + 1,
|
||||
CFG_PCI2_IO_BASE,
|
||||
CFG_PCI2_IO_PHYS,
|
||||
CFG_PCI2_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 2;
|
||||
|
||||
/*
|
||||
* Hose scan.
|
||||
*/
|
||||
pci_register_hose(hose);
|
||||
|
||||
hose->last_busno = pci_hose_scan(hose);
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_FLAT_TREE
|
||||
void
|
||||
ft_pci_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
u32 *p;
|
||||
int len;
|
||||
|
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
|
||||
if (p != NULL) {
|
||||
p[0] = pci_hose[0].first_busno;
|
||||
p[1] = pci_hose[0].last_busno;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MPC85XX_PCI2
|
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
|
||||
if (p != NULL) {
|
||||
p[0] = pci_hose[1].first_busno;
|
||||
p[1] = pci_hose[1].last_busno;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_OF_FLAT_TREE */
|
||||
#endif /* CONFIG_PCI */
|
||||
|
|
|
|||
|
|
@ -100,6 +100,9 @@ Updated 13-July-2004 Jon Loeliger
|
|||
SW7[1:4] = 0101 = 5 => 5 x 66 = 330 CCB Sysclk
|
||||
SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock
|
||||
|
||||
In order to use PCI-X (only in the first PCI slot. The one with
|
||||
the RIO connector), you need to set SW1[4] (config) to 1 (off).
|
||||
Also, configure the board to run PCI at 66 MHz.
|
||||
|
||||
2. MEMORY MAP TO WORK WITH LINUX KERNEL
|
||||
|
||||
|
|
|
|||
|
|
@ -187,7 +187,7 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
|
|||
} else {
|
||||
/* We don't support prefetchable memory for now, so disable */
|
||||
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
|
||||
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);
|
||||
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
|
||||
}
|
||||
|
||||
if (pci_io) {
|
||||
|
|
|
|||
|
|
@ -246,7 +246,6 @@ typedef struct ccsr_lbc {
|
|||
|
||||
/*
|
||||
* PCI Registers(0x8000-0x9000)
|
||||
* Omitting Reserved(0x9000-0x2_0000)
|
||||
*/
|
||||
typedef struct ccsr_pcix {
|
||||
uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */
|
||||
|
|
@ -309,9 +308,27 @@ typedef struct ccsr_pcix {
|
|||
uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */
|
||||
uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */
|
||||
uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */
|
||||
char res11[94688];
|
||||
uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */
|
||||
char res11[476];
|
||||
} ccsr_pcix_t;
|
||||
|
||||
#define PCIX_COMMAND 0x62
|
||||
#define POWAR_EN 0x80000000
|
||||
#define POWAR_IO_READ 0x00080000
|
||||
#define POWAR_MEM_READ 0x00040000
|
||||
#define POWAR_IO_WRITE 0x00008000
|
||||
#define POWAR_MEM_WRITE 0x00004000
|
||||
#define POWAR_MEM_512M 0x0000001c
|
||||
#define POWAR_IO_1M 0x00000013
|
||||
|
||||
#define PIWAR_EN 0x80000000
|
||||
#define PIWAR_PF 0x20000000
|
||||
#define PIWAR_LOCAL 0x00f00000
|
||||
#define PIWAR_READ_SNOOP 0x00050000
|
||||
#define PIWAR_WRITE_SNOOP 0x00005000
|
||||
#define PIWAR_MEM_2G 0x0000001e
|
||||
|
||||
|
||||
/*
|
||||
* L2 Cache Registers(0x2_0000-0x2_1000)
|
||||
*/
|
||||
|
|
@ -1572,6 +1589,8 @@ typedef struct ccsr_gur {
|
|||
char res15[61651];
|
||||
} ccsr_gur_t;
|
||||
|
||||
#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
|
||||
|
||||
typedef struct immap {
|
||||
ccsr_local_ecm_t im_local_ecm;
|
||||
ccsr_ddr_t im_ddr;
|
||||
|
|
@ -1579,6 +1598,8 @@ typedef struct immap {
|
|||
ccsr_duart_t im_duart;
|
||||
ccsr_lbc_t im_lbc;
|
||||
ccsr_pcix_t im_pcix;
|
||||
ccsr_pcix_t im_pcix2;
|
||||
char reserved[90112];
|
||||
ccsr_l2cache_t im_l2cache;
|
||||
ccsr_dma_t im_dma;
|
||||
ccsr_tsec_t im_tsec1;
|
||||
|
|
|
|||
|
|
@ -68,6 +68,10 @@
|
|||
* The board, however, can run at 66MHz. In any event, this value
|
||||
* must match the settings of some switches. Details can be found
|
||||
* in the README.mpc85xxads.
|
||||
*
|
||||
* XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
|
||||
* 33MHz to accommodate, based on a PCI pin.
|
||||
* Note that PCI-X won't work at 33MHz.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ
|
||||
|
|
@ -293,6 +297,21 @@
|
|||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_FLAT_TREE 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
/* maximum size of the flat tree (8K) */
|
||||
#define OF_FLAT_TREE_MAX_SIZE 8192
|
||||
|
||||
#define OF_CPU "PowerPC,8540@0"
|
||||
#define OF_SOC "soc8540@e0000000"
|
||||
#define OF_TBCLK (bd->bi_busfreq / 8)
|
||||
#define OF_STDOUT_PATH "/soc8540@e0000000/serial@4500"
|
||||
|
||||
#define CFG_64BIT_VSPRINTF 1
|
||||
#define CFG_64BIT_STRTOUL 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
|
|
@ -312,9 +331,10 @@
|
|||
#define CFG_PCI1_MEM_BASE 0x80000000
|
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
|
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI1_IO_BASE 0xe2000000
|
||||
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
|
||||
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||
|
||||
#define CFG_PCI1_IO_BASE 0x0
|
||||
#define CFG_PCI1_IO_PHYS 0xe2000000
|
||||
#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
|
|
|
|||
|
|
@ -308,6 +308,18 @@ extern unsigned long get_clock_freq(void);
|
|||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_FLAT_TREE 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
/* maximum size of the flat tree (8K) */
|
||||
#define OF_FLAT_TREE_MAX_SIZE 8192
|
||||
|
||||
#define OF_CPU "PowerPC,8541@0"
|
||||
#define OF_SOC "soc8541@e0000000"
|
||||
#define OF_TBCLK (bd->bi_busfreq / 8)
|
||||
#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600"
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
|
|
@ -323,32 +335,27 @@ extern unsigned long get_clock_freq(void);
|
|||
#define CFG_PCI1_MEM_BASE 0x80000000
|
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
|
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI1_IO_BASE 0xe2000000
|
||||
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
|
||||
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||
#define CFG_PCI1_IO_BASE 0x00000000
|
||||
#define CFG_PCI1_IO_PHYS 0xe2000000
|
||||
#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
|
||||
|
||||
#define CFG_PCI2_MEM_BASE 0xa0000000
|
||||
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
|
||||
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI2_IO_BASE 0xe3000000
|
||||
#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
|
||||
#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
|
||||
#define CFG_PCI2_IO_BASE 0x00000000
|
||||
#define CFG_PCI2_IO_PHYS 0xe2100000
|
||||
#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */
|
||||
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
#define CONFIG_MPC85XX_PCI2
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#undef CONFIG_EEPRO100
|
||||
#undef CONFIG_TULIP
|
||||
|
||||
#if !defined(CONFIG_PCI_PNP)
|
||||
#define PCI_ENET0_IOADDR 0xe0000000
|
||||
#define PCI_ENET0_MEMADDR 0xe0000000
|
||||
#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
|
||||
#endif
|
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
|
||||
|
||||
|
|
|
|||
|
|
@ -314,6 +314,18 @@ extern unsigned long get_clock_freq(void);
|
|||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_FLAT_TREE 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
/* maximum size of the flat tree (8K) */
|
||||
#define OF_FLAT_TREE_MAX_SIZE 8192
|
||||
|
||||
#define OF_CPU "PowerPC,8548@0"
|
||||
#define OF_SOC "soc8548@e0000000"
|
||||
#define OF_TBCLK (bd->bi_busfreq / 8)
|
||||
#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600"
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
|
|
@ -329,32 +341,27 @@ extern unsigned long get_clock_freq(void);
|
|||
#define CFG_PCI1_MEM_BASE 0x80000000
|
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
|
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI1_IO_BASE 0xe2000000
|
||||
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
|
||||
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||
#define CFG_PCI1_IO_BASE 0x00000000
|
||||
#define CFG_PCI1_IO_PHYS 0xe2000000
|
||||
#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
|
||||
|
||||
#define CFG_PCI2_MEM_BASE 0xa0000000
|
||||
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
|
||||
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI2_IO_BASE 0xe3000000
|
||||
#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
|
||||
#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
|
||||
#define CFG_PCI2_IO_BASE 0x00000000
|
||||
#define CFG_PCI2_IO_PHYS 0xe2100000
|
||||
#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
|
||||
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_85XX_PCI2
|
||||
|
||||
#undef CONFIG_EEPRO100
|
||||
#undef CONFIG_TULIP
|
||||
|
||||
#if !defined(CONFIG_PCI_PNP)
|
||||
#define PCI_ENET0_IOADDR 0xe0000000
|
||||
#define PCI_ENET0_MEMADDR 0xe0000000
|
||||
#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
|
||||
#endif
|
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
|
||||
|
||||
|
|
@ -374,7 +381,7 @@ extern unsigned long get_clock_freq(void);
|
|||
#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
|
||||
#define CONFIG_MPC85XX_TSEC3 1
|
||||
#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2"
|
||||
#define CONFIG_MPC85XX_TSEC4 1
|
||||
#undef CONFIG_MPC85XX_TSEC4
|
||||
#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3"
|
||||
#undef CONFIG_MPC85XX_FEC
|
||||
|
||||
|
|
|
|||
|
|
@ -308,6 +308,18 @@ extern unsigned long get_clock_freq(void);
|
|||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_FLAT_TREE 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
/* maximum size of the flat tree (8K) */
|
||||
#define OF_FLAT_TREE_MAX_SIZE 8192
|
||||
|
||||
#define OF_CPU "PowerPC,8555@0"
|
||||
#define OF_SOC "soc8555@e0000000"
|
||||
#define OF_TBCLK (bd->bi_busfreq / 8)
|
||||
#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600"
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
|
|
@ -323,33 +335,28 @@ extern unsigned long get_clock_freq(void);
|
|||
#define CFG_PCI1_MEM_BASE 0x80000000
|
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
|
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI1_IO_BASE 0xe2000000
|
||||
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
|
||||
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||
#define CFG_PCI1_IO_BASE 0x00000000
|
||||
#define CFG_PCI1_IO_PHYS 0xe2000000
|
||||
#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
|
||||
|
||||
#define CFG_PCI2_MEM_BASE 0xa0000000
|
||||
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
|
||||
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI2_IO_BASE 0xe3000000
|
||||
#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
|
||||
#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
|
||||
#define CFG_PCI2_IO_BASE 0x00000000
|
||||
#define CFG_PCI2_IO_PHYS 0xe2100000
|
||||
#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
|
||||
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_MPC85XX_PCI2
|
||||
|
||||
#undef CONFIG_EEPRO100
|
||||
#undef CONFIG_TULIP
|
||||
|
||||
#if !defined(CONFIG_PCI_PNP)
|
||||
#define PCI_ENET0_IOADDR 0xe0000000
|
||||
#define PCI_ENET0_MEMADDR 0xe0000000
|
||||
#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
|
||||
#endif
|
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
|
|
|||
|
|
@ -290,6 +290,18 @@
|
|||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_FLAT_TREE 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
/* maximum size of the flat tree (8K) */
|
||||
#define OF_FLAT_TREE_MAX_SIZE 8192
|
||||
|
||||
#define OF_CPU "PowerPC,8560@0"
|
||||
#define OF_SOC "soc8560@e0000000"
|
||||
#define OF_TBCLK (bd->bi_busfreq / 8)
|
||||
#define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500"
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
|
|
|
|||
|
|
@ -36,19 +36,18 @@ struct boot_param_header {
|
|||
|
||||
struct ft_cxt {
|
||||
struct boot_param_header *bph;
|
||||
int max_size; /* maximum size of tree */
|
||||
int overflow; /* set when this happens */
|
||||
u8 *p, *pstr, *pres; /* running pointers */
|
||||
u8 *p_begin, *pstr_begin, *pres_begin; /* starting pointers */
|
||||
u8 *p_anchor; /* start of constructed area */
|
||||
int struct_size, strings_size, res_size;
|
||||
u8 *p_rsvmap;
|
||||
u8 *p_start; /* pointer to beginning of dt_struct */
|
||||
u8 *p_end; /* pointer to end of dt_strings */
|
||||
u8 *p; /* pointer to end of dt_struct and beginning of dt_strings */
|
||||
};
|
||||
|
||||
void ft_begin_node(struct ft_cxt *cxt, const char *name);
|
||||
void ft_init_cxt(struct ft_cxt *cxt, void *blob);
|
||||
void ft_end_node(struct ft_cxt *cxt);
|
||||
|
||||
void ft_begin_tree(struct ft_cxt *cxt);
|
||||
int ft_end_tree(struct ft_cxt *cxt);
|
||||
void ft_end_tree(struct ft_cxt *cxt);
|
||||
void ft_finalize_tree(struct ft_cxt *cxt);
|
||||
|
||||
void ft_nop(struct ft_cxt *cxt);
|
||||
void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz);
|
||||
|
|
@ -57,14 +56,14 @@ void ft_prop_int(struct ft_cxt *cxt, const char *name, int val);
|
|||
void ft_begin(struct ft_cxt *cxt, void *blob, int max_size);
|
||||
void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size);
|
||||
|
||||
void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end);
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
void ft_board_setup(void *blob, bd_t *bd);
|
||||
#endif
|
||||
void ft_setup(void *blob, bd_t * bd, ulong initrd_start, ulong initrd_end);
|
||||
|
||||
void ft_dump_blob(const void *bphp);
|
||||
void ft_merge_blob(struct ft_cxt *cxt, void *blob);
|
||||
void *ft_get_prop(void *bphp, const char *propname, int *szp);
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
void ft_board_setup(void *blob, bd_t *bd);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -271,11 +271,14 @@
|
|||
#define PCI_AGP_SIZEOF 12
|
||||
|
||||
/* PCI-X registers */
|
||||
#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */+#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
|
||||
|
||||
#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
|
||||
#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
|
||||
#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
|
||||
#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
|
||||
#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
|
||||
|
||||
|
||||
/* Slot Identification */
|
||||
|
||||
#define PCI_SID_ESR 2 /* Expansion Slot Register */
|
||||
|
|
|
|||
Loading…
Reference in a new issue