mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-12 22:33:18 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts: arch/arm/include/asm/mach-types.h Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
commit
922d27b596
154 changed files with 11375 additions and 1798 deletions
|
@ -372,6 +372,7 @@ Stefan Roese <sr@denx.de>
|
|||
ebony PPC440GP
|
||||
glacier PPC460GT
|
||||
haleakala PPC405EXr
|
||||
icon PPC440SPe
|
||||
katmai PPC440SPe
|
||||
kilauea PPC405EX
|
||||
lwmon5 PPC440EPx
|
||||
|
|
2
MAKEALL
2
MAKEALL
|
@ -186,6 +186,7 @@ LIST_4xx=" \
|
|||
ADCIOP \
|
||||
alpr \
|
||||
AP1000 \
|
||||
APC405 \
|
||||
AR405 \
|
||||
arches \
|
||||
ASH405 \
|
||||
|
@ -223,6 +224,7 @@ LIST_4xx=" \
|
|||
hcu5 \
|
||||
HH405 \
|
||||
HUB405 \
|
||||
icon \
|
||||
intip \
|
||||
JSE \
|
||||
KAREF \
|
||||
|
|
15
Makefile
15
Makefile
|
@ -22,9 +22,9 @@
|
|||
#
|
||||
|
||||
VERSION = 2010
|
||||
PATCHLEVEL = 03
|
||||
PATCHLEVEL = 06
|
||||
SUBLEVEL =
|
||||
EXTRAVERSION =
|
||||
EXTRAVERSION = -rc1
|
||||
ifneq "$(SUBLEVEL)" ""
|
||||
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
|
||||
else
|
||||
|
@ -38,9 +38,9 @@ HOSTARCH := $(shell uname -m | \
|
|||
-e s/sun4u/sparc64/ \
|
||||
-e s/arm.*/arm/ \
|
||||
-e s/sa110/arm/ \
|
||||
-e s/powerpc/ppc/ \
|
||||
-e s/ppc64/ppc/ \
|
||||
-e s/macppc/ppc/)
|
||||
-e s/ppc64/powerpc/ \
|
||||
-e s/ppc/powerpc/ \
|
||||
-e s/macppc/powerpc/)
|
||||
|
||||
HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \
|
||||
sed -e 's/\(cygwin\).*/cygwin/')
|
||||
|
@ -313,7 +313,7 @@ $(obj)u-boot.ldr.srec: $(obj)u-boot.ldr
|
|||
$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ -I binary
|
||||
|
||||
$(obj)u-boot.img: $(obj)u-boot.bin
|
||||
./tools/mkimage -A $(ARCH) -T firmware -C none \
|
||||
$(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
|
||||
-a $(TEXT_BASE) -e 0 \
|
||||
-n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
|
||||
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
|
||||
|
@ -1357,6 +1357,9 @@ HH405_config: unconfig
|
|||
HUB405_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) powerpc ppc4xx hub405 esd
|
||||
|
||||
icon_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) powerpc ppc4xx icon mosaixtech
|
||||
|
||||
# Compact-Center(codename intip) & DevCon-Center use different U-Boot images
|
||||
intip_config \
|
||||
devconcenter_config: unconfig
|
||||
|
|
5
README
5
README
|
@ -3303,6 +3303,11 @@ o If both the SROM and the environment contain a MAC address, and the
|
|||
o If neither SROM nor the environment contain a MAC address, an error
|
||||
is raised.
|
||||
|
||||
If Ethernet drivers implement the 'write_hwaddr' function, valid MAC addresses
|
||||
will be programmed into hardware as part of the initialization process. This
|
||||
may be skipped by setting the appropriate 'ethmacskip' environment variable.
|
||||
The naming convention is as follows:
|
||||
"ethmacskip" (=>eth0), "eth1macskip" (=>eth1) etc.
|
||||
|
||||
Image Formats:
|
||||
==============
|
||||
|
|
2
arch/.gitignore
vendored
Normal file
2
arch/.gitignore
vendored
Normal file
|
@ -0,0 +1,2 @@
|
|||
/*/include/asm/arch
|
||||
/*/include/asm/proc
|
|
@ -151,7 +151,7 @@ void set_timer (ulong t)
|
|||
timestamp = time_to_tick(t);
|
||||
}
|
||||
|
||||
/* delay x useconds AND perserve advance timstamp value */
|
||||
/* delay x useconds AND preserve advance timestamp value */
|
||||
void __udelay (unsigned long usec)
|
||||
{
|
||||
unsigned long long tmp;
|
||||
|
|
|
@ -73,25 +73,25 @@ void set_timer (ulong t)
|
|||
timestamp = t;
|
||||
}
|
||||
|
||||
/* delay x useconds AND perserve advance timstamp value */
|
||||
/* delay x useconds AND preserve advance timestamp value */
|
||||
void __udelay (unsigned long usec)
|
||||
{
|
||||
ulong tmo, tmp;
|
||||
|
||||
if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
|
||||
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
|
||||
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
|
||||
tmo /= 1000; /* finish normalize. */
|
||||
} else { /* else small number, don't kill it prior to HZ multiply */
|
||||
if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
|
||||
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
|
||||
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
|
||||
tmo /= 1000; /* finish normalize. */
|
||||
} else { /* else small number, don't kill it prior to HZ multiply */
|
||||
tmo = usec * CONFIG_SYS_HZ;
|
||||
tmo /= (1000*1000);
|
||||
}
|
||||
|
||||
tmp = get_timer (0); /* get current timestamp */
|
||||
if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */
|
||||
if ( (tmo + tmp + 1) < tmp ) /* if setting this forward will roll time stamp */
|
||||
reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */
|
||||
else
|
||||
tmo += tmp; /* else, set advancing stamp wake up time */
|
||||
tmo += tmp; /* else, set advancing stamp wake up time */
|
||||
while (get_timer_masked () < tmo)/* loop till event */
|
||||
/*NOP*/;
|
||||
}
|
||||
|
@ -100,16 +100,16 @@ void reset_timer_masked (void)
|
|||
{
|
||||
/* reset time */
|
||||
lastinc = READ_TIMER; /* capture current incrementer value time */
|
||||
timestamp = 0; /* start "advancing" time stamp from 0 */
|
||||
timestamp = 0; /* start "advancing" time stamp from 0 */
|
||||
}
|
||||
|
||||
ulong get_timer_masked (void)
|
||||
{
|
||||
ulong now = READ_TIMER; /* current tick value */
|
||||
|
||||
if (now >= lastinc) /* normal mode (non roll) */
|
||||
if (now >= lastinc) /* normal mode (non roll) */
|
||||
timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */
|
||||
else /* we have rollover of incrementer */
|
||||
else /* we have rollover of incrementer */
|
||||
timestamp += (0xFFFFFFFF - lastinc) + now;
|
||||
lastinc = now;
|
||||
return timestamp;
|
||||
|
|
|
@ -155,8 +155,8 @@ void set_timer(ulong t)
|
|||
timestamp = t;
|
||||
}
|
||||
|
||||
/* delay x useconds AND perserve advance timstamp value */
|
||||
void udelay(unsigned long usec)
|
||||
/* delay x useconds AND preserve advance timestamp value */
|
||||
void __udelay(unsigned long usec)
|
||||
{
|
||||
long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
|
||||
unsigned long now, last = readl(&tmr->timer3_counter);
|
||||
|
|
|
@ -79,14 +79,14 @@ void set_timer (ulong t)
|
|||
timestamp = t;
|
||||
}
|
||||
|
||||
/* delay x useconds AND perserve advance timstamp value */
|
||||
/* delay x useconds AND preserve advance timestamp value */
|
||||
void __udelay (unsigned long usec)
|
||||
{
|
||||
ulong tmo, tmp;
|
||||
|
||||
if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
|
||||
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
|
||||
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
|
||||
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
|
||||
tmo /= 1000; /* finish normalize. */
|
||||
}else{ /* else small number, don't kill it prior to HZ multiply */
|
||||
tmo = usec * CONFIG_SYS_HZ;
|
||||
|
|
|
@ -108,14 +108,14 @@ void set_timer (ulong t)
|
|||
timestamp = t;
|
||||
}
|
||||
|
||||
/* delay x useconds AND perserve advance timstamp value */
|
||||
/* delay x useconds AND preserve advance timestamp value */
|
||||
void __udelay (unsigned long usec)
|
||||
{
|
||||
ulong tmo, tmp;
|
||||
|
||||
if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
|
||||
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
|
||||
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
|
||||
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
|
||||
tmo /= 1000; /* finish normalize. */
|
||||
}else{ /* else small number, don't kill it prior to HZ multiply */
|
||||
tmo = usec * CONFIG_SYS_HZ;
|
||||
|
|
|
@ -102,7 +102,7 @@ void set_timer(ulong t)
|
|||
timestamp = t;
|
||||
}
|
||||
|
||||
/* delay x useconds AND perserve advance timstamp value */
|
||||
/* delay x useconds AND preserve advance timestamp value */
|
||||
void __udelay(unsigned long usec)
|
||||
{
|
||||
unsigned long now, start, tmo;
|
||||
|
|
|
@ -2824,6 +2824,44 @@ extern unsigned int __machine_arch_type;
|
|||
#define MACH_TYPE_GINGER 2841
|
||||
#define MACH_TYPE_TNY_T3530 2842
|
||||
#define MACH_TYPE_PCA102 2843
|
||||
#define MACH_TYPE_SPADE 2844
|
||||
#define MACH_TYPE_MXC25_TOPAZ 2845
|
||||
#define MACH_TYPE_T5325 2846
|
||||
#define MACH_TYPE_GW2361 2847
|
||||
#define MACH_TYPE_ELOG 2848
|
||||
#define MACH_TYPE_INCOME 2849
|
||||
#define MACH_TYPE_BCM589X 2850
|
||||
#define MACH_TYPE_ETNA 2851
|
||||
#define MACH_TYPE_HAWKS 2852
|
||||
#define MACH_TYPE_MESON 2853
|
||||
#define MACH_TYPE_XSBASE255 2854
|
||||
#define MACH_TYPE_PVM2030 2855
|
||||
#define MACH_TYPE_MIOA502 2856
|
||||
#define MACH_TYPE_VVBOX_SDORIG2 2857
|
||||
#define MACH_TYPE_VVBOX_SDLITE2 2858
|
||||
#define MACH_TYPE_VVBOX_SDPRO4 2859
|
||||
#define MACH_TYPE_HTC_SPV_M700 2860
|
||||
#define MACH_TYPE_MX257SX 2861
|
||||
#define MACH_TYPE_GONI 2862
|
||||
#define MACH_TYPE_MSM8X55_SVLTE_FFA 2863
|
||||
#define MACH_TYPE_MSM8X55_SVLTE_SURF 2864
|
||||
#define MACH_TYPE_QUICKSTEP 2865
|
||||
#define MACH_TYPE_DMW96 2866
|
||||
#define MACH_TYPE_HAMMERHEAD 2867
|
||||
#define MACH_TYPE_TRIDENT 2868
|
||||
#define MACH_TYPE_LIGHTNING 2869
|
||||
#define MACH_TYPE_ICONNECT 2870
|
||||
#define MACH_TYPE_AUTOBOT 2871
|
||||
#define MACH_TYPE_COCONUT 2872
|
||||
#define MACH_TYPE_DURIAN 2873
|
||||
#define MACH_TYPE_CAYENNE 2874
|
||||
#define MACH_TYPE_FUJI 2875
|
||||
#define MACH_TYPE_SYNOLOGY_6282 2876
|
||||
#define MACH_TYPE_EM1SY 2877
|
||||
#define MACH_TYPE_M502 2878
|
||||
#define MACH_TYPE_MATRIX518 2879
|
||||
#define MACH_TYPE_TINY_GURNARD 2880
|
||||
#define MACH_TYPE_SPEAR1310 2881
|
||||
|
||||
#ifdef CONFIG_ARCH_EBSA110
|
||||
# ifdef machine_arch_type
|
||||
|
@ -23964,9 +24002,9 @@ extern unsigned int __machine_arch_type;
|
|||
# else
|
||||
# define machine_arch_type MACH_TYPE_MARVELL_NEWDB
|
||||
# endif
|
||||
# define machine_is_marvell_newdb() (machine_arch_type == MACH_TYPE_MARVELL_NEWDB)
|
||||
# define machine_is_dove_avng() (machine_arch_type == MACH_TYPE_MARVELL_NEWDB)
|
||||
#else
|
||||
# define machine_is_marvell_newdb() (0)
|
||||
# define machine_is_dove_avng() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_VANDIHUD
|
||||
|
@ -32616,9 +32654,9 @@ extern unsigned int __machine_arch_type;
|
|||
# else
|
||||
# define machine_arch_type MACH_TYPE_WHITESTONE
|
||||
# endif
|
||||
# define machine_is_whitestone() (machine_arch_type == MACH_TYPE_WHITESTONE)
|
||||
# define machine_is_htcwhitestone() (machine_arch_type == MACH_TYPE_WHITESTONE)
|
||||
#else
|
||||
# define machine_is_whitestone() (0)
|
||||
# define machine_is_htcwhitestone() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_AT91SAM9263NIT
|
||||
|
@ -35772,9 +35810,9 @@ extern unsigned int __machine_arch_type;
|
|||
# else
|
||||
# define machine_arch_type MACH_TYPE_LPC2
|
||||
# endif
|
||||
# define machine_is_lpc2() (machine_arch_type == MACH_TYPE_LPC2)
|
||||
# define machine_is_lpc_evo() (machine_arch_type == MACH_TYPE_LPC2)
|
||||
#else
|
||||
# define machine_is_lpc2() (0)
|
||||
# define machine_is_lpc_evo() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_OLYMPUS
|
||||
|
@ -36569,6 +36607,462 @@ extern unsigned int __machine_arch_type;
|
|||
# define machine_is_pca102() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_SPADE
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_SPADE
|
||||
# endif
|
||||
# define machine_is_spade() (machine_arch_type == MACH_TYPE_SPADE)
|
||||
#else
|
||||
# define machine_is_spade() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_MXC25_TOPAZ
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_MXC25_TOPAZ
|
||||
# endif
|
||||
# define machine_is_mxc25_topaz() (machine_arch_type == MACH_TYPE_MXC25_TOPAZ)
|
||||
#else
|
||||
# define machine_is_mxc25_topaz() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_T5325
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_T5325
|
||||
# endif
|
||||
# define machine_is_t5325() (machine_arch_type == MACH_TYPE_T5325)
|
||||
#else
|
||||
# define machine_is_t5325() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_GW2361
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_GW2361
|
||||
# endif
|
||||
# define machine_is_gw2361() (machine_arch_type == MACH_TYPE_GW2361)
|
||||
#else
|
||||
# define machine_is_gw2361() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_ELOG
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_ELOG
|
||||
# endif
|
||||
# define machine_is_elog() (machine_arch_type == MACH_TYPE_ELOG)
|
||||
#else
|
||||
# define machine_is_elog() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_INCOME
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_INCOME
|
||||
# endif
|
||||
# define machine_is_income() (machine_arch_type == MACH_TYPE_INCOME)
|
||||
#else
|
||||
# define machine_is_income() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_BCM589X
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_BCM589X
|
||||
# endif
|
||||
# define machine_is_bcm589x() (machine_arch_type == MACH_TYPE_BCM589X)
|
||||
#else
|
||||
# define machine_is_bcm589x() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_ETNA
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_ETNA
|
||||
# endif
|
||||
# define machine_is_etna() (machine_arch_type == MACH_TYPE_ETNA)
|
||||
#else
|
||||
# define machine_is_etna() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_HAWKS
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_HAWKS
|
||||
# endif
|
||||
# define machine_is_hawks() (machine_arch_type == MACH_TYPE_HAWKS)
|
||||
#else
|
||||
# define machine_is_hawks() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_MESON
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_MESON
|
||||
# endif
|
||||
# define machine_is_meson() (machine_arch_type == MACH_TYPE_MESON)
|
||||
#else
|
||||
# define machine_is_meson() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_XSBASE255
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_XSBASE255
|
||||
# endif
|
||||
# define machine_is_xsbase255() (machine_arch_type == MACH_TYPE_XSBASE255)
|
||||
#else
|
||||
# define machine_is_xsbase255() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_PVM2030
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_PVM2030
|
||||
# endif
|
||||
# define machine_is_pvm2030() (machine_arch_type == MACH_TYPE_PVM2030)
|
||||
#else
|
||||
# define machine_is_pvm2030() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_MIOA502
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_MIOA502
|
||||
# endif
|
||||
# define machine_is_mioa502() (machine_arch_type == MACH_TYPE_MIOA502)
|
||||
#else
|
||||
# define machine_is_mioa502() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_VVBOX_SDORIG2
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_VVBOX_SDORIG2
|
||||
# endif
|
||||
# define machine_is_vvbox_sdorig2() (machine_arch_type == MACH_TYPE_VVBOX_SDORIG2)
|
||||
#else
|
||||
# define machine_is_vvbox_sdorig2() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_VVBOX_SDLITE2
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_VVBOX_SDLITE2
|
||||
# endif
|
||||
# define machine_is_vvbox_sdlite2() (machine_arch_type == MACH_TYPE_VVBOX_SDLITE2)
|
||||
#else
|
||||
# define machine_is_vvbox_sdlite2() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_VVBOX_SDPRO4
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_VVBOX_SDPRO4
|
||||
# endif
|
||||
# define machine_is_vvbox_sdpro4() (machine_arch_type == MACH_TYPE_VVBOX_SDPRO4)
|
||||
#else
|
||||
# define machine_is_vvbox_sdpro4() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_HTC_SPV_M700
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_HTC_SPV_M700
|
||||
# endif
|
||||
# define machine_is_htc_spv_m700() (machine_arch_type == MACH_TYPE_HTC_SPV_M700)
|
||||
#else
|
||||
# define machine_is_htc_spv_m700() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_MX257SX
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_MX257SX
|
||||
# endif
|
||||
# define machine_is_mx257sx() (machine_arch_type == MACH_TYPE_MX257SX)
|
||||
#else
|
||||
# define machine_is_mx257sx() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_GONI
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_GONI
|
||||
# endif
|
||||
# define machine_is_goni() (machine_arch_type == MACH_TYPE_GONI)
|
||||
#else
|
||||
# define machine_is_goni() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_MSM8X55_SVLTE_FFA
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_MSM8X55_SVLTE_FFA
|
||||
# endif
|
||||
# define machine_is_msm8x55_svlte_ffa() (machine_arch_type == MACH_TYPE_MSM8X55_SVLTE_FFA)
|
||||
#else
|
||||
# define machine_is_msm8x55_svlte_ffa() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_MSM8X55_SVLTE_SURF
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_MSM8X55_SVLTE_SURF
|
||||
# endif
|
||||
# define machine_is_msm8x55_svlte_surf() (machine_arch_type == MACH_TYPE_MSM8X55_SVLTE_SURF)
|
||||
#else
|
||||
# define machine_is_msm8x55_svlte_surf() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_QUICKSTEP
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_QUICKSTEP
|
||||
# endif
|
||||
# define machine_is_quickstep() (machine_arch_type == MACH_TYPE_QUICKSTEP)
|
||||
#else
|
||||
# define machine_is_quickstep() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_DMW96
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_DMW96
|
||||
# endif
|
||||
# define machine_is_dmw96() (machine_arch_type == MACH_TYPE_DMW96)
|
||||
#else
|
||||
# define machine_is_dmw96() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_HAMMERHEAD
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_HAMMERHEAD
|
||||
# endif
|
||||
# define machine_is_hammerhead() (machine_arch_type == MACH_TYPE_HAMMERHEAD)
|
||||
#else
|
||||
# define machine_is_hammerhead() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_TRIDENT
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_TRIDENT
|
||||
# endif
|
||||
# define machine_is_trident() (machine_arch_type == MACH_TYPE_TRIDENT)
|
||||
#else
|
||||
# define machine_is_trident() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_LIGHTNING
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_LIGHTNING
|
||||
# endif
|
||||
# define machine_is_lightning() (machine_arch_type == MACH_TYPE_LIGHTNING)
|
||||
#else
|
||||
# define machine_is_lightning() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_ICONNECT
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_ICONNECT
|
||||
# endif
|
||||
# define machine_is_iconnect() (machine_arch_type == MACH_TYPE_ICONNECT)
|
||||
#else
|
||||
# define machine_is_iconnect() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_AUTOBOT
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_AUTOBOT
|
||||
# endif
|
||||
# define machine_is_autobot() (machine_arch_type == MACH_TYPE_AUTOBOT)
|
||||
#else
|
||||
# define machine_is_autobot() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_COCONUT
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_COCONUT
|
||||
# endif
|
||||
# define machine_is_coconut() (machine_arch_type == MACH_TYPE_COCONUT)
|
||||
#else
|
||||
# define machine_is_coconut() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_DURIAN
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_DURIAN
|
||||
# endif
|
||||
# define machine_is_durian() (machine_arch_type == MACH_TYPE_DURIAN)
|
||||
#else
|
||||
# define machine_is_durian() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_CAYENNE
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_CAYENNE
|
||||
# endif
|
||||
# define machine_is_cayenne() (machine_arch_type == MACH_TYPE_CAYENNE)
|
||||
#else
|
||||
# define machine_is_cayenne() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_FUJI
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_FUJI
|
||||
# endif
|
||||
# define machine_is_fuji() (machine_arch_type == MACH_TYPE_FUJI)
|
||||
#else
|
||||
# define machine_is_fuji() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_SYNOLOGY_6282
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_SYNOLOGY_6282
|
||||
# endif
|
||||
# define machine_is_synology_6282() (machine_arch_type == MACH_TYPE_SYNOLOGY_6282)
|
||||
#else
|
||||
# define machine_is_synology_6282() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_EM1SY
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_EM1SY
|
||||
# endif
|
||||
# define machine_is_em1sy() (machine_arch_type == MACH_TYPE_EM1SY)
|
||||
#else
|
||||
# define machine_is_em1sy() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_M502
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_M502
|
||||
# endif
|
||||
# define machine_is_m502() (machine_arch_type == MACH_TYPE_M502)
|
||||
#else
|
||||
# define machine_is_m502() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_MATRIX518
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_MATRIX518
|
||||
# endif
|
||||
# define machine_is_matrix518() (machine_arch_type == MACH_TYPE_MATRIX518)
|
||||
#else
|
||||
# define machine_is_matrix518() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_TINY_GURNARD
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_TINY_GURNARD
|
||||
# endif
|
||||
# define machine_is_tiny_gurnard() (machine_arch_type == MACH_TYPE_TINY_GURNARD)
|
||||
#else
|
||||
# define machine_is_tiny_gurnard() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_SPEAR1310
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_SPEAR1310
|
||||
# endif
|
||||
# define machine_is_spear1310() (machine_arch_type == MACH_TYPE_SPEAR1310)
|
||||
#else
|
||||
# define machine_is_spear1310() (0)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These have not yet been registered
|
||||
*/
|
||||
|
|
|
@ -16,3 +16,8 @@ int raise (int signum)
|
|||
printf("raise: Signal # %d caught\n", signum);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Dummy function to avoid linker complaints */
|
||||
void __aeabi_unwind_cpp_pr0(void)
|
||||
{
|
||||
};
|
||||
|
|
|
@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
|
|||
LIB = $(obj)lib$(CPU).a
|
||||
|
||||
START = start.o start16.o resetvec.o
|
||||
COBJS = serial.o interrupts.o cpu.o
|
||||
COBJS = interrupts.o cpu.o
|
||||
|
||||
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
|
|
|
@ -5,6 +5,9 @@
|
|||
* (C) Copyright 2002
|
||||
* Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
|
||||
*
|
||||
* Portions of this file are derived from the Linux kernel source
|
||||
* Copyright (C) 1991, 1992 Linus Torvalds
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
|
@ -32,12 +35,112 @@
|
|||
".hidden irq_"#x"\n" \
|
||||
".type irq_"#x", @function\n" \
|
||||
"irq_"#x":\n" \
|
||||
"pushl %ebp\n" \
|
||||
"movl %esp,%ebp\n" \
|
||||
"pusha\n" \
|
||||
"pushl $"#x"\n" \
|
||||
"jmp irq_common_entry\n"
|
||||
|
||||
/*
|
||||
* Volatile isn't enough to prevent the compiler from reordering the
|
||||
* read/write functions for the control registers and messing everything up.
|
||||
* A memory clobber would solve the problem, but would prevent reordering of
|
||||
* all loads stores around it, which can hurt performance. Solution is to
|
||||
* use a variable and mimic reads and writes to it to enforce serialization
|
||||
*/
|
||||
static unsigned long __force_order;
|
||||
|
||||
static inline unsigned long read_cr0(void)
|
||||
{
|
||||
unsigned long val;
|
||||
asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline unsigned long read_cr2(void)
|
||||
{
|
||||
unsigned long val;
|
||||
asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline unsigned long read_cr3(void)
|
||||
{
|
||||
unsigned long val;
|
||||
asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline unsigned long read_cr4(void)
|
||||
{
|
||||
unsigned long val;
|
||||
asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline unsigned long get_debugreg(int regno)
|
||||
{
|
||||
unsigned long val = 0; /* Damn you, gcc! */
|
||||
|
||||
switch (regno) {
|
||||
case 0:
|
||||
asm("mov %%db0, %0" :"=r" (val));
|
||||
break;
|
||||
case 1:
|
||||
asm("mov %%db1, %0" :"=r" (val));
|
||||
break;
|
||||
case 2:
|
||||
asm("mov %%db2, %0" :"=r" (val));
|
||||
break;
|
||||
case 3:
|
||||
asm("mov %%db3, %0" :"=r" (val));
|
||||
break;
|
||||
case 6:
|
||||
asm("mov %%db6, %0" :"=r" (val));
|
||||
break;
|
||||
case 7:
|
||||
asm("mov %%db7, %0" :"=r" (val));
|
||||
break;
|
||||
default:
|
||||
val = 0;
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
void dump_regs(struct pt_regs *regs)
|
||||
{
|
||||
unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
|
||||
unsigned long d0, d1, d2, d3, d6, d7;
|
||||
|
||||
printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
|
||||
(u16)regs->xcs, regs->eip, regs->eflags);
|
||||
|
||||
printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
|
||||
regs->eax, regs->ebx, regs->ecx, regs->edx);
|
||||
printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
|
||||
regs->esi, regs->edi, regs->ebp, regs->esp);
|
||||
printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
|
||||
(u16)regs->xds, (u16)regs->xes, (u16)regs->xfs, (u16)regs->xgs, (u16)regs->xss);
|
||||
|
||||
cr0 = read_cr0();
|
||||
cr2 = read_cr2();
|
||||
cr3 = read_cr3();
|
||||
cr4 = read_cr4();
|
||||
|
||||
printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
|
||||
cr0, cr2, cr3, cr4);
|
||||
|
||||
d0 = get_debugreg(0);
|
||||
d1 = get_debugreg(1);
|
||||
d2 = get_debugreg(2);
|
||||
d3 = get_debugreg(3);
|
||||
|
||||
printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
|
||||
d0, d1, d2, d3);
|
||||
|
||||
d6 = get_debugreg(6);
|
||||
d7 = get_debugreg(7);
|
||||
printf("DR6: %08lx DR7: %08lx\n",
|
||||
d6, d7);
|
||||
}
|
||||
|
||||
struct idt_entry {
|
||||
u16 base_low;
|
||||
u16 selector;
|
||||
|
@ -122,7 +225,7 @@ int disable_interrupts(void)
|
|||
}
|
||||
|
||||
/* IRQ Low-Level Service Routine */
|
||||
__isr__ irq_llsr(int ip, int seg, int irq)
|
||||
__isr__ irq_llsr(struct pt_regs *regs)
|
||||
{
|
||||
/*
|
||||
* For detailed description of each exception, refer to:
|
||||
|
@ -131,73 +234,92 @@ __isr__ irq_llsr(int ip, int seg, int irq)
|
|||
* Order Number: 253665-029US, November 2008
|
||||
* Table 6-1. Exceptions and Interrupts
|
||||
*/
|
||||
switch (irq) {
|
||||
switch (regs->orig_eax) {
|
||||
case 0x00:
|
||||
printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip);
|
||||
printf("Divide Error (Division by zero)\n");
|
||||
dump_regs(regs);
|
||||
while(1);
|
||||
break;
|
||||
case 0x01:
|
||||
printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip);
|
||||
printf("Debug Interrupt (Single step)\n");
|
||||
dump_regs(regs);
|
||||
break;
|
||||
case 0x02:
|
||||
printf("NMI Interrupt at %04x:%08x\n", seg, ip);
|
||||
printf("NMI Interrupt\n");
|
||||
dump_regs(regs);
|
||||
break;
|
||||
case 0x03:
|
||||
printf("Breakpoint at %04x:%08x\n", seg, ip);
|
||||
printf("Breakpoint\n");
|
||||
dump_regs(regs);
|
||||
break;
|
||||
case 0x04:
|
||||
printf("Overflow at %04x:%08x\n", seg, ip);
|
||||
printf("Overflow\n");
|
||||
dump_regs(regs);
|
||||
while(1);
|
||||
break;
|
||||
case 0x05:
|
||||
printf("BOUND Range Exceeded at %04x:%08x\n", seg, ip);
|
||||
printf("BOUND Range Exceeded\n");
|
||||
dump_regs(regs);
|
||||
while(1);
|
||||
break;
|
||||
case 0x06:
|
||||
printf("Invalid Opcode (UnDefined Opcode) at %04x:%08x\n", seg, ip);
|
||||
printf("Invalid Opcode (UnDefined Opcode)\n");
|
||||
dump_regs(regs);
|
||||
while(1);
|
||||
break;
|
||||
case 0x07:
|
||||
printf("Device Not Available (No Math Coprocessor) at %04x:%08x\n", seg, ip);
|
||||
printf("Device Not Available (No Math Coprocessor)\n");
|
||||
dump_regs(regs);
|
||||
while(1);
|
||||
break;
|
||||
case 0x08:
|
||||
printf("Double fault at %04x:%08x\n", seg, ip);
|
||||
printf("Double fault\n");
|
||||
dump_regs(regs);
|
||||
while(1);
|
||||
break;
|
||||
case 0x09:
|
||||
printf("Co-processor segment overrun at %04x:%08x\n", seg, ip);
|
||||
printf("Co-processor segment overrun\n");
|
||||
dump_regs(regs);
|
||||
while(1);
|
||||
break;
|
||||
case 0x0a:
|
||||
printf("Invalid TSS at %04x:%08x\n", seg, ip);
|
||||
printf("Invalid TSS\n");
|
||||
dump_regs(regs);
|
||||
break;
|
||||
case 0x0b:
|
||||
printf("Segment Not Present at %04x:%08x\n", seg, ip);
|
||||
printf("Segment Not Present\n");
|
||||
dump_regs(regs);
|
||||
while(1);
|
||||
break;
|
||||
case 0x0c:
|
||||
printf("Stack Segment Fault at %04x:%08x\n", seg, ip);
|
||||
printf("Stack Segment Fault\n");
|
||||
dump_regs(regs);
|
||||
while(1);
|
||||
break;
|
||||
case 0x0d:
|
||||
printf("General Protection at %04x:%08x\n", seg, ip);
|
||||
printf("General Protection\n");
|
||||
dump_regs(regs);
|
||||
break;
|
||||
case 0x0e:
|
||||
printf("Page fault at %04x:%08x\n", seg, ip);
|
||||
printf("Page fault\n");
|
||||
dump_regs(regs);
|
||||
while(1);
|
||||
break;
|
||||
case 0x0f:
|
||||
printf("Floating-Point Error (Math Fault) at %04x:%08x\n", seg, ip);
|
||||
printf("Floating-Point Error (Math Fault)\n");
|
||||
dump_regs(regs);
|
||||
break;
|
||||
case 0x10:
|
||||
printf("Alignment check at %04x:%08x\n", seg, ip);
|
||||
printf("Alignment check\n");
|
||||
dump_regs(regs);
|
||||
break;
|
||||
case 0x11:
|
||||
printf("Machine Check at %04x:%08x\n", seg, ip);
|
||||
printf("Machine Check\n");
|
||||
dump_regs(regs);
|
||||
break;
|
||||
case 0x12:
|
||||
printf("SIMD Floating-Point Exception at %04x:%08x\n", seg, ip);
|
||||
printf("SIMD Floating-Point Exception\n");
|
||||
dump_regs(regs);
|
||||
break;
|
||||
case 0x13:
|
||||
case 0x14:
|
||||
|
@ -212,12 +334,13 @@ __isr__ irq_llsr(int ip, int seg, int irq)
|
|||
case 0x1d:
|
||||
case 0x1e:
|
||||
case 0x1f:
|
||||
printf("Reserved Exception %d at %04x:%08x\n", irq, seg, ip);
|
||||
printf("Reserved Exception\n");
|
||||
dump_regs(regs);
|
||||
break;
|
||||
|
||||
default:
|
||||
/* Hardware or User IRQ */
|
||||
do_irq(irq);
|
||||
do_irq(regs->orig_eax);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -226,22 +349,45 @@ __isr__ irq_llsr(int ip, int seg, int irq)
|
|||
* fully relocatable code.
|
||||
* - The call to irq_llsr will be a relative jump
|
||||
* - The IRQ entries will be guaranteed to be in order
|
||||
* It's a bit annoying that we need to waste 3 bytes per interrupt entry
|
||||
* (total of 768 code bytes), but we MUST create a Stack Frame and this is
|
||||
* the easiest way I could do it. Maybe it can be made better later.
|
||||
* Interrupt entries are now very small (a push and a jump) but they are
|
||||
* now slower (all registers pushed on stack which provides complete
|
||||
* crash dumps in the low level handlers
|
||||
*/
|
||||
asm(".globl irq_common_entry\n" \
|
||||
".hidden irq_common_entry\n" \
|
||||
".type irq_common_entry, @function\n" \
|
||||
"irq_common_entry:\n" \
|
||||
"pushl $0\n" \
|
||||
"pushl $0\n" \
|
||||
"cld\n" \
|
||||
"pushl %gs\n" \
|
||||
"pushl %fs\n" \
|
||||
"pushl %es\n" \
|
||||
"pushl %ds\n" \
|
||||
"pushl %eax\n" \
|
||||
"pushl %ebp\n" \
|
||||
"pushl %edi\n" \
|
||||
"pushl %esi\n" \
|
||||
"pushl %edx\n" \
|
||||
"pushl %ecx\n" \
|
||||
"pushl %ebx\n" \
|
||||
"mov %esp, %eax\n" \
|
||||
"pushl %ebp\n" \
|
||||
"movl %esp,%ebp\n" \
|
||||
"pushl %eax\n" \
|
||||
"call irq_llsr\n" \
|
||||
"popl %eax\n" \
|
||||
"popl %eax\n" \
|
||||
"popl %eax\n" \
|
||||
"popa\n" \
|
||||
"leave\n"\
|
||||
"popl %ebx\n" \
|
||||
"popl %ecx\n" \
|
||||
"popl %edx\n" \
|
||||
"popl %esi\n" \
|
||||
"popl %edi\n" \
|
||||
"popl %ebp\n" \
|
||||
"popl %eax\n" \
|
||||
"popl %ds\n" \
|
||||
"popl %es\n" \
|
||||
"popl %fs\n" \
|
||||
"popl %gs\n" \
|
||||
"add $4, %esp\n" \
|
||||
"iret\n" \
|
||||
DECLARE_INTERRUPT(0) \
|
||||
DECLARE_INTERRUPT(1) \
|
||||
|
|
|
@ -44,24 +44,24 @@ void init_sc520(void)
|
|||
/* Set the UARTxCTL register at it's slower,
|
||||
* baud clock giving us a 1.8432 MHz reference
|
||||
*/
|
||||
sc520_mmcr->uart1ctl = 0x07;
|
||||
sc520_mmcr->uart2ctl = 0x07;
|
||||
writeb(0x07, &sc520_mmcr->uart1ctl);
|
||||
writeb(0x07, &sc520_mmcr->uart2ctl);
|
||||
|
||||
/* first set the timer pin mapping */
|
||||
sc520_mmcr->clksel = 0x72; /* no clock frequency selected, use 1.1892MHz */
|
||||
writeb(0x72, &sc520_mmcr->clksel); /* no clock frequency selected, use 1.1892MHz */
|
||||
|
||||
/* enable PCI bus arbitrer */
|
||||
sc520_mmcr->sysarbctl = 0x02; /* enable concurrent mode */
|
||||
writeb(0x02, &sc520_mmcr->sysarbctl); /* enable concurrent mode */
|
||||
|
||||
sc520_mmcr->sysarbmenb = 0x1f; /* enable external grants */
|
||||
sc520_mmcr->hbctl = 0x04; /* enable posted-writes */
|
||||
writeb(0x1f, &sc520_mmcr->sysarbmenb); /* enable external grants */
|
||||
writeb(0x04, &sc520_mmcr->hbctl); /* enable posted-writes */
|
||||
|
||||
if (CONFIG_SYS_SC520_HIGH_SPEED) {
|
||||
sc520_mmcr->cpuctl = 0x02; /* set it to 133 MHz and write back */
|
||||
writeb(0x02, &sc520_mmcr->cpuctl); /* set it to 133 MHz and write back */
|
||||
gd->cpu_clk = 133000000;
|
||||
printf("## CPU Speed set to 133MHz\n");
|
||||
} else {
|
||||
sc520_mmcr->cpuctl = 0x01; /* set it to 100 MHz and write back */
|
||||
writeb(0x01, &sc520_mmcr->cpuctl); /* set it to 100 MHz and write back */
|
||||
printf("## CPU Speed set to 100MHz\n");
|
||||
gd->cpu_clk = 100000000;
|
||||
}
|
||||
|
@ -74,7 +74,7 @@ void init_sc520(void)
|
|||
"loop 0b\n": : : "ecx");
|
||||
|
||||
/* turn on the SDRAM write buffer */
|
||||
sc520_mmcr->dbctl = 0x11;
|
||||
writeb(0x11, &sc520_mmcr->dbctl);
|
||||
|
||||
/* turn on the cache and disable write through */
|
||||
asm("movl %%cr0, %%eax\n"
|
||||
|
@ -88,6 +88,7 @@ unsigned long init_sc520_dram(void)
|
|||
|
||||
u32 dram_present=0;
|
||||
u32 dram_ctrl;
|
||||
|
||||
#ifdef CONFIG_SYS_SDRAM_DRCTMCTL
|
||||
/* these memory control registers are set up in the assember part,
|
||||
* in sc520_asm.S, during 'mem_init'. If we muck with them here,
|
||||
|
@ -97,7 +98,8 @@ unsigned long init_sc520_dram(void)
|
|||
* simply dictates it.
|
||||
*/
|
||||
#else
|
||||
int val;
|
||||
u8 tmp;
|
||||
u8 val;
|
||||
|
||||
int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY;
|
||||
int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE;
|
||||
|
@ -116,9 +118,10 @@ unsigned long init_sc520_dram(void)
|
|||
val = 3; /* 62.4us */
|
||||
}
|
||||
|
||||
sc520_mmcr->drcctl = (sc520_mmcr->drcctl & 0xcf) | (val<<4);
|
||||
tmp = (readb(&sc520_mmcr->drcctl) & 0xcf) | (val<<4);
|
||||
writeb(tmp, &sc520_mmcr->drcctl);
|
||||
|
||||
val = sc520_mmcr->drctmctl & 0xf0;
|
||||
val = readb(&sc520_mmcr->drctmctl) & 0xf0;
|
||||
|
||||
if (cas_precharge_delay==3) {
|
||||
val |= 0x04; /* 3T */
|
||||
|
@ -133,12 +136,12 @@ unsigned long init_sc520_dram(void)
|
|||
} else {
|
||||
val |= 1;
|
||||
}
|
||||
sc520_mmcr->drctmctl = val;
|
||||
writeb(val, &c520_mmcr->drctmctl);
|
||||
#endif
|
||||
|
||||
/* We read-back the configuration of the dram
|
||||
* controller that the assembly code wrote */
|
||||
dram_ctrl = sc520_mmcr->drcbendadr;
|
||||
dram_ctrl = readl(&sc520_mmcr->drcbendadr);
|
||||
|
||||
bd->bi_dram[0].start = 0;
|
||||
if (dram_ctrl & 0x80) {
|
||||
|
@ -191,7 +194,7 @@ void reset_cpu(ulong addr)
|
|||
{
|
||||
printf("Resetting using SC520 MMCR\n");
|
||||
/* Write a '1' to the SYS_RST of the RESCFG MMCR */
|
||||
sc520_mmcr->rescfg = 0x01;
|
||||
writeb(0x01, &sc520_mmcr->rescfg);
|
||||
|
||||
/* NOTREACHED */
|
||||
}
|
||||
|
|
|
@ -25,48 +25,85 @@
|
|||
* copyright is included below
|
||||
*/
|
||||
|
||||
/*
|
||||
* =============================================================================
|
||||
/* TITLE SIZER - Aspen DRAM Sizing Routine.
|
||||
* =============================================================================
|
||||
*
|
||||
* Copyright 1999 Advanced Micro Devices, Inc.
|
||||
* Copyright 1999 Advanced Micro Devices, Inc.
|
||||
* You may redistribute this program and/or modify this program under the terms
|
||||
* of the GNU General Public License as published by the Free Software Foundation;
|
||||
* either version 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is the property of Advanced Micro Devices, Inc (AMD) which
|
||||
* specifically grants the user the right to modify, use and distribute this
|
||||
* software provided this COPYRIGHT NOTICE is not removed or altered. All
|
||||
* other rights are reserved by AMD.
|
||||
* This program is distributed WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
|
||||
* WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY
|
||||
* OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF
|
||||
* THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE.
|
||||
* IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, LOSS OF INFORMAITON) ARISING OUT OF THE USE OF OR INABILITY
|
||||
* TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGES. BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR
|
||||
* LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
|
||||
* LIMITATION MAY NOT APPLY TO YOU.
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors that may appear in
|
||||
* the Materials nor any responsibility to support or update the Materials.
|
||||
* AMD retains the right to make changes to its test specifications at any
|
||||
* time, without notice.
|
||||
* THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY
|
||||
* OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF
|
||||
* THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE.
|
||||
* IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR INABILITY
|
||||
* TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGES. BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR
|
||||
* LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
|
||||
* LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* So that all may benefit from your experience, please report any problems
|
||||
* or suggestions about this software back to AMD. Please include your name,
|
||||
* company, telephone number, AMD product requiring support and question or
|
||||
* problem encountered.
|
||||
*
|
||||
* Advanced Micro Devices, Inc. Worldwide support and contact
|
||||
* Embedded Processor Division information available at:
|
||||
* Systems Engineering epd.support@amd.com
|
||||
* 5204 E. Ben White Blvd. -or-
|
||||
* Austin, TX 78741 http://www.amd.com/html/support/techsup.html
|
||||
* ============================================================================
|
||||
* AMD does not assume any responsibility for any errors that may appear in
|
||||
* the Materials nor any responsibility to support or update the Materials.
|
||||
* AMD retains the right to make changes to its test specifications at any
|
||||
* time, without notice.
|
||||
* ==============================================================================
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* AUTHOR : Buddy Fey - Original.
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* FILE : sizer.asm - SDRAM DIMM Sizing Algorithm
|
||||
*
|
||||
*
|
||||
*
|
||||
* FUNCTIONS : sizemem() - jumped to, not called. To be executed after
|
||||
* reset to determine the size of the SDRAM DIMMs. Initializes
|
||||
* the memory subsystem.
|
||||
*
|
||||
*
|
||||
* AUTHOR : Buddy Fey - Original.
|
||||
*
|
||||
*
|
||||
* DESCRIPTION : Performs sizing on SDRAM DIMMs on ASPEN processor.
|
||||
* NOTE: This is a small memory model version
|
||||
*
|
||||
*
|
||||
* INPUTS : BP contains return address offset
|
||||
* CACHE is assumed to be disabled.
|
||||
* The FS segment limit has already been set to big real mode
|
||||
* (full 32-bit addressing capability)
|
||||
*
|
||||
*
|
||||
* OUTPUTS : None
|
||||
*
|
||||
*
|
||||
* REG USE : ax,bx,cx,dx,di,si,bp, fs
|
||||
*
|
||||
*
|
||||
* REVISION : See PVCS info below
|
||||
*
|
||||
*
|
||||
* TEST PLAN CROSS REFERENCE:
|
||||
*
|
||||
*
|
||||
* $Workfile: $
|
||||
* $Revision: 1.2 $
|
||||
* $Date: 1999/09/22 12:49:33 $
|
||||
* $Author: chipf $
|
||||
* $Log: sizer.asm $
|
||||
* Revision 1.2 1999/09/22 12:49:33 chipf
|
||||
* Add legal header
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
|
@ -463,7 +500,7 @@ emptybank:
|
|||
/* just have your hardware desinger _GIVE_ you what you need here! */
|
||||
movl $DRCTMCTL, %edi
|
||||
movb $CONFIG_SYS_SDRAM_DRCTMCTL,%al
|
||||
movb (%edi), %al
|
||||
movb %al, (%edi)
|
||||
#else
|
||||
#if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T)
|
||||
/* set the CAS latency now since it is hard to do
|
||||
|
@ -498,48 +535,21 @@ bad_ram:
|
|||
|
||||
dram_done:
|
||||
|
||||
/* readback DRCBENDADR and return the number
|
||||
* of available ram bytes in %eax */
|
||||
|
||||
movl $DRCBENDADR, %edi /* DRAM ending address register */
|
||||
|
||||
movl (%edi), %eax
|
||||
movl %eax, %ecx
|
||||
andl $0x80000000, %ecx
|
||||
jz bank2
|
||||
andl $0x7f000000, %eax
|
||||
shrl $2, %eax
|
||||
movl %eax, %ebx
|
||||
|
||||
bank2: movl (%edi), %eax
|
||||
movl %eax, %ecx
|
||||
andl $0x00800000, %ecx
|
||||
jz bank1
|
||||
andl $0x007f0000, %eax
|
||||
shll $6, %eax
|
||||
movl %eax, %ebx
|
||||
|
||||
bank1: movl (%edi), %eax
|
||||
movl %eax, %ecx
|
||||
andl $0x00008000, %ecx
|
||||
jz bank0
|
||||
andl $0x00007f00, %eax
|
||||
shll $14, %eax
|
||||
movl %eax, %ebx
|
||||
|
||||
bank0: movl (%edi), %eax
|
||||
movl %eax, %ecx
|
||||
andl $0x00000080, %ecx
|
||||
jz done
|
||||
andl $0x0000007f, %eax
|
||||
shll $22, %eax
|
||||
movl %eax, %ebx
|
||||
|
||||
|
||||
done:
|
||||
movl %ebx, %eax
|
||||
|
||||
#if CONFIG_SYS_SDRAM_ECC_ENABLE
|
||||
/*
|
||||
* We are in the middle of an existing 'call' - Need to store the
|
||||
* existing return address before making another 'call'
|
||||
*/
|
||||
movl %ebp, %ebx
|
||||
|
||||
/* Get the memory size */
|
||||
movl $init_ecc, %ebp
|
||||
jmpl get_mem_size
|
||||
|
||||
init_ecc:
|
||||
/* Restore the orignal return address */
|
||||
movl %ebx, %ebp
|
||||
|
||||
/* A nominal memory test: just a byte at each address line */
|
||||
movl %eax, %ecx
|
||||
shrl $0x1, %ecx
|
||||
|
@ -576,6 +586,50 @@ set_ecc:
|
|||
mov $0x05, %al
|
||||
movb %al, (%edi)
|
||||
#endif
|
||||
|
||||
out:
|
||||
jmp *%ebp
|
||||
|
||||
/*
|
||||
* Read and decode the sc520 DRCBENDADR MMCR and return the number of
|
||||
* available ram bytes in %eax
|
||||
*/
|
||||
.globl get_mem_size
|
||||
get_mem_size:
|
||||
movl $DRCBENDADR, %edi /* DRAM ending address register */
|
||||
|
||||
bank0: movl (%edi), %eax
|
||||
movl %eax, %ecx
|
||||
andl $0x00000080, %ecx
|
||||
jz bank1
|
||||
andl $0x0000007f, %eax
|
||||
shll $22, %eax
|
||||
movl %eax, %ebx
|
||||
|
||||
bank1: movl (%edi), %eax
|
||||
movl %eax, %ecx
|
||||
andl $0x00008000, %ecx
|
||||
jz bank2
|
||||
andl $0x00007f00, %eax
|
||||
shll $14, %eax
|
||||
movl %eax, %ebx
|
||||
|
||||
bank2: movl (%edi), %eax
|
||||
movl %eax, %ecx
|
||||
andl $0x00800000, %ecx
|
||||
jz bank3
|
||||
andl $0x007f0000, %eax
|
||||
shll $6, %eax
|
||||
movl %eax, %ebx
|
||||
|
||||
bank3: movl (%edi), %eax
|
||||
movl %eax, %ecx
|
||||
andl $0x80000000, %ecx
|
||||
jz done
|
||||
andl $0x7f000000, %eax
|
||||
shrl $2, %eax
|
||||
movl %eax, %ebx
|
||||
|
||||
done:
|
||||
movl %ebx, %eax
|
||||
jmp *%ebp
|
||||
|
|
|
@ -25,7 +25,9 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <pci.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/pci.h>
|
||||
#include <asm/ic/pci.h>
|
||||
#include <asm/ic/sc520.h>
|
||||
|
||||
static struct {
|
||||
|
@ -63,6 +65,8 @@ int sc520_pci_ints[15] = {
|
|||
int pci_sc520_set_irq(int pci_pin, int irq)
|
||||
{
|
||||
int i;
|
||||
u8 tmpb;
|
||||
u16 tmpw;
|
||||
|
||||
# if 1
|
||||
printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
|
||||
|
@ -80,31 +84,34 @@ int pci_sc520_set_irq(int pci_pin, int irq)
|
|||
|
||||
/* PCI interrupt mapping (A through D)*/
|
||||
for (i=0; i<=3 ;i++) {
|
||||
if (sc520_mmcr->pci_int_map[i] == sc520_irq[irq].priority)
|
||||
sc520_mmcr->pci_int_map[i] = SC520_IRQ_DISABLED;
|
||||
if (readb(&sc520_mmcr->pci_int_map[i]) == sc520_irq[irq].priority)
|
||||
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]);
|
||||
}
|
||||
|
||||
/* GP IRQ interrupt mapping */
|
||||
for (i=0; i<=10 ;i++) {
|
||||
if (sc520_mmcr->gp_int_map[i] == sc520_irq[irq].priority)
|
||||
sc520_mmcr->gp_int_map[i] = SC520_IRQ_DISABLED;
|
||||
if (readb(&sc520_mmcr->gp_int_map[i]) == sc520_irq[irq].priority)
|
||||
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]);
|
||||
}
|
||||
|
||||
/* Set the trigger to level */
|
||||
sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] =
|
||||
sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] | sc520_irq[irq].level_bit;
|
||||
tmpb = readb(&sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
|
||||
tmpb |= sc520_irq[irq].level_bit;
|
||||
writeb(tmpb, &sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
|
||||
|
||||
|
||||
if (pci_pin < 4) {
|
||||
/* PCI INTA-INTD */
|
||||
/* route the interrupt */
|
||||
sc520_mmcr->pci_int_map[pci_pin] = sc520_irq[irq].priority;
|
||||
writeb(sc520_irq[irq].priority, &sc520_mmcr->pci_int_map[pci_pin]);
|
||||
} else {
|
||||
/* GPIRQ0-GPIRQ10 used for additional PCI INTS */
|
||||
sc520_mmcr->gp_int_map[pci_pin - 4] = sc520_irq[irq].priority;
|
||||
writeb(sc520_irq[irq].priority, &sc520_mmcr->gp_int_map[pci_pin - 4]);
|
||||
|
||||
/* also set the polarity in this case */
|
||||
sc520_mmcr->intpinpol = sc520_mmcr->intpinpol | (1 << (pci_pin-4));
|
||||
tmpw = readw(&sc520_mmcr->intpinpol);
|
||||
tmpw |= (1 << (pci_pin-4));
|
||||
writew(tmpw, &sc520_mmcr->intpinpol);
|
||||
}
|
||||
|
||||
/* register the pin */
|
||||
|
@ -118,43 +125,7 @@ void pci_sc520_init(struct pci_controller *hose)
|
|||
{
|
||||
hose->first_busno = 0;
|
||||
hose->last_busno = 0xff;
|
||||
|
||||
/* System memory space */
|
||||
pci_set_region(hose->regions + 0,
|
||||
SC520_PCI_MEMORY_BUS,
|
||||
SC520_PCI_MEMORY_PHYS,
|
||||
SC520_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
|
||||
|
||||
/* PCI memory space */
|
||||
pci_set_region(hose->regions + 1,
|
||||
SC520_PCI_MEM_BUS,
|
||||
SC520_PCI_MEM_PHYS,
|
||||
SC520_PCI_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* ISA/PCI memory space */
|
||||
pci_set_region(hose->regions + 2,
|
||||
SC520_ISA_MEM_BUS,
|
||||
SC520_ISA_MEM_PHYS,
|
||||
SC520_ISA_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* PCI I/O space */
|
||||
pci_set_region(hose->regions + 3,
|
||||
SC520_PCI_IO_BUS,
|
||||
SC520_PCI_IO_PHYS,
|
||||
SC520_PCI_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
/* ISA/PCI I/O space */
|
||||
pci_set_region(hose->regions + 4,
|
||||
SC520_ISA_IO_BUS,
|
||||
SC520_ISA_IO_PHYS,
|
||||
SC520_ISA_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 5;
|
||||
hose->region_count = pci_set_regions(hose);
|
||||
|
||||
pci_setup_type1(hose,
|
||||
SC520_REG_ADDR,
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
/* stuff specific for the sc520, but independent of implementation */
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/ic/ssi.h>
|
||||
#include <asm/ic/sc520.h>
|
||||
|
||||
|
@ -61,34 +62,34 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
|
|||
temp |= PHS_INV_ENB;
|
||||
}
|
||||
|
||||
sc520_mmcr->ssictl = temp;
|
||||
writeb(temp, &sc520_mmcr->ssictl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u8 ssi_txrx_byte(u8 data)
|
||||
{
|
||||
sc520_mmcr->ssixmit = data;
|
||||
while (sc520_mmcr->ssista & SSISTA_BSY);
|
||||
sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMITRCV;
|
||||
while (sc520_mmcr->ssista & SSISTA_BSY);
|
||||
writeb(data, &sc520_mmcr->ssixmit);
|
||||
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
|
||||
writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd);
|
||||
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
|
||||
|
||||
return sc520_mmcr->ssircv;
|
||||
return readb(&sc520_mmcr->ssircv);
|
||||
}
|
||||
|
||||
|
||||
void ssi_tx_byte(u8 data)
|
||||
{
|
||||
sc520_mmcr->ssixmit = data;
|
||||
while (sc520_mmcr->ssista & SSISTA_BSY);
|
||||
sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMIT;
|
||||
writeb(data, &sc520_mmcr->ssixmit);
|
||||
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
|
||||
writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd);
|
||||
}
|
||||
|
||||
u8 ssi_rx_byte(void)
|
||||
{
|
||||
while (sc520_mmcr->ssista & SSISTA_BSY);
|
||||
sc520_mmcr->ssicmd = SSICMD_CMD_SEL_RCV;
|
||||
while (sc520_mmcr->ssista & SSISTA_BSY);
|
||||
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
|
||||
writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd);
|
||||
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
|
||||
|
||||
return sc520_mmcr->ssircv;
|
||||
return readb(&sc520_mmcr->ssircv);
|
||||
}
|
||||
|
|
|
@ -24,13 +24,14 @@
|
|||
/* stuff specific for the sc520, but independent of implementation */
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/interrupt.h>
|
||||
#include <asm/ic/sc520.h>
|
||||
|
||||
void sc520_timer_isr(void)
|
||||
{
|
||||
/* Ack the GP Timer Interrupt */
|
||||
sc520_mmcr->gptmrsta = 0x02;
|
||||
writeb(0x02, &sc520_mmcr->gptmrsta);
|
||||
}
|
||||
|
||||
int timer_init(void)
|
||||
|
@ -42,43 +43,47 @@ int timer_init(void)
|
|||
irq_install_handler (0, timer_isr, NULL);
|
||||
|
||||
/* Map GP Timer 1 to Master PIC IR0 */
|
||||
sc520_mmcr->gp_tmr_int_map[1] = 0x01;
|
||||
writeb(0x01, &sc520_mmcr->gp_tmr_int_map[1]);
|
||||
|
||||
/* Disable GP Timers 1 & 2 - Allow configuration writes */
|
||||
sc520_mmcr->gptmr1ctl = 0x4000;
|
||||
sc520_mmcr->gptmr2ctl = 0x4000;
|
||||
writew(0x4000, &sc520_mmcr->gptmr1ctl);
|
||||
writew(0x4000, &sc520_mmcr->gptmr2ctl);
|
||||
|
||||
/* Reset GP Timers 1 & 2 */
|
||||
sc520_mmcr->gptmr1cnt = 0x0000;
|
||||
sc520_mmcr->gptmr2cnt = 0x0000;
|
||||
writew(0x0000, &sc520_mmcr->gptmr1cnt);
|
||||
writew(0x0000, &sc520_mmcr->gptmr2cnt);
|
||||
|
||||
/* Setup GP Timer 2 as a 100kHz (10us) prescaler */
|
||||
sc520_mmcr->gptmr2maxcmpa = 83;
|
||||
sc520_mmcr->gptmr2ctl = 0xc001;
|
||||
writew(83, &sc520_mmcr->gptmr2maxcmpa);
|
||||
writew(0xc001, &sc520_mmcr->gptmr2ctl);
|
||||
|
||||
/* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */
|
||||
sc520_mmcr->gptmr1maxcmpa = 100;
|
||||
sc520_mmcr->gptmr1ctl = 0xe009;
|
||||
writew(100, &sc520_mmcr->gptmr1maxcmpa);
|
||||
writew(0xe009, &sc520_mmcr->gptmr1ctl);
|
||||
|
||||
unmask_irq (0);
|
||||
|
||||
/* Clear the GP Timer 1 status register to get the show rolling*/
|
||||
sc520_mmcr->gptmrsta = 0x02;
|
||||
writeb(0x02, &sc520_mmcr->gptmrsta);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Allow boards to override udelay implementation */
|
||||
void __udelay(unsigned long usec)
|
||||
__attribute__((weak, alias("sc520_udelay")));
|
||||
|
||||
void sc520_udelay(unsigned long usec)
|
||||
{
|
||||
int m = 0;
|
||||
long u;
|
||||
long temp;
|
||||
|
||||
temp = sc520_mmcr->swtmrmilli;
|
||||
temp = sc520_mmcr->swtmrmicro;
|
||||
temp = readw(&sc520_mmcr->swtmrmilli);
|
||||
temp = readw(&sc520_mmcr->swtmrmicro);
|
||||
|
||||
do {
|
||||
m += sc520_mmcr->swtmrmilli;
|
||||
u = sc520_mmcr->swtmrmicro + (m * 1000);
|
||||
m += readw(&sc520_mmcr->swtmrmilli);
|
||||
u = readw(&sc520_mmcr->swtmrmicro) + (m * 1000);
|
||||
} while (u < usec);
|
||||
}
|
||||
|
|
|
@ -1,506 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Daniel Engström, Omicron Ceti AB, daniel@omicron.se
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
/*------------------------------------------------------------------------------+ */
|
||||
|
||||
/*
|
||||
* This source code is dual-licensed. You may use it under the terms of the
|
||||
* GNU General Public License version 2, or under the license below.
|
||||
*
|
||||
* This source code has been made available to you by IBM on an AS-IS
|
||||
* basis. Anyone receiving this source is licensed under IBM
|
||||
* copyrights to use it in any way he or she deems fit, including
|
||||
* copying it, modifying it, compiling it, and redistributing it either
|
||||
* with or without modifications. No license under IBM patents or
|
||||
* patent applications is to be implied by the copyright license.
|
||||
*
|
||||
* Any user of this software should understand that IBM cannot provide
|
||||
* technical support for this software and will not be responsible for
|
||||
* any consequences resulting from the use of this software.
|
||||
*
|
||||
* Any person who transfers this source code or any derivative work
|
||||
* must include the IBM copyright notice, this paragraph, and the
|
||||
* preceding two paragraphs in the transferred software.
|
||||
*
|
||||
* COPYRIGHT I B M CORPORATION 1995
|
||||
* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
|
||||
*/
|
||||
/*------------------------------------------------------------------------------- */
|
||||
|
||||
#include <common.h>
|
||||
#include <watchdog.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/ibmpc.h>
|
||||
|
||||
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#include <malloc.h>
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_RBR 0x00
|
||||
#define UART_THR 0x00
|
||||
#define UART_IER 0x01
|
||||
#define UART_IIR 0x02
|
||||
#define UART_FCR 0x02
|
||||
#define UART_LCR 0x03
|
||||
#define UART_MCR 0x04
|
||||
#define UART_LSR 0x05
|
||||
#define UART_MSR 0x06
|
||||
#define UART_SCR 0x07
|
||||
#define UART_DLL 0x00
|
||||
#define UART_DLM 0x01
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| Line Status Register.
|
||||
+-----------------------------------------------------------------------------*/
|
||||
#define asyncLSRDataReady1 0x01
|
||||
#define asyncLSROverrunError1 0x02
|
||||
#define asyncLSRParityError1 0x04
|
||||
#define asyncLSRFramingError1 0x08
|
||||
#define asyncLSRBreakInterrupt1 0x10
|
||||
#define asyncLSRTxHoldEmpty1 0x20
|
||||
#define asyncLSRTxShiftEmpty1 0x40
|
||||
#define asyncLSRRxFifoError1 0x80
|
||||
|
||||
|
||||
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| Fifo
|
||||
+-----------------------------------------------------------------------------*/
|
||||
typedef struct {
|
||||
char *rx_buffer;
|
||||
ulong rx_put;
|
||||
ulong rx_get;
|
||||
int cts;
|
||||
} serial_buffer_t;
|
||||
|
||||
volatile serial_buffer_t buf_info;
|
||||
static int serial_buffer_active=0;
|
||||
#endif
|
||||
|
||||
|
||||
static int serial_div(int baudrate)
|
||||
{
|
||||
|
||||
switch (baudrate) {
|
||||
case 1200:
|
||||
return 96;
|
||||
case 9600:
|
||||
return 12;
|
||||
case 19200:
|
||||
return 6;
|
||||
case 38400:
|
||||
return 3;
|
||||
case 57600:
|
||||
return 2;
|
||||
case 115200:
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 12;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Minimal serial functions needed to use one of the SMC ports
|
||||
* as serial console interface.
|
||||
*/
|
||||
|
||||
int serial_init(void)
|
||||
{
|
||||
volatile char val;
|
||||
int bdiv = serial_div(gd->baudrate);
|
||||
|
||||
outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */
|
||||
outb(bdiv, UART0_BASE + UART_DLL); /* set baudrate divisor */
|
||||
outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */
|
||||
outb(0x03, UART0_BASE + UART_LCR); /* clear DLAB; set 8 bits, no parity */
|
||||
outb(0x01, UART0_BASE + UART_FCR); /* enable FIFO */
|
||||
outb(0x0b, UART0_BASE + UART_MCR); /* Set DTR and RTS active */
|
||||
val = inb(UART0_BASE + UART_LSR); /* clear line status */
|
||||
val = inb(UART0_BASE + UART_RBR); /* read receive buffer */
|
||||
outb(0x00, UART0_BASE + UART_SCR); /* set scratchpad */
|
||||
outb(0x00, UART0_BASE + UART_IER); /* set interrupt enable reg */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void serial_setbrg(void)
|
||||
{
|
||||
unsigned short bdiv;
|
||||
|
||||
bdiv = serial_div(gd->baudrate);
|
||||
|
||||
outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */
|
||||
outb(bdiv&0xff, UART0_BASE + UART_DLL); /* set baudrate divisor */
|
||||
outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */
|
||||
outb(0x03, UART0_BASE + UART_LCR); /* clear DLAB; set 8 bits, no parity */
|
||||
}
|
||||
|
||||
|
||||
void serial_putc(const char c)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (c == '\n')
|
||||
serial_putc ('\r');
|
||||
|
||||
/* check THRE bit, wait for transmiter available */
|
||||
for (i = 1; i < 3500; i++) {
|
||||
if ((inb (UART0_BASE + UART_LSR) & 0x20) == 0x20) {
|
||||
break;
|
||||
}
|
||||
udelay(100);
|
||||
}
|
||||
outb(c, UART0_BASE + UART_THR); /* put character out */
|
||||
}
|
||||
|
||||
|
||||
void serial_puts(const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
serial_putc(*s++);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
int serial_getc(void)
|
||||
{
|
||||
unsigned char status = 0;
|
||||
|
||||
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
if (serial_buffer_active) {
|
||||
return serial_buffered_getc();
|
||||
}
|
||||
#endif
|
||||
|
||||
while (1) {
|
||||
#if defined(CONFIG_HW_WATCHDOG)
|
||||
WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */
|
||||
#endif /* CONFIG_HW_WATCHDOG */
|
||||
status = inb(UART0_BASE + UART_LSR);
|
||||
if ((status & asyncLSRDataReady1) != 0x0) {
|
||||
break;
|
||||
}
|
||||
if ((status & ( asyncLSRFramingError1 |
|
||||
asyncLSROverrunError1 |
|
||||
asyncLSRParityError1 |
|
||||
asyncLSRBreakInterrupt1 )) != 0) {
|
||||
outb(asyncLSRFramingError1 |
|
||||
asyncLSROverrunError1 |
|
||||
asyncLSRParityError1 |
|
||||
asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR);
|
||||
}
|
||||
}
|
||||
return (0x000000ff & (int) inb (UART0_BASE));
|
||||
}
|
||||
|
||||
|
||||
int serial_tstc(void)
|
||||
{
|
||||
unsigned char status;
|
||||
|
||||
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
if (serial_buffer_active) {
|
||||
return serial_buffered_tstc();
|
||||
}
|
||||
#endif
|
||||
|
||||
status = inb(UART0_BASE + UART_LSR);
|
||||
if ((status & asyncLSRDataReady1) != 0x0) {
|
||||
return (1);
|
||||
}
|
||||
if ((status & ( asyncLSRFramingError1 |
|
||||
asyncLSROverrunError1 |
|
||||
asyncLSRParityError1 |
|
||||
asyncLSRBreakInterrupt1 )) != 0) {
|
||||
outb(asyncLSRFramingError1 |
|
||||
asyncLSROverrunError1 |
|
||||
asyncLSRParityError1 |
|
||||
asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
|
||||
void serial_isr(void *arg)
|
||||
{
|
||||
int space;
|
||||
int c;
|
||||
int rx_put = buf_info.rx_put;
|
||||
|
||||
if (buf_info.rx_get <= rx_put) {
|
||||
space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - buf_info.rx_get);
|
||||
} else {
|
||||
space = buf_info.rx_get - rx_put;
|
||||
}
|
||||
|
||||
while (inb(UART0_BASE + UART_LSR) & 1) {
|
||||
c = inb(UART0_BASE);
|
||||
if (space) {
|
||||
buf_info.rx_buffer[rx_put++] = c;
|
||||
space--;
|
||||
|
||||
if (rx_put == buf_info.rx_get) {
|
||||
buf_info.rx_get++;
|
||||
if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) {
|
||||
buf_info.rx_get = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) {
|
||||
rx_put = 0;
|
||||
if (0 == buf_info.rx_get) {
|
||||
buf_info.rx_get = 1;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
|
||||
/* Stop flow by setting RTS inactive */
|
||||
outb(inb(UART0_BASE + UART_MCR) & (0xFF ^ 0x02),
|
||||
UART0_BASE + UART_MCR);
|
||||
}
|
||||
}
|
||||
buf_info.rx_put = rx_put;
|
||||
}
|
||||
|
||||
void serial_buffered_init(void)
|
||||
{
|
||||
serial_puts ("Switching to interrupt driven serial input mode.\n");
|
||||
buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
|
||||
buf_info.rx_put = 0;
|
||||
buf_info.rx_get = 0;
|
||||
|
||||
if (inb (UART0_BASE + UART_MSR) & 0x10) {
|
||||
serial_puts ("Check CTS signal present on serial port: OK.\n");
|
||||
buf_info.cts = 1;
|
||||
} else {
|
||||
serial_puts ("WARNING: CTS signal not present on serial port.\n");
|
||||
buf_info.cts = 0;
|
||||
}
|
||||
|
||||
irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
|
||||
serial_isr /*interrupt_handler_t *handler */ ,
|
||||
(void *) &buf_info /*void *arg */ );
|
||||
|
||||
/* Enable "RX Data Available" Interrupt on UART */
|
||||
/* outb(inb(UART0_BASE + UART_IER) |0x01, UART0_BASE + UART_IER); */
|
||||
outb(0x01, UART0_BASE + UART_IER);
|
||||
|
||||
/* Set DTR and RTS active, enable interrupts */
|
||||
outb(inb (UART0_BASE + UART_MCR) | 0x0b, UART0_BASE + UART_MCR);
|
||||
|
||||
/* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */
|
||||
outb( /*(1 << 6) |*/ 1, UART0_BASE + UART_FCR);
|
||||
|
||||
serial_buffer_active = 1;
|
||||
}
|
||||
|
||||
void serial_buffered_putc (const char c)
|
||||
{
|
||||
int i;
|
||||
/* Wait for CTS */
|
||||
#if defined(CONFIG_HW_WATCHDOG)
|
||||
while (!(inb (UART0_BASE + UART_MSR) & 0x10))
|
||||
WATCHDOG_RESET ();
|
||||
#else
|
||||
if (buf_info.cts) {
|
||||
for (i=0;i<1000;i++) {
|
||||
if ((inb (UART0_BASE + UART_MSR) & 0x10)) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (i!=1000) {
|
||||
buf_info.cts = 0;
|
||||
}
|
||||
} else {
|
||||
if ((inb (UART0_BASE + UART_MSR) & 0x10)) {
|
||||
buf_info.cts = 1;
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
serial_putc (c);
|
||||
}
|
||||
|
||||
void serial_buffered_puts(const char *s)
|
||||
{
|
||||
serial_puts (s);
|
||||
}
|
||||
|
||||
int serial_buffered_getc(void)
|
||||
{
|
||||
int space;
|
||||
int c;
|
||||
int rx_get = buf_info.rx_get;
|
||||
int rx_put;
|
||||
|
||||
#if defined(CONFIG_HW_WATCHDOG)
|
||||
while (rx_get == buf_info.rx_put)
|
||||
WATCHDOG_RESET ();
|
||||
#else
|
||||
while (rx_get == buf_info.rx_put);
|
||||
#endif
|
||||
c = buf_info.rx_buffer[rx_get++];
|
||||
if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO) {
|
||||
rx_get = 0;
|
||||
}
|
||||
buf_info.rx_get = rx_get;
|
||||
|
||||
rx_put = buf_info.rx_put;
|
||||
if (rx_get <= rx_put) {
|
||||
space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
|
||||
} else {
|
||||
space = rx_get - rx_put;
|
||||
}
|
||||
if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
|
||||
/* Start flow by setting RTS active */
|
||||
outb(inb (UART0_BASE + UART_MCR) | 0x02, UART0_BASE + UART_MCR);
|
||||
}
|
||||
|
||||
return c;
|
||||
}
|
||||
|
||||
int serial_buffered_tstc(void)
|
||||
{
|
||||
return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
|
||||
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
/*
|
||||
AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
|
||||
number 0 or number 1
|
||||
- if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
|
||||
configuration has been already done
|
||||
- if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
|
||||
configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
|
||||
*/
|
||||
#if (CONFIG_KGDB_SER_INDEX & 2)
|
||||
void kgdb_serial_init(void)
|
||||
{
|
||||
volatile char val;
|
||||
bdiv = serial_div (CONFIG_KGDB_BAUDRATE);
|
||||
|
||||
/*
|
||||
* Init onboard 16550 UART
|
||||
*/
|
||||
outb(0x80, UART1_BASE + UART_LCR); /* set DLAB bit */
|
||||
outb((bdiv & 0xff), UART1_BASE + UART_DLL); /* set divisor for 9600 baud */
|
||||
outb((bdiv >> 8 ), UART1_BASE + UART_DLM); /* set divisor for 9600 baud */
|
||||
outb(0x03, UART1_BASE + UART_LCR); /* line control 8 bits no parity */
|
||||
outb(0x00, UART1_BASE + UART_FCR); /* disable FIFO */
|
||||
outb(0x00, UART1_BASE + UART_MCR); /* no modem control DTR RTS */
|
||||
val = inb(UART1_BASE + UART_LSR); /* clear line status */
|
||||
val = inb(UART1_BASE + UART_RBR); /* read receive buffer */
|
||||
outb(0x00, UART1_BASE + UART_SCR); /* set scratchpad */
|
||||
outb(0x00, UART1_BASE + UART_IER); /* set interrupt enable reg */
|
||||
}
|
||||
|
||||
|
||||
void putDebugChar(const char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
serial_putc ('\r');
|
||||
|
||||
outb(c, UART1_BASE + UART_THR); /* put character out */
|
||||
|
||||
/* check THRE bit, wait for transfer done */
|
||||
while ((inb(UART1_BASE + UART_LSR) & 0x20) != 0x20);
|
||||
}
|
||||
|
||||
|
||||
void putDebugStr(const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
serial_putc(*s++);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
int getDebugChar(void)
|
||||
{
|
||||
unsigned char status = 0;
|
||||
|
||||
while (1) {
|
||||
status = inb(UART1_BASE + UART_LSR);
|
||||
if ((status & asyncLSRDataReady1) != 0x0) {
|
||||
break;
|
||||
}
|
||||
if ((status & ( asyncLSRFramingError1 |
|
||||
asyncLSROverrunError1 |
|
||||
asyncLSRParityError1 |
|
||||
asyncLSRBreakInterrupt1 )) != 0) {
|
||||
outb(asyncLSRFramingError1 |
|
||||
asyncLSROverrunError1 |
|
||||
asyncLSRParityError1 |
|
||||
asyncLSRBreakInterrupt1, UART1_BASE + UART_LSR);
|
||||
}
|
||||
}
|
||||
return (0x000000ff & (int) inb(UART1_BASE));
|
||||
}
|
||||
|
||||
|
||||
void kgdb_interruptible(int yes)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
|
||||
|
||||
void kgdb_serial_init(void)
|
||||
{
|
||||
serial_printf ("[on serial] ");
|
||||
}
|
||||
|
||||
void putDebugChar(int c)
|
||||
{
|
||||
serial_putc (c);
|
||||
}
|
||||
|
||||
void putDebugStr(const char *str)
|
||||
{
|
||||
serial_puts (str);
|
||||
}
|
||||
|
||||
int getDebugChar(void)
|
||||
{
|
||||
return serial_getc ();
|
||||
}
|
||||
|
||||
void kgdb_interruptible(int yes)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif /* (CONFIG_KGDB_SER_INDEX & 2) */
|
||||
#endif
|
|
@ -33,7 +33,27 @@
|
|||
.type _start, @function
|
||||
.globl _i386boot_start
|
||||
_i386boot_start:
|
||||
/*
|
||||
* This is the fail safe 32-bit bootstrap entry point. The
|
||||
* following code is not executed from a cold-reset (actually, a
|
||||
* lot of it is, but from real-mode after cold reset. It is
|
||||
* repeated here to put the board into a state as close to cold
|
||||
* reset as necessary)
|
||||
*/
|
||||
cli
|
||||
cld
|
||||
|
||||
/* Turn of cache (this might require a 486-class CPU) */
|
||||
movl %cr0, %eax
|
||||
orl $0x60000000,%eax
|
||||
movl %eax, %cr0
|
||||
wbinvd
|
||||
|
||||
/* Tell 32-bit code it is being entered from an in-RAM copy */
|
||||
movw $0x0000, %bx
|
||||
_start:
|
||||
/* This is the 32-bit cold-reset entry point */
|
||||
|
||||
movl $0x18,%eax /* Load our segement registes, the
|
||||
* gdt have already been loaded by start16.S */
|
||||
movw %ax,%fs
|
||||
|
@ -42,6 +62,18 @@ _start:
|
|||
movw %ax,%es
|
||||
movw %ax,%ss
|
||||
|
||||
/* Clear the interupt vectors */
|
||||
lidt blank_idt_ptr
|
||||
|
||||
/*
|
||||
* Skip low-level board and memory initialization if not starting
|
||||
* from cold-reset. This allows us to do a fail safe boot-strap
|
||||
* into a new build of U-Boot from a known-good boot flash
|
||||
*/
|
||||
movw $0x0001, %ax
|
||||
cmpw %ax, %bx
|
||||
jne mem_init_ret
|
||||
|
||||
/* We call a few functions in the board support package
|
||||
* since we have no stack yet we'll have to use %ebp
|
||||
* to store the return address */
|
||||
|
@ -63,6 +95,58 @@ early_board_init_ret:
|
|||
jmp mem_init
|
||||
mem_init_ret:
|
||||
|
||||
/* fetch memory size (into %eax) */
|
||||
mov $get_mem_size_ret, %ebp
|
||||
jmp get_mem_size
|
||||
get_mem_size_ret:
|
||||
|
||||
/*
|
||||
* We are now in 'Flat Protected Mode' and we know how much memory
|
||||
* the board has. The (temporary) Global Descriptor Table is not
|
||||
* in a 'Safe' place (it is either in Flash which can be erased or
|
||||
* reprogrammed or in a fail-safe boot-strap image which could be
|
||||
* over-written).
|
||||
*
|
||||
* Move the final gdt to a safe place (top of RAM) and load it.
|
||||
* This is not a trivial excercise - the lgdt instruction does not
|
||||
* have a register operand (memory only) and we may well be
|
||||
* running from Flash, so self modifying code will not work here.
|
||||
* To overcome this, we copy a stub into upper memory along with
|
||||
* the GDT.
|
||||
*/
|
||||
|
||||
/* Reduce upper memory limit by (Stub + GDT Pointer + GDT) */
|
||||
subl $(end_gdt_setup - start_gdt_setup), %eax
|
||||
|
||||
/* Copy the GDT and Stub */
|
||||
movl $start_gdt_setup, %esi
|
||||
movl %eax, %edi
|
||||
movl $(end_gdt_setup - start_gdt_setup), %ecx
|
||||
shrl $2, %ecx
|
||||
cld
|
||||
rep movsl
|
||||
|
||||
/* write the lgdt 'parameter' */
|
||||
subl $(jmp_instr - start_gdt_setup - 4), %ebp
|
||||
addl %eax, %ebp
|
||||
movl $(gdt_ptr - start_gdt_setup), %ebx
|
||||
addl %eax, %ebx
|
||||
movl %ebx, (%ebp)
|
||||
|
||||
/* write the gdt address into the pointer */
|
||||
movl $(gdt_addr - start_gdt_setup), %ebp
|
||||
addl %eax, %ebp
|
||||
movl $(gdt - start_gdt_setup), %ebx
|
||||
addl %eax, %ebx
|
||||
movl %ebx, (%ebp)
|
||||
|
||||
/* Save the return address */
|
||||
movl $load_gdt_ret, %ebp
|
||||
|
||||
/* Load the new (safe) Global Descriptor Table */
|
||||
jmp *%eax
|
||||
|
||||
load_gdt_ret:
|
||||
/* Check we have enough memory for stack */
|
||||
movl $CONFIG_SYS_STACK_SIZE, %ecx
|
||||
cmpl %ecx, %eax
|
||||
|
@ -133,3 +217,56 @@ stack_ok:
|
|||
die: hlt
|
||||
jmp die
|
||||
hlt
|
||||
|
||||
blank_idt_ptr:
|
||||
.word 0 /* limit */
|
||||
.long 0 /* base */
|
||||
|
||||
.align 4
|
||||
start_gdt_setup:
|
||||
lgdt gdt_ptr
|
||||
jmp_instr:
|
||||
jmp *%ebp
|
||||
|
||||
.align 4
|
||||
gdt_ptr:
|
||||
.word 0x30 /* limit (48 bytes = 6 GDT entries) */
|
||||
gdt_addr:
|
||||
.long gdt /* base */
|
||||
|
||||
/* The GDT table ...
|
||||
*
|
||||
* Selector Type
|
||||
* 0x00 NULL
|
||||
* 0x08 Unused
|
||||
* 0x10 32bit code
|
||||
* 0x18 32bit data/stack
|
||||
* 0x20 16bit code
|
||||
* 0x28 16bit data/stack
|
||||
*/
|
||||
|
||||
.align 4
|
||||
gdt:
|
||||
.word 0, 0, 0, 0 /* NULL */
|
||||
.word 0, 0, 0, 0 /* unused */
|
||||
|
||||
.word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */
|
||||
.word 0 /* base address = 0 */
|
||||
.word 0x9B00 /* code read/exec */
|
||||
.word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */
|
||||
|
||||
.word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */
|
||||
.word 0x0 /* base address = 0 */
|
||||
.word 0x9300 /* data read/write */
|
||||
.word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */
|
||||
|
||||
.word 0xFFFF /* 64kb */
|
||||
.word 0 /* base address = 0 */
|
||||
.word 0x9b00 /* data read/write */
|
||||
.word 0x0010 /* granularity = 1 (+5th nibble of limit) */
|
||||
|
||||
.word 0xFFFF /* 64kb */
|
||||
.word 0 /* base address = 0 */
|
||||
.word 0x9300 /* data read/write */
|
||||
.word 0x0010 /* granularity = 1 (+5th nibble of limit) */
|
||||
end_gdt_setup:
|
||||
|
|
|
@ -44,11 +44,9 @@ board_init16_ret:
|
|||
movl %eax, %cr0
|
||||
wbinvd
|
||||
|
||||
/* load the descriptor tables */
|
||||
o32 cs lidt idt_ptr
|
||||
/* load the temporary Global Descriptor Table */
|
||||
o32 cs lgdt gdt_ptr
|
||||
|
||||
|
||||
/* Now, we enter protected mode */
|
||||
movl %cr0, %eax
|
||||
orl $1,%eax
|
||||
|
@ -57,6 +55,8 @@ o32 cs lgdt gdt_ptr
|
|||
/* Flush the prefetch queue */
|
||||
jmp ff
|
||||
ff:
|
||||
/* Tell 32-bit code it is being entered from hard-reset */
|
||||
movw $0x0001, %bx
|
||||
|
||||
/* Finally jump to the 32bit initialization code */
|
||||
movw $code32start, %ax
|
||||
|
@ -68,12 +68,13 @@ code32start:
|
|||
.long _start /* offset */
|
||||
.word 0x10 /* segment */
|
||||
|
||||
idt_ptr:
|
||||
.word 0 /* limit */
|
||||
.long 0 /* base */
|
||||
|
||||
/*
|
||||
* The following Global Descriptor Table is just enough to get us into
|
||||
* 'Flat Protected Mode' - It will be discarded as soon as the final
|
||||
* GDT is setup in a safe location in RAM
|
||||
*/
|
||||
gdt_ptr:
|
||||
.word 0x30 /* limit (48 bytes = 6 GDT entries) */
|
||||
.word 0x20 /* limit (32 bytes = 4 GDT entries) */
|
||||
.long BOOT_SEG + gdt /* base */
|
||||
|
||||
/* The GDT table ...
|
||||
|
@ -83,8 +84,6 @@ gdt_ptr:
|
|||
* 0x08 Unused
|
||||
* 0x10 32bit code
|
||||
* 0x18 32bit data/stack
|
||||
* 0x20 16bit code
|
||||
* 0x28 16bit data/stack
|
||||
*/
|
||||
|
||||
gdt:
|
||||
|
@ -100,13 +99,3 @@ gdt:
|
|||
.word 0x0 /* base address = 0 */
|
||||
.word 0x9300 /* data read/write */
|
||||
.word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */
|
||||
|
||||
.word 0xFFFF /* 64kb */
|
||||
.word 0 /* base address = 0 */
|
||||
.word 0x9b00 /* data read/write */
|
||||
.word 0x0010 /* granularity = 1 (+5th nibble of limit) */
|
||||
|
||||
.word 0xFFFF /* 64kb */
|
||||
.word 0 /* base address = 0 */
|
||||
.word 0x9300 /* data read/write */
|
||||
.word 0x0010 /* granularity = 1 (+5th nibble of limit) */
|
||||
|
|
120
arch/i386/include/asm/bootparam.h
Normal file
120
arch/i386/include/asm/bootparam.h
Normal file
|
@ -0,0 +1,120 @@
|
|||
#ifndef _ASM_X86_BOOTPARAM_H
|
||||
#define _ASM_X86_BOOTPARAM_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/screen_info.h>
|
||||
#include <linux/apm_bios.h>
|
||||
#include <linux/edd.h>
|
||||
#include <asm/e820.h>
|
||||
#include <asm/ist.h>
|
||||
#include <asm/video/edid.h>
|
||||
|
||||
/* setup data types */
|
||||
#define SETUP_NONE 0
|
||||
#define SETUP_E820_EXT 1
|
||||
|
||||
/* extensible setup data list node */
|
||||
struct setup_data {
|
||||
__u64 next;
|
||||
__u32 type;
|
||||
__u32 len;
|
||||
__u8 data[0];
|
||||
};
|
||||
|
||||
struct setup_header {
|
||||
__u8 setup_sects;
|
||||
__u16 root_flags;
|
||||
__u32 syssize;
|
||||
__u16 ram_size;
|
||||
#define RAMDISK_IMAGE_START_MASK 0x07FF
|
||||
#define RAMDISK_PROMPT_FLAG 0x8000
|
||||
#define RAMDISK_LOAD_FLAG 0x4000
|
||||
__u16 vid_mode;
|
||||
__u16 root_dev;
|
||||
__u16 boot_flag;
|
||||
__u16 jump;
|
||||
__u32 header;
|
||||
__u16 version;
|
||||
__u32 realmode_swtch;
|
||||
__u16 start_sys;
|
||||
__u16 kernel_version;
|
||||
__u8 type_of_loader;
|
||||
__u8 loadflags;
|
||||
#define LOADED_HIGH (1<<0)
|
||||
#define QUIET_FLAG (1<<5)
|
||||
#define KEEP_SEGMENTS (1<<6)
|
||||
#define CAN_USE_HEAP (1<<7)
|
||||
__u16 setup_move_size;
|
||||
__u32 code32_start;
|
||||
__u32 ramdisk_image;
|
||||
__u32 ramdisk_size;
|
||||
__u32 bootsect_kludge;
|
||||
__u16 heap_end_ptr;
|
||||
__u8 ext_loader_ver;
|
||||
__u8 ext_loader_type;
|
||||
__u32 cmd_line_ptr;
|
||||
__u32 initrd_addr_max;
|
||||
__u32 kernel_alignment;
|
||||
__u8 relocatable_kernel;
|
||||
__u8 _pad2[3];
|
||||
__u32 cmdline_size;
|
||||
__u32 hardware_subarch;
|
||||
__u64 hardware_subarch_data;
|
||||
__u32 payload_offset;
|
||||
__u32 payload_length;
|
||||
__u64 setup_data;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct sys_desc_table {
|
||||
__u16 length;
|
||||
__u8 table[14];
|
||||
};
|
||||
|
||||
struct efi_info {
|
||||
__u32 efi_loader_signature;
|
||||
__u32 efi_systab;
|
||||
__u32 efi_memdesc_size;
|
||||
__u32 efi_memdesc_version;
|
||||
__u32 efi_memmap;
|
||||
__u32 efi_memmap_size;
|
||||
__u32 efi_systab_hi;
|
||||
__u32 efi_memmap_hi;
|
||||
};
|
||||
|
||||
/* The so-called "zeropage" */
|
||||
struct boot_params {
|
||||
struct screen_info screen_info; /* 0x000 */
|
||||
struct apm_bios_info apm_bios_info; /* 0x040 */
|
||||
__u8 _pad2[4]; /* 0x054 */
|
||||
__u64 tboot_addr; /* 0x058 */
|
||||
struct ist_info ist_info; /* 0x060 */
|
||||
__u8 _pad3[16]; /* 0x070 */
|
||||
__u8 hd0_info[16]; /* obsolete! */ /* 0x080 */
|
||||
__u8 hd1_info[16]; /* obsolete! */ /* 0x090 */
|
||||
struct sys_desc_table sys_desc_table; /* 0x0a0 */
|
||||
__u8 _pad4[144]; /* 0x0b0 */
|
||||
struct edid_info edid_info; /* 0x140 */
|
||||
struct efi_info efi_info; /* 0x1c0 */
|
||||
__u32 alt_mem_k; /* 0x1e0 */
|
||||
__u32 scratch; /* Scratch field! */ /* 0x1e4 */
|
||||
__u8 e820_entries; /* 0x1e8 */
|
||||
__u8 eddbuf_entries; /* 0x1e9 */
|
||||
__u8 edd_mbr_sig_buf_entries; /* 0x1ea */
|
||||
__u8 _pad6[6]; /* 0x1eb */
|
||||
struct setup_header hdr; /* setup header */ /* 0x1f1 */
|
||||
__u8 _pad7[0x290-0x1f1-sizeof(struct setup_header)];
|
||||
__u32 edd_mbr_sig_buffer[EDD_MBR_SIG_MAX]; /* 0x290 */
|
||||
struct e820entry e820_map[E820MAX]; /* 0x2d0 */
|
||||
__u8 _pad8[48]; /* 0xcd0 */
|
||||
struct edd_info eddbuf[EDDMAXNR]; /* 0xd00 */
|
||||
__u8 _pad9[276]; /* 0xeec */
|
||||
} __attribute__((packed));
|
||||
|
||||
enum {
|
||||
X86_SUBARCH_PC = 0,
|
||||
X86_SUBARCH_LGUEST,
|
||||
X86_SUBARCH_XEN,
|
||||
X86_SUBARCH_MRST,
|
||||
X86_NR_SUBARCHS,
|
||||
};
|
||||
#endif /* _ASM_X86_BOOTPARAM_H */
|
155
arch/i386/include/asm/e820.h
Normal file
155
arch/i386/include/asm/e820.h
Normal file
|
@ -0,0 +1,155 @@
|
|||
#ifndef _ASM_X86_E820_H
|
||||
#define _ASM_X86_E820_H
|
||||
#define E820MAP 0x2d0 /* our map */
|
||||
#define E820MAX 128 /* number of entries in E820MAP */
|
||||
|
||||
/*
|
||||
* Legacy E820 BIOS limits us to 128 (E820MAX) nodes due to the
|
||||
* constrained space in the zeropage. If we have more nodes than
|
||||
* that, and if we've booted off EFI firmware, then the EFI tables
|
||||
* passed us from the EFI firmware can list more nodes. Size our
|
||||
* internal memory map tables to have room for these additional
|
||||
* nodes, based on up to three entries per node for which the
|
||||
* kernel was built: MAX_NUMNODES == (1 << CONFIG_NODES_SHIFT),
|
||||
* plus E820MAX, allowing space for the possible duplicate E820
|
||||
* entries that might need room in the same arrays, prior to the
|
||||
* call to sanitize_e820_map() to remove duplicates. The allowance
|
||||
* of three memory map entries per node is "enough" entries for
|
||||
* the initial hardware platform motivating this mechanism to make
|
||||
* use of additional EFI map entries. Future platforms may want
|
||||
* to allow more than three entries per node or otherwise refine
|
||||
* this size.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Odd: 'make headers_check' complains about numa.h if I try
|
||||
* to collapse the next two #ifdef lines to a single line:
|
||||
* #if defined(__KERNEL__) && defined(CONFIG_EFI)
|
||||
*/
|
||||
#ifdef __KERNEL__
|
||||
#ifdef CONFIG_EFI
|
||||
#include <linux/numa.h>
|
||||
#define E820_X_MAX (E820MAX + 3 * MAX_NUMNODES)
|
||||
#else /* ! CONFIG_EFI */
|
||||
#define E820_X_MAX E820MAX
|
||||
#endif
|
||||
#else /* ! __KERNEL__ */
|
||||
#define E820_X_MAX E820MAX
|
||||
#endif
|
||||
|
||||
#define E820NR 0x1e8 /* # entries in E820MAP */
|
||||
|
||||
#define E820_RAM 1
|
||||
#define E820_RESERVED 2
|
||||
#define E820_ACPI 3
|
||||
#define E820_NVS 4
|
||||
#define E820_UNUSABLE 5
|
||||
|
||||
/* reserved RAM used by kernel itself */
|
||||
#define E820_RESERVED_KERN 128
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/types.h>
|
||||
struct e820entry {
|
||||
__u64 addr; /* start of memory segment */
|
||||
__u64 size; /* size of memory segment */
|
||||
__u32 type; /* type of memory segment */
|
||||
} __attribute__((packed));
|
||||
|
||||
struct e820map {
|
||||
__u32 nr_map;
|
||||
struct e820entry map[E820_X_MAX];
|
||||
};
|
||||
|
||||
#define ISA_START_ADDRESS 0xa0000
|
||||
#define ISA_END_ADDRESS 0x100000
|
||||
|
||||
#define BIOS_BEGIN 0x000a0000
|
||||
#define BIOS_END 0x00100000
|
||||
|
||||
#ifdef __KERNEL__
|
||||
/* see comment in arch/x86/kernel/e820.c */
|
||||
extern struct e820map e820;
|
||||
extern struct e820map e820_saved;
|
||||
|
||||
extern unsigned long pci_mem_start;
|
||||
extern int e820_any_mapped(u64 start, u64 end, unsigned type);
|
||||
extern int e820_all_mapped(u64 start, u64 end, unsigned type);
|
||||
extern void e820_add_region(u64 start, u64 size, int type);
|
||||
extern void e820_print_map(char *who);
|
||||
extern int
|
||||
sanitize_e820_map(struct e820entry *biosmap, int max_nr_map, u32 *pnr_map);
|
||||
extern u64 e820_update_range(u64 start, u64 size, unsigned old_type,
|
||||
unsigned new_type);
|
||||
extern u64 e820_remove_range(u64 start, u64 size, unsigned old_type,
|
||||
int checktype);
|
||||
extern void update_e820(void);
|
||||
extern void e820_setup_gap(void);
|
||||
extern int e820_search_gap(unsigned long *gapstart, unsigned long *gapsize,
|
||||
unsigned long start_addr, unsigned long long end_addr);
|
||||
struct setup_data;
|
||||
extern void parse_e820_ext(struct setup_data *data, unsigned long pa_data);
|
||||
|
||||
#if defined(CONFIG_X86_64) || \
|
||||
(defined(CONFIG_X86_32) && defined(CONFIG_HIBERNATION))
|
||||
extern void e820_mark_nosave_regions(unsigned long limit_pfn);
|
||||
#else
|
||||
static inline void e820_mark_nosave_regions(unsigned long limit_pfn)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MEMTEST
|
||||
extern void early_memtest(unsigned long start, unsigned long end);
|
||||
#else
|
||||
static inline void early_memtest(unsigned long start, unsigned long end)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
extern unsigned long end_user_pfn;
|
||||
|
||||
extern u64 find_e820_area(u64 start, u64 end, u64 size, u64 align);
|
||||
extern u64 find_e820_area_size(u64 start, u64 *sizep, u64 align);
|
||||
extern void reserve_early(u64 start, u64 end, char *name);
|
||||
extern void reserve_early_overlap_ok(u64 start, u64 end, char *name);
|
||||
extern void free_early(u64 start, u64 end);
|
||||
extern void early_res_to_bootmem(u64 start, u64 end);
|
||||
extern u64 early_reserve_e820(u64 startt, u64 sizet, u64 align);
|
||||
|
||||
extern unsigned long e820_end_of_ram_pfn(void);
|
||||
extern unsigned long e820_end_of_low_ram_pfn(void);
|
||||
extern int e820_find_active_region(const struct e820entry *ei,
|
||||
unsigned long start_pfn,
|
||||
unsigned long last_pfn,
|
||||
unsigned long *ei_startpfn,
|
||||
unsigned long *ei_endpfn);
|
||||
extern void e820_register_active_regions(int nid, unsigned long start_pfn,
|
||||
unsigned long end_pfn);
|
||||
extern u64 e820_hole_size(u64 start, u64 end);
|
||||
extern void finish_e820_parsing(void);
|
||||
extern void e820_reserve_resources(void);
|
||||
extern void e820_reserve_resources_late(void);
|
||||
extern void setup_memory_map(void);
|
||||
extern char *default_machine_specific_memory_setup(void);
|
||||
|
||||
/*
|
||||
* Returns true iff the specified range [s,e) is completely contained inside
|
||||
* the ISA region.
|
||||
*/
|
||||
/*
|
||||
static inline bool is_ISA_range(u64 s, u64 e)
|
||||
{
|
||||
return s >= ISA_START_ADDRESS && e <= ISA_END_ADDRESS;
|
||||
}
|
||||
*/
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#ifdef __KERNEL__
|
||||
/* #include <linux/ioport.h> */
|
||||
|
||||
#define HIGH_MEMORY (1024*1024)
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* _ASM_X86_E820_H */
|
|
@ -24,6 +24,35 @@
|
|||
#ifndef _ASM_IC_SC520_PCI_H_
|
||||
#define _ASM_IC_SC520_PCI_H_ 1
|
||||
|
||||
/* bus mapping constants (used for PCI core initialization) */ /* bus mapping constants */
|
||||
#define SC520_REG_ADDR 0x00000cf8
|
||||
#define SC520_REG_DATA 0x00000cfc
|
||||
|
||||
#define SC520_ISA_MEM_PHYS 0x00000000
|
||||
#define SC520_ISA_MEM_BUS 0x00000000
|
||||
#define SC520_ISA_MEM_SIZE 0x01000000
|
||||
|
||||
#define SC520_ISA_IO_PHYS 0x00000000
|
||||
#define SC520_ISA_IO_BUS 0x00000000
|
||||
#define SC520_ISA_IO_SIZE 0x00001000
|
||||
|
||||
/* PCI I/O space from 0x1000 to 0xdfff
|
||||
* (make 0xe000-0xfdff available for stuff like PCCard boot) */
|
||||
#define SC520_PCI_IO_PHYS 0x00001000
|
||||
#define SC520_PCI_IO_BUS 0x00001000
|
||||
#define SC520_PCI_IO_SIZE 0x0000d000
|
||||
|
||||
/* system memory from 0x00000000 to 0x0fffffff */
|
||||
#define SC520_PCI_MEMORY_PHYS 0x00000000
|
||||
#define SC520_PCI_MEMORY_BUS 0x00000000
|
||||
#define SC520_PCI_MEMORY_SIZE 0x10000000
|
||||
|
||||
/* PCI bus memory from 0x10000000 to 0x26ffffff
|
||||
* (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */
|
||||
#define SC520_PCI_MEM_PHYS 0x10000000
|
||||
#define SC520_PCI_MEM_BUS 0x10000000
|
||||
#define SC520_PCI_MEM_SIZE 0x17000000
|
||||
|
||||
/* pin number used for PCI interrupt mappings */
|
||||
#define SC520_PCI_INTA 0
|
||||
#define SC520_PCI_INTB 1
|
||||
|
@ -44,6 +73,7 @@
|
|||
extern int sc520_pci_ints[];
|
||||
|
||||
void pci_sc520_init(struct pci_controller *hose);
|
||||
int pci_set_regions(struct pci_controller *hose);
|
||||
int pci_sc520_set_irq(int pci_pin, int irq);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
|
||||
void init_sc520(void);
|
||||
unsigned long init_sc520_dram(void);
|
||||
void sc520_udelay(unsigned long usec);
|
||||
|
||||
/* Memory mapped configuration registers */
|
||||
typedef struct sc520_mmcr {
|
||||
|
@ -292,35 +293,6 @@ extern volatile sc520_mmcr_t *sc520_mmcr;
|
|||
#define UART2_DIS 0x02 /* UART2 Disable */
|
||||
#define UART1_DIS 0x01 /* UART1 Disable */
|
||||
|
||||
/* bus mapping constants (used for PCI core initialization) */ /* bus mapping constants */
|
||||
#define SC520_REG_ADDR 0x00000cf8
|
||||
#define SC520_REG_DATA 0x00000cfc
|
||||
|
||||
#define SC520_ISA_MEM_PHYS 0x00000000
|
||||
#define SC520_ISA_MEM_BUS 0x00000000
|
||||
#define SC520_ISA_MEM_SIZE 0x01000000
|
||||
|
||||
#define SC520_ISA_IO_PHYS 0x00000000
|
||||
#define SC520_ISA_IO_BUS 0x00000000
|
||||
#define SC520_ISA_IO_SIZE 0x00001000
|
||||
|
||||
/* PCI I/O space from 0x1000 to 0xdfff
|
||||
* (make 0xe000-0xfdff available for stuff like PCCard boot) */
|
||||
#define SC520_PCI_IO_PHYS 0x00001000
|
||||
#define SC520_PCI_IO_BUS 0x00001000
|
||||
#define SC520_PCI_IO_SIZE 0x0000d000
|
||||
|
||||
/* system memory from 0x00000000 to 0x0fffffff */
|
||||
#define SC520_PCI_MEMORY_PHYS 0x00000000
|
||||
#define SC520_PCI_MEMORY_BUS 0x00000000
|
||||
#define SC520_PCI_MEMORY_SIZE 0x10000000
|
||||
|
||||
/* PCI bus memory from 0x10000000 to 0x26ffffff
|
||||
* (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */
|
||||
#define SC520_PCI_MEM_PHYS 0x10000000
|
||||
#define SC520_PCI_MEM_BUS 0x10000000
|
||||
#define SC520_PCI_MEM_SIZE 0x17000000
|
||||
|
||||
/* 0x28000000 - 0x3fffffff is used by the flash banks */
|
||||
|
||||
/* 0x40000000 - 0xffffffff is not adressable by the SC520 */
|
||||
|
|
1
arch/i386/include/asm/ioctl.h
Normal file
1
arch/i386/include/asm/ioctl.h
Normal file
|
@ -0,0 +1 @@
|
|||
#include <asm-generic/ioctl.h>
|
34
arch/i386/include/asm/ist.h
Normal file
34
arch/i386/include/asm/ist.h
Normal file
|
@ -0,0 +1,34 @@
|
|||
#ifndef _ASM_X86_IST_H
|
||||
#define _ASM_X86_IST_H
|
||||
|
||||
/*
|
||||
* Include file for the interface to IST BIOS
|
||||
* Copyright 2002 Andy Grover <andrew.grover@intel.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2, or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*/
|
||||
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct ist_info {
|
||||
__u32 signature;
|
||||
__u32 command;
|
||||
__u32 event;
|
||||
__u32 perf_level;
|
||||
};
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
extern struct ist_info ist_info;
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* _ASM_X86_IST_H */
|
|
@ -43,6 +43,8 @@ int cpu_init_interrupts(void);
|
|||
int board_init(void);
|
||||
int dram_init(void);
|
||||
|
||||
void setup_pcat_compatibility(void);
|
||||
|
||||
void isa_unmap_rom(u32 addr);
|
||||
u32 isa_map_rom(u32 bus_addr, int size);
|
||||
|
||||
|
|
1
arch/i386/include/asm/unaligned.h
Normal file
1
arch/i386/include/asm/unaligned.h
Normal file
|
@ -0,0 +1 @@
|
|||
#include <asm-generic/unaligned.h>
|
16
arch/i386/include/asm/video/edid.h
Normal file
16
arch/i386/include/asm/video/edid.h
Normal file
|
@ -0,0 +1,16 @@
|
|||
#ifndef __linux_video_edid_h__
|
||||
#define __linux_video_edid_h__
|
||||
|
||||
#if !defined(__KERNEL__) || defined(CONFIG_X86)
|
||||
|
||||
struct edid_info {
|
||||
unsigned char dummy[128];
|
||||
};
|
||||
|
||||
#ifdef __KERNEL__
|
||||
extern struct edid_info edid_info;
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __linux_video_edid_h__ */
|
|
@ -141,7 +141,7 @@ static void setvector(int vector, u16 segment, void *handler)
|
|||
|
||||
int bios_setup(void)
|
||||
{
|
||||
ulong i386boot_bios = (ulong)&_i386boot_bios;
|
||||
ulong i386boot_bios = (ulong)&_i386boot_bios + gd->reloc_off;
|
||||
ulong i386boot_bios_size = (ulong)&_i386boot_bios_size;
|
||||
|
||||
static int done=0;
|
||||
|
|
|
@ -37,6 +37,7 @@
|
|||
#include <malloc.h>
|
||||
#include <net.h>
|
||||
#include <ide.h>
|
||||
#include <serial.h>
|
||||
#include <asm/u-boot-i386.h>
|
||||
#include <elf.h>
|
||||
|
||||
|
@ -52,7 +53,9 @@ extern ulong _i386boot_rel_dyn_start;
|
|||
extern ulong _i386boot_rel_dyn_end;
|
||||
extern ulong _i386boot_bss_start;
|
||||
extern ulong _i386boot_bss_size;
|
||||
void ram_bootstrap (void *);
|
||||
|
||||
void ram_bootstrap (void *, ulong);
|
||||
|
||||
const char version_string[] =
|
||||
U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")";
|
||||
|
||||
|
@ -147,7 +150,6 @@ static void display_flash_config (ulong size)
|
|||
typedef int (init_fnc_t) (void);
|
||||
|
||||
init_fnc_t *init_sequence[] = {
|
||||
serial_init,
|
||||
cpu_init_r, /* basic cpu dependent setup */
|
||||
board_early_init_r, /* basic board dependent setup */
|
||||
dram_init, /* configure available RAM banks */
|
||||
|
@ -162,6 +164,7 @@ init_fnc_t *init_sequence[] = {
|
|||
NULL,
|
||||
};
|
||||
|
||||
static gd_t gd_data;
|
||||
gd_t *gd;
|
||||
|
||||
/*
|
||||
|
@ -174,21 +177,18 @@ void board_init_f (ulong stack_limit)
|
|||
Elf32_Rel *rel_dyn_start = (Elf32_Rel *)&_i386boot_rel_dyn_start;
|
||||
Elf32_Rel *rel_dyn_end = (Elf32_Rel *)&_i386boot_rel_dyn_end;
|
||||
void *bss_start = &_i386boot_bss_start;
|
||||
void *bss_size = &_i386boot_bss_size;
|
||||
ulong bss_size = (ulong)&_i386boot_bss_size;
|
||||
|
||||
size_t uboot_size;
|
||||
void *ram_start;
|
||||
ulong uboot_size;
|
||||
void *dest_addr;
|
||||
ulong rel_offset;
|
||||
Elf32_Rel *re;
|
||||
|
||||
void (*start_func)(void *);
|
||||
void (*start_func)(void *, ulong);
|
||||
|
||||
/* compiler optimization barrier needed for GCC >= 3.4 */
|
||||
__asm__ __volatile__("": : :"memory");
|
||||
|
||||
uboot_size = (size_t)u_boot_cmd_end - (size_t)text_start;
|
||||
ram_start = (void *)stack_limit - (uboot_size + (ulong)bss_size);
|
||||
rel_offset = text_start - ram_start;
|
||||
uboot_size = (ulong)u_boot_cmd_end - (ulong)text_start;
|
||||
dest_addr = (void *)stack_limit - (uboot_size + (ulong)bss_size);
|
||||
rel_offset = text_start - dest_addr;
|
||||
start_func = ram_bootstrap - rel_offset;
|
||||
|
||||
/* First stage CPU initialization */
|
||||
|
@ -200,10 +200,10 @@ void board_init_f (ulong stack_limit)
|
|||
hang();
|
||||
|
||||
/* Copy U-Boot into RAM */
|
||||
memcpy(ram_start, text_start, (size_t)uboot_size);
|
||||
memcpy(dest_addr, text_start, uboot_size);
|
||||
|
||||
/* Clear BSS */
|
||||
memset(bss_start - rel_offset, 0, (size_t)bss_size);
|
||||
memset(bss_start - rel_offset, 0, bss_size);
|
||||
|
||||
/* Perform relocation adjustments */
|
||||
for (re = rel_dyn_start; re < rel_dyn_end; re++)
|
||||
|
@ -213,27 +213,39 @@ void board_init_f (ulong stack_limit)
|
|||
*(ulong *)(re->r_offset - rel_offset) -= (Elf32_Addr)rel_offset;
|
||||
}
|
||||
|
||||
start_func(ram_start);
|
||||
|
||||
/* NOTREACHED - relocate_code() does not return */
|
||||
/* Enter the relocated U-Boot! */
|
||||
start_func(dest_addr, rel_offset);
|
||||
/* NOTREACHED - board_init_f() does not return */
|
||||
while(1);
|
||||
}
|
||||
|
||||
/*
|
||||
* All attempts to jump straight from board_init_f() to board_init_r()
|
||||
* have failed, hence this special 'bootstrap' function.
|
||||
* We cannot initialize gd_data in board_init_f() because we would be
|
||||
* attempting to write to flash (I have even tried using manual relocation
|
||||
* adjustments on pointers but it just won't work) and board_init_r() does
|
||||
* not have enough arguments to allow us to pass the relocation offset
|
||||
* straight up. This bootstrap function (which runs in RAM) is used to
|
||||
* setup gd_data in order to pass the relocation offset to the rest of
|
||||
* U-Boot.
|
||||
*
|
||||
* TODO: The compiler optimization barrier is intended to stop GCC from
|
||||
* optimizing this function into board_init_f(). It seems to work without
|
||||
* it, but I've left it in to be sure. I think also that the barrier in
|
||||
* board_init_r() is no longer needed, but left it in 'just in case'
|
||||
*/
|
||||
void ram_bootstrap (void *ram_start)
|
||||
void ram_bootstrap (void *dest_addr, ulong rel_offset)
|
||||
{
|
||||
static gd_t gd_data;
|
||||
|
||||
/* compiler optimization barrier needed for GCC >= 3.4 */
|
||||
__asm__ __volatile__("": : :"memory");
|
||||
|
||||
board_init_r(&gd_data, (ulong)ram_start);
|
||||
/* tell others: relocation done */
|
||||
gd_data.reloc_off = rel_offset;
|
||||
gd_data.flags |= GD_FLG_RELOC;
|
||||
|
||||
board_init_r(&gd_data, (ulong)dest_addr);
|
||||
}
|
||||
|
||||
void board_init_r(gd_t *id, ulong ram_start)
|
||||
void board_init_r(gd_t *id, ulong dest_addr)
|
||||
{
|
||||
char *s;
|
||||
int i;
|
||||
|
@ -247,16 +259,13 @@ void board_init_r(gd_t *id, ulong ram_start)
|
|||
/* compiler optimization barrier needed for GCC >= 3.4 */
|
||||
__asm__ __volatile__("": : :"memory");
|
||||
|
||||
memset (gd, 0, sizeof (gd_t));
|
||||
gd->bd = &bd_data;
|
||||
memset (gd->bd, 0, sizeof (bd_t));
|
||||
show_boot_progress(0x22);
|
||||
|
||||
gd->baudrate = CONFIG_BAUDRATE;
|
||||
|
||||
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
|
||||
|
||||
mem_malloc_init((((ulong)ram_start - CONFIG_SYS_MALLOC_LEN)+3)&~3,
|
||||
mem_malloc_init((((ulong)dest_addr - CONFIG_SYS_MALLOC_LEN)+3)&~3,
|
||||
CONFIG_SYS_MALLOC_LEN);
|
||||
|
||||
for (init_fnc_ptr = init_sequence, i=0; *init_fnc_ptr; ++init_fnc_ptr, i++) {
|
||||
|
@ -268,6 +277,9 @@ void board_init_r(gd_t *id, ulong ram_start)
|
|||
}
|
||||
show_boot_progress(0x23);
|
||||
|
||||
#ifdef CONFIG_SERIAL_MULTI
|
||||
serial_initialize();
|
||||
#endif
|
||||
/* configure available FLASH banks */
|
||||
size = flash_init();
|
||||
display_flash_config(size);
|
||||
|
@ -280,8 +292,10 @@ void board_init_r(gd_t *id, ulong ram_start)
|
|||
show_boot_progress(0x26);
|
||||
|
||||
|
||||
#ifdef CONFIG_CMD_NET
|
||||
/* IP Address */
|
||||
bd_data.bi_ip_addr = getenv_IPaddr ("ipaddr");
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
/*
|
||||
|
@ -420,10 +434,17 @@ void hang (void)
|
|||
unsigned long do_go_exec (ulong (*entry)(int, char *[]), int argc, char *argv[])
|
||||
{
|
||||
/*
|
||||
* TODO: Test this function - changed to fix compiler error.
|
||||
* Original code was:
|
||||
* return (entry >> 1) (argc, argv);
|
||||
* with a comment about Nios function pointers are address >> 1
|
||||
* x86 does not use a dedicated register to pass the pointer
|
||||
* to the global_data
|
||||
*/
|
||||
argv[-1] = (char *)gd;
|
||||
|
||||
return (entry) (argc, argv);
|
||||
}
|
||||
|
||||
void setup_pcat_compatibility(void)
|
||||
__attribute__((weak, alias("__setup_pcat_compatibility")));
|
||||
|
||||
void __setup_pcat_compatibility(void)
|
||||
{
|
||||
}
|
||||
|
|
|
@ -37,7 +37,7 @@ extern char realmode_enter;
|
|||
|
||||
int realmode_setup(void)
|
||||
{
|
||||
ulong i386boot_realmode = (ulong)&_i386boot_realmode;
|
||||
ulong i386boot_realmode = (ulong)&_i386boot_realmode + gd->reloc_off;
|
||||
ulong i386boot_realmode_size = (ulong)&_i386boot_realmode_size;
|
||||
|
||||
/* copy the realmode switch code */
|
||||
|
|
|
@ -34,6 +34,8 @@
|
|||
#include <asm/zimage.h>
|
||||
#include <asm/realmode.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <asm/bootparam.h>
|
||||
#include <asm/ic/sc520.h>
|
||||
|
||||
/*
|
||||
* Memory lay-out:
|
||||
|
@ -90,48 +92,56 @@ void *load_zimage(char *image, unsigned long kernel_size,
|
|||
int big_image;
|
||||
void *load_address;
|
||||
|
||||
struct setup_header *hdr = (struct setup_header *)(image + SETUP_SECTS_OFF);
|
||||
|
||||
setup_base = (void*)DEFAULT_SETUP_BASE; /* base address for real-mode segment */
|
||||
|
||||
if (KERNEL_MAGIC != *(u16*)(image + BOOT_FLAG_OFF)) {
|
||||
printf("Error: Invalid kernel magic (found 0x%04x, expected 0xaa55)\n",
|
||||
*(u16*)(image + BOOT_FLAG_OFF));
|
||||
if (KERNEL_MAGIC != hdr->boot_flag) {
|
||||
printf("Error: Invalid Boot Flag (found 0x%04x, expected 0x%04x)\n",
|
||||
hdr->boot_flag, KERNEL_MAGIC);
|
||||
return 0;
|
||||
} else {
|
||||
printf("Valid Boot Flag\n");
|
||||
}
|
||||
|
||||
|
||||
/* determine boot protocol version */
|
||||
if (KERNEL_V2_MAGIC == *(u32*)(image+HEADER_OFF)) {
|
||||
bootproto = *(u16*)(image+VERSION_OFF);
|
||||
if (KERNEL_V2_MAGIC == hdr->header) {
|
||||
printf("Magic signature found\n");
|
||||
|
||||
bootproto = hdr->version;
|
||||
} else {
|
||||
/* Very old kernel */
|
||||
printf("Magic signature not found\n");
|
||||
bootproto = 0x0100;
|
||||
}
|
||||
|
||||
/* determine size of setup */
|
||||
if (0 == *(u8*)(image + SETUP_SECTS_OFF)) {
|
||||
if (0 == hdr->setup_sects) {
|
||||
printf("Setup Sectors = 0 (defaulting to 4)\n");
|
||||
setup_size = 5 * 512;
|
||||
} else {
|
||||
setup_size = (*(u8*)(image + SETUP_SECTS_OFF) + 1) * 512;
|
||||
setup_size = (hdr->setup_sects + 1) * 512;
|
||||
}
|
||||
|
||||
printf("Setup Size = 0x%8.8lx\n", (ulong)setup_size);
|
||||
|
||||
if (setup_size > SETUP_MAX_SIZE) {
|
||||
printf("Error: Setup is too large (%d bytes)\n", setup_size);
|
||||
}
|
||||
|
||||
/* Determine image type */
|
||||
big_image = (bootproto >= 0x0200) && (*(u8*)(image + LOADFLAGS_OFF) & BIG_KERNEL_FLAG);
|
||||
big_image = (bootproto >= 0x0200) && (hdr->loadflags & BIG_KERNEL_FLAG);
|
||||
|
||||
/* Derermine load address */
|
||||
load_address = (void*)(big_image ? BZIMAGE_LOAD_ADDR:ZIMAGE_LOAD_ADDR);
|
||||
/* Determine load address */
|
||||
load_address = (void*)(big_image ? BZIMAGE_LOAD_ADDR : ZIMAGE_LOAD_ADDR);
|
||||
|
||||
/* load setup */
|
||||
printf("Moving Real-Mode Code to 0x%8.8lx (%d bytes)\n", (ulong)setup_base, setup_size);
|
||||
memmove(setup_base, image, setup_size);
|
||||
|
||||
printf("Using boot protocol version %x.%02x\n",
|
||||
(bootproto & 0xff00) >> 8, bootproto & 0xff);
|
||||
|
||||
|
||||
if (bootproto == 0x0100) {
|
||||
|
||||
*(u16*)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC;
|
||||
|
@ -154,48 +164,58 @@ void *load_zimage(char *image, unsigned long kernel_size,
|
|||
memset((void*)0x90000 + setup_size, 0, SETUP_MAX_SIZE-setup_size);
|
||||
}
|
||||
|
||||
/* We are now setting up the real-mode version of the header */
|
||||
hdr = (struct setup_header *)(setup_base + SETUP_SECTS_OFF);
|
||||
|
||||
if (bootproto >= 0x0200) {
|
||||
*(u8*)(setup_base + TYPE_OF_LOADER_OFF) = 0xff;
|
||||
printf("Linux kernel version %s\n",
|
||||
(char*)(setup_base + SETUP_START_OFFSET +
|
||||
*(u16*)(setup_base + START_SYS_OFF + 2)));
|
||||
hdr->type_of_loader = 8;
|
||||
|
||||
if (hdr->setup_sects >= 15)
|
||||
printf("Linux kernel version %s\n", (char *)
|
||||
(setup_base + (hdr->kernel_version + 0x200)));
|
||||
else
|
||||
printf("Setup Sectors < 15 - Cannot print kernel version.\n");
|
||||
|
||||
if (initrd_addr) {
|
||||
printf("Initial RAM disk at linear address 0x%08lx, size %ld bytes\n",
|
||||
initrd_addr, initrd_size);
|
||||
|
||||
*(u32*)(setup_base + RAMDISK_IMAGE_OFF) = initrd_addr;
|
||||
*(u32*)(setup_base + RAMDISK_SIZE_OFF)=initrd_size;
|
||||
hdr->ramdisk_image = initrd_addr;
|
||||
hdr->ramdisk_size = initrd_size;
|
||||
}
|
||||
}
|
||||
|
||||
if (bootproto >= 0x0201) {
|
||||
*(u16*)(setup_base + HEAP_END_PTR_OFF) = HEAP_END_OFFSET;
|
||||
|
||||
/* CAN_USE_HEAP */
|
||||
*(u8*)(setup_base + LOADFLAGS_OFF) =
|
||||
*(u8*)(setup_base + LOADFLAGS_OFF) | HEAP_FLAG;
|
||||
hdr->heap_end_ptr = HEAP_END_OFFSET;
|
||||
hdr->loadflags |= HEAP_FLAG;
|
||||
}
|
||||
|
||||
if (bootproto >= 0x0202) {
|
||||
*(u32*)(setup_base + CMD_LINE_PTR_OFF) = (u32)setup_base + COMMAND_LINE_OFFSET;
|
||||
hdr->cmd_line_ptr = (u32)setup_base + COMMAND_LINE_OFFSET;
|
||||
} else if (bootproto >= 0x0200) {
|
||||
|
||||
*(u16*)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC;
|
||||
*(u16*)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET;
|
||||
*(u16*)(setup_base + SETUP_MOVE_SIZE_OFF) = 0x9100;
|
||||
|
||||
hdr->setup_move_size = 0x9100;
|
||||
}
|
||||
|
||||
if (bootproto >= 0x0204)
|
||||
kernel_size = hdr->syssize * 16;
|
||||
else
|
||||
kernel_size -= setup_size;
|
||||
|
||||
|
||||
if (big_image) {
|
||||
if ((kernel_size - setup_size) > BZIMAGE_MAX_SIZE) {
|
||||
if ((kernel_size) > BZIMAGE_MAX_SIZE) {
|
||||
printf("Error: bzImage kernel too big! (size: %ld, max: %d)\n",
|
||||
kernel_size - setup_size, BZIMAGE_MAX_SIZE);
|
||||
kernel_size, BZIMAGE_MAX_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
} else if ((kernel_size - setup_size) > ZIMAGE_MAX_SIZE) {
|
||||
} else if ((kernel_size) > ZIMAGE_MAX_SIZE) {
|
||||
printf("Error: zImage kernel too big! (size: %ld, max: %d)\n",
|
||||
kernel_size - setup_size, ZIMAGE_MAX_SIZE);
|
||||
kernel_size, ZIMAGE_MAX_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -203,10 +223,10 @@ void *load_zimage(char *image, unsigned long kernel_size,
|
|||
build_command_line(setup_base + COMMAND_LINE_OFFSET, auto_boot);
|
||||
|
||||
printf("Loading %czImage at address 0x%08x (%ld bytes)\n", big_image ? 'b' : ' ',
|
||||
(u32)load_address, kernel_size - setup_size);
|
||||
(u32)load_address, kernel_size);
|
||||
|
||||
|
||||
memmove(load_address, image + setup_size, kernel_size - setup_size);
|
||||
memmove(load_address, image + setup_size, kernel_size);
|
||||
|
||||
/* ready for booting */
|
||||
return setup_base;
|
||||
|
@ -218,8 +238,51 @@ void boot_zimage(void *setup_base)
|
|||
|
||||
memset(®s, 0, sizeof(struct pt_regs));
|
||||
regs.xds = (u32)setup_base >> 4;
|
||||
regs.xss = 0x9000;
|
||||
regs.xes = regs.xds;
|
||||
regs.xss = regs.xds;
|
||||
regs.esp = 0x9000;
|
||||
regs.eflags = 0;
|
||||
enter_realmode(((u32)setup_base+SETUP_START_OFFSET)>>4, 0, ®s, ®s);
|
||||
}
|
||||
|
||||
int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
void *base_ptr;
|
||||
void *bzImage_addr;
|
||||
ulong bzImage_size = 0;
|
||||
|
||||
disable_interrupts();
|
||||
|
||||
/* Setup board for maximum PC/AT Compatibility */
|
||||
setup_pcat_compatibility();
|
||||
|
||||
/* argv[1] holds the address of the bzImage */
|
||||
bzImage_addr = (void *)simple_strtoul(argv[1], NULL, 16);
|
||||
|
||||
if (argc == 3)
|
||||
bzImage_size = simple_strtoul(argv[2], NULL, 16);
|
||||
|
||||
/* Lets look for*/
|
||||
base_ptr = load_zimage (bzImage_addr, bzImage_size, 0, 0, 0);
|
||||
|
||||
if (NULL == base_ptr) {
|
||||
printf ("## Kernel loading failed ...\n");
|
||||
} else {
|
||||
printf ("## Transferring control to Linux (at address %08x) ...\n",
|
||||
(u32)base_ptr);
|
||||
|
||||
/* we assume that the kernel is in place */
|
||||
printf("\nStarting kernel ...\n\n");
|
||||
|
||||
boot_zimage(base_ptr);
|
||||
/* does not return */
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
zboot, 3, 0, do_zboot,
|
||||
"Boot bzImage",
|
||||
""
|
||||
);
|
||||
|
|
|
@ -37,11 +37,11 @@ COBJS-y += interrupts.o
|
|||
COBJS-y += iopin.o
|
||||
COBJS-y += serial.o
|
||||
COBJS-y += speed.o
|
||||
COBJS-${CONFIG_FSL_DIU_FB} += diu.o
|
||||
COBJS-${CONFIG_FSL_DIU_FB} += ../../../../board/freescale/common/fsl_diu_fb.o
|
||||
COBJS-${CONFIG_FSL_DIU_FB} += ../../../../board/freescale/common/fsl_logo_bmp.o
|
||||
COBJS-${CONFIG_CMD_IDE} += ide.o
|
||||
COBJS-${CONFIG_IIM} += iim.o
|
||||
COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
|
||||
COBJS-$(CONFIG_FSL_DIU_FB) += ../../../../board/freescale/common/fsl_diu_fb.o
|
||||
COBJS-$(CONFIG_FSL_DIU_FB) += ../../../../board/freescale/common/fsl_logo_bmp.o
|
||||
COBJS-$(CONFIG_CMD_IDE) += ide.o
|
||||
COBJS-$(CONFIG_IIM) += iim.o
|
||||
COBJS-$(CONFIG_PCI) += pci.o
|
||||
|
||||
COBJS := $(COBJS-y)
|
||||
|
|
|
@ -154,26 +154,6 @@ void ft_cpu_setup(void *blob, bd_t *bd)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BOOTCOUNT_LIMIT
|
||||
|
||||
void bootcount_store (ulong a)
|
||||
{
|
||||
volatile ulong *save_addr = (volatile ulong *) (MPC5XXX_CDM_BRDCRMB);
|
||||
|
||||
*save_addr = (BOOTCOUNT_MAGIC & 0xffff0000) | a;
|
||||
}
|
||||
|
||||
ulong bootcount_load (void)
|
||||
{
|
||||
volatile ulong *save_addr = (volatile ulong *) (MPC5XXX_CDM_BRDCRMB);
|
||||
|
||||
if ((*save_addr & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
|
||||
return 0;
|
||||
else
|
||||
return (*save_addr & 0x0000ffff);
|
||||
}
|
||||
#endif /* CONFIG_BOOTCOUNT_LIMIT */
|
||||
|
||||
#ifdef CONFIG_MPC5xxx_FEC
|
||||
/* Default initializations for FEC controllers. To override,
|
||||
* create a board-specific function called:
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* (C) Copyright 2003-2010
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* This file is based on mpc4200fec.c,
|
||||
|
@ -27,10 +27,6 @@ static void tfifo_print (char *devname, mpc8220_fec_priv * fec);
|
|||
static void rfifo_print (char *devname, mpc8220_fec_priv * fec);
|
||||
#endif /* DEBUG */
|
||||
|
||||
#ifdef DEBUG
|
||||
static u32 local_crc32 (char *string, unsigned int crc_value, int len);
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
u8 data[1500]; /* actual data */
|
||||
int length; /* actual length */
|
||||
|
@ -962,39 +958,4 @@ int fec8220_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
static u32 local_crc32 (char *string, unsigned int crc_value, int len)
|
||||
{
|
||||
int i;
|
||||
char c;
|
||||
unsigned int crc, count;
|
||||
|
||||
/*
|
||||
* crc32 algorithm
|
||||
*/
|
||||
/*
|
||||
* crc = 0xffffffff; * The initialized value should be 0xffffffff
|
||||
*/
|
||||
crc = crc_value;
|
||||
|
||||
for (i = len; --i >= 0;) {
|
||||
c = *string++;
|
||||
for (count = 0; count < 8; count++) {
|
||||
if ((c & 0x01) ^ (crc & 0x01)) {
|
||||
crc >>= 1;
|
||||
crc = crc ^ 0xedb88320;
|
||||
} else {
|
||||
crc >>= 1;
|
||||
}
|
||||
c >>= 1;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* In big endian system, do byte swaping for crc value
|
||||
*/
|
||||
return crc;
|
||||
}
|
||||
#endif /* DEBUG */
|
||||
|
||||
#endif /* CONFIG_MPC8220_FEC */
|
||||
|
|
|
@ -195,27 +195,3 @@ ulong post_word_load (void)
|
|||
}
|
||||
|
||||
#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
|
||||
|
||||
#ifdef CONFIG_BOOTCOUNT_LIMIT
|
||||
|
||||
void bootcount_store (ulong a)
|
||||
{
|
||||
volatile ulong *save_addr =
|
||||
(volatile ulong *)(CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR);
|
||||
|
||||
save_addr[0] = a;
|
||||
save_addr[1] = BOOTCOUNT_MAGIC;
|
||||
}
|
||||
|
||||
ulong bootcount_load (void)
|
||||
{
|
||||
volatile ulong *save_addr =
|
||||
(volatile ulong *)(CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR);
|
||||
|
||||
if (save_addr[1] != BOOTCOUNT_MAGIC)
|
||||
return 0;
|
||||
else
|
||||
return save_addr[0];
|
||||
}
|
||||
|
||||
#endif /* CONFIG_BOOTCOUNT_LIMIT */
|
||||
|
|
|
@ -304,33 +304,3 @@ int cpu_mmc_init(bd_t *bis)
|
|||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BOOTCOUNT_LIMIT
|
||||
|
||||
#if !defined(CONFIG_MPC8360)
|
||||
#error "CONFIG_BOOTCOUNT_LIMIT only for MPC8360 implemented"
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_BOOTCOUNT_ADDR)
|
||||
#define CONFIG_BOOTCOUNT_ADDR (0x110000 + QE_MURAM_SIZE - 2 * sizeof(unsigned long))
|
||||
#endif
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
void bootcount_store (ulong a)
|
||||
{
|
||||
void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR);
|
||||
out_be32 (reg, a);
|
||||
out_be32 (reg + 4, BOOTCOUNT_MAGIC);
|
||||
}
|
||||
|
||||
ulong bootcount_load (void)
|
||||
{
|
||||
void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR);
|
||||
|
||||
if (in_be32 (reg + 4) != BOOTCOUNT_MAGIC)
|
||||
return 0;
|
||||
else
|
||||
return in_be32 (reg);
|
||||
}
|
||||
#endif /* CONFIG_BOOTCOUNT_LIMIT */
|
||||
|
|
|
@ -65,16 +65,16 @@ void cpu_init_f (volatile immap_t * im)
|
|||
{
|
||||
__be32 acr_mask =
|
||||
#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
|
||||
(ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
|
||||
ACR_PIPE_DEP |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
|
||||
(ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
|
||||
ACR_RPTCNT |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
|
||||
(ACR_APARK << ACR_APARK_SHIFT) |
|
||||
ACR_APARK |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
|
||||
(ACR_PARKM << ACR_PARKM_SHIFT) |
|
||||
ACR_PARKM |
|
||||
#endif
|
||||
0;
|
||||
__be32 acr_val =
|
||||
|
@ -93,16 +93,16 @@ void cpu_init_f (volatile immap_t * im)
|
|||
0;
|
||||
__be32 spcr_mask =
|
||||
#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
|
||||
(SPCR_OPT << SPCR_OPT_SHIFT) |
|
||||
SPCR_OPT |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
|
||||
(SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
|
||||
SPCR_TSECEP |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
|
||||
(SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
|
||||
SPCR_TSEC1EP |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
|
||||
(SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
|
||||
SPCR_TSEC2EP |
|
||||
#endif
|
||||
0;
|
||||
__be32 spcr_val =
|
||||
|
@ -121,34 +121,34 @@ void cpu_init_f (volatile immap_t * im)
|
|||
0;
|
||||
__be32 sccr_mask =
|
||||
#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
|
||||
(SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
|
||||
SCCR_ENCCM |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
|
||||
(SCCR_PCICM << SCCR_PCICM_SHIFT) |
|
||||
SCCR_PCICM |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
|
||||
(SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
|
||||
SCCR_TSECCM |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
|
||||
(SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
|
||||
SCCR_TSEC1CM |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
|
||||
(SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
|
||||
SCCR_TSEC2CM |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
|
||||
(SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
|
||||
SCCR_TSEC1ON |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
|
||||
(SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
|
||||
SCCR_TSEC2ON |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
|
||||
(SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
|
||||
SCCR_USBMPHCM |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
|
||||
(SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
|
||||
SCCR_USBDRCM |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
|
||||
(SCCR_SATACM << SCCR_SATACM_SHIFT) |
|
||||
SCCR_SATACM |
|
||||
#endif
|
||||
0;
|
||||
__be32 sccr_val =
|
||||
|
|
|
@ -507,7 +507,7 @@ init_e300_core: /* time t 10 */
|
|||
|
||||
lis r3, CONFIG_SYS_IMMR@h
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
/* Initialise the Wathcdog values and reset it (if req) */
|
||||
/* Initialise the Watchdog values and reset it (if req) */
|
||||
/*------------------------------------------------------*/
|
||||
lis r4, CONFIG_SYS_WATCHDOG_VALUE
|
||||
ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
|
||||
|
@ -520,7 +520,7 @@ init_e300_core: /* time t 10 */
|
|||
li r4, -0x55C7
|
||||
sth r4, SWSRR@l(r3)
|
||||
#else
|
||||
/* Disable Wathcdog */
|
||||
/* Disable Watchdog */
|
||||
/*-------------------*/
|
||||
lwz r4, SWCRR(r3)
|
||||
/* Check to see if its enabled for disabling
|
||||
|
@ -739,6 +739,7 @@ setup_bats:
|
|||
* Note: requires that all cache bits in
|
||||
* HID0 are in the low half word.
|
||||
*/
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
.globl icache_enable
|
||||
icache_enable:
|
||||
mfspr r3, HID0
|
||||
|
@ -767,6 +768,7 @@ icache_status:
|
|||
mfspr r3, HID0
|
||||
rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
|
||||
blr
|
||||
#endif /* !CONFIG_NAND_SPL */
|
||||
|
||||
.globl dcache_enable
|
||||
dcache_enable:
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2007-2009 Freescale Semiconductor, Inc.
|
||||
* Copyright 2007-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2003 Motorola Inc.
|
||||
* Modified by Xianghua Xiao, X.Xiao@motorola.com
|
||||
|
@ -30,9 +30,11 @@
|
|||
#include <watchdog.h>
|
||||
#include <asm/processor.h>
|
||||
#include <ioports.h>
|
||||
#include <sata.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
#include "mp.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
@ -418,3 +420,13 @@ void arch_preboot_os(void)
|
|||
|
||||
setup_ivors();
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
|
||||
int sata_initialize(void)
|
||||
{
|
||||
if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
|
||||
return __sata_initialize();
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -1,17 +1,31 @@
|
|||
/*
|
||||
* Copyright (C) 2008 Freescale Semicondutor, Inc.
|
||||
* Copyright 2008,2010 Freescale Semiconductor, Inc.
|
||||
* Dave Liu <daveliu@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
|
||||
/* PORDEVSR register */
|
||||
#define GUTS_PORDEVSR_OFFS 0xc
|
||||
|
@ -52,6 +66,61 @@
|
|||
#define FSL_SRDSCR3_LANEE_SGMII 0x00000000
|
||||
#define FSL_SRDSCR3_LANEE_SATA 0x00150005
|
||||
|
||||
|
||||
#define SRDS1_MAX_LANES 8
|
||||
#define SRDS2_MAX_LANES 2
|
||||
|
||||
static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
|
||||
[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
|
||||
[0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
|
||||
[0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
|
||||
[0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3},
|
||||
};
|
||||
|
||||
static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
|
||||
[0x1] = {SATA1, SATA2},
|
||||
[0x3] = {SATA1, NONE},
|
||||
[0x4] = {SGMII_TSEC1, SGMII_TSEC3},
|
||||
[0x6] = {SGMII_TSEC1, NONE},
|
||||
};
|
||||
|
||||
int is_serdes_configured(enum srds_prtcl device)
|
||||
{
|
||||
int i;
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 pordevsr = in_be32(&gur->pordevsr);
|
||||
u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
|
||||
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
|
||||
|
||||
u32 srds2_cfg = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >>
|
||||
GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT;
|
||||
|
||||
debug("%s: dev = %d\n", __FUNCTION__, device);
|
||||
debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg);
|
||||
debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_cfg);
|
||||
|
||||
if (srds1_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
|
||||
printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (srds2_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
|
||||
printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_cfg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < SRDS1_MAX_LANES; i++) {
|
||||
if (serdes1_cfg_tbl[srds1_cfg][i] == device)
|
||||
return 1;
|
||||
}
|
||||
for (i = 0; i < SRDS2_MAX_LANES; i++) {
|
||||
if (serdes2_cfg_tbl[srds2_cfg][i] == device)
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void fsl_serdes_init(void)
|
||||
{
|
||||
void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
|
|
|
@ -103,29 +103,3 @@ ulong post_word_load (void)
|
|||
}
|
||||
|
||||
#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
|
||||
|
||||
#ifdef CONFIG_BOOTCOUNT_LIMIT
|
||||
|
||||
void bootcount_store (ulong a)
|
||||
{
|
||||
volatile ulong *save_addr =
|
||||
(volatile ulong *)( ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem +
|
||||
CPM_BOOTCOUNT_ADDR );
|
||||
|
||||
save_addr[0] = a;
|
||||
save_addr[1] = BOOTCOUNT_MAGIC;
|
||||
}
|
||||
|
||||
ulong bootcount_load (void)
|
||||
{
|
||||
volatile ulong *save_addr =
|
||||
(volatile ulong *)( ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem +
|
||||
CPM_BOOTCOUNT_ADDR );
|
||||
|
||||
if (save_addr[1] != BOOTCOUNT_MAGIC)
|
||||
return 0;
|
||||
else
|
||||
return save_addr[0];
|
||||
}
|
||||
|
||||
#endif /* CONFIG_BOOTCOUNT_LIMIT */
|
||||
|
|
|
@ -175,8 +175,8 @@ determine_refresh_rate_ps(const unsigned int spd_refresh)
|
|||
* ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3
|
||||
* Not certain if any good value exists for CL=2
|
||||
*/
|
||||
/* CL2 CL3 CL4 CL5 CL6 */
|
||||
unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500 };
|
||||
/* CL2 CL3 CL4 CL5 CL6 CL7*/
|
||||
unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500, 1875 };
|
||||
|
||||
unsigned int
|
||||
compute_derated_DDR2_CAS_latency(unsigned int mclk_ps)
|
||||
|
|
|
@ -56,18 +56,6 @@ static struct pci_info pci_config_info[] =
|
|||
#elif defined(CONFIG_MPC8536)
|
||||
static struct pci_info pci_config_info[] =
|
||||
{
|
||||
[LAW_TRGT_IF_PCI] = {
|
||||
.cfg = 0,
|
||||
},
|
||||
[LAW_TRGT_IF_PCIE_1] = {
|
||||
.cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7),
|
||||
},
|
||||
[LAW_TRGT_IF_PCIE_2] = {
|
||||
.cfg = (1 << 5) | (1 << 7),
|
||||
},
|
||||
[LAW_TRGT_IF_PCIE_3] = {
|
||||
.cfg = (1 << 7),
|
||||
},
|
||||
};
|
||||
#elif defined(CONFIG_MPC8544)
|
||||
static struct pci_info pci_config_info[] =
|
||||
|
|
|
@ -51,27 +51,3 @@ ulong post_word_load (void)
|
|||
}
|
||||
|
||||
#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
|
||||
|
||||
#ifdef CONFIG_BOOTCOUNT_LIMIT
|
||||
|
||||
void bootcount_store (ulong a)
|
||||
{
|
||||
volatile ulong *save_addr =
|
||||
(volatile ulong *)(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_BOOTCOUNT_ADDR);
|
||||
|
||||
save_addr[0] = a;
|
||||
save_addr[1] = BOOTCOUNT_MAGIC;
|
||||
}
|
||||
|
||||
ulong bootcount_load (void)
|
||||
{
|
||||
volatile ulong *save_addr =
|
||||
(volatile ulong *)(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_BOOTCOUNT_ADDR);
|
||||
|
||||
if (save_addr[1] != BOOTCOUNT_MAGIC)
|
||||
return 0;
|
||||
else
|
||||
return save_addr[0];
|
||||
}
|
||||
|
||||
#endif /* CONFIG_BOOTCOUNT_LIMIT */
|
||||
|
|
|
@ -245,6 +245,7 @@
|
|||
#define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */
|
||||
#define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */
|
||||
#define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */
|
||||
#define MxMR_UWPL 0x08000000 /* LUPWAIT Polarity Mask */
|
||||
#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
|
||||
#define MxMR_OP_WARR 0x10000000 /* Write to Array */
|
||||
#define MxMR_OP_RARR 0x20000000 /* Read from Array */
|
||||
|
|
|
@ -1,21 +1,48 @@
|
|||
/*
|
||||
* Copyright 2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __FSL_SERDES_H
|
||||
#define __FSL_SERDES_H
|
||||
|
||||
#include <config.h>
|
||||
|
||||
#define FSL_SERDES_CLK_100 (0 << 28)
|
||||
#define FSL_SERDES_CLK_125 (1 << 28)
|
||||
#define FSL_SERDES_CLK_150 (3 << 28)
|
||||
#define FSL_SERDES_PROTO_SATA 0
|
||||
#define FSL_SERDES_PROTO_PEX 1
|
||||
#define FSL_SERDES_PROTO_PEX_X2 2
|
||||
#define FSL_SERDES_PROTO_SGMII 3
|
||||
#define FSL_SERDES_VDD_1V 1
|
||||
enum srds_prtcl {
|
||||
NONE = 0,
|
||||
PCIE1,
|
||||
PCIE2,
|
||||
PCIE3,
|
||||
PCIE4,
|
||||
SATA1,
|
||||
SATA2,
|
||||
SRIO1,
|
||||
SRIO2,
|
||||
SGMII_FM1,
|
||||
SGMII_FM2,
|
||||
SGMII_TSEC1,
|
||||
SGMII_TSEC2,
|
||||
SGMII_TSEC3,
|
||||
SGMII_TSEC4,
|
||||
XAUI_FM1,
|
||||
XAUI_FM2,
|
||||
AURORA,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_FSL_SERDES
|
||||
extern void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd);
|
||||
#else
|
||||
static void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) {}
|
||||
#endif /* CONFIG_FSL_SERDES */
|
||||
int is_serdes_configured(enum srds_prtcl device);
|
||||
|
||||
#endif /* __FSL_SERDES_H */
|
||||
|
|
|
@ -33,6 +33,7 @@ SOBJS-y += reloc.o
|
|||
COBJS-y += bat_rw.o
|
||||
COBJS-y += board.o
|
||||
COBJS-y += bootm.o
|
||||
COBJS-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount.o
|
||||
COBJS-y += cache.o
|
||||
COBJS-y += extable.o
|
||||
COBJS-y += interrupts.o
|
||||
|
|
92
arch/powerpc/lib/bootcount.c
Normal file
92
arch/powerpc/lib/bootcount.c
Normal file
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* (C) Copyright 2010
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
/*
|
||||
* Only override CONFIG_SYS_BOOTCOUNT_ADDR if not already defined. This
|
||||
* way, some boards can define it directly in their config header.
|
||||
*/
|
||||
#if !defined(CONFIG_SYS_BOOTCOUNT_ADDR)
|
||||
|
||||
#if defined(CONFIG_MPC5xxx)
|
||||
#define CONFIG_SYS_BOOTCOUNT_ADDR (MPC5XXX_CDM_BRDCRMB)
|
||||
#define CONFIG_SYS_BOOTCOUNT_SINGLEWORD
|
||||
#endif /* defined(CONFIG_MPC5xxx) */
|
||||
|
||||
#if defined(CONFIG_8xx)
|
||||
#define CONFIG_SYS_BOOTCOUNT_ADDR (((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + \
|
||||
CPM_BOOTCOUNT_ADDR)
|
||||
#endif /* defined(CONFIG_8xx) */
|
||||
|
||||
#if defined(CONFIG_MPC8260)
|
||||
#include <asm/cpm_8260.h>
|
||||
|
||||
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR)
|
||||
#endif /* defined(CONFIG_MPC8260) */
|
||||
|
||||
#if defined(CONFIG_MPC8360)
|
||||
#include <asm/immap_qe.h>
|
||||
|
||||
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \
|
||||
QE_MURAM_SIZE - 2 * sizeof(u32))
|
||||
#endif /* defined(CONFIG_MPC8360) */
|
||||
|
||||
#if defined(CONFIG_4xx)
|
||||
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_OCM_DATA_ADDR + \
|
||||
CONFIG_SYS_BOOTCOUNT_ADDR)
|
||||
#endif /* defined(CONFIG_4xx) */
|
||||
|
||||
#endif /* !defined(CONFIG_SYS_BOOTCOUNT_ADDR) */
|
||||
|
||||
void bootcount_store(ulong a)
|
||||
{
|
||||
void *reg = (void *)CONFIG_SYS_BOOTCOUNT_ADDR;
|
||||
|
||||
#if defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD)
|
||||
out_be32(reg, (BOOTCOUNT_MAGIC & 0xffff0000) | a);
|
||||
#else
|
||||
out_be32(reg, a);
|
||||
out_be32(reg + 4, BOOTCOUNT_MAGIC);
|
||||
#endif
|
||||
}
|
||||
|
||||
ulong bootcount_load(void)
|
||||
{
|
||||
void *reg = (void *)CONFIG_SYS_BOOTCOUNT_ADDR;
|
||||
|
||||
#if defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD)
|
||||
u32 tmp = in_be32(reg);
|
||||
|
||||
if ((tmp & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
|
||||
return 0;
|
||||
else
|
||||
return (tmp & 0x0000ffff);
|
||||
#else
|
||||
if (in_be32(reg + 4) != BOOTCOUNT_MAGIC)
|
||||
return 0;
|
||||
else
|
||||
return in_be32(reg);
|
||||
#endif
|
||||
}
|
|
@ -163,8 +163,8 @@ void arch_lmb_reserve(struct lmb *lmb)
|
|||
sp = get_sp();
|
||||
debug ("## Current stack ends at 0x%08lx\n", sp);
|
||||
|
||||
/* adjust sp by 1K to be safe */
|
||||
sp -= 1024;
|
||||
/* adjust sp by 4K to be safe */
|
||||
sp -= 4096;
|
||||
lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - sp));
|
||||
|
||||
return ;
|
||||
|
|
|
@ -146,14 +146,7 @@ void mv_phy_88e1121_init(char *name)
|
|||
miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0);
|
||||
|
||||
/* reset the phy */
|
||||
if (miiphy_read (name, devadr, PHY_BMCR, ®) != 0) {
|
||||
printf("Err..(%s) PHY status read failed\n", __FUNCTION__);
|
||||
return;
|
||||
}
|
||||
if (miiphy_write (name, devadr, PHY_BMCR, reg | 0x8000) != 0) {
|
||||
printf("Err..(%s) PHY reset failed\n", __FUNCTION__);
|
||||
return;
|
||||
}
|
||||
miiphy_reset(name, devadr);
|
||||
|
||||
printf("88E1121 Initialized on %s\n", name);
|
||||
}
|
||||
|
|
|
@ -340,10 +340,6 @@ void serial_puts (const char *c)
|
|||
{
|
||||
return;
|
||||
}
|
||||
void serial_addr (unsigned int i)
|
||||
{
|
||||
return;
|
||||
}
|
||||
int serial_getc (void)
|
||||
{
|
||||
return 0;
|
||||
|
|
|
@ -21,7 +21,7 @@
|
|||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0x38040000
|
||||
TEXT_BASE = 0x06000000
|
||||
CFLAGS_common/dlmalloc.o += -Wa,--no-warn -fno-strict-aliasing
|
||||
PLATFORM_RELFLAGS += -fvisibility=hidden
|
||||
PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
|
||||
|
|
|
@ -24,6 +24,8 @@
|
|||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/ic/sc520.h>
|
||||
#include <net.h>
|
||||
#include <netdev.h>
|
||||
|
||||
#ifdef CONFIG_HW_WATCHDOG
|
||||
#include <watchdog.h>
|
||||
|
@ -43,10 +45,13 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
|
||||
|
||||
static void enet_timer_isr(void);
|
||||
static void enet_toggle_run_led(void);
|
||||
|
||||
void init_sc520_enet (void)
|
||||
{
|
||||
/* Set CPU Speed to 100MHz */
|
||||
sc520_mmcr->cpuctl = 0x01;
|
||||
writeb(0x01, &sc520_mmcr->cpuctl);
|
||||
|
||||
/* wait at least one millisecond */
|
||||
asm("movl $0x2000,%%ecx\n"
|
||||
|
@ -55,7 +60,7 @@ void init_sc520_enet (void)
|
|||
"loop 0b\n": : : "ecx");
|
||||
|
||||
/* turn on the SDRAM write buffer */
|
||||
sc520_mmcr->dbctl = 0x11;
|
||||
writeb(0x11, &sc520_mmcr->dbctl);
|
||||
|
||||
/* turn on the cache and disable write through */
|
||||
asm("movl %%cr0, %%eax\n"
|
||||
|
@ -70,51 +75,52 @@ int board_early_init_f(void)
|
|||
{
|
||||
init_sc520_enet();
|
||||
|
||||
sc520_mmcr->gpcsrt = 0x01; /* GP Chip Select Recovery Time */
|
||||
sc520_mmcr->gpcspw = 0x07; /* GP Chip Select Pulse Width */
|
||||
sc520_mmcr->gpcsoff = 0x00; /* GP Chip Select Offset */
|
||||
sc520_mmcr->gprdw = 0x05; /* GP Read pulse width */
|
||||
sc520_mmcr->gprdoff = 0x01; /* GP Read offset */
|
||||
sc520_mmcr->gpwrw = 0x05; /* GP Write pulse width */
|
||||
sc520_mmcr->gpwroff = 0x01; /* GP Write offset */
|
||||
writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select Recovery Time */
|
||||
writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse Width */
|
||||
writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select Offset */
|
||||
writeb(0x05, &sc520_mmcr->gprdw); /* GP Read pulse width */
|
||||
writeb(0x01, &sc520_mmcr->gprdoff); /* GP Read offset */
|
||||
writeb(0x05, &sc520_mmcr->gpwrw); /* GP Write pulse width */
|
||||
writeb(0x01, &sc520_mmcr->gpwroff); /* GP Write offset */
|
||||
|
||||
sc520_mmcr->piodata15_0 = 0x0630; /* PIO15_PIO0 Data */
|
||||
sc520_mmcr->piodata31_16 = 0x2000; /* PIO31_PIO16 Data */
|
||||
sc520_mmcr->piodir31_16 = 0x2000; /* GPIO Direction */
|
||||
sc520_mmcr->piodir15_0 = 0x87b5; /* GPIO Direction */
|
||||
sc520_mmcr->piopfs31_16 = 0x0dfe; /* GPIO pin function 31-16 reg */
|
||||
sc520_mmcr->piopfs15_0 = 0x200a; /* GPIO pin function 15-0 reg */
|
||||
sc520_mmcr->cspfs = 0x00f8; /* Chip Select Pin Function Select */
|
||||
writew(0x0630, &sc520_mmcr->piodata15_0); /* PIO15_PIO0 Data */
|
||||
writew(0x2000, &sc520_mmcr->piodata31_16); /* PIO31_PIO16 Data */
|
||||
writew(0x2000, &sc520_mmcr->piodir31_16); /* GPIO Direction */
|
||||
writew(0x87b5, &sc520_mmcr->piodir15_0); /* GPIO Direction */
|
||||
writew(0x0dfe, &sc520_mmcr->piopfs31_16); /* GPIO pin function 31-16 reg */
|
||||
writew(0x200a, &sc520_mmcr->piopfs15_0); /* GPIO pin function 15-0 reg */
|
||||
writeb(0xf8, &sc520_mmcr->cspfs); /* Chip Select Pin Function Select */
|
||||
|
||||
sc520_mmcr->par[2] = 0x200713f8; /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
|
||||
sc520_mmcr->par[3] = 0x2c0712f8; /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
|
||||
sc520_mmcr->par[4] = 0x300711f8; /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
|
||||
sc520_mmcr->par[5] = 0x340710f8; /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
|
||||
sc520_mmcr->par[6] = 0xe3ffc000; /* SDRAM (0x00000000, 128MB) */
|
||||
sc520_mmcr->par[7] = 0xaa3fd000; /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
|
||||
sc520_mmcr->par[8] = 0xca3fd100; /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
|
||||
sc520_mmcr->par[9] = 0x4203d900; /* SRAM (GPCS0, 0x19000000, 1MB) */
|
||||
sc520_mmcr->par[10] = 0x4e03d910; /* SRAM (GPCS3, 0x19100000, 1MB) */
|
||||
sc520_mmcr->par[11] = 0x50018100; /* DP-RAM (GPCS4, 0x18100000, 4kB) */
|
||||
sc520_mmcr->par[12] = 0x54020000; /* CFLASH1 (0x200000000, 4kB) */
|
||||
sc520_mmcr->par[13] = 0x5c020001; /* CFLASH2 (0x200010000, 4kB) */
|
||||
/* sc520_mmcr->par14 = 0x8bfff800; */ /* BOOTCS at 0x18000000 */
|
||||
/* sc520_mmcr->par15 = 0x38201000; */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
|
||||
writel(0x200713f8, &sc520_mmcr->par[2]); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
|
||||
writel(0x2c0712f8, &sc520_mmcr->par[3]); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
|
||||
writel(0x300711f8, &sc520_mmcr->par[4]); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
|
||||
writel(0x340710f8, &sc520_mmcr->par[5]); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
|
||||
writel(0xe3ffc000, &sc520_mmcr->par[6]); /* SDRAM (0x00000000, 128MB) */
|
||||
writel(0xaa3fd000, &sc520_mmcr->par[7]); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
|
||||
writel(0xca3fd100, &sc520_mmcr->par[8]); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
|
||||
writel(0x4203d900, &sc520_mmcr->par[9]); /* SRAM (GPCS0, 0x19000000, 1MB) */
|
||||
writel(0x4e03d910, &sc520_mmcr->par[10]); /* SRAM (GPCS3, 0x19100000, 1MB) */
|
||||
writel(0x50018100, &sc520_mmcr->par[11]); /* DP-RAM (GPCS4, 0x18100000, 4kB) */
|
||||
writel(0x54020000, &sc520_mmcr->par[12]); /* CFLASH1 (0x200000000, 4kB) */
|
||||
writel(0x5c020001, &sc520_mmcr->par[13]); /* CFLASH2 (0x200010000, 4kB) */
|
||||
/* writel(0x8bfff800, &sc520_mmcr->par14); */ /* BOOTCS at 0x18000000 */
|
||||
/* writel(0x38201000, &sc520_mmcr->par15); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
|
||||
|
||||
/* Disable Watchdog */
|
||||
sc520_mmcr->wdtmrctl = 0x3333;
|
||||
sc520_mmcr->wdtmrctl = 0xcccc;
|
||||
sc520_mmcr->wdtmrctl = 0x0000;
|
||||
writew(0x3333, &sc520_mmcr->wdtmrctl);
|
||||
writew(0xcccc, &sc520_mmcr->wdtmrctl);
|
||||
writew(0x0000, &sc520_mmcr->wdtmrctl);
|
||||
|
||||
/* Chip Select Configuration */
|
||||
sc520_mmcr->bootcsctl = 0x0033;
|
||||
sc520_mmcr->romcs1ctl = 0x0615;
|
||||
sc520_mmcr->romcs2ctl = 0x0615;
|
||||
writew(0x0033, &sc520_mmcr->bootcsctl);
|
||||
writew(0x0615, &sc520_mmcr->romcs1ctl);
|
||||
writew(0x0615, &sc520_mmcr->romcs2ctl);
|
||||
|
||||
sc520_mmcr->adddecctl = 0x02;
|
||||
sc520_mmcr->uart1ctl = 0x07;
|
||||
sc520_mmcr->sysarbctl = 0x06;
|
||||
sc520_mmcr->sysarbmenb = 0x0003;
|
||||
writeb(0x00, &sc520_mmcr->adddecctl);
|
||||
writeb(0x07, &sc520_mmcr->uart1ctl);
|
||||
writeb(0x07, &sc520_mmcr->uart2ctl);
|
||||
writeb(0x06, &sc520_mmcr->sysarbctl);
|
||||
writew(0x0003, &sc520_mmcr->sysarbmenb);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -157,6 +163,10 @@ int last_stage_init(void)
|
|||
|
||||
major = minor = 0;
|
||||
|
||||
outb(0x00, LED_LATCH_ADDRESS);
|
||||
|
||||
register_timer_isr (enet_timer_isr);
|
||||
|
||||
printf("Serck Controls eNET\n");
|
||||
|
||||
return 0;
|
||||
|
@ -172,3 +182,84 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
|
|||
} else
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
||||
void setup_pcat_compatibility()
|
||||
{
|
||||
/* disable global interrupt mode */
|
||||
writeb(0x40, &sc520_mmcr->picicr);
|
||||
|
||||
/* set all irqs to edge */
|
||||
writeb(0x00, &sc520_mmcr->pic_mode[0]);
|
||||
writeb(0x00, &sc520_mmcr->pic_mode[1]);
|
||||
writeb(0x00, &sc520_mmcr->pic_mode[2]);
|
||||
|
||||
/*
|
||||
* active low polarity on PIC interrupt pins,
|
||||
* active high polarity on all other irq pins
|
||||
*/
|
||||
writew(0x0000,&sc520_mmcr->intpinpol);
|
||||
|
||||
/* Set PIT 0 -> IRQ0, RTC -> IRQ8, FP error -> IRQ13 */
|
||||
writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
|
||||
writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
|
||||
writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
|
||||
|
||||
/* Disable all other interrupt sources */
|
||||
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
|
||||
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
|
||||
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
|
||||
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
|
||||
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
|
||||
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[0]); /* disable PCI INT A */
|
||||
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[1]); /* disable PCI INT B */
|
||||
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[2]); /* disable PCI INT C */
|
||||
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[3]); /* disable PCI INT D */
|
||||
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->dmabcintmap); /* disable DMA INT */
|
||||
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
|
||||
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
|
||||
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
|
||||
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
|
||||
}
|
||||
|
||||
void enet_timer_isr(void)
|
||||
{
|
||||
static long enet_ticks = 0;
|
||||
|
||||
enet_ticks++;
|
||||
|
||||
/* Toggle Watchdog every 100ms */
|
||||
if ((enet_ticks % 100) == 0)
|
||||
hw_watchdog_reset();
|
||||
|
||||
/* Toggle Run LED every 500ms */
|
||||
if ((enet_ticks % 500) == 0)
|
||||
enet_toggle_run_led();
|
||||
}
|
||||
|
||||
void hw_watchdog_reset(void)
|
||||
{
|
||||
/* Watchdog Reset must be atomic */
|
||||
long flag = disable_interrupts();
|
||||
|
||||
if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
|
||||
sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
|
||||
else
|
||||
sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;
|
||||
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
}
|
||||
|
||||
void enet_toggle_run_led(void)
|
||||
{
|
||||
unsigned char leds_state= inb(LED_LATCH_ADDRESS);
|
||||
if (leds_state & LED_RUN_BITMASK)
|
||||
outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS);
|
||||
else
|
||||
outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
|
||||
}
|
||||
|
|
|
@ -93,3 +93,36 @@ void pci_init_board(void)
|
|||
{
|
||||
pci_sc520_init(&enet_hose);
|
||||
}
|
||||
|
||||
int pci_set_regions(struct pci_controller *hose)
|
||||
{
|
||||
/* System memory space */
|
||||
pci_set_region(hose->regions + 0,
|
||||
SC520_PCI_MEMORY_BUS,
|
||||
SC520_PCI_MEMORY_PHYS,
|
||||
SC520_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
|
||||
|
||||
/* ISA/PCI memory space */
|
||||
pci_set_region(hose->regions + 1,
|
||||
SC520_ISA_MEM_BUS,
|
||||
SC520_ISA_MEM_PHYS,
|
||||
SC520_ISA_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* PCI I/O space */
|
||||
pci_set_region(hose->regions + 2,
|
||||
SC520_PCI_IO_BUS,
|
||||
SC520_PCI_IO_PHYS,
|
||||
SC520_PCI_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
/* ISA/PCI I/O space */
|
||||
pci_set_region(hose->regions + 3,
|
||||
SC520_ISA_IO_BUS,
|
||||
SC520_ISA_IO_PHYS,
|
||||
SC520_ISA_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
return 4;
|
||||
}
|
||||
|
|
|
@ -31,5 +31,6 @@
|
|||
#define LED_RX_BITMASK 0x08
|
||||
#define LED_TX_BITMASK 0x10
|
||||
#define LED_ERR_BITMASK 0x20
|
||||
#define WATCHDOG_PIO_BIT 0x8000
|
||||
|
||||
#endif /* HARDWARE_H_ */
|
||||
|
|
|
@ -27,7 +27,7 @@ ENTRY(_start)
|
|||
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x38040000; /* Location of bootcode in flash */
|
||||
. = 0x06000000; /* Location of bootcode in flash */
|
||||
_i386boot_text_start = .;
|
||||
.text : { *(.text); }
|
||||
|
||||
|
@ -97,14 +97,13 @@ SECTIONS
|
|||
* at reset and the code have to fit.
|
||||
* The fff0 offset of resetvec is important, however.
|
||||
*/
|
||||
|
||||
. = 0xfffffe00;
|
||||
.start32 : AT (0x3807fe00) { *(.start32); }
|
||||
.start32 : AT (0x0603fe00) { *(.start32); }
|
||||
|
||||
. = 0xf800;
|
||||
.start16 : AT (0x3807f800) { *(.start16); }
|
||||
.start16 : AT (0x0603f800) { *(.start16); }
|
||||
|
||||
. = 0xfff0;
|
||||
.resetvec : AT (0x3807fff0) { *(.resetvec); }
|
||||
.resetvec : AT (0x0603fff0) { *(.resetvec); }
|
||||
_i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) );
|
||||
}
|
||||
|
|
|
@ -1090,3 +1090,15 @@ U_BOOT_CMD(
|
|||
"Show Marvell strapping register",
|
||||
"Show Marvell strapping register (ResetSampleLow ResetSampleHigh)"
|
||||
);
|
||||
|
||||
int do_pldver(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
printf("PLD version:0x%02x\n", in_8((void *)CONFIG_SYS_PLD_VER));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
pldver, 1, 1, do_pldver,
|
||||
"Show PLD version",
|
||||
"Show PLD version)");
|
||||
|
|
|
@ -538,14 +538,14 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
|
|||
break;
|
||||
/*------------------------------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
#ifdef CONFIG_ECC
|
||||
#ifdef CONFIG_MV64360_ECC
|
||||
case 11: /* Error Check Type */
|
||||
dimmInfo->errorCheckType = data[i];
|
||||
DP (printf
|
||||
("Error Check Type (0=NONE): %d\n",
|
||||
dimmInfo->errorCheckType));
|
||||
break;
|
||||
#endif
|
||||
#endif /* of ifdef CONFIG_MV64360_ECC */
|
||||
/*------------------------------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
case 12: /* Refresh Interval */
|
||||
|
@ -1254,6 +1254,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
|
|||
ulong tmp;
|
||||
ulong tmp_sdram_mode = 0; /* 0x141c */
|
||||
ulong tmp_dunit_control_low = 0; /* 0x1404 */
|
||||
uint sdram_config_reg = CONFIG_SYS_SDRAM_CONFIG;
|
||||
int i;
|
||||
|
||||
/* sanity checking */
|
||||
|
@ -1269,7 +1270,6 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
|
|||
DP (printf
|
||||
("Module is registered, but we do not support registered Modules !!!\n"));
|
||||
|
||||
|
||||
/* delay line */
|
||||
set_dfcdlInit (); /* may be its not needed */
|
||||
DP (printf ("Delay line set done\n"));
|
||||
|
@ -1281,8 +1281,16 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
|
|||
("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MV64360_ECC
|
||||
if ((info->errorCheckType == 0x2) && (CPCI750_ECC_TEST)) {
|
||||
/* DRAM has ECC, so turn it on */
|
||||
sdram_config_reg |= BIT18;
|
||||
DP(printf("Enabling ECC\n"));
|
||||
}
|
||||
#endif /* of ifdef CONFIG_MV64360_ECC */
|
||||
|
||||
/* SDRAM configuration */
|
||||
GT_REG_WRITE (SDRAM_CONFIG, 0x58200400);
|
||||
GT_REG_WRITE(SDRAM_CONFIG, sdram_config_reg);
|
||||
DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)));
|
||||
|
||||
/* SDRAM open pages controll keep open as much as I can */
|
||||
|
@ -1598,7 +1606,84 @@ dram_size(long int *base, long int maxsize)
|
|||
return maxsize;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
#ifdef CONFIG_MV64360_ECC
|
||||
/*
|
||||
* mv_dma_is_channel_active:
|
||||
* Checks if a engine is busy.
|
||||
*/
|
||||
int mv_dma_is_channel_active(int engine)
|
||||
{
|
||||
ulong data;
|
||||
|
||||
data = GTREGREAD(MV64360_DMA_CHANNEL0_CONTROL + 4 * engine);
|
||||
if (data & BIT14) /* activity status */
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* mv_dma_set_memory_space:
|
||||
* Set a DMA memory window for the DMA's address decoding map.
|
||||
*/
|
||||
int mv_dma_set_memory_space(ulong mem_space, ulong mem_space_target,
|
||||
ulong mem_space_attr, ulong base_address,
|
||||
ulong size)
|
||||
{
|
||||
ulong temp;
|
||||
|
||||
/* The base address must be aligned to the size. */
|
||||
if (base_address % size != 0)
|
||||
return 0;
|
||||
|
||||
if (size >= 0x10000) {
|
||||
size &= 0xffff0000;
|
||||
base_address = (base_address & 0xffff0000);
|
||||
/* Set the new attributes */
|
||||
GT_REG_WRITE(MV64360_DMA_BASE_ADDR_REG0 + mem_space * 8,
|
||||
(base_address | mem_space_target |
|
||||
mem_space_attr));
|
||||
GT_REG_WRITE((MV64360_DMA_SIZE_REG0 + mem_space * 8),
|
||||
(size - 1) & 0xffff0000);
|
||||
temp = GTREGREAD(MV64360_DMA_BASE_ADDR_ENABLE_REG);
|
||||
GT_REG_WRITE(DMA_BASE_ADDR_ENABLE_REG,
|
||||
(temp & ~(BIT0 << mem_space)));
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* mv_dma_transfer:
|
||||
* Transfer data from source_addr to dest_addr on one of the 4 DMA channels.
|
||||
*/
|
||||
int mv_dma_transfer(int engine, ulong source_addr,
|
||||
ulong dest_addr, ulong bytes, ulong command)
|
||||
{
|
||||
ulong eng_off_reg; /* Engine Offset Register */
|
||||
|
||||
if (bytes > 0xffff)
|
||||
command = command | BIT31; /* DMA_16M_DESCRIPTOR_MODE */
|
||||
|
||||
command = command | ((command >> 6) & 0x7);
|
||||
eng_off_reg = engine * 4;
|
||||
GT_REG_WRITE(MV64360_DMA_CHANNEL0_BYTE_COUNT + eng_off_reg,
|
||||
bytes);
|
||||
GT_REG_WRITE(MV64360_DMA_CHANNEL0_SOURCE_ADDR + eng_off_reg,
|
||||
source_addr);
|
||||
GT_REG_WRITE(MV64360_DMA_CHANNEL0_DESTINATION_ADDR + eng_off_reg,
|
||||
dest_addr);
|
||||
command |= BIT12 /* DMA_CHANNEL_ENABLE */
|
||||
| BIT9; /* DMA_NON_CHAIN_MODE */
|
||||
|
||||
/* Activate DMA engine By writting to mv_dma_control_register */
|
||||
GT_REG_WRITE(MV64360_DMA_CHANNEL0_CONTROL + eng_off_reg, command);
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif /* of ifdef CONFIG_MV64360_ECC */
|
||||
|
||||
/* ppcboot interface function to SDRAM init - this is where all the
|
||||
* controlling logic happens */
|
||||
|
@ -1607,10 +1692,13 @@ initdram(int board_type)
|
|||
{
|
||||
int s0 = 0, s1 = 0;
|
||||
int checkbank[4] = { [0 ... 3] = 0 };
|
||||
ulong bank_no, realsize, total, check;
|
||||
ulong realsize, total, check;
|
||||
AUX_MEM_DIMM_INFO dimmInfo1;
|
||||
AUX_MEM_DIMM_INFO dimmInfo2;
|
||||
int nhr;
|
||||
int bank_no, nhr;
|
||||
#ifdef CONFIG_MV64360_ECC
|
||||
ulong dest, mem_space_attr;
|
||||
#endif /* of ifdef CONFIG_MV64360_ECC */
|
||||
|
||||
/* first, use the SPD to get info about the SDRAM/ DDRRAM */
|
||||
|
||||
|
@ -1668,6 +1756,28 @@ initdram(int board_type)
|
|||
realsize = dram_size((long int *)total, check);
|
||||
memory_map_bank(bank_no, total, realsize);
|
||||
|
||||
#ifdef CONFIG_MV64360_ECC
|
||||
if (((dimmInfo1.errorCheckType != 0) &&
|
||||
((dimmInfo2.errorCheckType != 0) ||
|
||||
(dimmInfo2.numOfModuleBanks == 0))) &&
|
||||
(CPCI750_ECC_TEST)) {
|
||||
printf("ECC Initialization of Bank %d:", bank_no);
|
||||
mem_space_attr = ((~(BIT0 << bank_no)) & 0xf) << 8;
|
||||
mv_dma_set_memory_space(0, 0, mem_space_attr, total,
|
||||
realsize);
|
||||
for (dest = total; dest < total + realsize;
|
||||
dest += _8M) {
|
||||
mv_dma_transfer(0, total, dest, _8M,
|
||||
BIT8 | /* DMA_DTL_128BYTES */
|
||||
BIT3 | /* DMA_HOLD_SOURCE_ADDR */
|
||||
BIT11); /* DMA_BLOCK_TRANSFER_MODE */
|
||||
while (mv_dma_is_channel_active(0))
|
||||
;
|
||||
}
|
||||
printf(" PASS\n");
|
||||
}
|
||||
#endif /* of ifdef CONFIG_MV64360_ECC */
|
||||
|
||||
total += realsize;
|
||||
}
|
||||
|
||||
|
@ -1700,3 +1810,30 @@ int set_dfcdlInit (void)
|
|||
|
||||
return (0);
|
||||
}
|
||||
|
||||
int do_show_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
unsigned int ecc_counter;
|
||||
unsigned int ecc_addr;
|
||||
|
||||
GT_REG_READ(0x1458, &ecc_counter);
|
||||
GT_REG_READ(0x1450, &ecc_addr);
|
||||
GT_REG_WRITE(0x1450, 0);
|
||||
|
||||
printf("Error Counter since Reset: %8d\n", ecc_counter);
|
||||
printf("Last error address :0x%08x (" , ecc_addr & 0xfffffff8);
|
||||
if (ecc_addr & 0x01)
|
||||
printf("double");
|
||||
else
|
||||
printf("single");
|
||||
printf(" bit) at DDR-RAM CS#%d\n", ((ecc_addr & 0x6) >> 1));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
U_BOOT_CMD(
|
||||
show_ecc, 1, 1, do_show_ecc,
|
||||
"Show Marvell MV64360 ECC Info",
|
||||
"Show Marvell MV64360 ECC Counter and last error."
|
||||
);
|
||||
|
|
|
@ -25,4 +25,4 @@
|
|||
# esd PLU405 boards
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xFFFA0000
|
||||
TEXT_BASE = 0xFFF80000
|
||||
|
|
|
@ -29,18 +29,18 @@ endif
|
|||
|
||||
LIB = $(obj)lib$(VENDOR).a
|
||||
|
||||
COBJS-${CONFIG_FSL_CADMUS} += cadmus.o
|
||||
COBJS-${CONFIG_FSL_VIA} += cds_via.o
|
||||
COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o
|
||||
COBJS-${CONFIG_FSL_PIXIS} += pixis.o
|
||||
COBJS-${CONFIG_FSL_NGPIXIS} += ngpixis.o
|
||||
COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o
|
||||
COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o
|
||||
COBJS-${CONFIG_FSL_SGMII_RISER} += sgmii_riser.o
|
||||
COBJS-$(CONFIG_FSL_CADMUS) += cadmus.o
|
||||
COBJS-$(CONFIG_FSL_VIA) += cds_via.o
|
||||
COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o fsl_logo_bmp.o
|
||||
COBJS-$(CONFIG_FSL_PIXIS) += pixis.o
|
||||
COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
|
||||
COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o
|
||||
COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o
|
||||
COBJS-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o
|
||||
|
||||
COBJS-${CONFIG_MPC8541CDS} += cds_pci_ft.o
|
||||
COBJS-${CONFIG_MPC8548CDS} += cds_pci_ft.o
|
||||
COBJS-${CONFIG_MPC8555CDS} += cds_pci_ft.o
|
||||
COBJS-$(CONFIG_MPC8541CDS) += cds_pci_ft.o
|
||||
COBJS-$(CONFIG_MPC8548CDS) += cds_pci_ft.o
|
||||
COBJS-$(CONFIG_MPC8555CDS) += cds_pci_ft.o
|
||||
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2007 Freescale Semiconductor, Inc.
|
||||
* Copyright 2007, 2010 Freescale Semiconductor, Inc.
|
||||
* York Sun <yorksun@freescale.com>
|
||||
*
|
||||
* FSL DIU Framebuffer driver
|
||||
|
@ -26,6 +26,7 @@
|
|||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <malloc.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include "fsl_diu_fb.h"
|
||||
|
||||
|
@ -267,9 +268,9 @@ int fsl_diu_init(int xres,
|
|||
|
||||
memset(info->screen_base, 0, info->smem_len);
|
||||
|
||||
dr.diu_reg->desc[0] = (unsigned int) &dummy_ad;
|
||||
dr.diu_reg->desc[1] = (unsigned int) &dummy_ad;
|
||||
dr.diu_reg->desc[2] = (unsigned int) &dummy_ad;
|
||||
out_be32(&dr.diu_reg->desc[0], (int)&dummy_ad);
|
||||
out_be32(&dr.diu_reg->desc[1], (int)&dummy_ad);
|
||||
out_be32(&dr.diu_reg->desc[2], (int)&dummy_ad);
|
||||
debug("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]);
|
||||
debug("dummy desc[0] = 0x%x\n", hw->desc[0]);
|
||||
|
||||
|
@ -331,26 +332,26 @@ int fsl_diu_init(int xres,
|
|||
|
||||
/* Program DIU registers */
|
||||
|
||||
hw->gamma = (unsigned int) gamma.paddr;
|
||||
hw->cursor= (unsigned int) cursor.paddr;
|
||||
hw->bgnd = 0x007F7F7F; /* BGND */
|
||||
hw->bgnd_wb = 0; /* BGND_WB */
|
||||
hw->disp_size = var->yres << 16 | var->xres; /* DISP SIZE */
|
||||
hw->wb_size = 0; /* WB SIZE */
|
||||
hw->wb_mem_addr = 0; /* WB MEM ADDR */
|
||||
hw->hsyn_para = var->left_margin << 22 | /* BP_H */
|
||||
out_be32(&hw->gamma, (int)gamma.paddr);
|
||||
out_be32(&hw->cursor, (int)cursor.paddr);
|
||||
out_be32(&hw->bgnd, 0x007F7F7F);
|
||||
out_be32(&hw->bgnd_wb, 0); /* BGND_WB */
|
||||
out_be32(&hw->disp_size, var->yres << 16 | var->xres); /* DISP SIZE */
|
||||
out_be32(&hw->wb_size, 0); /* WB SIZE */
|
||||
out_be32(&hw->wb_mem_addr, 0); /* WB MEM ADDR */
|
||||
out_be32(&hw->hsyn_para, var->left_margin << 22 | /* BP_H */
|
||||
var->hsync_len << 11 | /* PW_H */
|
||||
var->right_margin; /* FP_H */
|
||||
hw->vsyn_para = var->upper_margin << 22 | /* BP_V */
|
||||
var->right_margin); /* FP_H */
|
||||
|
||||
out_be32(&hw->vsyn_para, var->upper_margin << 22 | /* BP_V */
|
||||
var->vsync_len << 11 | /* PW_V */
|
||||
var->lower_margin; /* FP_V */
|
||||
|
||||
hw->syn_pol = 0; /* SYNC SIGNALS POLARITY */
|
||||
hw->thresholds = 0x00037800; /* The Thresholds */
|
||||
hw->int_status = 0; /* INTERRUPT STATUS */
|
||||
hw->int_mask = 0; /* INT MASK */
|
||||
hw->plut = 0x01F5F666;
|
||||
var->lower_margin); /* FP_V */
|
||||
|
||||
out_be32(&hw->syn_pol, 0); /* SYNC SIGNALS POLARITY */
|
||||
out_be32(&hw->thresholds, 0x00037800); /* The Thresholds */
|
||||
out_be32(&hw->int_status, 0); /* INTERRUPT STATUS */
|
||||
out_be32(&hw->int_mask, 0); /* INT MASK */
|
||||
out_be32(&hw->plut, 0x01F5F666);
|
||||
/* Pixel Clock configuration */
|
||||
debug("DIU pixclock in ps - %d\n", var->pixclock);
|
||||
diu_set_pixel_clock(var->pixclock);
|
||||
|
@ -390,8 +391,8 @@ static int fsl_diu_enable_panel(struct fb_info *info)
|
|||
struct diu_ad *ad = &fsl_diu_fb_ad;
|
||||
|
||||
debug("Entered: enable_panel\n");
|
||||
if (hw->desc[0] != (unsigned int)ad)
|
||||
hw->desc[0] = (unsigned int)ad;
|
||||
if (in_be32(&hw->desc[0]) != (unsigned)ad)
|
||||
out_be32(&hw->desc[0], (unsigned)ad);
|
||||
debug("desc[0] = 0x%x\n", hw->desc[0]);
|
||||
return 0;
|
||||
}
|
||||
|
@ -401,8 +402,8 @@ static int fsl_diu_disable_panel(struct fb_info *info)
|
|||
struct diu *hw = dr.diu_reg;
|
||||
|
||||
debug("Entered: disable_panel\n");
|
||||
if (hw->desc[0] != (unsigned int)&dummy_ad)
|
||||
hw->desc[0] = (unsigned int)&dummy_ad;
|
||||
if (in_be32(&hw->desc[0]) != (unsigned)&dummy_ad)
|
||||
out_be32(&hw->desc[0], (unsigned)&dummy_ad);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -443,7 +444,7 @@ static void enable_lcdc(void)
|
|||
|
||||
debug("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled);
|
||||
if (!fb_enabled) {
|
||||
hw->diu_mode = dr.mode;
|
||||
out_be32(&hw->diu_mode, dr.mode);
|
||||
fb_enabled++;
|
||||
}
|
||||
debug("diu_mode = %d\n", hw->diu_mode);
|
||||
|
@ -455,7 +456,7 @@ static void disable_lcdc(void)
|
|||
|
||||
debug("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled);
|
||||
if (fb_enabled) {
|
||||
hw->diu_mode = 0;
|
||||
out_be32(&hw->diu_mode, 0);
|
||||
fb_enabled = 0;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -28,15 +28,7 @@
|
|||
#include <asm/mmu.h>
|
||||
|
||||
struct law_entry law_table[] = {
|
||||
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
|
||||
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
|
||||
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
|
||||
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_1),
|
||||
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
|
||||
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_2),
|
||||
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
|
||||
SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
|
||||
SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
|
||||
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
|
||||
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
|
||||
};
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2008-2009 Freescale Semiconductor, Inc.
|
||||
* Copyright 2008-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -30,6 +30,7 @@
|
|||
#include <asm/fsl_pci.h>
|
||||
#include <asm/fsl_ddr_sdram.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
#include <spd.h>
|
||||
#include <miiphy.h>
|
||||
#include <libfdt.h>
|
||||
|
@ -219,9 +220,13 @@ void pci_init_board(void)
|
|||
|
||||
puts("\n");
|
||||
#ifdef CONFIG_PCIE3
|
||||
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
|
||||
pcie_configured = is_serdes_configured(PCIE3);
|
||||
|
||||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
|
||||
set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
|
||||
LAW_TRGT_IF_PCIE_3);
|
||||
set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
|
||||
LAW_TRGT_IF_PCIE_3);
|
||||
SET_STD_PCIE_INFO(pci_info[num], 3);
|
||||
pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
|
||||
printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n",
|
||||
|
@ -239,9 +244,13 @@ void pci_init_board(void)
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE1
|
||||
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
|
||||
pcie_configured = is_serdes_configured(PCIE1);
|
||||
|
||||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||
set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M,
|
||||
LAW_TRGT_IF_PCIE_1);
|
||||
set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
|
||||
LAW_TRGT_IF_PCIE_1);
|
||||
SET_STD_PCIE_INFO(pci_info[num], 1);
|
||||
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
|
||||
printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n",
|
||||
|
@ -259,9 +268,13 @@ void pci_init_board(void)
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE2
|
||||
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
|
||||
pcie_configured = is_serdes_configured(PCIE2);
|
||||
|
||||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
|
||||
set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M,
|
||||
LAW_TRGT_IF_PCIE_2);
|
||||
set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
|
||||
LAW_TRGT_IF_PCIE_2);
|
||||
SET_STD_PCIE_INFO(pci_info[num], 2);
|
||||
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
|
||||
printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n",
|
||||
|
@ -285,6 +298,10 @@ void pci_init_board(void)
|
|||
pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
|
||||
|
||||
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
|
||||
set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M,
|
||||
LAW_TRGT_IF_PCI);
|
||||
set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K,
|
||||
LAW_TRGT_IF_PCI);
|
||||
SET_STD_PCI_INFO(pci_info[num], 1);
|
||||
pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
|
||||
printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
|
||||
|
@ -481,17 +498,6 @@ get_board_ddr_clk(ulong dummy)
|
|||
}
|
||||
#endif
|
||||
|
||||
int sata_initialize(void)
|
||||
{
|
||||
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
uint sdrs2_io_sel =
|
||||
(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
|
||||
if (sdrs2_io_sel & 0x04)
|
||||
return 1;
|
||||
|
||||
return __sata_initialize();
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#ifdef CONFIG_TSEC_ENET
|
||||
|
@ -540,15 +546,23 @@ void ft_board_setup(void *blob, bd_t *bd)
|
|||
|
||||
#ifdef CONFIG_PCI1
|
||||
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
|
||||
#else
|
||||
ft_fsl_pci_setup(blob, "pci0", NULL);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE2
|
||||
ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
|
||||
#else
|
||||
ft_fsl_pci_setup(blob, "pci1", NULL);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE2
|
||||
ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
|
||||
#else
|
||||
ft_fsl_pci_setup(blob, "pci2", NULL);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE1
|
||||
ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);
|
||||
#else
|
||||
ft_fsl_pci_setup(blob, "pci3", NULL);
|
||||
#endif
|
||||
#ifdef CONFIG_FSL_SGMII_RISER
|
||||
fsl_sgmii_riser_fdt_fixup(blob);
|
||||
|
|
|
@ -27,7 +27,7 @@ COBJS-y += $(BOARD).o
|
|||
COBJS-$(CONFIG_FSL_DDR2) += ddr.o
|
||||
COBJS-y += law.o
|
||||
|
||||
COBJS-${CONFIG_FSL_DIU_FB} += mpc8610hpcd_diu.o
|
||||
COBJS-$(CONFIG_FSL_DIU_FB) += mpc8610hpcd_diu.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2007-2009
|
||||
* (C) Copyright 2007-2010
|
||||
* Larry Johnson, lrj@acm.org
|
||||
*
|
||||
* (C) Copyright 2006-2007
|
||||
|
@ -417,7 +417,7 @@ int misc_init_r(void)
|
|||
* then connect the CompactFlash controller to the PowerPC USB
|
||||
* port.
|
||||
*/
|
||||
printf("Attaching CompactFalsh controller to PPC USB\n");
|
||||
printf("Attaching CompactFlash controller to PPC USB\n");
|
||||
out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02,
|
||||
in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02) | 0x10);
|
||||
} else {
|
||||
|
@ -425,7 +425,7 @@ int misc_init_r(void)
|
|||
printf("Warning: \"korat_usbcf\" is not set to a legal "
|
||||
"value (\"ppc\" or \"pci\")\n");
|
||||
|
||||
printf("Attaching CompactFalsh controller to PCI USB\n");
|
||||
printf("Attaching CompactFlash controller to PCI USB\n");
|
||||
}
|
||||
if (act == NULL || strcmp(act, "hostdev") == 0) {
|
||||
/* SDR Setting */
|
||||
|
|
|
@ -32,12 +32,13 @@ SOBJS := $(addprefix $(obj),$(SOBJS))
|
|||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
@mkimage -T script -C none -n M7_script -d bootscript $(obj)bootscript.img
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
rm -f $(LIB) core *.bak $(obj).depend $(obj)bootscript.img
|
||||
|
||||
#########################################################################
|
||||
|
||||
|
|
|
@ -36,13 +36,13 @@ SOBJS := $(addprefix $(obj),$(SOBJS))
|
|||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
@mkimage -T script -C none -n mvSMR_Script -d bootscript bootscript.img
|
||||
@mkimage -T script -C none -n mvSMR_Script -d bootscript $(obj)bootscript.img
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
rm -f $(LIB) core *.bak $(obj).depend $(obj)bootscript.img
|
||||
|
||||
#########################################################################
|
||||
|
||||
|
|
|
@ -55,11 +55,11 @@ SECTIONS
|
|||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the first two sectors (=8KB) of our S29GL flash chip */
|
||||
arch/powerpc/cpu/mpc5xxx/start.o (.text)
|
||||
arch/powerpc/cpu/mpc5xxx/traps.o (.text)
|
||||
lib/crc32.o (.text)
|
||||
arch/powerpc/lib/cache.o (.text)
|
||||
arch/powerpc/lib/time.o (.text)
|
||||
arch/powerpc/cpu/mpc5xxx/start.o (.text)
|
||||
arch/powerpc/cpu/mpc5xxx/traps.o (.text)
|
||||
lib/crc32.o (.text)
|
||||
arch/powerpc/lib/cache.o (.text)
|
||||
arch/powerpc/lib/time.o (.text)
|
||||
|
||||
/* This is only needed to force failure if size of above code will ever */
|
||||
/* increase and grow into reserved space. */
|
||||
|
|
53
board/mosaixtech/icon/Makefile
Normal file
53
board/mosaixtech/icon/Makefile
Normal file
|
@ -0,0 +1,53 @@
|
|||
#
|
||||
# (C) Copyright 2009-2010
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS-y := $(BOARD).o
|
||||
COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
|
||||
SOBJS = init.o
|
||||
|
||||
COBJS := $(COBJS-y)
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
55
board/mosaixtech/icon/chip_config.c
Normal file
55
board/mosaixtech/icon/chip_config.c
Normal file
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* (C) Copyright 2009-2010
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/ppc4xx_config.h>
|
||||
|
||||
struct ppc4xx_config ppc4xx_config_val[] = {
|
||||
{
|
||||
"400-133", "CPU: 400 PLB: 133 OPB: 66 EBC: 66",
|
||||
{ 0x86, 0x78, 0xc2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
|
||||
},
|
||||
{
|
||||
"500-166", "CPU: 500 PLB: 166 OPB: 83 EBC: 83",
|
||||
{ 0x87, 0x78, 0xf2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
|
||||
},
|
||||
{
|
||||
"533-133", "CPU: 533 PLB: 133 OPB: 66 EBC: 66",
|
||||
{ 0x87, 0x79, 0x02, 0x52, 0x05, 0xa5, 0x04, 0xe1 }
|
||||
},
|
||||
{
|
||||
"667-133", "CPU: 667 PLB: 133 OPB: 66 EBC: 66",
|
||||
{ 0x87, 0x79, 0x42, 0x56, 0x05, 0xa5, 0x04, 0xe1 }
|
||||
},
|
||||
{
|
||||
"667-166", "CPU: 667 PLB: 166 OPB: 83 EBC: 83",
|
||||
{ 0x87, 0x79, 0x42, 0x06, 0x05, 0xa5, 0x04, 0xe1 }
|
||||
},
|
||||
{
|
||||
"800-160", "CPU: 800 PLB: 160 OPB: 53 EBC: 17",
|
||||
{ 0x86, 0x79, 0x81, 0xa7, 0x07, 0xa5, 0x04, 0xe1 }
|
||||
},
|
||||
};
|
||||
|
||||
int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
|
34
board/mosaixtech/icon/config.mk
Normal file
34
board/mosaixtech/icon/config.mk
Normal file
|
@ -0,0 +1,34 @@
|
|||
#
|
||||
# (C) Copyright 2009-2010
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xFFFA0000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
|
||||
ifeq ($(debug),1)
|
||||
PLATFORM_CPPFLAGS += -DDEBUG
|
||||
endif
|
||||
|
||||
ifeq ($(dbcr),1)
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
|
||||
endif
|
319
board/mosaixtech/icon/icon.c
Normal file
319
board/mosaixtech/icon/icon.c
Normal file
|
@ -0,0 +1,319 @@
|
|||
/*
|
||||
* (C) Copyright 2009-2010
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ppc4xx.h>
|
||||
#include <i2c.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/4xx_pcie.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
unsigned long mfr;
|
||||
|
||||
/*
|
||||
* Interrupt controller setup for the ICON 440SPe board.
|
||||
*
|
||||
*--------------------------------------------------------------------
|
||||
* IRQ | Source | Pol. | Sensi.| Crit.
|
||||
*--------+-----------------------------------+-------+-------+-------
|
||||
* IRQ 00 | UART0 | High | Level | Non
|
||||
* IRQ 01 | UART1 | High | Level | Non
|
||||
* IRQ 02 | IIC0 | High | Level | Non
|
||||
* IRQ 03 | IIC1 | High | Level | Non
|
||||
* IRQ 04 | PCI0X0 MSG IN | High | Level | Non
|
||||
* IRQ 05 | PCI0X0 CMD Write | High | Level | Non
|
||||
* IRQ 06 | PCI0X0 Power Mgt | High | Level | Non
|
||||
* IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non
|
||||
* IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non
|
||||
* IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non
|
||||
* IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non
|
||||
* IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit
|
||||
* IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non
|
||||
* IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non
|
||||
* IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non
|
||||
* IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non
|
||||
* IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non
|
||||
* IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit
|
||||
* IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non
|
||||
* IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non
|
||||
* IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non
|
||||
* IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non
|
||||
* IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non
|
||||
* IRQ 23 | I2O Inbound Doorbell | High | Level | Non
|
||||
* IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non
|
||||
* IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non
|
||||
* IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non
|
||||
* IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non
|
||||
* IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non
|
||||
* IRQ 29 | GPT Down Count Timer | Rising| Edge | Non
|
||||
* IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non
|
||||
* IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit.
|
||||
*--------------------------------------------------------------------
|
||||
* IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non
|
||||
* IRQ 33 | MAL Serr | High | Level | Non
|
||||
* IRQ 34 | MAL Txde | High | Level | Non
|
||||
* IRQ 35 | MAL Rxde | High | Level | Non
|
||||
* IRQ 36 | DMC CE or DMC UE | High | Level | Non
|
||||
* IRQ 37 | EBC or UART2 | High |Lvl Edg| Non
|
||||
* IRQ 38 | MAL TX EOB | High | Level | Non
|
||||
* IRQ 39 | MAL RX EOB | High | Level | Non
|
||||
* IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non
|
||||
* IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non
|
||||
* IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non
|
||||
* IRQ 43 | L2 Cache | Risin | Edge | Non
|
||||
* IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non
|
||||
* IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non
|
||||
* IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non
|
||||
* IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non
|
||||
* IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non
|
||||
* IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non
|
||||
* IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non
|
||||
* IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non
|
||||
* IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non
|
||||
* IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non
|
||||
* IRQ 54 | DMA Error | High | Level | Non
|
||||
* IRQ 55 | DMA I2O Error | High | Level | Non
|
||||
* IRQ 56 | Serial ROM | High | Level | Non
|
||||
* IRQ 57 | PCIX0 Error | High | Edge | Non
|
||||
* IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non
|
||||
* IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non
|
||||
* IRQ 60 | EMAC0 Interrupt | High | Level | Non
|
||||
* IRQ 61 | EMAC0 Wake-up | High | Level | Non
|
||||
* IRQ 62 | Reserved | High | Level | Non
|
||||
* IRQ 63 | XOR | High | Level | Non
|
||||
*--------------------------------------------------------------------
|
||||
* IRQ 64 | PE0 AL | High | Level | Non
|
||||
* IRQ 65 | PE0 VPD Access | Risin | Edge | Non
|
||||
* IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non
|
||||
* IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non
|
||||
* IRQ 68 | PE0 TCR | High | Level | Non
|
||||
* IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non
|
||||
* IRQ 70 | PE0 DCR Error | High | Level | Non
|
||||
* IRQ 71 | Reserved | N/A | N/A | Non
|
||||
* IRQ 72 | PE1 AL | High | Level | Non
|
||||
* IRQ 73 | PE1 VPD Access | Risin | Edge | Non
|
||||
* IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non
|
||||
* IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non
|
||||
* IRQ 76 | PE1 TCR | High | Level | Non
|
||||
* IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non
|
||||
* IRQ 78 | PE1 DCR Error | High | Level | Non
|
||||
* IRQ 79 | Reserved | N/A | N/A | Non
|
||||
* IRQ 80 | PE2 AL | High | Level | Non
|
||||
* IRQ 81 | PE2 VPD Access | Risin | Edge | Non
|
||||
* IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non
|
||||
* IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non
|
||||
* IRQ 84 | PE2 TCR | High | Level | Non
|
||||
* IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non
|
||||
* IRQ 86 | PE2 DCR Error | High | Level | Non
|
||||
* IRQ 87 | Reserved | N/A | N/A | Non
|
||||
* IRQ 88 | External IRQ(5) | Progr | Progr | Non
|
||||
* IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non
|
||||
* IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non
|
||||
* IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non
|
||||
* IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non
|
||||
* IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non
|
||||
* IRQ 94 | Reserved | N/A | N/A | Non
|
||||
* IRQ 95 | Reserved | N/A | N/A | Non
|
||||
*--------------------------------------------------------------------
|
||||
* IRQ 96 | PE0 INTA | High | Level | Non
|
||||
* IRQ 97 | PE0 INTB | High | Level | Non
|
||||
* IRQ 98 | PE0 INTC | High | Level | Non
|
||||
* IRQ 99 | PE0 INTD | High | Level | Non
|
||||
* IRQ 100| PE1 INTA | High | Level | Non
|
||||
* IRQ 101| PE1 INTB | High | Level | Non
|
||||
* IRQ 102| PE1 INTC | High | Level | Non
|
||||
* IRQ 103| PE1 INTD | High | Level | Non
|
||||
* IRQ 104| PE2 INTA | High | Level | Non
|
||||
* IRQ 105| PE2 INTB | High | Level | Non
|
||||
* IRQ 106| PE2 INTC | High | Level | Non
|
||||
* IRQ 107| PE2 INTD | Risin | Edge | Non
|
||||
* IRQ 108| PCI Express MSI Level 4 | Risin | Edge | Non
|
||||
* IRQ 109| PCI Express MSI Level 5 | Risin | Edge | Non
|
||||
* IRQ 110| PCI Express MSI Level 6 | Risin | Edge | Non
|
||||
* IRQ 111| PCI Express MSI Level 7 | Risin | Edge | Non
|
||||
* IRQ 116| PCI Express MSI Level 12 | Risin | Edge | Non
|
||||
* IRQ 112| PCI Express MSI Level 8 | Risin | Edge | Non
|
||||
* IRQ 113| PCI Express MSI Level 9 | Risin | Edge | Non
|
||||
* IRQ 114| PCI Express MSI Level 10 | Risin | Edge | Non
|
||||
* IRQ 115| PCI Express MSI Level 11 | Risin | Edge | Non
|
||||
* IRQ 117| PCI Express MSI Level 13 | Risin | Edge | Non
|
||||
* IRQ 118| PCI Express MSI Level 14 | Risin | Edge | Non
|
||||
* IRQ 119| PCI Express MSI Level 15 | Risin | Edge | Non
|
||||
* IRQ 120| PCI Express MSI Level 16 | Risin | Edge | Non
|
||||
* IRQ 121| PCI Express MSI Level 17 | Risin | Edge | Non
|
||||
* IRQ 122| PCI Express MSI Level 18 | Risin | Edge | Non
|
||||
* IRQ 123| PCI Express MSI Level 19 | Risin | Edge | Non
|
||||
* IRQ 124| PCI Express MSI Level 20 | Risin | Edge | Non
|
||||
* IRQ 125| PCI Express MSI Level 21 | Risin | Edge | Non
|
||||
* IRQ 126| PCI Express MSI Level 22 | Risin | Edge | Non
|
||||
* IRQ 127| PCI Express MSI Level 23 | Risin | Edge | Non
|
||||
*/
|
||||
|
||||
/*
|
||||
* Put UICs in PowerPC 440SPe mode.
|
||||
* Initialise UIC registers. Clear all interrupts. Disable all
|
||||
* interrupts. Set critical interrupt values. Set interrupt polarities.
|
||||
* Set interrupt trigger levels. Make bit 0 High priority. Clear all
|
||||
* interrupts again.
|
||||
*/
|
||||
mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */
|
||||
mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */
|
||||
mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical IRQs */
|
||||
mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/
|
||||
mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
|
||||
mtdcr(UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */
|
||||
mtdcr(UIC3SR, 0x00000000); /* clear all interrupts*/
|
||||
mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts*/
|
||||
|
||||
mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
|
||||
mtdcr(UIC2ER, 0x00000000); /* disable all interrupts*/
|
||||
mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical IRQs */
|
||||
mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/
|
||||
mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
|
||||
mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */
|
||||
mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */
|
||||
mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
|
||||
|
||||
mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts*/
|
||||
mtdcr(UIC1ER, 0x00000000); /* disable all interrupts*/
|
||||
mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical IRQs */
|
||||
mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
|
||||
mtdcr(UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/
|
||||
mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */
|
||||
mtdcr(UIC1SR, 0x00000000); /* clear all interrupts*/
|
||||
mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts*/
|
||||
|
||||
mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
|
||||
mtdcr(UIC0ER, 0x00000000); /* disable all int. excepted cascade */
|
||||
mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical IRQs */
|
||||
mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/
|
||||
mtdcr(UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */
|
||||
mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */
|
||||
mtdcr(UIC0SR, 0x00000000); /* clear all interrupts*/
|
||||
mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts*/
|
||||
|
||||
mfsdr(SDR0_MFR, mfr);
|
||||
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
|
||||
mtsdr(SDR0_MFR, mfr);
|
||||
|
||||
mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
|
||||
|
||||
out_be32((void *)GPIO0_OR, CONFIG_SYS_GPIO_OR);
|
||||
out_be32((void *)GPIO0_ODR, CONFIG_SYS_GPIO_ODR);
|
||||
out_be32((void *)GPIO0_TCR, CONFIG_SYS_GPIO_TCR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
/*
|
||||
* ICON has 64MBytes of NOR FLASH (Spansion 29GL512), but the
|
||||
* boot EBC mapping only supports a maximum of 16MBytes
|
||||
* (4.ff00.0000 - 4.ffff.ffff).
|
||||
* To solve this problem, the FLASH has to get remapped to another
|
||||
* EBC address which accepts bigger regions:
|
||||
*
|
||||
* 0xfc00.0000 -> 4.ec00.0000
|
||||
*/
|
||||
|
||||
/* Remap the NOR FLASH to 0xec00.0000 ... 0xefff.ffff */
|
||||
mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
|
||||
|
||||
/* Remove TLB entry of boot EBC mapping */
|
||||
remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
|
||||
|
||||
/* Add TLB entry for 0xfc00.0000 -> 0x4.ec00.0000 */
|
||||
program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
|
||||
CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
|
||||
|
||||
/*
|
||||
* Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
|
||||
* 0xfc00.0000 is possible
|
||||
*/
|
||||
|
||||
/*
|
||||
* Clear potential errors resulting from auto-calibration.
|
||||
* If not done, then we could get an interrupt later on when
|
||||
* exceptions are enabled.
|
||||
*/
|
||||
set_mcsr(get_mcsr());
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
char *s = getenv("serial#");
|
||||
|
||||
printf("Board: ICON");
|
||||
if (s != NULL) {
|
||||
puts(", serial# ");
|
||||
puts(s);
|
||||
}
|
||||
putc('\n');
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
|
||||
* board specific values.
|
||||
*
|
||||
* Tested successfully with the following SODIMM:
|
||||
* Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
|
||||
*
|
||||
* Tests with Micron MT4HTF6464HZ-667H1 showed problems in "cold" state,
|
||||
* directly after power-up. Only after running for more than 10 minutes
|
||||
* real stable auto-calibration windows could be found.
|
||||
*/
|
||||
u32 ddr_wrdtr(u32 default_val)
|
||||
{
|
||||
return SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV;
|
||||
}
|
||||
|
||||
u32 ddr_clktr(u32 default_val)
|
||||
{
|
||||
return SDRAM_CLKTR_CLKP_180_DEG_ADV;
|
||||
}
|
||||
|
||||
/*
|
||||
* Override the weak default implementation and return the
|
||||
* last PCIe slot number (max number - 1).
|
||||
*/
|
||||
int board_pcie_last(void)
|
||||
{
|
||||
/* Only 2 PCIe ports used on ICON, so the last one is 1 */
|
||||
return 1;
|
||||
}
|
88
board/mosaixtech/icon/init.S
Normal file
88
board/mosaixtech/icon/init.S
Normal file
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* (C) Copyright 2009-2010
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <config.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
/*
|
||||
* TLB TABLE
|
||||
*
|
||||
* This table is used by the cpu boot code to setup the initial tlb
|
||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
||||
* this table lets each board set things up however they like.
|
||||
*
|
||||
* Pointer to the table is returned in r1
|
||||
*
|
||||
*/
|
||||
|
||||
.section .bootpg,"ax"
|
||||
|
||||
.globl tlbtab
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
|
||||
/*
|
||||
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
|
||||
* use the speed up boot process. It is patched after relocation to
|
||||
* enable SA_I.
|
||||
*/
|
||||
tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
|
||||
4, AC_RWX | SA_G) /* TLB 0 */
|
||||
|
||||
/*
|
||||
* TLB entries for SDRAM are not needed on this platform.
|
||||
* They are dynamically generated in the SPD DDR(2) detection
|
||||
* routine.
|
||||
*/
|
||||
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4,
|
||||
AC_RWX | SA_I)
|
||||
|
||||
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4,
|
||||
AC_RW | SA_IG)
|
||||
|
||||
tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K,
|
||||
CONFIG_SYS_ACE_BASE_PHYS_L, CONFIG_SYS_ACE_BASE_PHYS_H,
|
||||
AC_RW | SA_IG)
|
||||
|
||||
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
|
||||
AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC,
|
||||
AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD,
|
||||
AC_RW | SA_IG)
|
||||
|
||||
tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD,
|
||||
AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD,
|
||||
AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD,
|
||||
AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD,
|
||||
AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD,
|
||||
AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD,
|
||||
AC_RW | SA_IG)
|
||||
tlbtab_end
|
|
@ -29,16 +29,17 @@
|
|||
#include <mpc83xx.h>
|
||||
#include <ns16550.h>
|
||||
#include <nand.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: Sheldon Instruments SIMPC8313\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
static struct pci_region pci_regions[] = {
|
||||
{
|
||||
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
|
||||
|
@ -91,6 +92,40 @@ void pci_init_board(void)
|
|||
int misc_init_r(void)
|
||||
{
|
||||
int rc = 0;
|
||||
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
fsl_lbus_t *lbus = &immap->lbus;
|
||||
u32 *mxmr = &lbus->mamr; /* Pointer to mamr */
|
||||
|
||||
/* UPM Table Configuration Code */
|
||||
static uint UPMATable[] = {
|
||||
/* Read Single-Beat (RSS) */
|
||||
0x0fff0c00, 0x0fffdc00, 0x0fff0c05, 0xfffffc00,
|
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
|
||||
/* Read Burst (RBS) */
|
||||
0x0fff0c00, 0x0ffcdc00, 0x0ffc0c00, 0x0ffc0f0c,
|
||||
0x0ffccf0c, 0x0ffc0f0c, 0x0ffcce0c, 0x3ffc0c05,
|
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
|
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
|
||||
/* Write Single-Beat (WSS) */
|
||||
0x0ffc0c00, 0x0ffcdc00, 0x0ffc0c05, 0xfffffc00,
|
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
|
||||
/* Write Burst (WBS) */
|
||||
0x0ffc0c00, 0x0fffcc0c, 0x0fff0c00, 0x0fffcc00,
|
||||
0x0fff1c00, 0x0fffcf0c, 0x0fff0f0c, 0x0fffcf0c,
|
||||
0x0fff0c0c, 0x0fffcc0c, 0x0fff0c05, 0xfffffc00,
|
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
|
||||
/* Refresh Timer (RTS) */
|
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
|
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
|
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
|
||||
/* Exception Condition (EXS) */
|
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
|
||||
};
|
||||
|
||||
upmconfig(UPMA, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
|
||||
|
||||
/* Set LUPWAIT to be active low and enabled */
|
||||
out_be32(mxmr, MxMR_UWPL | MxMR_GPL_x4DIS);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
|
|
@ -344,11 +344,8 @@ static int bootm_load_os(image_info_t os, ulong *load_end, int boot_progress)
|
|||
printf (" XIP %s ... ", type_name);
|
||||
} else {
|
||||
printf (" Loading %s ... ", type_name);
|
||||
|
||||
if (load != image_start) {
|
||||
memmove_wd ((void *)load,
|
||||
(void *)image_start, image_len, CHUNKSZ);
|
||||
}
|
||||
memmove_wd ((void *)load, (void *)image_start,
|
||||
image_len, CHUNKSZ);
|
||||
}
|
||||
*load_end = load + image_len;
|
||||
puts("OK\n");
|
||||
|
|
|
@ -34,7 +34,7 @@
|
|||
#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_CMD_MTDPARTS)
|
||||
#include <jffs2/jffs2.h>
|
||||
|
||||
/* parition handling routines */
|
||||
/* partition handling routines */
|
||||
int mtdparts_init(void);
|
||||
int mtd_id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num);
|
||||
int find_dev_and_part(const char *id, struct mtd_device **dev,
|
||||
|
@ -368,7 +368,7 @@ int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
addr_first = part->offset + info->start[0];
|
||||
addr_last = addr_first + part->size - 1;
|
||||
|
||||
printf ("Erase Flash Parition %s, "
|
||||
printf ("Erase Flash Partition %s, "
|
||||
"bank %ld, 0x%08lx - 0x%08lx ",
|
||||
argv[1], bank, addr_first,
|
||||
addr_last);
|
||||
|
@ -576,7 +576,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
addr_first = part->offset + info->start[0];
|
||||
addr_last = addr_first + part->size - 1;
|
||||
|
||||
printf ("%sProtect Flash Parition %s, "
|
||||
printf ("%sProtect Flash Partition %s, "
|
||||
"bank %ld, 0x%08lx - 0x%08lx\n",
|
||||
p ? "" : "Un", argv[1],
|
||||
bank, addr_first, addr_last);
|
||||
|
|
|
@ -103,16 +103,6 @@
|
|||
#include <onenand_uboot.h>
|
||||
#endif
|
||||
|
||||
/* enable/disable debugging messages */
|
||||
#define DEBUG_MTDPARTS
|
||||
#undef DEBUG_MTDPARTS
|
||||
|
||||
#ifdef DEBUG_MTDPARTS
|
||||
# define DEBUGF(fmt, args...) printf(fmt ,##args)
|
||||
#else
|
||||
# define DEBUGF(fmt, args...)
|
||||
#endif
|
||||
|
||||
/* special size referring to all the remaining space in a partition */
|
||||
#define SIZE_REMAINING 0xFFFFFFFF
|
||||
|
||||
|
@ -243,7 +233,7 @@ static void index_partitions(void)
|
|||
struct list_head *dentry;
|
||||
struct mtd_device *dev;
|
||||
|
||||
DEBUGF("--- index partitions ---\n");
|
||||
debug("--- index partitions ---\n");
|
||||
|
||||
if (current_mtd_dev) {
|
||||
mtddevnum = 0;
|
||||
|
@ -261,12 +251,12 @@ static void index_partitions(void)
|
|||
part = mtd_part_info(current_mtd_dev, current_mtd_partnum);
|
||||
setenv("mtddevname", part->name);
|
||||
|
||||
DEBUGF("=> mtddevnum %d,\n=> mtddevname %s\n", mtddevnum, part->name);
|
||||
debug("=> mtddevnum %d,\n=> mtddevname %s\n", mtddevnum, part->name);
|
||||
} else {
|
||||
setenv("mtddevnum", NULL);
|
||||
setenv("mtddevname", NULL);
|
||||
|
||||
DEBUGF("=> mtddevnum NULL\n=> mtddevname NULL\n");
|
||||
debug("=> mtddevnum NULL\n=> mtddevname NULL\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -277,7 +267,7 @@ static void current_save(void)
|
|||
{
|
||||
char buf[16];
|
||||
|
||||
DEBUGF("--- current_save ---\n");
|
||||
debug("--- current_save ---\n");
|
||||
|
||||
if (current_mtd_dev) {
|
||||
sprintf(buf, "%s%d,%d", MTD_DEV_TYPE(current_mtd_dev->id->type),
|
||||
|
@ -286,12 +276,12 @@ static void current_save(void)
|
|||
setenv("partition", buf);
|
||||
strncpy(last_partition, buf, 16);
|
||||
|
||||
DEBUGF("=> partition %s\n", buf);
|
||||
debug("=> partition %s\n", buf);
|
||||
} else {
|
||||
setenv("partition", NULL);
|
||||
last_partition[0] = '\0';
|
||||
|
||||
DEBUGF("=> partition NULL\n");
|
||||
debug("=> partition NULL\n");
|
||||
}
|
||||
index_partitions();
|
||||
}
|
||||
|
@ -505,7 +495,7 @@ static int part_sort_add(struct mtd_device *dev, struct part_info *part)
|
|||
part->dev = dev;
|
||||
|
||||
if (list_empty(&dev->parts)) {
|
||||
DEBUGF("part_sort_add: list empty\n");
|
||||
debug("part_sort_add: list empty\n");
|
||||
list_add(&part->link, &dev->parts);
|
||||
dev->num_parts++;
|
||||
index_partitions();
|
||||
|
@ -598,7 +588,7 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i
|
|||
/* fetch the partition size */
|
||||
if (*p == '-') {
|
||||
/* assign all remaining space to this partition */
|
||||
DEBUGF("'-': remaining size assigned\n");
|
||||
debug("'-': remaining size assigned\n");
|
||||
size = SIZE_REMAINING;
|
||||
p++;
|
||||
} else {
|
||||
|
@ -683,7 +673,7 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i
|
|||
part->name[name_len - 1] = '\0';
|
||||
INIT_LIST_HEAD(&part->link);
|
||||
|
||||
DEBUGF("+ partition: name %-22s size 0x%08x offset 0x%08x mask flags %d\n",
|
||||
debug("+ partition: name %-22s size 0x%08x offset 0x%08x mask flags %d\n",
|
||||
part->name, part->size,
|
||||
part->offset, part->mask_flags);
|
||||
|
||||
|
@ -837,14 +827,16 @@ static int device_parse(const char *const mtd_dev, const char **ret, struct mtd_
|
|||
u32 offset;
|
||||
int err = 1;
|
||||
|
||||
p = mtd_dev;
|
||||
*retdev = NULL;
|
||||
*ret = NULL;
|
||||
debug("===device_parse===\n");
|
||||
|
||||
DEBUGF("===device_parse===\n");
|
||||
assert(retdev);
|
||||
*retdev = NULL;
|
||||
|
||||
if (ret)
|
||||
*ret = NULL;
|
||||
|
||||
/* fetch <mtd-id> */
|
||||
mtd_id = p;
|
||||
mtd_id = p = mtd_dev;
|
||||
if (!(p = strchr(mtd_id, ':'))) {
|
||||
printf("no <mtd-id> identifier\n");
|
||||
return 1;
|
||||
|
@ -858,11 +850,11 @@ static int device_parse(const char *const mtd_dev, const char **ret, struct mtd_
|
|||
return 1;
|
||||
}
|
||||
|
||||
DEBUGF("dev type = %d (%s), dev num = %d, mtd-id = %s\n",
|
||||
debug("dev type = %d (%s), dev num = %d, mtd-id = %s\n",
|
||||
id->type, MTD_DEV_TYPE(id->type),
|
||||
id->num, id->mtd_id);
|
||||
pend = strchr(p, ';');
|
||||
DEBUGF("parsing partitions %.*s\n", (pend ? pend - p : strlen(p)), p);
|
||||
debug("parsing partitions %.*s\n", (pend ? pend - p : strlen(p)), p);
|
||||
|
||||
|
||||
/* parse partitions */
|
||||
|
@ -908,17 +900,20 @@ static int device_parse(const char *const mtd_dev, const char **ret, struct mtd_
|
|||
return 1;
|
||||
}
|
||||
|
||||
DEBUGF("\ntotal partitions: %d\n", num_parts);
|
||||
debug("\ntotal partitions: %d\n", num_parts);
|
||||
|
||||
/* check for next device presence */
|
||||
if (p) {
|
||||
if (*p == ';') {
|
||||
*ret = ++p;
|
||||
if (ret)
|
||||
*ret = ++p;
|
||||
} else if (*p == '\0') {
|
||||
*ret = p;
|
||||
if (ret)
|
||||
*ret = p;
|
||||
} else {
|
||||
printf("unexpected character '%c' at the end of device\n", *p);
|
||||
*ret = NULL;
|
||||
if (ret)
|
||||
*ret = NULL;
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
@ -946,7 +941,7 @@ static int device_parse(const char *const mtd_dev, const char **ret, struct mtd_
|
|||
|
||||
*retdev = dev;
|
||||
|
||||
DEBUGF("===\n\n");
|
||||
debug("===\n\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -998,13 +993,13 @@ static struct mtdids* id_find_by_mtd_id(const char *mtd_id, unsigned int mtd_id_
|
|||
struct list_head *entry;
|
||||
struct mtdids *id;
|
||||
|
||||
DEBUGF("--- id_find_by_mtd_id: '%.*s' (len = %d)\n",
|
||||
debug("--- id_find_by_mtd_id: '%.*s' (len = %d)\n",
|
||||
mtd_id_len, mtd_id, mtd_id_len);
|
||||
|
||||
list_for_each(entry, &mtdids) {
|
||||
id = list_entry(entry, struct mtdids, link);
|
||||
|
||||
DEBUGF("entry: '%s' (len = %d)\n",
|
||||
debug("entry: '%s' (len = %d)\n",
|
||||
id->mtd_id, strlen(id->mtd_id));
|
||||
|
||||
if (mtd_id_len != strlen(id->mtd_id))
|
||||
|
@ -1074,7 +1069,7 @@ static int generate_mtdparts(char *buf, u32 buflen)
|
|||
u32 size, offset, len, part_cnt;
|
||||
u32 maxlen = buflen - 1;
|
||||
|
||||
DEBUGF("--- generate_mtdparts ---\n");
|
||||
debug("--- generate_mtdparts ---\n");
|
||||
|
||||
if (list_empty(&devices)) {
|
||||
buf[0] = '\0';
|
||||
|
@ -1216,7 +1211,7 @@ static void list_partitions(void)
|
|||
struct mtd_device *dev;
|
||||
int part_num;
|
||||
|
||||
DEBUGF("\n---list_partitions---\n");
|
||||
debug("\n---list_partitions---\n");
|
||||
list_for_each(dentry, &devices) {
|
||||
dev = list_entry(dentry, struct mtd_device, link);
|
||||
printf("\ndevice %s%d <%s>, # parts = %d\n",
|
||||
|
@ -1281,7 +1276,7 @@ int find_dev_and_part(const char *id, struct mtd_device **dev,
|
|||
u8 type, dnum, pnum;
|
||||
const char *p;
|
||||
|
||||
DEBUGF("--- find_dev_and_part ---\nid = %s\n", id);
|
||||
debug("--- find_dev_and_part ---\nid = %s\n", id);
|
||||
|
||||
list_for_each(dentry, &devices) {
|
||||
*part_num = 0;
|
||||
|
@ -1342,7 +1337,7 @@ static int delete_partition(const char *id)
|
|||
|
||||
if (find_dev_and_part(id, &dev, &pnum, &part) == 0) {
|
||||
|
||||
DEBUGF("delete_partition: device = %s%d, partition %d = (%s) 0x%08x@0x%08x\n",
|
||||
debug("delete_partition: device = %s%d, partition %d = (%s) 0x%08x@0x%08x\n",
|
||||
MTD_DEV_TYPE(dev->id->type), dev->id->num, pnum,
|
||||
part->name, part->size, part->offset);
|
||||
|
||||
|
@ -1373,7 +1368,7 @@ static int parse_mtdparts(const char *const mtdparts)
|
|||
struct mtd_device *dev;
|
||||
int err = 1;
|
||||
|
||||
DEBUGF("\n---parse_mtdparts---\nmtdparts = %s\n\n", p);
|
||||
debug("\n---parse_mtdparts---\nmtdparts = %s\n\n", p);
|
||||
|
||||
/* delete all devices and partitions */
|
||||
if (mtd_devices_init() != 0) {
|
||||
|
@ -1395,7 +1390,7 @@ static int parse_mtdparts(const char *const mtdparts)
|
|||
if ((device_parse(p, &p, &dev) != 0) || (!dev))
|
||||
break;
|
||||
|
||||
DEBUGF("+ device: %s\t%d\t%s\n", MTD_DEV_TYPE(dev->id->type),
|
||||
debug("+ device: %s\t%d\t%s\n", MTD_DEV_TYPE(dev->id->type),
|
||||
dev->id->num, dev->id->mtd_id);
|
||||
|
||||
/* check if parsed device is already on the list */
|
||||
|
@ -1436,12 +1431,12 @@ static int parse_mtdids(const char *const ids)
|
|||
u32 size;
|
||||
int ret = 1;
|
||||
|
||||
DEBUGF("\n---parse_mtdids---\nmtdids = %s\n\n", ids);
|
||||
debug("\n---parse_mtdids---\nmtdids = %s\n\n", ids);
|
||||
|
||||
/* clean global mtdids list */
|
||||
list_for_each_safe(entry, n, &mtdids) {
|
||||
id_tmp = list_entry(entry, struct mtdids, link);
|
||||
DEBUGF("mtdids del: %d %d\n", id_tmp->type, id_tmp->num);
|
||||
debug("mtdids del: %d %d\n", id_tmp->type, id_tmp->num);
|
||||
list_del(entry);
|
||||
free(id_tmp);
|
||||
}
|
||||
|
@ -1507,7 +1502,7 @@ static int parse_mtdids(const char *const ids)
|
|||
id->mtd_id[mtd_id_len - 1] = '\0';
|
||||
INIT_LIST_HEAD(&id->link);
|
||||
|
||||
DEBUGF("+ id %s%d\t%16d bytes\t%s\n",
|
||||
debug("+ id %s%d\t%16d bytes\t%s\n",
|
||||
MTD_DEV_TYPE(id->type), id->num,
|
||||
id->size, id->mtd_id);
|
||||
|
||||
|
@ -1541,7 +1536,7 @@ int mtdparts_init(void)
|
|||
int ids_changed;
|
||||
char tmp_ep[PARTITION_MAXLEN];
|
||||
|
||||
DEBUGF("\n---mtdparts_init---\n");
|
||||
debug("\n---mtdparts_init---\n");
|
||||
if (!initialized) {
|
||||
INIT_LIST_HEAD(&mtdids);
|
||||
INIT_LIST_HEAD(&devices);
|
||||
|
@ -1562,18 +1557,18 @@ int mtdparts_init(void)
|
|||
if (current_partition)
|
||||
strncpy(tmp_ep, current_partition, PARTITION_MAXLEN);
|
||||
|
||||
DEBUGF("last_ids : %s\n", last_ids);
|
||||
DEBUGF("env_ids : %s\n", ids);
|
||||
DEBUGF("last_parts: %s\n", last_parts);
|
||||
DEBUGF("env_parts : %s\n\n", parts);
|
||||
debug("last_ids : %s\n", last_ids);
|
||||
debug("env_ids : %s\n", ids);
|
||||
debug("last_parts: %s\n", last_parts);
|
||||
debug("env_parts : %s\n\n", parts);
|
||||
|
||||
DEBUGF("last_partition : %s\n", last_partition);
|
||||
DEBUGF("env_partition : %s\n", current_partition);
|
||||
debug("last_partition : %s\n", last_partition);
|
||||
debug("env_partition : %s\n", current_partition);
|
||||
|
||||
/* if mtdids varible is empty try to use defaults */
|
||||
if (!ids) {
|
||||
if (mtdids_default) {
|
||||
DEBUGF("mtdids variable not defined, using default\n");
|
||||
debug("mtdids variable not defined, using default\n");
|
||||
ids = mtdids_default;
|
||||
setenv("mtdids", (char *)ids);
|
||||
} else {
|
||||
|
@ -1629,7 +1624,7 @@ int mtdparts_init(void)
|
|||
current_mtd_partnum = 0;
|
||||
current_save();
|
||||
|
||||
DEBUGF("mtdparts_init: current_mtd_dev = %s%d, current_mtd_partnum = %d\n",
|
||||
debug("mtdparts_init: current_mtd_dev = %s%d, current_mtd_partnum = %d\n",
|
||||
MTD_DEV_TYPE(current_mtd_dev->id->type),
|
||||
current_mtd_dev->id->num, current_mtd_partnum);
|
||||
}
|
||||
|
@ -1648,7 +1643,7 @@ int mtdparts_init(void)
|
|||
struct mtd_device *cdev;
|
||||
u8 pnum;
|
||||
|
||||
DEBUGF("--- getting current partition: %s\n", tmp_ep);
|
||||
debug("--- getting current partition: %s\n", tmp_ep);
|
||||
|
||||
if (find_dev_and_part(tmp_ep, &cdev, &pnum, &p) == 0) {
|
||||
current_mtd_dev = cdev;
|
||||
|
@ -1656,7 +1651,7 @@ int mtdparts_init(void)
|
|||
current_save();
|
||||
}
|
||||
} else if (getenv("partition") == NULL) {
|
||||
DEBUGF("no partition variable set, setting...\n");
|
||||
debug("no partition variable set, setting...\n");
|
||||
current_save();
|
||||
}
|
||||
|
||||
|
@ -1680,7 +1675,7 @@ static struct part_info* mtd_part_info(struct mtd_device *dev, unsigned int part
|
|||
if (!dev)
|
||||
return NULL;
|
||||
|
||||
DEBUGF("\n--- mtd_part_info: partition number %d for device %s%d (%s)\n",
|
||||
debug("\n--- mtd_part_info: partition number %d for device %s%d (%s)\n",
|
||||
part_num, MTD_DEV_TYPE(dev->id->type),
|
||||
dev->id->num, dev->id->mtd_id);
|
||||
|
||||
|
@ -1816,12 +1811,12 @@ int do_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
}
|
||||
sprintf(tmpbuf, "%s:%s(%s)%s",
|
||||
id->mtd_id, argv[3], argv[4], argv[5] ? argv[5] : "");
|
||||
DEBUGF("add tmpbuf: %s\n", tmpbuf);
|
||||
debug("add tmpbuf: %s\n", tmpbuf);
|
||||
|
||||
if ((device_parse(tmpbuf, NULL, &dev) != 0) || (!dev))
|
||||
return 1;
|
||||
|
||||
DEBUGF("+ %s\t%d\t%s\n", MTD_DEV_TYPE(dev->id->type),
|
||||
debug("+ %s\t%d\t%s\n", MTD_DEV_TYPE(dev->id->type),
|
||||
dev->id->num, dev->id->mtd_id);
|
||||
|
||||
if ((dev_tmp = device_find(dev->id->type, dev->id->num)) == NULL) {
|
||||
|
@ -1845,7 +1840,7 @@ int do_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
|
||||
/* mtdparts del part-id */
|
||||
if ((argc == 3) && (strcmp(argv[1], "del") == 0)) {
|
||||
DEBUGF("del: part-id = %s\n", argv[2]);
|
||||
debug("del: part-id = %s\n", argv[2]);
|
||||
|
||||
return delete_partition(argv[2]);
|
||||
}
|
||||
|
|
|
@ -19,7 +19,7 @@
|
|||
|
||||
#if defined(CONFIG_CMD_MTDPARTS)
|
||||
|
||||
/* parition handling routines */
|
||||
/* partition handling routines */
|
||||
int mtdparts_init(void);
|
||||
int id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num);
|
||||
int find_dev_and_part(const char *id, struct mtd_device **dev,
|
||||
|
|
|
@ -330,154 +330,231 @@ static int onenand_dump(struct mtd_info *mtd, ulong off, int only_oob)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
static int do_onenand_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
struct onenand_chip *this;
|
||||
int blocksize;
|
||||
ulong addr, ofs;
|
||||
size_t len, retlen = 0;
|
||||
int ret = 0;
|
||||
char *cmd, *s;
|
||||
printf("%s\n", mtd->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int do_onenand_bad(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
ulong ofs;
|
||||
|
||||
mtd = &onenand_mtd;
|
||||
this = mtd->priv;
|
||||
blocksize = (1 << this->erase_shift);
|
||||
|
||||
cmd = argv[1];
|
||||
|
||||
switch (argc) {
|
||||
case 0:
|
||||
case 1:
|
||||
goto usage;
|
||||
|
||||
case 2:
|
||||
if (strcmp(cmd, "info") == 0) {
|
||||
printf("%s\n", mtd->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (strcmp(cmd, "bad") == 0) {
|
||||
/* Currently only one OneNAND device is supported */
|
||||
printf("\nDevice %d bad blocks:\n", 0);
|
||||
for (ofs = 0; ofs < mtd->size; ofs += mtd->erasesize) {
|
||||
if (mtd->block_isbad(mtd, ofs))
|
||||
printf(" %08x\n", (u32)ofs);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
default:
|
||||
/* At least 4 args */
|
||||
|
||||
/*
|
||||
* Syntax is:
|
||||
* 0 1 2 3 4
|
||||
* onenand erase [force] [off size]
|
||||
*/
|
||||
if ((strcmp(cmd, "erase") == 0) || (strcmp(cmd, "test") == 0)) {
|
||||
int force = argc > 2 && !strcmp("force", argv[2]);
|
||||
int o = force ? 3 : 2;
|
||||
int erase;
|
||||
|
||||
erase = strcmp(cmd, "erase") == 0; /* 1 = erase, 0 = test */
|
||||
printf("\nOneNAND %s: ", erase ? "erase" : "test");
|
||||
|
||||
/* skip first two or three arguments, look for offset and size */
|
||||
if (arg_off_size(argc - o, argv + o, &ofs, &len) != 0)
|
||||
return 1;
|
||||
|
||||
if (erase)
|
||||
ret = onenand_block_erase(ofs, len, force);
|
||||
else
|
||||
ret = onenand_block_test(ofs, len);
|
||||
|
||||
printf("%s\n", ret ? "ERROR" : "OK");
|
||||
|
||||
return ret == 0 ? 0 : 1;
|
||||
}
|
||||
|
||||
if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) {
|
||||
int read;
|
||||
int oob = 0;
|
||||
|
||||
if (argc < 4)
|
||||
goto usage;
|
||||
|
||||
addr = (ulong)simple_strtoul(argv[2], NULL, 16);
|
||||
|
||||
read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
|
||||
printf("\nOneNAND %s: ", read ? "read" : "write");
|
||||
if (arg_off_size(argc - 3, argv + 3, &ofs, &len) != 0)
|
||||
return 1;
|
||||
|
||||
s = strchr(cmd, '.');
|
||||
if ((s != NULL) && (!strcmp(s, ".oob")))
|
||||
oob = 1;
|
||||
|
||||
if (read) {
|
||||
ret = onenand_block_read(ofs, len, &retlen,
|
||||
(u8 *)addr, oob);
|
||||
} else {
|
||||
ret = onenand_block_write(ofs, len, &retlen,
|
||||
(u8 *)addr);
|
||||
}
|
||||
|
||||
printf(" %d bytes %s: %s\n", retlen,
|
||||
read ? "read" : "written", ret ? "ERROR" : "OK");
|
||||
|
||||
return ret == 0 ? 0 : 1;
|
||||
}
|
||||
|
||||
if (strcmp(cmd, "markbad") == 0) {
|
||||
argc -= 2;
|
||||
argv += 2;
|
||||
|
||||
if (argc <= 0)
|
||||
goto usage;
|
||||
|
||||
while (argc > 0) {
|
||||
addr = simple_strtoul(*argv, NULL, 16);
|
||||
|
||||
if (mtd->block_markbad(mtd, addr)) {
|
||||
printf("block 0x%08lx NOT marked "
|
||||
"as bad! ERROR %d\n",
|
||||
addr, ret);
|
||||
ret = 1;
|
||||
} else {
|
||||
printf("block 0x%08lx successfully "
|
||||
"marked as bad\n",
|
||||
addr);
|
||||
}
|
||||
--argc;
|
||||
++argv;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (strncmp(cmd, "dump", 4) == 0) {
|
||||
if (argc < 3)
|
||||
goto usage;
|
||||
|
||||
s = strchr(cmd, '.');
|
||||
ofs = (int)simple_strtoul(argv[2], NULL, 16);
|
||||
|
||||
if (s != NULL && strcmp(s, ".oob") == 0)
|
||||
ret = onenand_dump(mtd, ofs, 1);
|
||||
else
|
||||
ret = onenand_dump(mtd, ofs, 0);
|
||||
|
||||
return ret == 0 ? 1 : 0;
|
||||
}
|
||||
|
||||
break;
|
||||
/* Currently only one OneNAND device is supported */
|
||||
printf("\nDevice %d bad blocks:\n", 0);
|
||||
for (ofs = 0; ofs < mtd->size; ofs += mtd->erasesize) {
|
||||
if (mtd->block_isbad(mtd, ofs))
|
||||
printf(" %08x\n", (u32)ofs);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
usage:
|
||||
cmd_usage(cmdtp);
|
||||
return 1;
|
||||
static int do_onenand_read(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
char *s;
|
||||
int oob = 0;
|
||||
ulong addr, ofs;
|
||||
size_t len;
|
||||
int ret = 0;
|
||||
size_t retlen = 0;
|
||||
|
||||
if (argc < 3)
|
||||
{
|
||||
cmd_usage(cmdtp);
|
||||
return 1;
|
||||
}
|
||||
|
||||
s = strchr(argv[0], '.');
|
||||
if ((s != NULL) && (!strcmp(s, ".oob")))
|
||||
oob = 1;
|
||||
|
||||
addr = (ulong)simple_strtoul(argv[1], NULL, 16);
|
||||
|
||||
printf("\nOneNAND read: ");
|
||||
if (arg_off_size(argc - 2, argv + 2, &ofs, &len) != 0)
|
||||
return 1;
|
||||
|
||||
ret = onenand_block_read(ofs, len, &retlen, (u8 *)addr, oob);
|
||||
|
||||
printf(" %d bytes read: %s\n", retlen, ret ? "ERROR" : "OK");
|
||||
|
||||
return ret == 0 ? 0 : 1;
|
||||
}
|
||||
|
||||
static int do_onenand_write(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
ulong addr, ofs;
|
||||
size_t len;
|
||||
int ret = 0;
|
||||
size_t retlen = 0;
|
||||
|
||||
if (argc < 3)
|
||||
{
|
||||
cmd_usage(cmdtp);
|
||||
return 1;
|
||||
}
|
||||
|
||||
addr = (ulong)simple_strtoul(argv[1], NULL, 16);
|
||||
|
||||
printf("\nOneNAND write: ");
|
||||
if (arg_off_size(argc - 2, argv + 2, &ofs, &len) != 0)
|
||||
return 1;
|
||||
|
||||
ret = onenand_block_write(ofs, len, &retlen, (u8 *)addr);
|
||||
|
||||
printf(" %d bytes written: %s\n", retlen, ret ? "ERROR" : "OK");
|
||||
|
||||
return ret == 0 ? 0 : 1;
|
||||
}
|
||||
|
||||
static int do_onenand_erase(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
ulong ofs;
|
||||
int ret = 0;
|
||||
size_t len;
|
||||
int force;
|
||||
|
||||
/*
|
||||
* Syntax is:
|
||||
* 0 1 2 3 4
|
||||
* onenand erase [force] [off size]
|
||||
*/
|
||||
argc--;
|
||||
argv++;
|
||||
if (argc)
|
||||
{
|
||||
if (!strcmp("force", argv[0]))
|
||||
{
|
||||
force = 1;
|
||||
argc--;
|
||||
argv++;
|
||||
}
|
||||
}
|
||||
printf("\nOneNAND erase: ");
|
||||
|
||||
/* skip first two or three arguments, look for offset and size */
|
||||
if (arg_off_size(argc, argv, &ofs, &len) != 0)
|
||||
return 1;
|
||||
|
||||
ret = onenand_block_erase(ofs, len, force);
|
||||
|
||||
printf("%s\n", ret ? "ERROR" : "OK");
|
||||
|
||||
return ret == 0 ? 0 : 1;
|
||||
}
|
||||
|
||||
static int do_onenand_test(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
ulong ofs;
|
||||
int ret = 0;
|
||||
size_t len;
|
||||
|
||||
/*
|
||||
* Syntax is:
|
||||
* 0 1 2 3 4
|
||||
* onenand test [force] [off size]
|
||||
*/
|
||||
|
||||
printf("\nOneNAND test: ");
|
||||
|
||||
/* skip first two or three arguments, look for offset and size */
|
||||
if (arg_off_size(argc - 1, argv + 1, &ofs, &len) != 0)
|
||||
return 1;
|
||||
|
||||
ret = onenand_block_test(ofs, len);
|
||||
|
||||
printf("%s\n", ret ? "ERROR" : "OK");
|
||||
|
||||
return ret == 0 ? 0 : 1;
|
||||
}
|
||||
|
||||
static int do_onenand_dump(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
ulong ofs;
|
||||
int ret = 0;
|
||||
char *s;
|
||||
|
||||
if (argc < 2)
|
||||
{
|
||||
cmd_usage(cmdtp);
|
||||
return 1;
|
||||
}
|
||||
|
||||
s = strchr(argv[0], '.');
|
||||
ofs = (int)simple_strtoul(argv[1], NULL, 16);
|
||||
|
||||
if (s != NULL && strcmp(s, ".oob") == 0)
|
||||
ret = onenand_dump(mtd, ofs, 1);
|
||||
else
|
||||
ret = onenand_dump(mtd, ofs, 0);
|
||||
|
||||
return ret == 0 ? 1 : 0;
|
||||
}
|
||||
|
||||
static int do_onenand_markbad(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
int ret = 0;
|
||||
ulong addr;
|
||||
|
||||
argc -= 2;
|
||||
argv += 2;
|
||||
|
||||
if (argc <= 0)
|
||||
{
|
||||
cmd_usage(cmdtp);
|
||||
return 1;
|
||||
}
|
||||
|
||||
while (argc > 0) {
|
||||
addr = simple_strtoul(*argv, NULL, 16);
|
||||
|
||||
if (mtd->block_markbad(mtd, addr)) {
|
||||
printf("block 0x%08lx NOT marked "
|
||||
"as bad! ERROR %d\n",
|
||||
addr, ret);
|
||||
ret = 1;
|
||||
} else {
|
||||
printf("block 0x%08lx successfully "
|
||||
"marked as bad\n",
|
||||
addr);
|
||||
}
|
||||
--argc;
|
||||
++argv;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static cmd_tbl_t cmd_onenand_sub[] = {
|
||||
U_BOOT_CMD_MKENT(info, 1, 0, do_onenand_info, "", ""),
|
||||
U_BOOT_CMD_MKENT(bad, 1, 0, do_onenand_bad, "", ""),
|
||||
U_BOOT_CMD_MKENT(read, 4, 0, do_onenand_read, "", ""),
|
||||
U_BOOT_CMD_MKENT(write, 4, 0, do_onenand_write, "", ""),
|
||||
U_BOOT_CMD_MKENT(erase, 3, 0, do_onenand_erase, "", ""),
|
||||
U_BOOT_CMD_MKENT(test, 3, 0, do_onenand_test, "", ""),
|
||||
U_BOOT_CMD_MKENT(dump, 2, 0, do_onenand_dump, "", ""),
|
||||
U_BOOT_CMD_MKENT(markbad, CONFIG_SYS_MAXARGS, 0, do_onenand_markbad, "", ""),
|
||||
};
|
||||
|
||||
static int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
cmd_tbl_t *c;
|
||||
|
||||
mtd = &onenand_mtd;
|
||||
|
||||
/* Strip off leading 'onenand' command argument */
|
||||
argc--;
|
||||
argv++;
|
||||
|
||||
c = find_cmd_tbl(argv[0], &cmd_onenand_sub[0], ARRAY_SIZE(cmd_onenand_sub));
|
||||
|
||||
if (c) {
|
||||
return c->cmd(cmdtp, flag, argc, argv);
|
||||
} else {
|
||||
cmd_usage(cmdtp);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
|
@ -486,7 +563,7 @@ U_BOOT_CMD(
|
|||
"info - show available OneNAND devices\n"
|
||||
"onenand bad - show bad blocks\n"
|
||||
"onenand read[.oob] addr off size\n"
|
||||
"onenand write[.oob] addr off size\n"
|
||||
"onenand write addr off size\n"
|
||||
" read/write 'size' bytes starting at offset 'off'\n"
|
||||
" to/from memory address 'addr', skipping bad blocks.\n"
|
||||
"onenand erase [force] [off size] - erase 'size' bytes from\n"
|
||||
|
|
|
@ -516,6 +516,11 @@ int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
block_dev_desc_t *stor_dev;
|
||||
#endif
|
||||
|
||||
if (argc < 2) {
|
||||
cmd_usage(cmdtp);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if ((strncmp(argv[1], "reset", 5) == 0) ||
|
||||
(strncmp(argv[1], "start", 5) == 0)) {
|
||||
usb_stop();
|
||||
|
|
|
@ -188,6 +188,9 @@ static void install_auto_complete_handler(const char *cmd,
|
|||
|
||||
void install_auto_complete(void)
|
||||
{
|
||||
#if defined(CONFIG_CMD_EDITENV)
|
||||
install_auto_complete_handler("editenv", var_complete);
|
||||
#endif
|
||||
install_auto_complete_handler("printenv", var_complete);
|
||||
install_auto_complete_handler("setenv", var_complete);
|
||||
#if defined(CONFIG_CMD_RUN)
|
||||
|
|
|
@ -20,11 +20,15 @@ spd_check(const u8 *buf, u8 spd_rev, u8 spd_cksum)
|
|||
* Check SPD revision supported
|
||||
* Rev 1.2 or less supported by this code
|
||||
*/
|
||||
if (spd_rev > 0x12) {
|
||||
if (spd_rev >= 0x20) {
|
||||
printf("SPD revision %02X not supported by this code\n",
|
||||
spd_rev);
|
||||
return 1;
|
||||
}
|
||||
if (spd_rev > 0x13) {
|
||||
printf("SPD revision %02X not verified by this code\n",
|
||||
spd_rev);
|
||||
}
|
||||
|
||||
/*
|
||||
* Calculate checksum
|
||||
|
|
|
@ -450,6 +450,9 @@ phys_size_t getenv_bootm_size(void)
|
|||
|
||||
void memmove_wd (void *to, void *from, size_t len, ulong chunksz)
|
||||
{
|
||||
if (to == from)
|
||||
return;
|
||||
|
||||
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
|
||||
while (len > 0) {
|
||||
size_t tail = (len > chunksz) ? chunksz : len;
|
||||
|
|
|
@ -41,7 +41,8 @@ struct serial_device *__default_serial_console (void)
|
|||
#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|
||||
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \
|
||||
|| defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) \
|
||||
|| defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
|
||||
|| defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \
|
||||
|| defined(CONFIG_SYS_SC520)
|
||||
#if defined(CONFIG_CONS_INDEX) && defined(CONFIG_SYS_NS16550_SERIAL)
|
||||
#if (CONFIG_CONS_INDEX==1)
|
||||
return &eserial1_device;
|
||||
|
|
14
config.mk
14
config.mk
|
@ -64,9 +64,17 @@ HOSTSTRIP = strip
|
|||
#
|
||||
|
||||
ifeq ($(HOSTOS),darwin)
|
||||
HOSTCC = cc
|
||||
HOSTCFLAGS += -traditional-cpp
|
||||
HOSTLDFLAGS += -multiply_defined suppress
|
||||
# get major and minor product version (e.g. '10' and '6' for Snow Leopard)
|
||||
DARWIN_MAJOR_VERSION = $(shell sw_vers -productVersion | cut -f 1 -d '.')
|
||||
DARWIN_MINOR_VERSION = $(shell sw_vers -productVersion | cut -f 2 -d '.')
|
||||
|
||||
before-snow-leopard = $(shell if [ $(DARWIN_MAJOR_VERSION) -le 10 -a \
|
||||
$(DARWIN_MINOR_VERSION) -le 5 ] ; then echo "$(1)"; else echo "$(2)"; fi ;)
|
||||
|
||||
# Snow Leopards build environment has no longer restrictions as described above
|
||||
HOSTCC = $(call before-snow-leopard, "cc", "gcc")
|
||||
HOSTCFLAGS += $(call before-snow-leopard, "-traditional-cpp")
|
||||
HOSTLDFLAGS += $(call before-snow-leopard, "-multiply_defined suppress")
|
||||
else
|
||||
HOSTCC = gcc
|
||||
endif
|
||||
|
|
|
@ -5,7 +5,7 @@ To ebable, use the following #define in the board configuration file:
|
|||
#define CONFIG_JFFS2_NAND 1
|
||||
|
||||
Configuration of partitions is similar to how this is done in U-Boot
|
||||
for JFFS2 on top NOR flash. If a single parition is used, it can be
|
||||
for JFFS2 on top NOR flash. If a single partition is used, it can be
|
||||
configured using the following #defines in the configuration file:
|
||||
|
||||
#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */
|
||||
|
|
|
@ -70,6 +70,7 @@ int ape_register(bd_t *bis, int iobase)
|
|||
dev->halt = ape_halt;
|
||||
dev->send = ape_send;
|
||||
dev->recv = ape_recv;
|
||||
dev->write_hwaddr = ape_write_hwaddr;
|
||||
|
||||
eth_register(dev);
|
||||
|
||||
|
@ -102,11 +103,12 @@ not checking its state or doing random probing.
|
|||
-----------
|
||||
|
||||
Now that we've registered with the ethernet layer, we can start getting some
|
||||
real work done. You will need four functions:
|
||||
real work done. You will need five functions:
|
||||
int ape_init(struct eth_device *dev, bd_t *bis);
|
||||
int ape_send(struct eth_device *dev, volatile void *packet, int length);
|
||||
int ape_recv(struct eth_device *dev);
|
||||
int ape_halt(struct eth_device *dev);
|
||||
int ape_write_hwaddr(struct eth_device *dev);
|
||||
|
||||
The init function checks the hardware (probing/identifying) and gets it ready
|
||||
for send/recv operations. You often do things here such as resetting the MAC
|
||||
|
@ -150,6 +152,9 @@ The halt function should turn off / disable the hardware and place it back in
|
|||
its reset state. It can be called at any time (before any call to the related
|
||||
init function), so make sure it can handle this sort of thing.
|
||||
|
||||
The write_hwaddr function should program the MAC address stored in dev->enetaddr
|
||||
into the Ethernet controller.
|
||||
|
||||
So the call graph at this stage would look something like:
|
||||
some net operation (ping / tftp / whatever...)
|
||||
eth_init()
|
||||
|
|
|
@ -33,11 +33,13 @@ Correct flow of setting up the MAC address (summarized):
|
|||
1. Read from hardware in initialize() function
|
||||
2. Read from environment in net/eth.c after initialize()
|
||||
3. Give priority to the value in the environment if a conflict
|
||||
4. Program hardware in the device's init() function.
|
||||
4. Program the address into hardware if the following conditions are met:
|
||||
a) The relevant driver has a 'write_addr' function
|
||||
b) The user hasn't set an 'ethmacskip' environment variable
|
||||
c) The address is valid (unicast, not all-zeros)
|
||||
|
||||
If somebody wants to subvert the design philosophy, this can be done
|
||||
in the board-specific board_eth_init() function by calling eth_init()
|
||||
after all the NICs have been registered.
|
||||
Previous behavior had the MAC address always being programmed into hardware
|
||||
in the device's init() function.
|
||||
|
||||
-------
|
||||
Usage
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (C) 2008 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2008,2010 Freescale Semiconductor, Inc.
|
||||
* Dave Liu <daveliu@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
|
@ -22,6 +22,7 @@
|
|||
#include <command.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
#include <malloc.h>
|
||||
#include <libata.h>
|
||||
#include <fis.h>
|
||||
|
@ -129,6 +130,17 @@ int init_sata(int dev)
|
|||
return -1;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MPC85xx
|
||||
if ((dev == 0) && (!is_serdes_configured(SATA1))) {
|
||||
printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
|
||||
return -1;
|
||||
}
|
||||
if ((dev == 1) && (!is_serdes_configured(SATA2))) {
|
||||
printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Allocate SATA device driver struct */
|
||||
sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t));
|
||||
if (!sata) {
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* i2c.c - driver for Blackfin on-chip TWI/I2C
|
||||
*
|
||||
* Copyright (c) 2006-2008 Analog Devices Inc.
|
||||
* Copyright (c) 2006-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
@ -12,6 +12,35 @@
|
|||
#include <asm/blackfin.h>
|
||||
#include <asm/mach-common/bits/twi.h>
|
||||
|
||||
/* Every register is 32bit aligned, but only 16bits in size */
|
||||
#define ureg(name) u16 name; u16 __pad_##name;
|
||||
struct twi_regs {
|
||||
ureg(clkdiv);
|
||||
ureg(control);
|
||||
ureg(slave_ctl);
|
||||
ureg(slave_stat);
|
||||
ureg(slave_addr);
|
||||
ureg(master_ctl);
|
||||
ureg(master_stat);
|
||||
ureg(master_addr);
|
||||
ureg(int_stat);
|
||||
ureg(int_mask);
|
||||
ureg(fifo_ctl);
|
||||
ureg(fifo_stat);
|
||||
char __pad[0x50];
|
||||
ureg(xmt_data8);
|
||||
ureg(xmt_data16);
|
||||
ureg(rcv_data8);
|
||||
ureg(rcv_data16);
|
||||
};
|
||||
#undef ureg
|
||||
|
||||
/* U-Boot I2C framework allows only one active device at a time. */
|
||||
#ifdef TWI_CLKDIV
|
||||
#define TWI0_CLKDIV TWI_CLKDIV
|
||||
#endif
|
||||
static volatile struct twi_regs *twi = (void *)TWI0_CLKDIV;
|
||||
|
||||
#ifdef DEBUG
|
||||
# define dmemset(s, c, n) memset(s, c, n)
|
||||
#else
|
||||
|
@ -19,29 +48,10 @@
|
|||
#endif
|
||||
#define debugi(fmt, args...) \
|
||||
debug( \
|
||||
"MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t" \
|
||||
"%-20s:%-3i: " fmt "\n", \
|
||||
bfin_read_TWI_MASTER_STAT(), bfin_read_TWI_FIFO_STAT(), bfin_read_TWI_INT_STAT(), \
|
||||
"MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t%-20s:%-3i: " fmt "\n", \
|
||||
twi->master_stat, twi->fifo_stat, twi->int_stat, \
|
||||
__func__, __LINE__, ## args)
|
||||
|
||||
#ifdef TWI0_CLKDIV
|
||||
#define bfin_write_TWI_CLKDIV(val) bfin_write_TWI0_CLKDIV(val)
|
||||
#define bfin_read_TWI_CLKDIV(val) bfin_read_TWI0_CLKDIV(val)
|
||||
#define bfin_write_TWI_CONTROL(val) bfin_write_TWI0_CONTROL(val)
|
||||
#define bfin_read_TWI_CONTROL(val) bfin_read_TWI0_CONTROL(val)
|
||||
#define bfin_write_TWI_MASTER_ADDR(val) bfin_write_TWI0_MASTER_ADDR(val)
|
||||
#define bfin_write_TWI_XMT_DATA8(val) bfin_write_TWI0_XMT_DATA8(val)
|
||||
#define bfin_read_TWI_RCV_DATA8() bfin_read_TWI0_RCV_DATA8()
|
||||
#define bfin_read_TWI_INT_STAT() bfin_read_TWI0_INT_STAT()
|
||||
#define bfin_write_TWI_INT_STAT(val) bfin_write_TWI0_INT_STAT(val)
|
||||
#define bfin_read_TWI_MASTER_STAT() bfin_read_TWI0_MASTER_STAT()
|
||||
#define bfin_write_TWI_MASTER_STAT(val) bfin_write_TWI0_MASTER_STAT(val)
|
||||
#define bfin_read_TWI_MASTER_CTL() bfin_read_TWI0_MASTER_CTL()
|
||||
#define bfin_write_TWI_MASTER_CTL(val) bfin_write_TWI0_MASTER_CTL(val)
|
||||
#define bfin_write_TWI_INT_MASK(val) bfin_write_TWI0_INT_MASK(val)
|
||||
#define bfin_write_TWI_FIFO_CTL(val) bfin_write_TWI0_FIFO_CTL(val)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TWICLK_KHZ
|
||||
# error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED
|
||||
#endif
|
||||
|
@ -87,49 +97,48 @@ static int wait_for_completion(struct i2c_msg *msg)
|
|||
ulong timebase = get_timer(0);
|
||||
|
||||
do {
|
||||
int_stat = bfin_read_TWI_INT_STAT();
|
||||
int_stat = twi->int_stat;
|
||||
|
||||
if (int_stat & XMTSERV) {
|
||||
debugi("processing XMTSERV");
|
||||
bfin_write_TWI_INT_STAT(XMTSERV);
|
||||
twi->int_stat = XMTSERV;
|
||||
SSYNC();
|
||||
if (msg->alen) {
|
||||
bfin_write_TWI_XMT_DATA8(*(msg->abuf++));
|
||||
twi->xmt_data8 = *(msg->abuf++);
|
||||
--msg->alen;
|
||||
} else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
|
||||
bfin_write_TWI_XMT_DATA8(*(msg->buf++));
|
||||
twi->xmt_data8 = *(msg->buf++);
|
||||
--msg->len;
|
||||
} else {
|
||||
bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() |
|
||||
(msg->flags & I2C_M_COMBO ? RSTART | MDIR : STOP));
|
||||
twi->master_ctl |= (msg->flags & I2C_M_COMBO) ? RSTART | MDIR : STOP;
|
||||
SSYNC();
|
||||
}
|
||||
}
|
||||
if (int_stat & RCVSERV) {
|
||||
debugi("processing RCVSERV");
|
||||
bfin_write_TWI_INT_STAT(RCVSERV);
|
||||
twi->int_stat = RCVSERV;
|
||||
SSYNC();
|
||||
if (msg->len) {
|
||||
*(msg->buf++) = bfin_read_TWI_RCV_DATA8();
|
||||
*(msg->buf++) = twi->rcv_data8;
|
||||
--msg->len;
|
||||
} else if (msg->flags & I2C_M_STOP) {
|
||||
bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | STOP);
|
||||
twi->master_ctl |= STOP;
|
||||
SSYNC();
|
||||
}
|
||||
}
|
||||
if (int_stat & MERR) {
|
||||
debugi("processing MERR");
|
||||
bfin_write_TWI_INT_STAT(MERR);
|
||||
twi->int_stat = MERR;
|
||||
SSYNC();
|
||||
return msg->len;
|
||||
}
|
||||
if (int_stat & MCOMP) {
|
||||
debugi("processing MCOMP");
|
||||
bfin_write_TWI_INT_STAT(MCOMP);
|
||||
twi->int_stat = MCOMP;
|
||||
SSYNC();
|
||||
if (msg->flags & I2C_M_COMBO && msg->len) {
|
||||
bfin_write_TWI_MASTER_CTL((bfin_read_TWI_MASTER_CTL() & ~RSTART) |
|
||||
(min(msg->len, 0xff) << 6) | MEN | MDIR);
|
||||
twi->master_ctl = (twi->master_ctl & ~RSTART) |
|
||||
(min(msg->len, 0xff) << 6) | MEN | MDIR;
|
||||
SSYNC();
|
||||
} else
|
||||
break;
|
||||
|
@ -172,55 +181,54 @@ static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len,
|
|||
chip, addr, alen, buffer[0], len, flags, (flags & I2C_M_READ ? "rd" : "wr"));
|
||||
|
||||
/* wait for things to settle */
|
||||
while (bfin_read_TWI_MASTER_STAT() & BUSBUSY)
|
||||
while (twi->master_stat & BUSBUSY)
|
||||
if (ctrlc())
|
||||
return 1;
|
||||
|
||||
/* Set Transmit device address */
|
||||
bfin_write_TWI_MASTER_ADDR(chip);
|
||||
twi->master_addr = chip;
|
||||
|
||||
/* Clear the FIFO before starting things */
|
||||
bfin_write_TWI_FIFO_CTL(XMTFLUSH | RCVFLUSH);
|
||||
twi->fifo_ctl = XMTFLUSH | RCVFLUSH;
|
||||
SSYNC();
|
||||
bfin_write_TWI_FIFO_CTL(0);
|
||||
twi->fifo_ctl = 0;
|
||||
SSYNC();
|
||||
|
||||
/* prime the pump */
|
||||
if (msg.alen) {
|
||||
len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
|
||||
debugi("first byte=0x%02x", *msg.abuf);
|
||||
bfin_write_TWI_XMT_DATA8(*(msg.abuf++));
|
||||
twi->xmt_data8 = *(msg.abuf++);
|
||||
--msg.alen;
|
||||
} else if (!(msg.flags & I2C_M_READ) && msg.len) {
|
||||
debugi("first byte=0x%02x", *msg.buf);
|
||||
bfin_write_TWI_XMT_DATA8(*(msg.buf++));
|
||||
twi->xmt_data8 = *(msg.buf++);
|
||||
--msg.len;
|
||||
}
|
||||
|
||||
/* clear int stat */
|
||||
bfin_write_TWI_MASTER_STAT(-1);
|
||||
bfin_write_TWI_INT_STAT(-1);
|
||||
bfin_write_TWI_INT_MASK(0);
|
||||
twi->master_stat = -1;
|
||||
twi->int_stat = -1;
|
||||
twi->int_mask = 0;
|
||||
SSYNC();
|
||||
|
||||
/* Master enable */
|
||||
bfin_write_TWI_MASTER_CTL(
|
||||
(bfin_read_TWI_MASTER_CTL() & FAST) |
|
||||
twi->master_ctl =
|
||||
(twi->master_ctl & FAST) |
|
||||
(min(len, 0xff) << 6) | MEN |
|
||||
((msg.flags & I2C_M_READ) ? MDIR : 0)
|
||||
);
|
||||
((msg.flags & I2C_M_READ) ? MDIR : 0);
|
||||
SSYNC();
|
||||
debugi("CTL=0x%04x", bfin_read_TWI_MASTER_CTL());
|
||||
debugi("CTL=0x%04x", twi->master_ctl);
|
||||
|
||||
/* process the rest */
|
||||
ret = wait_for_completion(&msg);
|
||||
debugi("ret=%d", ret);
|
||||
|
||||
if (ret) {
|
||||
bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() & ~MEN);
|
||||
bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() & ~TWI_ENA);
|
||||
twi->master_ctl &= ~MEN;
|
||||
twi->control &= ~TWI_ENA;
|
||||
SSYNC();
|
||||
bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA);
|
||||
twi->control |= TWI_ENA;
|
||||
SSYNC();
|
||||
}
|
||||
|
||||
|
@ -238,10 +246,10 @@ int i2c_set_bus_speed(unsigned int speed)
|
|||
/* Set TWI interface clock */
|
||||
if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
|
||||
return -1;
|
||||
bfin_write_TWI_CLKDIV((clkdiv << 8) | (clkdiv & 0xff));
|
||||
twi->clkdiv = (clkdiv << 8) | (clkdiv & 0xff);
|
||||
|
||||
/* Don't turn it on */
|
||||
bfin_write_TWI_MASTER_CTL(speed > 100000 ? FAST : 0);
|
||||
twi->master_ctl = (speed > 100000 ? FAST : 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -253,7 +261,7 @@ int i2c_set_bus_speed(unsigned int speed)
|
|||
unsigned int i2c_get_bus_speed(void)
|
||||
{
|
||||
/* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */
|
||||
return 5000000 / (bfin_read_TWI_CLKDIV() & 0xff);
|
||||
return 5000000 / (twi->clkdiv & 0xff);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -269,24 +277,23 @@ void i2c_init(int speed, int slaveaddr)
|
|||
uint8_t prescale = ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F;
|
||||
|
||||
/* Set TWI internal clock as 10MHz */
|
||||
bfin_write_TWI_CONTROL(prescale);
|
||||
twi->control = prescale;
|
||||
|
||||
/* Set TWI interface clock as specified */
|
||||
i2c_set_bus_speed(speed);
|
||||
|
||||
/* Enable it */
|
||||
bfin_write_TWI_CONTROL(TWI_ENA | prescale);
|
||||
twi->control = TWI_ENA | prescale;
|
||||
SSYNC();
|
||||
|
||||
debugi("CONTROL:0x%04x CLKDIV:0x%04x",
|
||||
bfin_read_TWI_CONTROL(), bfin_read_TWI_CLKDIV());
|
||||
debugi("CONTROL:0x%04x CLKDIV:0x%04x", twi->control, twi->clkdiv);
|
||||
|
||||
#if CONFIG_SYS_I2C_SLAVE
|
||||
# error I2C slave support not tested/supported
|
||||
/* If they want us as a slave, do it */
|
||||
if (slaveaddr) {
|
||||
bfin_write_TWI_SLAVE_ADDR(slaveaddr);
|
||||
bfin_write_TWI_SLAVE_CTL(SEN);
|
||||
twi->slave_addr = slaveaddr;
|
||||
twi->slave_ctl = SEN;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
@ -329,3 +336,43 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
|||
{
|
||||
return i2c_transfer(chip, addr, alen, buffer, len, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* i2c_set_bus_num - change active I2C bus
|
||||
* @bus: bus index, zero based
|
||||
* @returns: 0 on success, non-0 on failure
|
||||
*/
|
||||
int i2c_set_bus_num(unsigned int bus)
|
||||
{
|
||||
switch (bus) {
|
||||
#if CONFIG_SYS_MAX_I2C_BUS > 0
|
||||
case 0: twi = (void *)TWI0_CLKDIV; return 0;
|
||||
#endif
|
||||
#if CONFIG_SYS_MAX_I2C_BUS > 1
|
||||
case 1: twi = (void *)TWI1_CLKDIV; return 0;
|
||||
#endif
|
||||
#if CONFIG_SYS_MAX_I2C_BUS > 2
|
||||
case 2: twi = (void *)TWI2_CLKDIV; return 0;
|
||||
#endif
|
||||
default: return -1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* i2c_get_bus_num - returns index of active I2C bus
|
||||
*/
|
||||
unsigned int i2c_get_bus_num(void)
|
||||
{
|
||||
switch ((unsigned long)twi) {
|
||||
#if CONFIG_SYS_MAX_I2C_BUS > 0
|
||||
case TWI0_CLKDIV: return 0;
|
||||
#endif
|
||||
#if CONFIG_SYS_MAX_I2C_BUS > 1
|
||||
case TWI1_CLKDIV: return 1;
|
||||
#endif
|
||||
#if CONFIG_SYS_MAX_I2C_BUS > 2
|
||||
case TWI2_CLKDIV: return 2;
|
||||
#endif
|
||||
default: return -1;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -103,7 +103,7 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
|
|||
/*
|
||||
* PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
|
||||
*/
|
||||
static int
|
||||
static void
|
||||
esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
|
||||
{
|
||||
struct fsl_esdhc *regs = mmc->priv;
|
||||
|
@ -125,7 +125,7 @@ esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
|
|||
&& --timeout);
|
||||
if (timeout <= 0) {
|
||||
printf("\nData Read Failed in PIO Mode.");
|
||||
return timeout;
|
||||
return;
|
||||
}
|
||||
while (size && (!(irqstat & IRQSTAT_TC))) {
|
||||
udelay(100); /* Wait before last byte transfer complete */
|
||||
|
@ -139,7 +139,7 @@ esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
|
|||
}
|
||||
} else {
|
||||
blocks = data->blocks;
|
||||
buffer = data->src;
|
||||
buffer = (char *)data->src;
|
||||
while (blocks) {
|
||||
timeout = PIO_TIMEOUT;
|
||||
size = data->blocksize;
|
||||
|
@ -148,7 +148,7 @@ esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
|
|||
&& --timeout);
|
||||
if (timeout <= 0) {
|
||||
printf("\nData Write Failed in PIO Mode.");
|
||||
return timeout;
|
||||
return;
|
||||
}
|
||||
while (size && (!(irqstat & IRQSTAT_TC))) {
|
||||
udelay(100); /* Wait before last byte transfer complete */
|
||||
|
@ -166,22 +166,12 @@ esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
|
|||
|
||||
static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
|
||||
{
|
||||
uint wml_value;
|
||||
int timeout;
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
|
||||
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
|
||||
uint wml_value;
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
|
||||
if (!(data->flags & MMC_DATA_READ)) {
|
||||
if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
|
||||
printf("\nThe SD card is locked. "
|
||||
"Can not write to a locked card.\n\n");
|
||||
return TIMEOUT;
|
||||
}
|
||||
esdhc_write32(®s->dsaddr, (u32)data->src);
|
||||
} else
|
||||
esdhc_write32(®s->dsaddr, (u32)data->dest);
|
||||
#else
|
||||
wml_value = data->blocksize/4;
|
||||
|
||||
if (data->flags & MMC_DATA_READ) {
|
||||
|
@ -202,7 +192,17 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
|
|||
wml_value << 16);
|
||||
esdhc_write32(®s->dsaddr, (u32)data->src);
|
||||
}
|
||||
#endif
|
||||
#else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
|
||||
if (!(data->flags & MMC_DATA_READ)) {
|
||||
if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
|
||||
printf("\nThe SD card is locked. "
|
||||
"Can not write to a locked card.\n\n");
|
||||
return TIMEOUT;
|
||||
}
|
||||
esdhc_write32(®s->dsaddr, (u32)data->src);
|
||||
} else
|
||||
esdhc_write32(®s->dsaddr, (u32)data->dest);
|
||||
#endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
|
||||
|
||||
esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
|
||||
|
||||
|
|
|
@ -696,8 +696,13 @@ static void schedule_ubi_work(struct ubi_device *ubi, struct ubi_work *wrk)
|
|||
list_add_tail(&wrk->list, &ubi->works);
|
||||
ubi_assert(ubi->works_count >= 0);
|
||||
ubi->works_count += 1;
|
||||
if (ubi->thread_enabled)
|
||||
wake_up_process(ubi->bgt_thread);
|
||||
|
||||
/*
|
||||
* U-Boot special: We have no bgt_thread in U-Boot!
|
||||
* So just call do_work() here directly.
|
||||
*/
|
||||
do_work(ubi);
|
||||
|
||||
spin_unlock(&ubi->wl_lock);
|
||||
}
|
||||
|
||||
|
|
|
@ -27,6 +27,7 @@ LIB := $(obj)libnet.a
|
|||
|
||||
COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
|
||||
COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
|
||||
COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o
|
||||
COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
|
||||
COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
|
||||
COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o
|
||||
|
@ -39,6 +40,7 @@ COBJS-$(CONFIG_E1000) += e1000.o
|
|||
COBJS-$(CONFIG_EEPRO100) += eepro100.o
|
||||
COBJS-$(CONFIG_ENC28J60) += enc28j60.o
|
||||
COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o
|
||||
COBJS-$(CONFIG_ETHOC) += ethoc.o
|
||||
COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o
|
||||
COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
|
||||
COBJS-$(CONFIG_FTMAC100) += ftmac100.o
|
||||
|
|
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Reference in a new issue