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Tsi108 on chip pci controller support.
If there is no pci card, the tsi108/109 pci configure read will cause a machine check exception to the processor. PCI error should also be cleared after the read. Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
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Zang Tiefei
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1 changed files with 178 additions and 0 deletions
178
drivers/tsi108_pci.c
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178
drivers/tsi108_pci.c
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/*
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* (C) Copyright 2004 Tundra Semiconductor Corp.
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* Alex Bounine <alexandreb@tundra.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* PCI initialisation for the Tsi108 EMU board.
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*/
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#include <config.h>
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#ifdef CONFIG_TSI108_PCI
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#include <common.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <tsi108.h>
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struct pci_controller local_hose;
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void tsi108_clear_pci_error(void)
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{
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u32 err_stat, err_addr, pci_stat;
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/*
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* Quietly clear errors signalled as result of PCI/X configuration read
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* requests.
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*/
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/* Read PB Error Log Registers */
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err_stat = *(volatile u32 *)(CFG_TSI108_CSR_BASE +
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TSI108_PB_REG_OFFSET + PB_ERRCS);
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err_addr = *(volatile u32 *)(CFG_TSI108_CSR_BASE +
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TSI108_PB_REG_OFFSET + PB_AERR);
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if (err_stat & PB_ERRCS_ES) {
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/* Clear PCI/X bus errors if applicable */
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if ((err_addr & 0xFF000000) == CFG_PCI_CFG_BASE) {
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/* Clear error flag */
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*(u32 *) (CFG_TSI108_CSR_BASE +
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TSI108_PB_REG_OFFSET + PB_ERRCS) =
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PB_ERRCS_ES;
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/* Clear read error reported in PB_ISR */
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*(u32 *) (CFG_TSI108_CSR_BASE +
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TSI108_PB_REG_OFFSET + PB_ISR) =
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PB_ISR_PBS_RD_ERR;
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/* Clear errors reported by PCI CSR (Normally Master Abort) */
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pci_stat = *(volatile u32 *)(CFG_TSI108_CSR_BASE +
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TSI108_PCI_REG_OFFSET +
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PCI_CSR);
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*(volatile u32 *)(CFG_TSI108_CSR_BASE +
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TSI108_PCI_REG_OFFSET + PCI_CSR) =
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pci_stat;
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*(volatile u32 *)(CFG_TSI108_CSR_BASE +
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TSI108_PCI_REG_OFFSET +
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PCI_IRP_STAT) = PCI_IRP_STAT_P_CSR;
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}
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}
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return;
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}
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unsigned int __get_pci_config_dword(u32 addr)
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{
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unsigned int retval;
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__asm__ __volatile__(" lwbrx %0,0,%1\n"
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"1: eieio\n"
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"2:\n"
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".section .fixup,\"ax\"\n"
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"3: li %0,-1\n"
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" b 2b\n"
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".section __ex_table,\"a\"\n"
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" .align 2\n"
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" .long 1b,3b\n"
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".text":"=r"(retval):"r"(addr));
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return (retval);
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}
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static int tsi108_read_config_dword(struct pci_controller *hose,
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pci_dev_t dev, int offset, u32 * value)
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{
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dev &= (CFG_PCI_CFG_SIZE - 1);
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dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc));
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*value = __get_pci_config_dword(dev);
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if (0xFFFFFFFF == *value)
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tsi108_clear_pci_error();
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return 0;
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}
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static int tsi108_write_config_dword(struct pci_controller *hose,
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pci_dev_t dev, int offset, u32 value)
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{
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dev &= (CFG_PCI_CFG_SIZE - 1);
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dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc));
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out_le32((volatile unsigned *)dev, value);
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return 0;
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}
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void pci_init_board(void)
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{
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struct pci_controller *hose = (struct pci_controller *)&local_hose;
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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pci_set_region(hose->regions + 0,
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CFG_PCI_MEMORY_BUS,
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CFG_PCI_MEMORY_PHYS,
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CFG_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* PCI memory space */
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pci_set_region(hose->regions + 1,
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CFG_PCI_MEM_BUS,
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CFG_PCI_MEM_PHYS, CFG_PCI_MEM_SIZE, PCI_REGION_MEM);
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/* PCI I/O space */
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pci_set_region(hose->regions + 2,
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CFG_PCI_IO_BUS,
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CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO);
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hose->region_count = 3;
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pci_set_ops(hose,
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pci_hose_read_config_byte_via_dword,
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pci_hose_read_config_word_via_dword,
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tsi108_read_config_dword,
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pci_hose_write_config_byte_via_dword,
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pci_hose_write_config_word_via_dword,
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tsi108_write_config_dword);
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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debug("Done PCI initialization\n");
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return;
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}
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#ifdef CONFIG_OF_FLAT_TREE
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void
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ft_pci_setup(void *blob, bd_t *bd)
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{
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u32 *p;
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int len;
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p = (u32 *)ft_get_prop(blob, "/" OF_TSI "/pci@1000/bus-range", &len);
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if (p != NULL) {
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p[0] = local_hose.first_busno;
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p[1] = local_hose.last_busno;
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}
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}
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#endif
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#endif /* CONFIG_TSI108_PCI */
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