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ARM: DRA7-evm: Enable HW leveling
Updating EMIF registers to enable HW leveling on DRA7-evm. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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parent
496edffdb2
commit
920638fa5e
1 changed files with 16 additions and 6 deletions
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@ -149,15 +149,15 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
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.read_idle_ctrl = 0x00050001,
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.zq_config = 0x0007190B,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
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.emif_ddr_phy_ctlr_1 = 0x0E24400A,
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.emif_ddr_phy_ctlr_1_init = 0x0024400B,
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.emif_ddr_phy_ctlr_1 = 0x0E24400B,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
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.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
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.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
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.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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@ -174,15 +174,15 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
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.read_idle_ctrl = 0x00050001,
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.zq_config = 0x0007190B,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
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.emif_ddr_phy_ctlr_1 = 0x0E24400A,
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.emif_ddr_phy_ctlr_1_init = 0x0024400B,
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.emif_ddr_phy_ctlr_1 = 0x0E24400B,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
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.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
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.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
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.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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@ -453,6 +453,11 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0
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};
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@ -488,6 +493,11 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0
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};
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