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armv8: ls2080aqds: Select QSPI CLK div via SCFG
QSPI module output SCLK divisor value is configured through SCFG. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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2 changed files with 6 additions and 0 deletions
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@ -140,6 +140,7 @@
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/* Supplemental Configuration */
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#define SCFG_BASE 0x01fc0000
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#define SCFG_USB3PRM1CR 0x000
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#define SCFG_QSPICLKCTLR 0x10
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#define TP_ITYP_AV 0x00000001 /* Initiator available */
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#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
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@ -26,6 +26,7 @@
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#define PIN_MUX_SEL_SDHC 0x00
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#define PIN_MUX_SEL_DSPI 0x0a
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#define SCFG_QSPICLKCTRL_DIV_20 (5 << 27)
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#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
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@ -219,6 +220,10 @@ int board_init(void)
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int board_early_init_f(void)
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{
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fsl_lsch3_early_init_f();
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#ifdef CONFIG_FSL_QSPI
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/* input clk: 1/2 platform clk, output: input/20 */
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out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
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#endif
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return 0;
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}
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