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ihs_mdio: Encapsulate register access

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To prepare for DM conversion, encapsulate all register accesses in
function calls.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
This commit is contained in:
Mario Six 2018-04-27 14:52:09 +02:00 committed by Tom Rini
parent 707e6ef964
commit 9139ac9d49
1 changed files with 34 additions and 7 deletions
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41
board/gdsys/common/ihs_mdio.c
View file

@ -11,6 +11,34 @@
#include "ihs_mdio.h" #include "ihs_mdio.h"
static inline u16 read_control(struct ihs_mdio_info *info)
{
u16 val;
FPGA_GET_REG(info->fpga, mdio.control, &val);
return val;
}
static inline void write_control(struct ihs_mdio_info *info, u16 val)
{
FPGA_SET_REG(info->fpga, mdio.control, val);
}
static inline void write_addr_data(struct ihs_mdio_info *info, u16 val)
{
FPGA_SET_REG(info->fpga, mdio.address_data, val);
}
static inline u16 read_rx_data(struct ihs_mdio_info *info)
{
u16 val;
FPGA_GET_REG(info->fpga, mdio.rx_data, &val);
return val;
}
static int ihs_mdio_idle(struct mii_dev *bus) static int ihs_mdio_idle(struct mii_dev *bus)
{ {
struct ihs_mdio_info *info = bus->priv; struct ihs_mdio_info *info = bus->priv;
@ -18,7 +46,7 @@ static int ihs_mdio_idle(struct mii_dev *bus)
unsigned int ctr = 0; unsigned int ctr = 0;
do { do {
FPGA_GET_REG(info->fpga, mdio.control, &val); val = read_control(info);
udelay(100); udelay(100);
if (ctr++ > 10) if (ctr++ > 10)
return -1; return -1;
@ -42,13 +70,13 @@ static int ihs_mdio_read(struct mii_dev *bus, int addr, int dev_addr,
ihs_mdio_idle(bus); ihs_mdio_idle(bus);
FPGA_SET_REG(info->fpga, mdio.control, write_control(info,
((addr & 0x1f) << 5) | (regnum & 0x1f) | (2 << 10)); ((addr & 0x1f) << 5) | (regnum & 0x1f) | (2 << 10));
/* wait for rx data available */ /* wait for rx data available */
udelay(100); udelay(100);
FPGA_GET_REG(info->fpga, mdio.rx_data, &val); val = read_rx_data(info);
return val; return val;
} }
@ -60,9 +88,8 @@ static int ihs_mdio_write(struct mii_dev *bus, int addr, int dev_addr,
ihs_mdio_idle(bus); ihs_mdio_idle(bus);
FPGA_SET_REG(info->fpga, mdio.address_data, value); write_addr_data(info, value);
FPGA_SET_REG(info->fpga, mdio.control, write_control(info, ((addr & 0x1f) << 5) | (regnum & 0x1f) | (1 << 10));
((addr & 0x1f) << 5) | (regnum & 0x1f) | (1 << 10));
return 0; return 0;
} }