mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-21 07:01:57 +00:00
Merge with /home/wd/git/u-boot/custodian/u-boot-coldfire
This commit is contained in:
Wolfgang Denk
commit
909627dca4
144 changed files with 22372 additions and 3270 deletions
45
CREDITS
45
CREDITS
|
|
@ -147,6 +147,11 @@ N: Daniel Engstr
|
|||
E: daniel@omicron.se
|
||||
D: x86 port, Support for sc520_cdp board
|
||||
|
||||
N: Hayden Fraser
|
||||
E: Hayden.Fraser@freescale.com
|
||||
D: Support for ColdFire MCF5253
|
||||
W: www.freescale.com
|
||||
|
||||
N: Dr. Wolfgang Grandegger
|
||||
E: wg@denx.de
|
||||
D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards
|
||||
|
|
@ -283,6 +288,11 @@ E: team@leox.org
|
|||
D: Support for LEOX boards, DS164x RTC
|
||||
W: http://www.leox.org
|
||||
|
||||
N: TsiChung Liew
|
||||
E: Tsi-Chung.Liew@freescale.com
|
||||
D: Support for ColdFire MCF523x, MCF532x, MCF5445x
|
||||
W: www.freescale.com
|
||||
|
||||
N: Leif Lindholm
|
||||
E: leif.lindholm@i3micro.com
|
||||
D: Support for AMD dbau1550 board.
|
||||
|
|
@ -297,6 +307,11 @@ N: Raymond Lo
|
|||
E: lo@routefree.com
|
||||
D: Support for DOS partitions
|
||||
|
||||
N: James MacAulay
|
||||
E: james.macaulay@amirix.com
|
||||
D: Suppport for Amirix AP1000
|
||||
W: www.amirix.com
|
||||
|
||||
N: Dan Malek
|
||||
E: dan@embeddedalley.com
|
||||
D: FADSROM, the grandfather of all of this
|
||||
|
|
@ -372,8 +387,9 @@ D: Support for the Wind River sbc405, sbc8240 board
|
|||
W: http://www.windriver.com
|
||||
|
||||
N: Stefan Roese
|
||||
E: stefan.roese@esd-electronics.com
|
||||
D: AMCC PPC401/403/405GP Support; Windows environment support
|
||||
E: sr@denx.de
|
||||
D: AMCC PPC4xx Support
|
||||
W: http://www.denx.de
|
||||
|
||||
N: Erwin Rol
|
||||
E: erwin@muffin.org
|
||||
|
|
@ -407,6 +423,11 @@ N: Art Shipkowski
|
|||
E: art@videon-central.com
|
||||
D: Support for NetSilicon NS7520
|
||||
|
||||
N: Michal Simek
|
||||
E: monstr@monstr.eu
|
||||
D: Support for Microblaze, ML401, XUPV2P board
|
||||
W: www.monstr.eu
|
||||
|
||||
N: Yasushi Shoji
|
||||
E: yashi@atmark-techno.com
|
||||
D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board
|
||||
|
|
@ -420,6 +441,11 @@ E: andrea.scian@dave-tech.it
|
|||
D: Port to B2 board
|
||||
W: www.dave-tech.it
|
||||
|
||||
N: Timur Tabi
|
||||
E: timur@freescale.com
|
||||
D: Support for MPC8349E-mITX
|
||||
W: www.freescale.com
|
||||
|
||||
N: Rob Taylor
|
||||
E: robt@flyingpig.com
|
||||
D: Port to MBX860T and Sandpoint8240
|
||||
|
|
@ -473,18 +499,3 @@ N: Alex Zuepke
|
|||
E: azu@sysgo.de
|
||||
D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
|
||||
W: www.elinos.com
|
||||
|
||||
N: James MacAulay
|
||||
E: james.macaulay@amirix.com
|
||||
D: Suppport for Amirix AP1000
|
||||
W: www.amirix.com
|
||||
|
||||
N: Timur Tabi
|
||||
E: timur@freescale.com
|
||||
D: Support for MPC8349E-mITX
|
||||
W: www.freescale.com
|
||||
|
||||
N: Michal Simek
|
||||
E: monstr@monstr.eu
|
||||
D: Support for Microblaze, ML401, XUPV2P board
|
||||
W: www.monstr.eu
|
||||
|
|
|
|||
10
MAINTAINERS
10
MAINTAINERS
|
|
@ -611,6 +611,16 @@ Zachary P. Landau <zachary.landau@labxtechnologies.com>
|
|||
|
||||
r5200 mcf52x2
|
||||
|
||||
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
|
||||
|
||||
M5235EVB mcf52x2
|
||||
M5329EVB mcf532x
|
||||
M54455EVB mcf5445x
|
||||
|
||||
Hayden Fraser <Hayden.Fraser@freescale.com>
|
||||
|
||||
M5253EVBE mcf52x2
|
||||
|
||||
#########################################################################
|
||||
# AVR32 Systems: #
|
||||
# #
|
||||
|
|
|
|||
7
MAKEALL
7
MAKEALL
|
|
@ -620,11 +620,16 @@ LIST_coldfire=" \
|
|||
EB+MCF-EV123 \
|
||||
EB+MCF-EV123_internal \
|
||||
idmr \
|
||||
M5235EVB \
|
||||
M5249EVB \
|
||||
M5253EVB \
|
||||
M5271EVB \
|
||||
M5272C3 \
|
||||
M5282EVB \
|
||||
TASREG \
|
||||
M5329EVB \
|
||||
M54455EVB \
|
||||
r5200 \
|
||||
TASREG \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
|
|
|
|||
67
Makefile
67
Makefile
|
|
@ -209,12 +209,14 @@ LIBS += drivers/libdrivers.a
|
|||
LIBS += drivers/bios_emulator/libatibiosemu.a
|
||||
LIBS += drivers/nand/libnand.a
|
||||
LIBS += drivers/nand_legacy/libnand_legacy.a
|
||||
LIBS += drivers/net/libnet.a
|
||||
ifeq ($(CPU),mpc83xx)
|
||||
LIBS += drivers/qe/qe.a
|
||||
endif
|
||||
ifeq ($(CPU),mpc85xx)
|
||||
LIBS += drivers/qe/qe.a
|
||||
endif
|
||||
LIBS += drivers/serial/libserial.a
|
||||
LIBS += drivers/sk98lin/libsk98lin.a
|
||||
LIBS += post/libpost.a post/drivers/libpostdrivers.a
|
||||
LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
|
||||
|
|
@ -1637,6 +1639,31 @@ ZPC1900_config: unconfig
|
|||
## Coldfire
|
||||
#########################################################################
|
||||
|
||||
M5235EVB_config \
|
||||
M5235EVB_Flash16_config \
|
||||
M5235EVB_Flash32_config: unconfig
|
||||
@case "$@" in \
|
||||
M5235EVB_config) FLASH=16;; \
|
||||
M5235EVB_Flash16_config) FLASH=16;; \
|
||||
M5235EVB_Flash32_config) FLASH=32;; \
|
||||
esac; \
|
||||
>include/config.h ; \
|
||||
if [ "$${FLASH}" != "16" ] ; then \
|
||||
echo "#define NORFLASH_PS32BIT 1" >> include/config.h ; \
|
||||
echo "TEXT_BASE = 0xFFC00000" > $(obj)board/freescale/m5235evb/config.tmp ; \
|
||||
cp $(obj)board/freescale/m5235evb/u-boot.32 $(obj)board/freescale/m5235evb/u-boot.lds ; \
|
||||
else \
|
||||
echo "TEXT_BASE = 0xFFE00000" > $(obj)board/freescale/m5235evb/config.tmp ; \
|
||||
cp $(obj)board/freescale/m5235evb/u-boot.16 $(obj)board/freescale/m5235evb/u-boot.lds ; \
|
||||
fi
|
||||
@$(MKCONFIG) -a M5235EVB m68k mcf523x m5235evb freescale
|
||||
|
||||
M5249EVB_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5249evb freescale
|
||||
|
||||
M5253EVBE_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5253evbe freescale
|
||||
|
||||
cobra5272_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 cobra5272
|
||||
|
||||
|
|
@ -1672,6 +1699,46 @@ TASREG_config : unconfig
|
|||
r5200_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 r5200
|
||||
|
||||
M5329AFEE_config \
|
||||
M5329BFEE_config : unconfig
|
||||
@case "$@" in \
|
||||
M5329AFEE_config) NAND=0;; \
|
||||
M5329BFEE_config) NAND=16;; \
|
||||
esac; \
|
||||
>include/config.h ; \
|
||||
if [ "$${NAND}" != "0" ] ; then \
|
||||
echo "#define NANDFLASH_SIZE $${NAND}" > $(obj)include/config.h ; \
|
||||
fi
|
||||
@$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale
|
||||
|
||||
M54455EVB_config \
|
||||
M54455EVB_atmel_config \
|
||||
M54455EVB_intel_config \
|
||||
M54455EVB_a33_config \
|
||||
M54455EVB_a66_config \
|
||||
M54455EVB_i33_config \
|
||||
M54455EVB_i66_config : unconfig
|
||||
@case "$@" in \
|
||||
M54455EVB_config) FLASH=ATMEL; FREQ=33333333;; \
|
||||
M54455EVB_atmel_config) FLASH=ATMEL; FREQ=33333333;; \
|
||||
M54455EVB_intel_config) FLASH=INTEL; FREQ=33333333;; \
|
||||
M54455EVB_a33_config) FLASH=ATMEL; FREQ=33333333;; \
|
||||
M54455EVB_a66_config) FLASH=ATMEL; FREQ=66666666;; \
|
||||
M54455EVB_i33_config) FLASH=INTEL; FREQ=33333333;; \
|
||||
M54455EVB_i66_config) FLASH=INTEL; FREQ=66666666;; \
|
||||
esac; \
|
||||
>include/config.h ; \
|
||||
if [ "$${FLASH}" == "INTEL" ] ; then \
|
||||
echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
|
||||
echo "... with INTEL boot..." ; \
|
||||
else \
|
||||
echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
|
||||
echo "... with ATMEL boot..." ; \
|
||||
fi; \
|
||||
echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
|
||||
echo "... with $${FREQ}Hz input clock"
|
||||
@$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale
|
||||
|
||||
#########################################################################
|
||||
## MPC83xx Systems
|
||||
#########################################################################
|
||||
|
|
|
|||
2
README
2
README
|
|
@ -136,6 +136,8 @@ Directory Hierarchy:
|
|||
- i386 Files specific to i386 CPUs
|
||||
- ixp Files specific to Intel XScale IXP CPUs
|
||||
- mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs
|
||||
- mcf532x Files specific to Freescale ColdFire MCF5329 CPUs
|
||||
- mcf5445x Files specific to Freescale ColdFire MCF5445x CPUs
|
||||
- mips Files specific to MIPS CPUs
|
||||
- mpc5xx Files specific to Freescale MPC5xx CPUs
|
||||
- mpc5xxx Files specific to Freescale MPC5xxx CPUs
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o
|
||||
COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o mii.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
|||
304
board/BuS/EB+MCF-EV123/mii.c
Normal file
304
board/BuS/EB+MCF-EV123/mii.c
Normal file
|
|
@ -0,0 +1,304 @@
|
|||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
if (setclear) {
|
||||
MCFGPIO_PASPAR |= 0x0F00;
|
||||
MCFGPIO_PEHLPAR = CFG_PEHLPAR;
|
||||
} else {
|
||||
MCFGPIO_PASPAR &= 0xF0FF;
|
||||
MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_AMD79C874VC "AMD79C874VC"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_AMD79C874VC);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
printf(STR_ID_AMD79C874VC);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY */
|
||||
|
||||
int mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
|
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o
|
||||
COBJS = $(BOARD).o flash.o mii.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
|||
|
|
@ -22,8 +22,7 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/m5272.h>
|
||||
#include <asm/immap_5272.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
|
||||
int checkboard (void)
|
||||
|
|
@ -35,7 +34,7 @@ int checkboard (void)
|
|||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
volatile sdramctrl_t *sdp = (sdramctrl_t *) (CFG_MBAR + MCFSIM_SDCR);
|
||||
volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
|
||||
|
||||
sdp->sdram_sdtr = 0xf539;
|
||||
sdp->sdram_sdcr = 0x4211;
|
||||
|
|
|
|||
303
board/cobra5272/mii.c
Normal file
303
board/cobra5272/mii.c
Normal file
|
|
@ -0,0 +1,303 @@
|
|||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
|
||||
} else {
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_AMD79C874VC "AMD79C874VC"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_AMD79C874VC);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
printf(STR_ID_AMD79C874VC);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY */
|
||||
|
||||
int mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
44
board/freescale/m5235evb/Makefile
Normal file
44
board/freescale/m5235evb/Makefile
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
#
|
||||
# (C) Copyright 2000-2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
28
board/freescale/m5235evb/config.mk
Normal file
28
board/freescale/m5235evb/config.mk
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
#
|
||||
# (C) Copyright 2000-2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
/*TEXT_BASE = 0xFFC00000*/
|
||||
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
|
||||
|
||||
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
|
||||
117
board/freescale/m5235evb/m5235evb.c
Normal file
117
board/freescale/m5235evb/m5235evb.c
Normal file
|
|
@ -0,0 +1,117 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: ");
|
||||
puts("Freescale M5235 EVB\n");
|
||||
return 0;
|
||||
};
|
||||
|
||||
long int initdram(int board_type)
|
||||
{
|
||||
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
|
||||
volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
|
||||
u32 dramsize, i, dramclk;
|
||||
|
||||
/*
|
||||
* When booting from external Flash, the port-size is less than
|
||||
* the port-size of SDRAM. In this case it is necessary to enable
|
||||
* Data[15:0] on Port Address/Data.
|
||||
*/
|
||||
gpio->par_ad =
|
||||
GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
|
||||
GPIO_PAR_AD_DATAL;
|
||||
|
||||
/* Initialize PAR to enable SDRAM signals */
|
||||
gpio->par_sdram =
|
||||
GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS |
|
||||
GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3);
|
||||
|
||||
dramsize = CFG_SDRAM_SIZE * 0x100000;
|
||||
for (i = 0x13; i < 0x20; i++) {
|
||||
if (dramsize == (1 << i))
|
||||
break;
|
||||
}
|
||||
i--;
|
||||
|
||||
if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) {
|
||||
dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ);
|
||||
|
||||
/* Initialize DRAM Control Register: DCR */
|
||||
sdram->dcr = SDRAMC_DCR_RTIM_9CLKS |
|
||||
SDRAMC_DCR_RTIM_6CLKS | SDRAMC_DCR_RC((15 * dramclk) >> 4);
|
||||
|
||||
/* Initialize DACR0 */
|
||||
sdram->dacr0 =
|
||||
SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
|
||||
SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
|
||||
|
||||
/* Initialize DMR0 */
|
||||
sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
|
||||
|
||||
/* Set IP (bit 3) in DACR */
|
||||
sdram->dacr0 |= SDRAMC_DARCn_IP;
|
||||
|
||||
/* Wait 30ns to allow banks to precharge */
|
||||
for (i = 0; i < 5; i++) {
|
||||
asm("nop");
|
||||
}
|
||||
|
||||
/* Write to this block to initiate precharge */
|
||||
*(u32 *) (CFG_SDRAM_BASE) = 0xA5A59696;
|
||||
|
||||
/* Set RE (bit 15) in DACR */
|
||||
sdram->dacr0 |= SDRAMC_DARCn_RE;
|
||||
|
||||
/* Wait for at least 8 auto refresh cycles to occur */
|
||||
for (i = 0; i < 0x2000; i++) {
|
||||
asm("nop");
|
||||
}
|
||||
|
||||
/* Finish the configuration by issuing the MRS. */
|
||||
sdram->dacr0 |= SDRAMC_DARCn_IMRS;
|
||||
|
||||
/* Write to the SDRAM Mode Register */
|
||||
*(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
|
||||
}
|
||||
|
||||
return dramsize;
|
||||
};
|
||||
|
||||
int testdram(void)
|
||||
{
|
||||
/* TODO: XXX XXX XXX */
|
||||
printf("DRAM test not implemented!\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
307
board/freescale/m5235evb/mii.c
Normal file
307
board/freescale/m5235evb/mii.c
Normal file
|
|
@ -0,0 +1,307 @@
|
|||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
gpio->par_feci2c |=
|
||||
(GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
|
||||
} else {
|
||||
gpio->par_feci2c &=
|
||||
~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
#define STR_ID_KS8721BL "KS8721BL"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_KS8721BL);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
printf(STR_ID_KS8721BL);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY */
|
||||
|
||||
int mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
145
board/freescale/m5235evb/u-boot.16
Normal file
145
board/freescale/m5235evb/u-boot.16
Normal file
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(m68k)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/mcf523x/start.o (.text)
|
||||
cpu/mcf523x/cpu_init.o (.text)
|
||||
lib_m68k/traps.o (.text)
|
||||
lib_m68k/interrupts.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .;
|
||||
common/environment.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
|
||||
.reloc :
|
||||
{
|
||||
__got_start = .;
|
||||
*(.got)
|
||||
__got_end = .;
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
_sbss = .;
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
153
board/freescale/m5235evb/u-boot.32
Normal file
153
board/freescale/m5235evb/u-boot.32
Normal file
|
|
@ -0,0 +1,153 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(m68k)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/mcf523x/start.o (.text)
|
||||
cpu/mcf523x/cpu.o (.text)
|
||||
cpu/mcf523x/cpu_init.o (.text)
|
||||
cpu/mcf523x/interrupts.o (.text)
|
||||
cpu/mcf523x/speed.o (.text)
|
||||
lib_m68k/libm68k.a (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
common/cmd_bootm.o (.text)
|
||||
common/cmd_flash.o (.text)
|
||||
common/cmd_elf.o (.text)
|
||||
common/cmd_mem.o (.text)
|
||||
common/console.o (.text)
|
||||
common/main.o (.text)
|
||||
lib_generic/libgeneric.a (.text)
|
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .;
|
||||
common/environment.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
|
||||
.reloc :
|
||||
{
|
||||
__got_start = .;
|
||||
*(.got)
|
||||
__got_end = .;
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
_sbss = .;
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
145
board/freescale/m5235evb/u-boot.lds
Normal file
145
board/freescale/m5235evb/u-boot.lds
Normal file
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(m68k)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/mcf523x/start.o (.text)
|
||||
cpu/mcf523x/cpu_init.o (.text)
|
||||
lib_m68k/traps.o (.text)
|
||||
lib_m68k/interrupts.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .;
|
||||
common/environment.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
|
||||
.reloc :
|
||||
{
|
||||
__got_start = .;
|
||||
*(.got)
|
||||
__got_end = .;
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
_sbss = .;
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
44
board/freescale/m5249evb/Makefile
Normal file
44
board/freescale/m5249evb/Makefile
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
25
board/freescale/m5249evb/config.mk
Normal file
25
board/freescale/m5249evb/config.mk
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
#
|
||||
# (C) Copyright 2000-2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xffe00000
|
||||
113
board/freescale/m5249evb/m5249evb.c
Normal file
113
board/freescale/m5249evb/m5249evb.c
Normal file
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* (C) Copyright 2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <malloc.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
|
||||
/* Prototypes */
|
||||
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
|
||||
|
||||
int checkboard (void) {
|
||||
ulong val;
|
||||
uchar val8;
|
||||
|
||||
puts ("Board: ");
|
||||
puts("Freescale M5249EVB");
|
||||
val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
|
||||
printf(" (Switch=%1X)\n", val8);
|
||||
|
||||
/*
|
||||
* Set LED on
|
||||
*/
|
||||
val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_GPIO1_LED;
|
||||
mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */
|
||||
|
||||
return 0;
|
||||
};
|
||||
|
||||
|
||||
long int initdram (int board_type) {
|
||||
unsigned long junk = 0xa5a59696;
|
||||
|
||||
/*
|
||||
* Note:
|
||||
* RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
|
||||
*/
|
||||
|
||||
#ifdef CFG_FAST_CLK
|
||||
/*
|
||||
* Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
|
||||
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
|
||||
*/
|
||||
mbar_writeShort(MCFSIM_DCR, 0x8239);
|
||||
#elif CFG_PLL_BYPASS
|
||||
/*
|
||||
* Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
|
||||
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
|
||||
*/
|
||||
mbar_writeShort(MCFSIM_DCR, 0x8202);
|
||||
#else
|
||||
/*
|
||||
* Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
|
||||
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
|
||||
*/
|
||||
mbar_writeShort(MCFSIM_DCR, 0x8222);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
|
||||
* PM=1 (continuous page mode)
|
||||
*/
|
||||
|
||||
/* RE=0 (keep auto-refresh disabled while setting up registers) */
|
||||
mbar_writeLong(MCFSIM_DACR0, 0x00003324);
|
||||
|
||||
/* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
|
||||
mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
|
||||
|
||||
/** Precharge sequence **/
|
||||
mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
|
||||
*((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */
|
||||
udelay(0x10); /* Allow several Precharge cycles */
|
||||
|
||||
/** Refresh Sequence **/
|
||||
mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
|
||||
udelay(0x7d0); /* Allow gobs of refresh cycles */
|
||||
|
||||
/** Mode Register initialization **/
|
||||
mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
|
||||
*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
|
||||
|
||||
return CFG_SDRAM_SIZE * 1024 * 1024;
|
||||
};
|
||||
|
||||
|
||||
int testdram (void) {
|
||||
/* TODO: XXX XXX XXX */
|
||||
printf ("DRAM test not implemented!\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
146
board/freescale/m5249evb/u-boot.lds
Normal file
146
board/freescale/m5249evb/u-boot.lds
Normal file
|
|
@ -0,0 +1,146 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(m68k)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/mcf52x2/start.o (.text)
|
||||
lib_m68k/traps.o (.text)
|
||||
cpu/mcf52x2/interrupts.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .;
|
||||
common/environment.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
|
||||
.reloc :
|
||||
{
|
||||
__got_start = .;
|
||||
*(.got)
|
||||
__got_end = .;
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
_sbss = .;
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
44
board/freescale/m5253evbe/Makefile
Normal file
44
board/freescale/m5253evbe/Makefile
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
25
board/freescale/m5253evbe/config.mk
Normal file
25
board/freescale/m5253evbe/config.mk
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
#
|
||||
# (C) Copyright 2000-2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xffe00000
|
||||
132
board/freescale/m5253evbe/m5253evbe.c
Normal file
132
board/freescale/m5253evbe/m5253evbe.c
Normal file
|
|
@ -0,0 +1,132 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* Hayden Fraser (Hayden.Fraser@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: ");
|
||||
puts("Freescale MCF5253 EVBE\n");
|
||||
return 0;
|
||||
};
|
||||
|
||||
long int initdram(int board_type)
|
||||
{
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Check to see if the SDRAM has already been initialized
|
||||
* by a run control tool
|
||||
*/
|
||||
if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
|
||||
u32 RC, dramsize;
|
||||
|
||||
RC = (CFG_CLK / 1000000) >> 1;
|
||||
RC = (RC * 15) >> 4;
|
||||
|
||||
/* Initialize DRAM Control Register: DCR */
|
||||
mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
|
||||
|
||||
mbar_writeLong(MCFSIM_DACR0, 0x00003224);
|
||||
|
||||
/* Initialize DMR0 */
|
||||
dramsize = ((CFG_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
|
||||
mbar_writeLong(MCFSIM_DMR0, dramsize | 1);
|
||||
|
||||
mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
|
||||
|
||||
/* Write to this block to initiate precharge */
|
||||
*(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5;
|
||||
|
||||
/* Set RE bit in DACR */
|
||||
mbar_writeLong(MCFSIM_DACR0,
|
||||
mbar_readLong(MCFSIM_DACR0) | 0x8000);
|
||||
|
||||
/* Wait for at least 8 auto refresh cycles to occur */
|
||||
udelay(500);
|
||||
|
||||
/* Finish the configuration by issuing the MRS */
|
||||
mbar_writeLong(MCFSIM_DACR0,
|
||||
mbar_readLong(MCFSIM_DACR0) | 0x0040);
|
||||
|
||||
*(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
|
||||
}
|
||||
|
||||
return CFG_SDRAM_SIZE * 1024 * 1024;
|
||||
}
|
||||
|
||||
int testdram(void)
|
||||
{
|
||||
/* TODO: XXX XXX XXX */
|
||||
printf("DRAM test not implemented!\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_IDE
|
||||
#include <ata.h>
|
||||
int ide_preinit(void)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
void ide_set_reset(int idereset)
|
||||
{
|
||||
volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR;
|
||||
long period;
|
||||
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
|
||||
int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
|
||||
{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
|
||||
{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
|
||||
{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
|
||||
{25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
|
||||
};
|
||||
|
||||
if (idereset) {
|
||||
ata->cr = 0; /* control reset */
|
||||
udelay(100);
|
||||
} else {
|
||||
mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
|
||||
|
||||
#define CALC_TIMING(t) (t + period - 1) / period
|
||||
period = 1000000000 / (CFG_CLK / 2); /* period in ns */
|
||||
|
||||
/*ata->ton = CALC_TIMING (180); */
|
||||
ata->t1 = CALC_TIMING(piotms[2][0]);
|
||||
ata->t2w = CALC_TIMING(piotms[2][1]);
|
||||
ata->t2r = CALC_TIMING(piotms[2][1]);
|
||||
ata->ta = CALC_TIMING(piotms[2][8]);
|
||||
ata->trd = CALC_TIMING(piotms[2][7]);
|
||||
ata->t4 = CALC_TIMING(piotms[2][3]);
|
||||
ata->t9 = CALC_TIMING(piotms[2][6]);
|
||||
|
||||
ata->cr = 0x40; /* IORDY enable */
|
||||
udelay(2000);
|
||||
ata->cr |= 0x01; /* IORDY enable */
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_CMD_IDE */
|
||||
144
board/freescale/m5253evbe/u-boot.lds
Normal file
144
board/freescale/m5253evbe/u-boot.lds
Normal file
|
|
@ -0,0 +1,144 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(m68k)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/mcf52x2/start.o (.text)
|
||||
lib_m68k/traps.o (.text)
|
||||
cpu/mcf52x2/interrupts.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .;
|
||||
common/environment.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
|
||||
.reloc :
|
||||
{
|
||||
__got_start = .;
|
||||
*(.got)
|
||||
__got_end = .;
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
_sbss = .;
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
44
board/freescale/m5329evb/Makefile
Normal file
44
board/freescale/m5329evb/Makefile
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
#
|
||||
# (C) Copyright 2000-2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o nand.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
25
board/freescale/m5329evb/config.mk
Normal file
25
board/freescale/m5329evb/config.mk
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
#
|
||||
# (C) Copyright 2000-2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0
|
||||
88
board/freescale/m5329evb/m5329evb.c
Normal file
88
board/freescale/m5329evb/m5329evb.c
Normal file
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: ");
|
||||
puts("Freescale FireEngine 5329 EVB\n");
|
||||
return 0;
|
||||
};
|
||||
|
||||
long int initdram(int board_type)
|
||||
{
|
||||
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
|
||||
u32 dramsize, i;
|
||||
|
||||
dramsize = CFG_SDRAM_SIZE * 0x100000;
|
||||
|
||||
for (i = 0x13; i < 0x20; i++) {
|
||||
if (dramsize == (1 << i))
|
||||
break;
|
||||
}
|
||||
i--;
|
||||
|
||||
sdram->cs0 = (CFG_SDRAM_BASE | i);
|
||||
sdram->cfg1 = CFG_SDRAM_CFG1;
|
||||
sdram->cfg2 = CFG_SDRAM_CFG2;
|
||||
|
||||
/* Issue PALL */
|
||||
sdram->ctrl = CFG_SDRAM_CTRL | 2;
|
||||
|
||||
/* Issue LEMR */
|
||||
sdram->mode = CFG_SDRAM_EMOD;
|
||||
sdram->mode = (CFG_SDRAM_MODE | 0x04000000);
|
||||
|
||||
udelay(500);
|
||||
|
||||
/* Issue PALL */
|
||||
sdram->ctrl = (CFG_SDRAM_CTRL | 2);
|
||||
|
||||
/* Perform two refresh cycles */
|
||||
sdram->ctrl = CFG_SDRAM_CTRL | 4;
|
||||
sdram->ctrl = CFG_SDRAM_CTRL | 4;
|
||||
|
||||
sdram->mode = CFG_SDRAM_MODE;
|
||||
|
||||
sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
|
||||
|
||||
udelay(100);
|
||||
|
||||
return dramsize;
|
||||
};
|
||||
|
||||
int testdram(void)
|
||||
{
|
||||
/* TODO: XXX XXX XXX */
|
||||
printf("DRAM test not implemented!\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
306
board/freescale/m5329evb/mii.c
Normal file
306
board/freescale/m5329evb/mii.c
Normal file
|
|
@ -0,0 +1,306 @@
|
|||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
|
||||
gpio->par_feci2c |=
|
||||
GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
|
||||
} else {
|
||||
gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
|
||||
gpio->par_feci2c &=
|
||||
~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_DP83848VV:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_DP83848VV);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_DP83848VV:
|
||||
printf(STR_ID_DP83848VV);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY */
|
||||
|
||||
int mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
114
board/freescale/m5329evb/nand.c
Normal file
114
board/freescale/m5329evb/nand.c
Normal file
|
|
@ -0,0 +1,114 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
#include <nand.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
|
||||
#define SET_CLE 0x10
|
||||
#define CLR_CLE ~SET_CLE
|
||||
#define SET_ALE 0x08
|
||||
#define CLR_ALE ~SET_ALE
|
||||
|
||||
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
|
||||
{
|
||||
struct nand_chip *this = mtdinfo->priv;
|
||||
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
|
||||
u32 nand_baseaddr = (u32) this->IO_ADDR_W;
|
||||
|
||||
switch (cmd) {
|
||||
case NAND_CTL_SETNCE:
|
||||
case NAND_CTL_CLRNCE:
|
||||
break;
|
||||
case NAND_CTL_SETCLE:
|
||||
nand_baseaddr |= SET_CLE;
|
||||
break;
|
||||
case NAND_CTL_CLRCLE:
|
||||
nand_baseaddr &= CLR_CLE;
|
||||
break;
|
||||
case NAND_CTL_SETALE:
|
||||
nand_baseaddr |= SET_ALE;
|
||||
break;
|
||||
case NAND_CTL_CLRALE:
|
||||
nand_baseaddr |= CLR_ALE;
|
||||
break;
|
||||
case NAND_CTL_SETWP:
|
||||
fbcs->csmr2 |= CSMR_WP;
|
||||
break;
|
||||
case NAND_CTL_CLRWP:
|
||||
fbcs->csmr2 &= ~CSMR_WP;
|
||||
break;
|
||||
}
|
||||
this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
|
||||
}
|
||||
|
||||
static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte)
|
||||
{
|
||||
struct nand_chip *this = mtdinfo->priv;
|
||||
*((volatile u8 *)(this->IO_ADDR_W)) = byte;
|
||||
}
|
||||
|
||||
static u8 nand_read_byte(struct mtd_info *mtdinfo)
|
||||
{
|
||||
struct nand_chip *this = mtdinfo->priv;
|
||||
return (u8) (*((volatile u8 *)this->IO_ADDR_R));
|
||||
}
|
||||
|
||||
static int nand_dev_ready(struct mtd_info *mtdinfo)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
*((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004;
|
||||
|
||||
/* set up pin configuration */
|
||||
gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
|
||||
gpio->pddr_timer |= 0x08;
|
||||
gpio->ppd_timer |= 0x08;
|
||||
gpio->pclrr_timer = 0;
|
||||
gpio->podr_timer = 0;
|
||||
|
||||
nand->chip_delay = 50;
|
||||
nand->eccmode = NAND_ECC_SOFT;
|
||||
nand->hwcontrol = nand_hwcontrol;
|
||||
nand->read_byte = nand_read_byte;
|
||||
nand->write_byte = nand_write_byte;
|
||||
nand->dev_ready = nand_dev_ready;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
144
board/freescale/m5329evb/u-boot.lds
Normal file
144
board/freescale/m5329evb/u-boot.lds
Normal file
|
|
@ -0,0 +1,144 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(m68k)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/mcf532x/start.o (.text)
|
||||
lib_m68k/traps.o (.text)
|
||||
lib_m68k/interrupts.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .;
|
||||
common/environment.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
|
||||
.reloc :
|
||||
{
|
||||
__got_start = .;
|
||||
*(.got)
|
||||
__got_end = .;
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
_sbss = .;
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
44
board/freescale/m54455evb/Makefile
Normal file
44
board/freescale/m54455evb/Makefile
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
#
|
||||
# (C) Copyright 2000-2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o mii.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
25
board/freescale/m54455evb/config.mk
Normal file
25
board/freescale/m54455evb/config.mk
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
#
|
||||
# (C) Copyright 2000-2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0
|
||||
974
board/freescale/m54455evb/flash.c
Normal file
974
board/freescale/m54455evb/flash.c
Normal file
|
|
@ -0,0 +1,974 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#include <asm/immap.h>
|
||||
|
||||
#ifndef CFG_FLASH_CFI
|
||||
typedef unsigned char FLASH_PORT_WIDTH;
|
||||
typedef volatile unsigned char FLASH_PORT_WIDTHV;
|
||||
|
||||
#define FPW FLASH_PORT_WIDTH
|
||||
#define FPWV FLASH_PORT_WIDTHV
|
||||
|
||||
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
|
||||
#define CFG_FLASH_NONCFI_WIDTH FLASH_CFI_8BIT
|
||||
|
||||
/* Intel-compatible flash commands */
|
||||
#define INTEL_PROGRAM 0x00100010
|
||||
#define INTEL_ERASE 0x00200020
|
||||
#define INTEL_WRSETUP 0x00400040
|
||||
#define INTEL_CLEAR 0x00500050
|
||||
#define INTEL_LOCKBIT 0x00600060
|
||||
#define INTEL_PROTECT 0x00010001
|
||||
#define INTEL_STATUS 0x00700070
|
||||
#define INTEL_READID 0x00900090
|
||||
#define INTEL_CFIQRY 0x00980098
|
||||
#define INTEL_SUSERASE 0x00B000B0
|
||||
#define INTEL_PROTPROG 0x00C000C0
|
||||
#define INTEL_CONFIRM 0x00D000D0
|
||||
#define INTEL_WRBLK 0x00e800e8
|
||||
#define INTEL_RESET 0x00FF00FF
|
||||
|
||||
/* Intel-compatible flash status bits */
|
||||
#define INTEL_FINISHED 0x00800080
|
||||
#define INTEL_OK 0x00800080
|
||||
#define INTEL_ERASESUS 0x00600060
|
||||
#define INTEL_WSM_SUS (INTEL_FINISHED | INTEL_ERASESUS)
|
||||
|
||||
/* 28F160C3B CFI Data offset - This could vary */
|
||||
#define INTEL_CFI_MFG 0x00 /* Manufacturer ID */
|
||||
#define INTEL_CFI_PART 0x01 /* Product ID */
|
||||
#define INTEL_CFI_LOCK 0x02 /* */
|
||||
#define INTEL_CFI_TWPRG 0x1F /* Typical Single Word Program Timeout 2^n us */
|
||||
#define INTEL_CFI_MBUFW 0x20 /* Typical Max Buffer Write Timeout 2^n us */
|
||||
#define INTEL_CFI_TERB 0x21 /* Typical Block Erase Timeout 2^n ms */
|
||||
#define INTEL_CFI_MWPRG 0x23 /* Maximum Word program timeout 2^n us */
|
||||
#define INTEL_CFI_MERB 0x25 /* Maximum Block Erase Timeout 2^n s */
|
||||
#define INTEL_CFI_SIZE 0x27 /* Device size 2^n bytes */
|
||||
#define INTEL_CFI_CAP 0x28
|
||||
#define INTEL_CFI_WRBUF 0x2A
|
||||
#define INTEL_CFI_BANK 0x2C /* Number of Bank */
|
||||
#define INTEL_CFI_BLK1A 0x2D /* Number of Blocks */
|
||||
#define INTEL_CFI_BLK1B 0x2E /* Number of Blocks */
|
||||
#define INTEL_CFI_SZ1A 0x2F /* Block Region Size */
|
||||
#define INTEL_CFI_SZ1B 0x30
|
||||
#define INTEL_CFI_BLK2A 0x31
|
||||
#define INTEL_CFI_BLK2B 0x32
|
||||
#define INTEL_CFI_SZ2A 0x33
|
||||
#define INTEL_CFI_SZ2B 0x34
|
||||
|
||||
#define FLASH_CYCLE1 0x0555
|
||||
#define FLASH_CYCLE2 0x0aaa
|
||||
|
||||
#define WR_BLOCK 0x20
|
||||
|
||||
/* not in the flash.h yet */
|
||||
#define FLASH_28F64P30T 0x00B9 /* Intel 28F64P30T ( 64M) */
|
||||
#define FLASH_28F64P30B 0x00BA /* Intel 28F64P30B ( 64M) */
|
||||
#define FLASH_28F128P30T 0x00BB /* Intel 28F128P30T ( 128M = 8M x 16 ) */
|
||||
#define FLASH_28F128P30B 0x00BC /* Intel 28F128P30B ( 128M = 8M x 16 ) */
|
||||
#define FLASH_28F256P30T 0x00BD /* Intel 28F256P30T ( 256M = 16M x 16 ) */
|
||||
#define FLASH_28F256P30B 0x00BE /* Intel 28F256P30B ( 256M = 16M x 16 ) */
|
||||
|
||||
#define SYNC __asm__("nop")
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
|
||||
ulong flash_get_size(FPWV * addr, flash_info_t * info);
|
||||
int flash_get_offsets(ulong base, flash_info_t * info);
|
||||
int flash_cmd_rd(volatile u16 * addr, int index);
|
||||
int write_data(flash_info_t * info, ulong dest, FPW data);
|
||||
int write_data_block(flash_info_t * info, ulong src, ulong dest);
|
||||
int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data);
|
||||
void inline spin_wheel(void);
|
||||
void flash_sync_real_protect(flash_info_t * info);
|
||||
uchar intel_sector_protected(flash_info_t * info, ushort sector);
|
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
|
||||
|
||||
ulong flash_init(void)
|
||||
{
|
||||
int i;
|
||||
ulong size = 0;
|
||||
ulong fbase = 0;
|
||||
|
||||
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
|
||||
memset(&flash_info[i], 0, sizeof(flash_info_t));
|
||||
|
||||
switch (i) {
|
||||
case 0:
|
||||
fbase = (ulong) CFG_FLASH0_BASE;
|
||||
break;
|
||||
case 1:
|
||||
fbase = (ulong) CFG_FLASH1_BASE;
|
||||
break;
|
||||
}
|
||||
|
||||
flash_get_size((FPWV *) fbase, &flash_info[i]);
|
||||
flash_get_offsets((ulong) fbase, &flash_info[i]);
|
||||
fbase += flash_info[i].size;
|
||||
size += flash_info[i].size;
|
||||
|
||||
/* get the h/w and s/w protection status in sync */
|
||||
flash_sync_real_protect(&flash_info[i]);
|
||||
}
|
||||
|
||||
/* Protect monitor and environment sectors */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CFG_MONITOR_BASE,
|
||||
CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
int flash_get_offsets(ulong base, flash_info_t * info)
|
||||
{
|
||||
int i, j, k;
|
||||
int sectors, bs, banks;
|
||||
ulong start;
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_ATM) {
|
||||
int sect[] = CFG_ATMEL_SECT;
|
||||
int sectsz[] = CFG_ATMEL_SECTSZ;
|
||||
|
||||
info->start[0] = base;
|
||||
for (k = 0, i = 0; i < CFG_ATMEL_REGION; i++) {
|
||||
for (j = 0; j < sect[i]; j++, k++) {
|
||||
info->start[k + 1] = info->start[k] + sectsz[i];
|
||||
info->protect[k] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
|
||||
volatile u16 *addr16 = (volatile u16 *)base;
|
||||
|
||||
*addr16 = (FPW) INTEL_RESET; /* restore read mode */
|
||||
*addr16 = (FPW) INTEL_READID;
|
||||
|
||||
banks = addr16[INTEL_CFI_BANK] & 0xff;
|
||||
|
||||
sectors = 0;
|
||||
info->start[0] = base;
|
||||
|
||||
for (k = 0, i = 0; i < banks; i++) {
|
||||
/* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec.
|
||||
* To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count
|
||||
* Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count
|
||||
*/
|
||||
bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8)
|
||||
| (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) *
|
||||
0x100);
|
||||
sectors =
|
||||
(addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1;
|
||||
|
||||
for (j = 0; j < sectors; j++, k++) {
|
||||
info->start[k + 1] = info->start[k] + bs;
|
||||
}
|
||||
}
|
||||
|
||||
*addr16 = (FPW) INTEL_RESET; /* restore read mode */
|
||||
}
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
void flash_print_info(flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_INTEL:
|
||||
printf("INTEL ");
|
||||
break;
|
||||
case FLASH_MAN_ATM:
|
||||
printf("ATMEL ");
|
||||
break;
|
||||
default:
|
||||
printf("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_AT040:
|
||||
printf("AT49BV040A\n");
|
||||
break;
|
||||
case FLASH_28F128J3A:
|
||||
printf("Intel 28F128J3A\n");
|
||||
break;
|
||||
default:
|
||||
printf("Unknown Chip Type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (info->size > 0x100000) {
|
||||
int remainder;
|
||||
|
||||
printf(" Size: %ld", info->size >> 20);
|
||||
|
||||
remainder = (info->size % 0x100000);
|
||||
if (remainder) {
|
||||
remainder >>= 10;
|
||||
remainder = (int)((float)
|
||||
(((float)remainder / (float)1024) *
|
||||
10000));
|
||||
printf(".%d ", remainder);
|
||||
}
|
||||
|
||||
printf("MB in %d Sectors\n", info->sector_count);
|
||||
} else
|
||||
printf(" Size: %ld KB in %d Sectors\n",
|
||||
info->size >> 10, info->sector_count);
|
||||
|
||||
printf(" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; ++i) {
|
||||
if ((i % 5) == 0)
|
||||
printf("\n ");
|
||||
printf(" %08lX%s",
|
||||
info->start[i], info->protect[i] ? " (RO)" : " ");
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
ulong flash_get_size(FPWV * addr, flash_info_t * info)
|
||||
{
|
||||
volatile u16 *addr16 = (volatile u16 *)addr;
|
||||
int intel = 0, banks = 0;
|
||||
u16 value;
|
||||
int i;
|
||||
|
||||
addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */
|
||||
addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */
|
||||
addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */
|
||||
|
||||
switch (addr[0] & 0xff) {
|
||||
case (u8) ATM_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_ATM;
|
||||
value = addr[1];
|
||||
break;
|
||||
case (u8) INTEL_MANUFACT:
|
||||
/* Terminate Atmel ID read */
|
||||
addr[0] = (FPWV) 0x00F000F0;
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
/* Write auto select command sequence and test FLASH answer */
|
||||
*addr16 = (FPW) INTEL_RESET; /* restore read mode */
|
||||
*addr16 = (FPW) INTEL_READID;
|
||||
|
||||
info->flash_id = FLASH_MAN_INTEL;
|
||||
value = (addr16[INTEL_CFI_MFG] << 8);
|
||||
value |= addr16[INTEL_CFI_PART] & 0xff;
|
||||
intel = 1;
|
||||
break;
|
||||
default:
|
||||
printf("Unknown Flash\n");
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
|
||||
*addr = (FPW) 0x00F000F0;
|
||||
*addr = (FPW) INTEL_RESET; /* restore read mode */
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
switch (value) {
|
||||
case (u8) ATM_ID_LV040:
|
||||
info->flash_id += FLASH_AT040;
|
||||
break;
|
||||
case (u16) INTEL_ID_28F128J3:
|
||||
info->flash_id += FLASH_28F128J3A;
|
||||
break;
|
||||
case (u16) INTEL_ID_28F64P30T:
|
||||
info->flash_id += FLASH_28F64P30T;
|
||||
break;
|
||||
case (u16) INTEL_ID_28F64P30B:
|
||||
info->flash_id += FLASH_28F64P30B;
|
||||
break;
|
||||
case (u16) INTEL_ID_28F128P30T:
|
||||
info->flash_id += FLASH_28F128P30T;
|
||||
break;
|
||||
case (u16) INTEL_ID_28F128P30B:
|
||||
info->flash_id += FLASH_28F128P30B;
|
||||
break;
|
||||
case (u16) INTEL_ID_28F256P30T:
|
||||
info->flash_id += FLASH_28F256P30T;
|
||||
break;
|
||||
case (u16) INTEL_ID_28F256P30B:
|
||||
info->flash_id += FLASH_28F256P30B;
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
break;
|
||||
}
|
||||
|
||||
if (intel) {
|
||||
/* Intel spec. under CFI section */
|
||||
u32 sz;
|
||||
int sectors, bs;
|
||||
|
||||
banks = addr16[INTEL_CFI_BANK] & 0xff;
|
||||
|
||||
sectors = sz = 0;
|
||||
for (i = 0; i < banks; i++) {
|
||||
/* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec.
|
||||
* To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count
|
||||
* Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count
|
||||
*/
|
||||
bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8)
|
||||
| (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) *
|
||||
0x100);
|
||||
sectors +=
|
||||
(addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1;
|
||||
sz += (bs * sectors);
|
||||
}
|
||||
|
||||
info->sector_count = sectors;
|
||||
info->size = sz;
|
||||
*addr = (FPW) INTEL_RESET; /* restore read mode */
|
||||
} else {
|
||||
int sect[] = CFG_ATMEL_SECT;
|
||||
int sectsz[] = CFG_ATMEL_SECTSZ;
|
||||
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
for (i = 0; i < CFG_ATMEL_REGION; i++) {
|
||||
info->sector_count += sect[i];
|
||||
info->size += sect[i] * sectsz[i];
|
||||
}
|
||||
|
||||
/* reset ID mode */
|
||||
addr[0] = (FPWV) 0x00F000F0;
|
||||
}
|
||||
|
||||
if (info->sector_count > CFG_MAX_FLASH_SECT) {
|
||||
printf("** ERROR: sector count %d > max (%d) **\n",
|
||||
info->sector_count, CFG_MAX_FLASH_SECT);
|
||||
info->sector_count = CFG_MAX_FLASH_SECT;
|
||||
}
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
int flash_cmd_rd(volatile u16 * addr, int index)
|
||||
{
|
||||
return (int)addr[index];
|
||||
}
|
||||
|
||||
/*
|
||||
* This function gets the u-boot flash sector protection status
|
||||
* (flash_info_t.protect[]) in sync with the sector protection
|
||||
* status stored in hardware.
|
||||
*/
|
||||
void flash_sync_real_protect(flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_28F160C3B:
|
||||
case FLASH_28F160C3T:
|
||||
case FLASH_28F320C3B:
|
||||
case FLASH_28F320C3T:
|
||||
case FLASH_28F640C3B:
|
||||
case FLASH_28F640C3T:
|
||||
for (i = 0; i < info->sector_count; ++i) {
|
||||
info->protect[i] = intel_sector_protected(info, i);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
/* no h/w protect support */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* checks if "sector" in bank "info" is protected. Should work on intel
|
||||
* strata flash chips 28FxxxJ3x in 8-bit mode.
|
||||
* Returns 1 if sector is protected (or timed-out while trying to read
|
||||
* protection status), 0 if it is not.
|
||||
*/
|
||||
uchar intel_sector_protected(flash_info_t * info, ushort sector)
|
||||
{
|
||||
FPWV *addr;
|
||||
FPWV *lock_conf_addr;
|
||||
ulong start;
|
||||
unsigned char ret;
|
||||
|
||||
/*
|
||||
* first, wait for the WSM to be finished. The rationale for
|
||||
* waiting for the WSM to become idle for at most
|
||||
* CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
|
||||
* because of: (1) erase, (2) program or (3) lock bit
|
||||
* configuration. So we just wait for the longest timeout of
|
||||
* the (1)-(3), i.e. the erase timeout.
|
||||
*/
|
||||
|
||||
/* wait at least 35ns (W12) before issuing Read Status Register */
|
||||
/*udelay(1); */
|
||||
addr = (FPWV *) info->start[sector];
|
||||
*addr = (FPW) INTEL_STATUS;
|
||||
|
||||
start = get_timer(0);
|
||||
while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
|
||||
if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
|
||||
*addr = (FPW) INTEL_RESET; /* restore read mode */
|
||||
printf("WSM busy too long, can't get prot status\n");
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
/* issue the Read Identifier Codes command */
|
||||
*addr = (FPW) INTEL_READID;
|
||||
|
||||
/* Intel example code uses offset of 4 for 8-bit flash */
|
||||
lock_conf_addr = (FPWV *) info->start[sector];
|
||||
ret = (lock_conf_addr[INTEL_CFI_LOCK] & (FPW) INTEL_PROTECT) ? 1 : 0;
|
||||
|
||||
/* put flash back in read mode */
|
||||
*addr = (FPW) INTEL_RESET;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int flash_erase(flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
int flag, prot, sect;
|
||||
ulong type, start, last;
|
||||
int rcode = 0, intel = 0;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN)
|
||||
printf("- missing\n");
|
||||
else
|
||||
printf("- no sectors to erase\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
type = (info->flash_id & FLASH_VENDMASK);
|
||||
|
||||
if (type != (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
|
||||
if (type != (FLASH_MAN_ATM & FLASH_VENDMASK)) {
|
||||
type = (info->flash_id & FLASH_VENDMASK);
|
||||
printf
|
||||
("Can't erase unknown flash type %08lx - aborted\n",
|
||||
info->flash_id);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (type == FLASH_MAN_INTEL)
|
||||
intel = 1;
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot)
|
||||
printf("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
else
|
||||
printf("\n");
|
||||
|
||||
start = get_timer(0);
|
||||
last = start;
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
|
||||
FPWV *addr = (FPWV *) (info->start[sect]);
|
||||
int min = 0;
|
||||
|
||||
printf(".");
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
start = get_timer(0);
|
||||
|
||||
if (intel) {
|
||||
*addr = (FPW) INTEL_READID;
|
||||
min = addr[INTEL_CFI_TERB] & 0xff;
|
||||
min = 1 << min; /* ms */
|
||||
min = (min / info->sector_count) * 1000;
|
||||
|
||||
/* start erase block */
|
||||
*addr = (FPW) INTEL_CLEAR; /* clear status register */
|
||||
*addr = (FPW) INTEL_ERASE; /* erase setup */
|
||||
*addr = (FPW) INTEL_CONFIRM; /* erase confirm */
|
||||
|
||||
while ((*addr & (FPW) INTEL_FINISHED) !=
|
||||
(FPW) INTEL_FINISHED) {
|
||||
|
||||
if (get_timer(start) >
|
||||
CFG_FLASH_ERASE_TOUT) {
|
||||
printf("Timeout\n");
|
||||
*addr = (FPW) INTEL_SUSERASE; /* suspend erase */
|
||||
*addr = (FPW) INTEL_RESET; /* reset to read mode */
|
||||
|
||||
rcode = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
*addr = (FPW) INTEL_RESET; /* resest to read mode */
|
||||
} else {
|
||||
FPWV *base; /* first address in bank */
|
||||
FPWV *atmeladdr;
|
||||
|
||||
flag = disable_interrupts();
|
||||
|
||||
atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */
|
||||
base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */
|
||||
|
||||
base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
|
||||
base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
|
||||
base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */
|
||||
base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
|
||||
base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
|
||||
*atmeladdr = (u8) 0x00300030; /* erase sector */
|
||||
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
while ((*atmeladdr & (u8) 0x00800080) !=
|
||||
(u8) 0x00800080) {
|
||||
if (get_timer(start) >
|
||||
CFG_FLASH_ERASE_TOUT) {
|
||||
printf("Timeout\n");
|
||||
*atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
|
||||
|
||||
rcode = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
*atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
|
||||
} /* Atmel or Intel */
|
||||
}
|
||||
}
|
||||
printf(" done\n");
|
||||
|
||||
return rcode;
|
||||
}
|
||||
|
||||
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
if (info->flash_id == FLASH_UNKNOWN)
|
||||
return 4;
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_ATM:
|
||||
{
|
||||
u16 data = 0;
|
||||
int bytes; /* number of bytes to program in current word */
|
||||
int left; /* number of bytes left to program */
|
||||
int i, res;
|
||||
|
||||
for (left = cnt, res = 0;
|
||||
left > 0 && res == 0;
|
||||
addr += sizeof(data), left -=
|
||||
sizeof(data) - bytes) {
|
||||
|
||||
bytes = addr & (sizeof(data) - 1);
|
||||
addr &= ~(sizeof(data) - 1);
|
||||
|
||||
/* combine source and destination data so can program
|
||||
* an entire word of 16 or 32 bits
|
||||
*/
|
||||
for (i = 0; i < sizeof(data); i++) {
|
||||
data <<= 8;
|
||||
if (i < bytes || i - bytes >= left)
|
||||
data += *((uchar *) addr + i);
|
||||
else
|
||||
data += *src++;
|
||||
}
|
||||
|
||||
data = (data >> 8) | (data << 8);
|
||||
res = write_word_atm(info, (FPWV *) addr, data);
|
||||
}
|
||||
return res;
|
||||
} /* case FLASH_MAN_ATM */
|
||||
|
||||
case FLASH_MAN_INTEL:
|
||||
{
|
||||
ulong cp, wp;
|
||||
u16 data;
|
||||
int count, i, l, rc, port_width;
|
||||
|
||||
/* get lower word aligned address */
|
||||
wp = addr;
|
||||
port_width = sizeof(FPW);
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
}
|
||||
|
||||
for (; i < port_width && cnt > 0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
|
||||
for (; cnt == 0 && i < port_width; ++i, ++cp)
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
|
||||
if ((rc = write_data(info, wp, data)) != 0)
|
||||
return (rc);
|
||||
|
||||
wp += port_width;
|
||||
}
|
||||
|
||||
if (cnt > WR_BLOCK) {
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
count = 0;
|
||||
while (cnt >= WR_BLOCK) {
|
||||
|
||||
if ((rc =
|
||||
write_data_block(info,
|
||||
(ulong) src,
|
||||
wp)) != 0)
|
||||
return (rc);
|
||||
|
||||
wp += WR_BLOCK;
|
||||
src += WR_BLOCK;
|
||||
cnt -= WR_BLOCK;
|
||||
|
||||
if (count++ > 0x800) {
|
||||
spin_wheel();
|
||||
count = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* handle word aligned part */
|
||||
if (cnt < WR_BLOCK) {
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
count = 0;
|
||||
while (cnt >= port_width) {
|
||||
data = 0;
|
||||
for (i = 0; i < port_width; ++i)
|
||||
data = (data << 8) | *src++;
|
||||
|
||||
if ((rc =
|
||||
write_data(info,
|
||||
(ulong) ((FPWV *) wp),
|
||||
(FPW) (data))) != 0)
|
||||
return (rc);
|
||||
|
||||
wp += port_width;
|
||||
cnt -= port_width;
|
||||
if (count++ > 0x800) {
|
||||
spin_wheel();
|
||||
count = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (cnt == 0)
|
||||
return ERR_OK;
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < port_width && cnt > 0;
|
||||
++i, ++cp) {
|
||||
data = (data << 8) | (*src++);
|
||||
--cnt;
|
||||
}
|
||||
for (; i < port_width; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
}
|
||||
|
||||
return write_data(info, (ulong) ((FPWV *) wp),
|
||||
(FPW) data);
|
||||
|
||||
} /* case FLASH_MAN_INTEL */
|
||||
|
||||
} /* switch */
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word or halfword to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
int write_data_block(flash_info_t * info, ulong src, ulong dest)
|
||||
{
|
||||
FPWV *srcaddr = (FPWV *) src;
|
||||
FPWV *dstaddr = (FPWV *) dest;
|
||||
ulong start;
|
||||
int flag, i;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
for (i = 0; i < WR_BLOCK; i++)
|
||||
if ((*dstaddr++ & 0xff) != 0xff) {
|
||||
printf("not erased at %08lx (%lx)\n",
|
||||
(ulong) dstaddr, *dstaddr);
|
||||
return (2);
|
||||
}
|
||||
|
||||
dstaddr = (FPWV *) dest;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
*dstaddr = (FPW) INTEL_WRBLK; /* write block setup */
|
||||
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
start = get_timer(0);
|
||||
|
||||
/* wait while polling the status register */
|
||||
while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) {
|
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
||||
*dstaddr = (FPW) INTEL_RESET; /* restore read mode */
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
|
||||
*dstaddr = (FPW) WR_BLOCK - 1; /* write 32 to buffer */
|
||||
for (i = 0; i < WR_BLOCK; i++)
|
||||
*dstaddr++ = *srcaddr++;
|
||||
|
||||
dstaddr -= 1;
|
||||
*dstaddr = (FPW) INTEL_CONFIRM; /* write 32 to buffer */
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
start = get_timer(0);
|
||||
|
||||
/* wait while polling the status register */
|
||||
while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) {
|
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
||||
*dstaddr = (FPW) INTEL_RESET; /* restore read mode */
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
|
||||
*dstaddr = (FPW) INTEL_RESET; /* restore read mode */
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word or halfword to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
int write_data(flash_info_t * info, ulong dest, FPW data)
|
||||
{
|
||||
FPWV *addr = (FPWV *) dest;
|
||||
ulong start;
|
||||
int flag;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*addr & data) != data) {
|
||||
printf("not erased at %08lx (%lx)\n", (ulong) addr,
|
||||
(ulong) * addr);
|
||||
return (2);
|
||||
}
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = (int)disable_interrupts();
|
||||
|
||||
*addr = (FPW) INTEL_CLEAR;
|
||||
*addr = (FPW) INTEL_RESET;
|
||||
|
||||
*addr = (FPW) INTEL_WRSETUP; /* write setup */
|
||||
*addr = data;
|
||||
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
start = get_timer(0);
|
||||
|
||||
/* wait while polling the status register */
|
||||
while ((*addr & (FPW) INTEL_OK) != (FPW) INTEL_OK) {
|
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
||||
*addr = (FPW) INTEL_SUSERASE; /* suspend mode */
|
||||
*addr = (FPW) INTEL_CLEAR; /* clear status */
|
||||
*addr = (FPW) INTEL_RESET; /* reset */
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
|
||||
*addr = (FPW) INTEL_CLEAR; /* clear status */
|
||||
*addr = (FPW) INTEL_RESET; /* restore read mode */
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash for ATMEL FLASH
|
||||
* A word is 16 bits, whichever the bus width of the flash bank
|
||||
* (not an individual chip) is.
|
||||
*
|
||||
* returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data)
|
||||
{
|
||||
ulong start;
|
||||
int flag, i;
|
||||
int res = 0; /* result, assume success */
|
||||
FPWV *base; /* first address in flash bank */
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((volatile u16 *)dest) & data) != data) {
|
||||
return (2);
|
||||
}
|
||||
|
||||
base = (FPWV *) (CFG_ATMEL_BASE);
|
||||
|
||||
for (i = 0; i < sizeof(u16); i++) {
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
|
||||
base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
|
||||
base[FLASH_CYCLE1] = (u8) 0x00A000A0; /* selects program mode */
|
||||
|
||||
*dest = data; /* start programming the data */
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
start = get_timer(0);
|
||||
|
||||
/* data polling for D7 */
|
||||
while (res == 0
|
||||
&& (*dest & (u8) 0x00800080) !=
|
||||
(data & (u8) 0x00800080)) {
|
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
||||
*dest = (u8) 0x00F000F0; /* reset bank */
|
||||
res = 1;
|
||||
}
|
||||
}
|
||||
|
||||
*dest++ = (u8) 0x00F000F0; /* reset bank */
|
||||
data >>= 8;
|
||||
}
|
||||
|
||||
return (res);
|
||||
}
|
||||
|
||||
void inline spin_wheel(void)
|
||||
{
|
||||
static int p = 0;
|
||||
static char w[] = "\\/-";
|
||||
|
||||
printf("\010%c", w[p]);
|
||||
(++p == 3) ? (p = 0) : 0;
|
||||
}
|
||||
|
||||
#ifdef CFG_FLASH_PROTECTION
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
int flash_real_protect(flash_info_t * info, long sector, int prot)
|
||||
{
|
||||
int rcode = 0; /* assume success */
|
||||
FPWV *addr; /* address of sector */
|
||||
FPW value;
|
||||
|
||||
addr = (FPWV *) (info->start[sector]);
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_28F160C3B:
|
||||
case FLASH_28F160C3T:
|
||||
case FLASH_28F320C3B:
|
||||
case FLASH_28F320C3T:
|
||||
case FLASH_28F640C3B:
|
||||
case FLASH_28F640C3T:
|
||||
*addr = (FPW) INTEL_RESET; /* make sure in read mode */
|
||||
*addr = (FPW) INTEL_LOCKBIT; /* lock command setup */
|
||||
|
||||
if (prot)
|
||||
*addr = (FPW) INTEL_PROTECT; /* lock sector */
|
||||
else
|
||||
*addr = (FPW) INTEL_CONFIRM; /* unlock sector */
|
||||
|
||||
/* now see if it really is locked/unlocked as requested */
|
||||
*addr = (FPW) INTEL_READID;
|
||||
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02.
|
||||
* D0 = 1 for each device if protected.
|
||||
* If at least one device is protected the sector is marked
|
||||
* protected, but return failure. Mixed protected and
|
||||
* unprotected devices within a sector should never happen.
|
||||
*/
|
||||
value = addr[2] & (FPW) INTEL_PROTECT;
|
||||
if (value == 0)
|
||||
info->protect[sector] = 0;
|
||||
else if (value == (FPW) INTEL_PROTECT)
|
||||
info->protect[sector] = 1;
|
||||
else {
|
||||
/* error, mixed protected and unprotected */
|
||||
rcode = 1;
|
||||
info->protect[sector] = 1;
|
||||
}
|
||||
if (info->protect[sector] != prot)
|
||||
rcode = 1; /* failed to protect/unprotect as requested */
|
||||
|
||||
/* reload all protection bits from hardware for now */
|
||||
flash_sync_real_protect(info);
|
||||
break;
|
||||
|
||||
default:
|
||||
/* no hardware protect that we support */
|
||||
info->protect[sector] = prot;
|
||||
break;
|
||||
}
|
||||
|
||||
return rcode;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
164
board/freescale/m54455evb/m54455evb.c
Normal file
164
board/freescale/m54455evb/m54455evb.c
Normal file
|
|
@ -0,0 +1,164 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <pci.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: ");
|
||||
puts("Freescale M54455 EVB\n");
|
||||
return 0;
|
||||
};
|
||||
|
||||
long int initdram(int board_type)
|
||||
{
|
||||
volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
|
||||
volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
|
||||
u32 dramsize, i;
|
||||
|
||||
dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1;
|
||||
|
||||
for (i = 0x13; i < 0x20; i++) {
|
||||
if (dramsize == (1 << i))
|
||||
break;
|
||||
}
|
||||
i--;
|
||||
|
||||
gpio->mscr_sdram = 0xAA;
|
||||
|
||||
sdram->sdcs0 = (CFG_SDRAM_BASE | i);
|
||||
sdram->sdcs1 = (CFG_SDRAM_BASE1 | i);
|
||||
|
||||
sdram->sdcfg1 = CFG_SDRAM_CFG1;
|
||||
sdram->sdcfg2 = CFG_SDRAM_CFG2;
|
||||
|
||||
/* Issue PALL */
|
||||
sdram->sdcr = CFG_SDRAM_CTRL | 2;
|
||||
|
||||
/* Issue LEMR */
|
||||
sdram->sdmr = CFG_SDRAM_EMOD | 0x408;
|
||||
sdram->sdmr = CFG_SDRAM_MODE | 0x300;
|
||||
|
||||
udelay(500);
|
||||
|
||||
/* Issue PALL */
|
||||
sdram->sdcr = CFG_SDRAM_CTRL | 2;
|
||||
|
||||
/* Perform two refresh cycles */
|
||||
sdram->sdcr = CFG_SDRAM_CTRL | 4;
|
||||
sdram->sdcr = CFG_SDRAM_CTRL | 4;
|
||||
|
||||
sdram->sdmr = CFG_SDRAM_MODE | 0x200;
|
||||
|
||||
sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
|
||||
|
||||
udelay(100);
|
||||
|
||||
return (dramsize << 1);
|
||||
};
|
||||
|
||||
int testdram(void)
|
||||
{
|
||||
/* TODO: XXX XXX XXX */
|
||||
printf("DRAM test not implemented!\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_IDE)
|
||||
#include <ata.h>
|
||||
|
||||
int ide_preinit(void)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_MASK) | 0x10;
|
||||
gpio->par_feci2c |=
|
||||
(gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
|
||||
GPIO_PAR_FECI2C_MDIO1_ATA_DIOW);
|
||||
gpio->par_ata |=
|
||||
(GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
|
||||
GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0
|
||||
| GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
|
||||
GPIO_PAR_ATA_IORDY_IORDY);
|
||||
gpio->par_pci |=
|
||||
(GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
void ide_set_reset(int idereset)
|
||||
{
|
||||
volatile atac_t *ata = (atac_t *) MMAP_ATA;
|
||||
long period;
|
||||
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
|
||||
int piotms[5][9] = {
|
||||
{70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
|
||||
{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
|
||||
{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
|
||||
{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
|
||||
{25, 70, 20, 10, 20, 5, 10, 0, 35}
|
||||
}; /* PIO 4 */
|
||||
|
||||
if (idereset) {
|
||||
ata->cr = 0; /* control reset */
|
||||
udelay(10000);
|
||||
} else {
|
||||
#define CALC_TIMING(t) (t + period - 1) / period
|
||||
period = 1000000000 / gd->bus_clk; /* period in ns */
|
||||
|
||||
/*ata->ton = CALC_TIMING (180); */
|
||||
ata->t1 = CALC_TIMING(piotms[2][0]);
|
||||
ata->t2w = CALC_TIMING(piotms[2][1]);
|
||||
ata->t2r = CALC_TIMING(piotms[2][1]);
|
||||
ata->ta = CALC_TIMING(piotms[2][8]);
|
||||
ata->trd = CALC_TIMING(piotms[2][7]);
|
||||
ata->t4 = CALC_TIMING(piotms[2][3]);
|
||||
ata->t9 = CALC_TIMING(piotms[2][6]);
|
||||
|
||||
ata->cr = 0x40; /* IORDY enable */
|
||||
udelay(200000);
|
||||
ata->cr |= 0x01; /* IORDY enable */
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
/*
|
||||
* Initialize PCI devices, report devices found.
|
||||
*/
|
||||
static struct pci_controller hose;
|
||||
extern void pci_mcf5445x_init(struct pci_controller *hose);
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
pci_mcf5445x_init(&hose);
|
||||
}
|
||||
#endif /* CONFIG_PCI */
|
||||
320
board/freescale/m54455evb/mii.c
Normal file
320
board/freescale/m54455evb/mii.c
Normal file
|
|
@ -0,0 +1,320 @@
|
|||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
|
||||
|
||||
if (setclear) {
|
||||
gpio->par_feci2c |=
|
||||
(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
|
||||
|
||||
if (info->iobase == CFG_FEC0_IOBASE)
|
||||
gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
|
||||
else
|
||||
gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
|
||||
} else {
|
||||
gpio->par_feci2c &=
|
||||
~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
|
||||
|
||||
if (info->iobase == CFG_FEC0_IOBASE)
|
||||
gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
|
||||
else
|
||||
gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
struct eth_device *dev;
|
||||
int i, miispd;
|
||||
u16 rst = 0;
|
||||
|
||||
dev = eth_get_dev();
|
||||
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET);
|
||||
for (i = 0; i < FEC_RESET_DELAY; ++i) {
|
||||
udelay(500);
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst);
|
||||
if ((rst & PHY_BMCR_RESET) == 0)
|
||||
break;
|
||||
}
|
||||
if (i == FEC_RESET_DELAY)
|
||||
printf("Mii reset timeout %d\n", i);
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_DP83848VV:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_DP83848VV);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_DP83848VV:
|
||||
printf(STR_ID_DP83848VV);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY */
|
||||
|
||||
int mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
144
board/freescale/m54455evb/u-boot.lds
Normal file
144
board/freescale/m54455evb/u-boot.lds
Normal file
|
|
@ -0,0 +1,144 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(m68k)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/mcf5445x/start.o (.text)
|
||||
lib_m68k/traps.o (.text)
|
||||
lib_m68k/interrupts.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .;
|
||||
common/environment.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
|
||||
.reloc :
|
||||
{
|
||||
__got_start = .;
|
||||
*(.got)
|
||||
__got_end = .;
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
_sbss = .;
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o
|
||||
COBJS = $(BOARD).o flash.o mii.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
|||
|
|
@ -22,8 +22,7 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/m5271.h>
|
||||
#include <asm/immap_5271.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
int checkboard (void) {
|
||||
puts ("Board: iDMR\n");
|
||||
|
|
|
|||
303
board/idmr/mii.c
Normal file
303
board/idmr/mii.c
Normal file
|
|
@ -0,0 +1,303 @@
|
|||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
if (setclear) {
|
||||
/* Enable Ethernet pins */
|
||||
mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
|
||||
} else {
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
#define STR_ID_KS8721BL "KS8721BL"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_KS8721BL);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
printf(STR_ID_KS8721BL);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY */
|
||||
|
||||
int mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
|
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o
|
||||
COBJS = $(BOARD).o mii.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
|||
|
|
@ -22,8 +22,7 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/m5271.h>
|
||||
#include <asm/immap_5271.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
int checkboard (void) {
|
||||
puts ("Board: Freescale M5271EVB\n");
|
||||
|
|
|
|||
303
board/m5271evb/mii.c
Normal file
303
board/m5271evb/mii.c
Normal file
|
|
@ -0,0 +1,303 @@
|
|||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
if (setclear) {
|
||||
/* Enable Ethernet pins */
|
||||
mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
|
||||
} else {
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
#define STR_ID_KS8721BL "KS8721BL"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_KS8721BL);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
printf(STR_ID_KS8721BL);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY */
|
||||
|
||||
int mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
|
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o
|
||||
COBJS = $(BOARD).o flash.o mii.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
|||
|
|
@ -22,18 +22,17 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/m5272.h>
|
||||
#include <asm/immap_5272.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
|
||||
int checkboard (void) {
|
||||
puts ("Board: ");
|
||||
puts("MOTOROLA MCF5272C3 EVB\n");
|
||||
puts ("Freescale MCF5272C3 EVB\n");
|
||||
return 0;
|
||||
};
|
||||
|
||||
long int initdram (int board_type) {
|
||||
volatile sdramctrl_t * sdp = (sdramctrl_t *)(CFG_MBAR + MCFSIM_SDCR);
|
||||
volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
|
||||
|
||||
sdp->sdram_sdtr = 0xf539;
|
||||
sdp->sdram_sdcr = 0x4211;
|
||||
|
|
|
|||
303
board/m5272c3/mii.c
Normal file
303
board/m5272c3/mii.c
Normal file
|
|
@ -0,0 +1,303 @@
|
|||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
|
||||
} else {
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_AMD79C874VC "AMD79C874VC"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_AMD79C874VC);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
printf(STR_ID_AMD79C874VC);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY */
|
||||
|
||||
int mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
|
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o
|
||||
COBJS = $(BOARD).o mii.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
|||
|
|
@ -22,4 +22,4 @@
|
|||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0x20000
|
||||
TEXT_BASE = 0xFFE00000
|
||||
|
|
|
|||
|
|
@ -1,378 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#define PHYS_FLASH_1 CFG_FLASH_BASE
|
||||
#define FLASH_BANK_SIZE 0x200000
|
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
|
||||
|
||||
void flash_print_info (flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case (AMD_MANUFACT & FLASH_VENDMASK):
|
||||
printf ("AMD: ");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case (AMD_ID_PL160CB & FLASH_TYPEMASK):
|
||||
printf ("AM29PL160CB (16Mbit)\n");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Chip Type\n");
|
||||
goto Done;
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
if ((i % 5) == 0) {
|
||||
printf ("\n ");
|
||||
}
|
||||
printf (" %08lX%s", info->start[i],
|
||||
info->protect[i] ? " (RO)" : " ");
|
||||
}
|
||||
printf ("\n");
|
||||
|
||||
Done:
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
int i, j;
|
||||
ulong size = 0;
|
||||
|
||||
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
|
||||
ulong flashbase = 0;
|
||||
|
||||
flash_info[i].flash_id =
|
||||
(AMD_MANUFACT & FLASH_VENDMASK) |
|
||||
(AMD_ID_PL160CB & FLASH_TYPEMASK);
|
||||
flash_info[i].size = FLASH_BANK_SIZE;
|
||||
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
|
||||
memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
|
||||
if (i == 0)
|
||||
flashbase = PHYS_FLASH_1;
|
||||
else
|
||||
panic ("configured to many flash banks!\n");
|
||||
|
||||
for (j = 0; j < flash_info[i].sector_count; j++) {
|
||||
if (j == 0) {
|
||||
/* 1st is 16 KiB */
|
||||
flash_info[i].start[j] = flashbase;
|
||||
}
|
||||
if ((j >= 1) && (j <= 2)) {
|
||||
/* 2nd and 3rd are 8 KiB */
|
||||
flash_info[i].start[j] =
|
||||
flashbase + 0x4000 + 0x2000 * (j - 1);
|
||||
}
|
||||
if (j == 3) {
|
||||
/* 4th is 32 KiB */
|
||||
flash_info[i].start[j] = flashbase + 0x8000;
|
||||
}
|
||||
if ((j >= 4) && (j <= 34)) {
|
||||
/* rest is 256 KiB */
|
||||
flash_info[i].start[j] =
|
||||
flashbase + 0x10000 + 0x10000 * (j -
|
||||
4);
|
||||
}
|
||||
}
|
||||
size += flash_info[i].size;
|
||||
}
|
||||
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CFG_FLASH_BASE,
|
||||
CFG_FLASH_BASE + 0xffff, &flash_info[0]);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
|
||||
#define CMD_READ_ARRAY 0x00F0
|
||||
#define CMD_UNLOCK1 0x00AA
|
||||
#define CMD_UNLOCK2 0x0055
|
||||
#define CMD_ERASE_SETUP 0x0080
|
||||
#define CMD_ERASE_CONFIRM 0x0030
|
||||
#define CMD_PROGRAM 0x00A0
|
||||
#define CMD_UNLOCK_BYPASS 0x0020
|
||||
|
||||
#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1)))
|
||||
#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1)))
|
||||
|
||||
#define BIT_ERASE_DONE 0x0080
|
||||
#define BIT_RDY_MASK 0x0080
|
||||
#define BIT_PROGRAM_ERROR 0x0020
|
||||
#define BIT_TIMEOUT 0x80000000 /* our flag */
|
||||
|
||||
#define READY 1
|
||||
#define ERR 2
|
||||
#define TMO 4
|
||||
|
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
ulong result;
|
||||
int iflag, cflag, prot, sect;
|
||||
int rc = ERR_OK;
|
||||
int chip1;
|
||||
|
||||
/* first look for protection bits */
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN)
|
||||
return ERR_UNKNOWN_FLASH_TYPE;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
return ERR_INVAL;
|
||||
}
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) !=
|
||||
(AMD_MANUFACT & FLASH_VENDMASK)) {
|
||||
return ERR_UNKNOWN_FLASH_VENDOR;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
if (prot)
|
||||
return ERR_PROTECTED;
|
||||
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
* (ticker) exception to happen while the flash
|
||||
* chip is in programming mode.
|
||||
*/
|
||||
|
||||
cflag = icache_status ();
|
||||
icache_disable ();
|
||||
iflag = disable_interrupts ();
|
||||
|
||||
printf ("\n");
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
|
||||
printf ("Erasing sector %2d ... ", sect);
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
set_timer (0);
|
||||
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
volatile u16 *addr =
|
||||
(volatile u16 *) (info->start[sect]);
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
*addr = CMD_ERASE_CONFIRM;
|
||||
|
||||
/* wait until flash is ready */
|
||||
chip1 = 0;
|
||||
|
||||
do {
|
||||
result = *addr;
|
||||
|
||||
/* check timeout */
|
||||
if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
|
||||
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
|
||||
chip1 = TMO;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!chip1
|
||||
&& (result & 0xFFFF) & BIT_ERASE_DONE)
|
||||
chip1 = READY;
|
||||
|
||||
} while (!chip1);
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
|
||||
|
||||
if (chip1 == ERR) {
|
||||
rc = ERR_PROG_ERROR;
|
||||
goto outahere;
|
||||
}
|
||||
if (chip1 == TMO) {
|
||||
rc = ERR_TIMOUT;
|
||||
goto outahere;
|
||||
}
|
||||
|
||||
printf ("ok.\n");
|
||||
} else { /* it was protected */
|
||||
|
||||
printf ("protected!\n");
|
||||
}
|
||||
}
|
||||
|
||||
if (ctrlc ())
|
||||
printf ("User Interrupt!\n");
|
||||
|
||||
outahere:
|
||||
/* allow flash to settle - wait 10 ms */
|
||||
udelay (10000);
|
||||
|
||||
if (iflag)
|
||||
enable_interrupts ();
|
||||
|
||||
if (cflag)
|
||||
icache_enable ();
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int write_word (flash_info_t * info, ulong dest, ulong data)
|
||||
{
|
||||
volatile u16 *addr = (volatile u16 *) dest;
|
||||
ulong result;
|
||||
int rc = ERR_OK;
|
||||
int cflag, iflag;
|
||||
int chip1;
|
||||
|
||||
/*
|
||||
* Check if Flash is (sufficiently) erased
|
||||
*/
|
||||
result = *addr;
|
||||
if ((result & data) != data)
|
||||
return ERR_NOT_ERASED;
|
||||
|
||||
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
* (ticker) exception to happen while the flash
|
||||
* chip is in programming mode.
|
||||
*/
|
||||
|
||||
cflag = icache_status ();
|
||||
icache_disable ();
|
||||
iflag = disable_interrupts ();
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
MEM_FLASH_ADDR1 = CMD_PROGRAM;
|
||||
*addr = data;
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
set_timer (0);
|
||||
|
||||
/* wait until flash is ready */
|
||||
chip1 = 0;
|
||||
do {
|
||||
result = *addr;
|
||||
|
||||
/* check timeout */
|
||||
if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
|
||||
chip1 = ERR | TMO;
|
||||
break;
|
||||
}
|
||||
if (!chip1 && ((result & 0x80) == (data & 0x80)))
|
||||
chip1 = READY;
|
||||
|
||||
} while (!chip1);
|
||||
|
||||
*addr = CMD_READ_ARRAY;
|
||||
|
||||
if (chip1 == ERR || *addr != data)
|
||||
rc = ERR_PROG_ERROR;
|
||||
|
||||
if (iflag)
|
||||
enable_interrupts ();
|
||||
|
||||
if (cflag)
|
||||
icache_enable ();
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong wp, data;
|
||||
int rc;
|
||||
|
||||
if (addr & 1) {
|
||||
printf ("unaligned destination not supported\n");
|
||||
return ERR_ALIGN;
|
||||
}
|
||||
|
||||
#if 0
|
||||
if (cnt & 1) {
|
||||
printf ("odd transfer sizes not supported\n");
|
||||
return ERR_ALIGN;
|
||||
}
|
||||
#endif
|
||||
|
||||
wp = addr;
|
||||
|
||||
if (addr & 1) {
|
||||
data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
|
||||
src);
|
||||
if ((rc = write_word (info, wp - 1, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 1;
|
||||
wp += 1;
|
||||
cnt -= 1;
|
||||
}
|
||||
|
||||
while (cnt >= 2) {
|
||||
data = *((volatile u16 *) src);
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 2;
|
||||
wp += 2;
|
||||
cnt -= 2;
|
||||
}
|
||||
|
||||
if (cnt == 1) {
|
||||
data = (*((volatile u8 *) src) << 8) |
|
||||
*((volatile u8 *) (wp + 1));
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 1;
|
||||
wp += 1;
|
||||
cnt -= 1;
|
||||
}
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
|
@ -22,14 +22,71 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
puts ("MOTOROLA M5272EVB Evaluation Board\n");
|
||||
puts ("Board: Freescale M5282EVB Evaluation Board\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
return 0x1000000;
|
||||
u32 dramsize, i, dramclk;
|
||||
|
||||
dramsize = CFG_SDRAM_SIZE * 0x100000;
|
||||
for (i = 0x13; i < 0x20; i++) {
|
||||
if (dramsize == (1 << i))
|
||||
break;
|
||||
}
|
||||
i--;
|
||||
|
||||
if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
|
||||
{
|
||||
dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ);
|
||||
|
||||
/* Initialize DRAM Control Register: DCR */
|
||||
MCFSDRAMC_DCR = (0
|
||||
| MCFSDRAMC_DCR_RTIM_6
|
||||
| MCFSDRAMC_DCR_RC((15 * dramclk)>>4));
|
||||
|
||||
/* Initialize DACR0 */
|
||||
MCFSDRAMC_DACR0 = (0
|
||||
| MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE)
|
||||
| MCFSDRAMC_DACR_CASL(1)
|
||||
| MCFSDRAMC_DACR_CBM(3)
|
||||
| MCFSDRAMC_DACR_PS_32);
|
||||
|
||||
/* Initialize DMR0 */
|
||||
MCFSDRAMC_DMR0 = (0
|
||||
| ((dramsize - 1) & 0xFFFC0000)
|
||||
| MCFSDRAMC_DMR_V);
|
||||
|
||||
/* Set IP (bit 3) in DACR */
|
||||
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
|
||||
|
||||
/* Wait 30ns to allow banks to precharge */
|
||||
for (i = 0; i < 5; i++) {
|
||||
asm ("nop");
|
||||
}
|
||||
|
||||
/* Write to this block to initiate precharge */
|
||||
*(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696;
|
||||
|
||||
/* Set RE (bit 15) in DACR */
|
||||
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
|
||||
|
||||
/* Wait for at least 8 auto refresh cycles to occur */
|
||||
for (i = 0; i < 2000; i++) {
|
||||
asm(" nop");
|
||||
}
|
||||
|
||||
/* Finish the configuration by issuing the IMRS. */
|
||||
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
|
||||
|
||||
/* Write to the SDRAM Mode Register */
|
||||
*(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
304
board/m5282evb/mii.c
Normal file
304
board/m5282evb/mii.c
Normal file
|
|
@ -0,0 +1,304 @@
|
|||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
if (setclear) {
|
||||
MCFGPIO_PASPAR |= 0x0F00;
|
||||
MCFGPIO_PEHLPAR = CFG_PEHLPAR;
|
||||
} else {
|
||||
MCFGPIO_PASPAR &= 0xF0FF;
|
||||
MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_AMD79C874VC "AMD79C874VC"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_AMD79C874VC);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
printf(STR_ID_AMD79C874VC);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY */
|
||||
|
||||
int mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
|
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o
|
||||
COBJS = $(BOARD).o mii.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
|||
303
board/r5200/mii.c
Normal file
303
board/r5200/mii.c
Normal file
|
|
@ -0,0 +1,303 @@
|
|||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
if (setclear) {
|
||||
/* Enable Ethernet pins */
|
||||
mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
|
||||
} else {
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
#define STR_ID_KS8721BL "KS8721BL"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY || (CONFIG_CMD_MII) */
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_KS8721BL);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
printf(STR_ID_KS8721BL);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY */
|
||||
|
||||
int mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
|
|
@ -207,6 +207,71 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
return 0;
|
||||
}
|
||||
|
||||
#elif defined(CONFIG_M68K) /* M68K */
|
||||
static void print_str(const char *, const char *);
|
||||
|
||||
int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
int i;
|
||||
bd_t *bd = gd->bd;
|
||||
char buf[32];
|
||||
|
||||
print_num ("memstart", (ulong)bd->bi_memstart);
|
||||
print_num ("memsize", (ulong)bd->bi_memsize);
|
||||
print_num ("flashstart", (ulong)bd->bi_flashstart);
|
||||
print_num ("flashsize", (ulong)bd->bi_flashsize);
|
||||
print_num ("flashoffset", (ulong)bd->bi_flashoffset);
|
||||
#if defined(CFG_INIT_RAM_ADDR)
|
||||
print_num ("sramstart", (ulong)bd->bi_sramstart);
|
||||
print_num ("sramsize", (ulong)bd->bi_sramsize);
|
||||
#endif
|
||||
#if defined(CFG_MBAR)
|
||||
print_num ("mbar", bd->bi_mbar_base);
|
||||
#endif
|
||||
print_str ("busfreq", strmhz(buf, bd->bi_busfreq));
|
||||
#ifdef CONFIG_PCI
|
||||
print_str ("pcifreq", strmhz(buf, bd->bi_pcifreq));
|
||||
#endif
|
||||
#ifdef CONFIG_EXTRA_CLOCK
|
||||
print_str ("flbfreq", strmhz(buf, bd->bi_flbfreq));
|
||||
print_str ("inpfreq", strmhz(buf, bd->bi_inpfreq));
|
||||
print_str ("vcofreq", strmhz(buf, bd->bi_vcofreq));
|
||||
#endif
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
puts ("ethaddr =");
|
||||
for (i=0; i<6; ++i) {
|
||||
printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_HAS_ETH1)
|
||||
puts ("\neth1addr =");
|
||||
for (i=0; i<6; ++i) {
|
||||
printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_HAS_ETH2)
|
||||
puts ("\neth2addr =");
|
||||
for (i=0; i<6; ++i) {
|
||||
printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_HAS_ETH3)
|
||||
puts ("\neth3addr =");
|
||||
for (i=0; i<6; ++i) {
|
||||
printf ("%c%02X", i ? ':' : ' ', bd->bi_enet3addr[i]);
|
||||
}
|
||||
#endif
|
||||
|
||||
puts ("\nip_addr = ");
|
||||
print_IPaddr (bd->bi_ip_addr);
|
||||
#endif
|
||||
printf ("\nbaudrate = %d bps\n", bd->bi_baudrate);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else /* ! PPC, which leaves MIPS */
|
||||
|
||||
int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
|
|
@ -270,7 +335,7 @@ static void print_num(const char *name, ulong value)
|
|||
printf ("%-12s= 0x%08lX\n", name, value);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PPC
|
||||
#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
|
||||
static void print_str(const char *name, const char *str)
|
||||
{
|
||||
printf ("%-12s= %6s MHz\n", name, str);
|
||||
|
|
|
|||
|
|
@ -438,7 +438,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
|||
int rcode = 0;
|
||||
char *devname;
|
||||
|
||||
#ifdef CONFIG_8xx
|
||||
#if defined(CONFIG_8xx) || defined(CONFIG_MCF532x)
|
||||
mii_init ();
|
||||
#endif
|
||||
|
||||
|
|
|
|||
48
cpu/mcf523x/Makefile
Normal file
48
cpu/mcf523x/Makefile
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
# CFLAGS += -DET_DEBUG
|
||||
|
||||
LIB = lib$(CPU).a
|
||||
|
||||
START = start.o
|
||||
COBJS = cpu.o speed.o cpu_init.o interrupts.o
|
||||
|
||||
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
START := $(addprefix $(obj),$(START))
|
||||
|
||||
all: $(obj).depend $(START) $(LIB)
|
||||
|
||||
$(LIB): $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
27
cpu/mcf523x/config.mk
Normal file
27
cpu/mcf523x/config.mk
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
#
|
||||
# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
|
||||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
|
||||
PLATFORM_CPPFLAGS += -m5307 -fPIC
|
||||
109
cpu/mcf523x/cpu.c
Normal file
109
cpu/mcf523x/cpu.c
Normal file
|
|
@ -0,0 +1,109 @@
|
|||
/*
|
||||
*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <watchdog.h>
|
||||
#include <command.h>
|
||||
|
||||
#include <asm/immap.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
|
||||
{
|
||||
volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
|
||||
|
||||
ccm->rcr = CCM_RCR_SOFTRST;
|
||||
/* we don't return! */
|
||||
return 0;
|
||||
};
|
||||
|
||||
int checkcpu(void)
|
||||
{
|
||||
volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
|
||||
u16 msk;
|
||||
u16 id = 0;
|
||||
u8 ver;
|
||||
|
||||
puts("CPU: ");
|
||||
msk = (ccm->cir >> 6);
|
||||
ver = (ccm->cir & 0x003f);
|
||||
switch (msk) {
|
||||
case 0x31:
|
||||
id = 5235;
|
||||
break;
|
||||
}
|
||||
|
||||
if (id) {
|
||||
printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
|
||||
ver);
|
||||
printf(" CPU CLK %d Mhz BUS CLK %d Mhz\n",
|
||||
(int)(gd->cpu_clk / 1000000),
|
||||
(int)(gd->bus_clk / 1000000));
|
||||
}
|
||||
|
||||
return 0;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
/* Called by macro WATCHDOG_RESET */
|
||||
void watchdog_reset(void)
|
||||
{
|
||||
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
|
||||
|
||||
wdp->sr = 0x5555; /* Count register */
|
||||
asm("nop");
|
||||
wdp->sr = 0xAAAA; /* Count register */
|
||||
}
|
||||
|
||||
int watchdog_disable(void)
|
||||
{
|
||||
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
|
||||
|
||||
/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
|
||||
wdp->cr |= WTM_WCR_HALTED; /* halted watchdog timer */
|
||||
|
||||
puts("WATCHDOG:disabled\n");
|
||||
return (0);
|
||||
}
|
||||
|
||||
int watchdog_init(void)
|
||||
{
|
||||
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
|
||||
u32 wdog_module = 0;
|
||||
|
||||
/* set timeout and enable watchdog */
|
||||
wdog_module = ((CFG_CLK / CFG_HZ) * CONFIG_WATCHDOG_TIMEOUT);
|
||||
wdog_module |= (wdog_module / 8192);
|
||||
wdp->mr = wdog_module;
|
||||
|
||||
wdp->cr = WTM_WCR_EN;
|
||||
puts("WATCHDOG:enabled\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
#endif /* CONFIG_WATCHDOG */
|
||||
145
cpu/mcf523x/cpu_init.c
Normal file
145
cpu/mcf523x/cpu_init.c
Normal file
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* (C) Copyright 2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <watchdog.h>
|
||||
|
||||
#include <asm/immap.h>
|
||||
|
||||
/*
|
||||
* Breath some life into the CPU...
|
||||
*
|
||||
* Set up the memory map,
|
||||
* initialize a bunch of registers,
|
||||
* initialize the UPM's
|
||||
*/
|
||||
void cpu_init_f(void)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
|
||||
volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
|
||||
volatile scm_t *scm = (scm_t *) MMAP_SCM;
|
||||
|
||||
/* watchdog is enabled by default - disable the watchdog */
|
||||
#ifndef CONFIG_WATCHDOG
|
||||
wdog->cr = 0;
|
||||
#endif
|
||||
|
||||
scm->rambar = (CFG_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
|
||||
|
||||
/* Port configuration */
|
||||
gpio->par_cs = 0;
|
||||
|
||||
#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
|
||||
fbcs->csar0 = CFG_CS0_BASE;
|
||||
fbcs->cscr0 = CFG_CS0_CTRL;
|
||||
fbcs->csmr0 = CFG_CS0_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
|
||||
gpio->par_cs |= GPIO_PAR_CS_CS1;
|
||||
fbcs->csar1 = CFG_CS1_BASE;
|
||||
fbcs->cscr1 = CFG_CS1_CTRL;
|
||||
fbcs->csmr1 = CFG_CS1_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
|
||||
gpio->par_cs |= GPIO_PAR_CS_CS2;
|
||||
fbcs->csar2 = CFG_CS2_BASE;
|
||||
fbcs->cscr2 = CFG_CS2_CTRL;
|
||||
fbcs->csmr2 = CFG_CS2_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
|
||||
gpio->par_cs |= GPIO_PAR_CS_CS3;
|
||||
fbcs->csar3 = CFG_CS3_BASE;
|
||||
fbcs->cscr3 = CFG_CS3_CTRL;
|
||||
fbcs->csmr3 = CFG_CS3_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
|
||||
gpio->par_cs |= GPIO_PAR_CS_CS4;
|
||||
fbcs->csar4 = CFG_CS4_BASE;
|
||||
fbcs->cscr4 = CFG_CS4_CTRL;
|
||||
fbcs->csmr4 = CFG_CS4_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
|
||||
gpio->par_cs |= GPIO_PAR_CS_CS5;
|
||||
fbcs->csar5 = CFG_CS5_BASE;
|
||||
fbcs->cscr5 = CFG_CS5_CTRL;
|
||||
fbcs->csmr5 = CFG_CS5_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CFG_CS6_BASE) && defined(CFG_CS6_MASK) && defined(CFG_CS6_CTRL))
|
||||
gpio->par_cs |= GPIO_PAR_CS_CS6;
|
||||
fbcs->csar6 = CFG_CS6_BASE;
|
||||
fbcs->cscr6 = CFG_CS6_CTRL;
|
||||
fbcs->csmr6 = CFG_CS6_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CFG_CS7_BASE) && defined(CFG_CS7_MASK) && defined(CFG_CS7_CTRL))
|
||||
gpio->par_cs |= GPIO_PAR_CS_CS7;
|
||||
fbcs->csar7 = CFG_CS7_BASE;
|
||||
fbcs->cscr7 = CFG_CS7_CTRL;
|
||||
fbcs->csmr7 = CFG_CS7_MASK;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_I2C
|
||||
gpio->par_feci2c &= ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK);
|
||||
gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA);
|
||||
#endif
|
||||
|
||||
icache_enable();
|
||||
}
|
||||
|
||||
/*
|
||||
* initialize higher level parts of CPU like timers
|
||||
*/
|
||||
int cpu_init_r(void)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
void uart_port_conf(void)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
/* Setup Ports: */
|
||||
switch (CFG_UART_PORT) {
|
||||
case 0:
|
||||
gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
|
||||
break;
|
||||
case 1:
|
||||
gpio->par_uart =
|
||||
(GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
|
||||
break;
|
||||
case 2:
|
||||
gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
|
||||
break;
|
||||
}
|
||||
}
|
||||
49
cpu/mcf523x/interrupts.c
Normal file
49
cpu/mcf523x/interrupts.c
Normal file
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* CPU specific interrupt routine */
|
||||
#include <common.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
int interrupt_init(void)
|
||||
{
|
||||
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
|
||||
|
||||
/* Make sure all interrupts are disabled */
|
||||
intp->imrl0 |= 0x1;
|
||||
|
||||
enable_interrupts();
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MCFTMR)
|
||||
void dtimer_intr_setup(void)
|
||||
{
|
||||
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
|
||||
|
||||
intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
|
||||
intp->imrl0 &= ~INTC_IPRL_INT0;
|
||||
intp->imrl0 &= ~CFG_TMRINTR_MASK;
|
||||
}
|
||||
#endif
|
||||
49
cpu/mcf523x/speed.c
Normal file
49
cpu/mcf523x/speed.c
Normal file
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
#include <asm/immap.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
/*
|
||||
* get_clocks() fills in gd->cpu_clock and gd->bus_clk
|
||||
*/
|
||||
int get_clocks(void)
|
||||
{
|
||||
volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
|
||||
|
||||
pll->syncr = PLL_SYNCR_MFD(1);
|
||||
|
||||
while (!(pll->synsr & PLL_SYNSR_LOCK));
|
||||
|
||||
gd->bus_clk = CFG_CLK;
|
||||
gd->cpu_clk = (gd->bus_clk * 2);
|
||||
|
||||
return (0);
|
||||
}
|
||||
340
cpu/mcf523x/start.S
Normal file
340
cpu/mcf523x/start.S
Normal file
|
|
@ -0,0 +1,340 @@
|
|||
/*
|
||||
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
|
||||
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include "version.h"
|
||||
|
||||
#ifndef CONFIG_IDENT_STRING
|
||||
#define CONFIG_IDENT_STRING ""
|
||||
#endif
|
||||
|
||||
#define _START _start
|
||||
#define _FAULT _fault
|
||||
|
||||
#define SAVE_ALL \
|
||||
move.w #0x2700,%sr; /* disable intrs */ \
|
||||
subl #60,%sp; /* space for 15 regs */ \
|
||||
moveml %d0-%d7/%a0-%a6,%sp@;
|
||||
|
||||
#define RESTORE_ALL \
|
||||
moveml %sp@,%d0-%d7/%a0-%a6; \
|
||||
addl #60,%sp; /* space for 15 regs */ \
|
||||
rte;
|
||||
|
||||
.text
|
||||
/*
|
||||
* Vector table. This is used for initial platform startup.
|
||||
* These vectors are to catch any un-intended traps.
|
||||
*/
|
||||
_vectors:
|
||||
|
||||
INITSP: .long 0x00000000 /* Initial SP */
|
||||
INITPC: .long _START /* Initial PC */
|
||||
vector02: .long _FAULT /* Access Error */
|
||||
vector03: .long _FAULT /* Address Error */
|
||||
vector04: .long _FAULT /* Illegal Instruction */
|
||||
vector05: .long _FAULT /* Reserved */
|
||||
vector06: .long _FAULT /* Reserved */
|
||||
vector07: .long _FAULT /* Reserved */
|
||||
vector08: .long _FAULT /* Privilege Violation */
|
||||
vector09: .long _FAULT /* Trace */
|
||||
vector0A: .long _FAULT /* Unimplemented A-Line */
|
||||
vector0B: .long _FAULT /* Unimplemented F-Line */
|
||||
vector0C: .long _FAULT /* Debug Interrupt */
|
||||
vector0D: .long _FAULT /* Reserved */
|
||||
vector0E: .long _FAULT /* Format Error */
|
||||
vector0F: .long _FAULT /* Unitialized Int. */
|
||||
|
||||
/* Reserved */
|
||||
vector10_17:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
|
||||
vector18: .long _FAULT /* Spurious Interrupt */
|
||||
vector19: .long _FAULT /* Autovector Level 1 */
|
||||
vector1A: .long _FAULT /* Autovector Level 2 */
|
||||
vector1B: .long _FAULT /* Autovector Level 3 */
|
||||
vector1C: .long _FAULT /* Autovector Level 4 */
|
||||
vector1D: .long _FAULT /* Autovector Level 5 */
|
||||
vector1E: .long _FAULT /* Autovector Level 6 */
|
||||
vector1F: .long _FAULT /* Autovector Level 7 */
|
||||
|
||||
/* TRAP #0 - #15 */
|
||||
vector20_2F:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
|
||||
/* Reserved */
|
||||
vector30_3F:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
|
||||
vector64_127:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
|
||||
vector128_191:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
|
||||
vector192_255:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
|
||||
.text
|
||||
|
||||
.globl _start
|
||||
_start:
|
||||
nop
|
||||
nop
|
||||
move.w #0x2700,%sr /* Mask off Interrupt */
|
||||
|
||||
/* Set vector base register at the beginning of the Flash */
|
||||
move.l #CFG_FLASH_BASE, %d0
|
||||
movec %d0, %VBR
|
||||
|
||||
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
|
||||
movec %d0, %RAMBAR1
|
||||
|
||||
/* invalidate and disable cache */
|
||||
move.l #0x01000000, %d0 /* Invalidate cache cmd */
|
||||
movec %d0, %CACR /* Invalidate cache */
|
||||
nop
|
||||
move.l #0, %d0
|
||||
movec %d0, %ACR0
|
||||
movec %d0, %ACR1
|
||||
|
||||
/* initialize general use internal ram */
|
||||
move.l #0, %d0
|
||||
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
|
||||
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a2
|
||||
move.l %d0, (%a1)
|
||||
move.l %d0, (%a2)
|
||||
|
||||
/* set stackpointer to end of internal ram to get some stackspace for the
|
||||
first c-code */
|
||||
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
|
||||
clr.l %sp@-
|
||||
|
||||
move.l #__got_start, %a5 /* put relocation table address to a5 */
|
||||
|
||||
bsr cpu_init_f /* run low-level CPU init code (from flash) */
|
||||
bsr board_init_f /* run low-level board init code (from flash) */
|
||||
|
||||
/* board_init_f() does not return */
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* void relocate_code (addr_sp, gd, addr_moni)
|
||||
*
|
||||
* This "function" does not return, instead it continues in RAM
|
||||
* after relocating the monitor code.
|
||||
*
|
||||
* r3 = dest
|
||||
* r4 = src
|
||||
* r5 = length in bytes
|
||||
* r6 = cachelinesize
|
||||
*/
|
||||
.globl relocate_code
|
||||
relocate_code:
|
||||
link.w %a6,#0
|
||||
move.l 8(%a6), %sp /* set new stack pointer */
|
||||
|
||||
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
|
||||
move.l 16(%a6), %a0 /* Save copy of Destination Address */
|
||||
|
||||
move.l #CFG_MONITOR_BASE, %a1
|
||||
move.l #__init_end, %a2
|
||||
move.l %a0, %a3
|
||||
|
||||
/* copy the code to RAM */
|
||||
1:
|
||||
move.l (%a1)+, (%a3)+
|
||||
cmp.l %a1,%a2
|
||||
bgt.s 1b
|
||||
|
||||
/*
|
||||
* We are done. Do not return, instead branch to second part of board
|
||||
* initialization, now running from RAM.
|
||||
*/
|
||||
move.l %a0, %a1
|
||||
add.l #(in_ram - CFG_MONITOR_BASE), %a1
|
||||
jmp (%a1)
|
||||
|
||||
in_ram:
|
||||
|
||||
clear_bss:
|
||||
/*
|
||||
* Now clear BSS segment
|
||||
*/
|
||||
move.l %a0, %a1
|
||||
add.l #(_sbss - CFG_MONITOR_BASE),%a1
|
||||
move.l %a0, %d1
|
||||
add.l #(_ebss - CFG_MONITOR_BASE),%d1
|
||||
6:
|
||||
clr.l (%a1)+
|
||||
cmp.l %a1,%d1
|
||||
bgt.s 6b
|
||||
|
||||
/*
|
||||
* fix got table in RAM
|
||||
*/
|
||||
move.l %a0, %a1
|
||||
add.l #(__got_start - CFG_MONITOR_BASE),%a1
|
||||
move.l %a1,%a5 /* * fix got pointer register a5 */
|
||||
|
||||
move.l %a0, %a2
|
||||
add.l #(__got_end - CFG_MONITOR_BASE),%a2
|
||||
|
||||
7:
|
||||
move.l (%a1),%d1
|
||||
sub.l #_start,%d1
|
||||
add.l %a0,%d1
|
||||
move.l %d1,(%a1)+
|
||||
cmp.l %a2, %a1
|
||||
bne 7b
|
||||
|
||||
/* calculate relative jump to board_init_r in ram */
|
||||
move.l %a0, %a1
|
||||
add.l #(board_init_r - CFG_MONITOR_BASE), %a1
|
||||
|
||||
/* set parameters for board_init_r */
|
||||
move.l %a0,-(%sp) /* dest_addr */
|
||||
move.l %d0,-(%sp) /* gd */
|
||||
jsr (%a1)
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* exception code */
|
||||
.globl _fault
|
||||
_fault:
|
||||
jmp _fault
|
||||
.globl _exc_handler
|
||||
|
||||
_exc_handler:
|
||||
SAVE_ALL
|
||||
movel %sp,%sp@-
|
||||
bsr exc_handler
|
||||
addql #4,%sp
|
||||
RESTORE_ALL
|
||||
|
||||
.globl _int_handler
|
||||
_int_handler:
|
||||
SAVE_ALL
|
||||
movel %sp,%sp@-
|
||||
bsr int_handler
|
||||
addql #4,%sp
|
||||
RESTORE_ALL
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* cache functions */
|
||||
.globl icache_enable
|
||||
icache_enable:
|
||||
move.l #0x01000000, %d0 /* Invalidate cache cmd */
|
||||
movec %d0, %CACR /* Invalidate cache */
|
||||
nop
|
||||
move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
|
||||
movec %d0, %ACR0 /* Enable cache */
|
||||
move.l #(CFG_FLASH_BASE + 0xc000), %d0 /* Setup cache mask */
|
||||
movec %d0, %ACR1 /* Enable cache */
|
||||
|
||||
move.l #0x80400100, %d0 /* Setup cache mask */
|
||||
movec %d0, %CACR /* Enable cache */
|
||||
nop
|
||||
|
||||
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
|
||||
moveq #1, %d0
|
||||
move.l %d0, (%a1)
|
||||
rts
|
||||
|
||||
.globl icache_disable
|
||||
icache_disable:
|
||||
move.l #0x00000100, %d0 /* Setup cache mask */
|
||||
movec %d0, %CACR /* Disable cache */
|
||||
clr.l %d0 /* Setup cache mask */
|
||||
movec %d0, %ACR0
|
||||
movec %d0, %ACR1
|
||||
|
||||
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
|
||||
moveq #0, %d0
|
||||
move.l %d0, (%a1)
|
||||
rts
|
||||
|
||||
.globl icache_status
|
||||
icache_status:
|
||||
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
|
||||
move.l (%a1), %d0
|
||||
rts
|
||||
|
||||
.globl icache_invalid
|
||||
icache_invalid:
|
||||
move.l #0x80600100, %d0 /* Setup cache mask */
|
||||
movec %d0, %CACR /* Enable cache */
|
||||
nop
|
||||
rts
|
||||
|
||||
.globl dcache_enable
|
||||
dcache_enable:
|
||||
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
|
||||
moveq #1, %d0
|
||||
move.l %d0, (%a1)
|
||||
rts
|
||||
|
||||
/* No dcache, just a dummy function */
|
||||
.globl dcache_disable
|
||||
dcache_disable:
|
||||
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
|
||||
moveq #0, %d0
|
||||
move.l %d0, (%a1)
|
||||
rts
|
||||
|
||||
.globl dcache_status
|
||||
dcache_status:
|
||||
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
|
||||
move.l (%a1), %d0
|
||||
rts
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
|
||||
.globl version_string
|
||||
version_string:
|
||||
.ascii U_BOOT_VERSION
|
||||
.ascii " (", __DATE__, " - ", __TIME__, ")"
|
||||
.ascii CONFIG_IDENT_STRING, "\0"
|
||||
|
|
@ -27,8 +27,8 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib$(CPU).a
|
||||
|
||||
START =
|
||||
COBJS = serial.o interrupts.o cpu.o speed.o cpu_init.o fec.o
|
||||
START = start.o
|
||||
COBJS = interrupts.o cpu.o speed.o cpu_init.o
|
||||
|
||||
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
|
|
|
|||
|
|
@ -28,33 +28,15 @@
|
|||
#include <common.h>
|
||||
#include <watchdog.h>
|
||||
#include <command.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#ifdef CONFIG_M5271
|
||||
#include <asm/immap_5271.h>
|
||||
#include <asm/m5271.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_M5272
|
||||
#include <asm/immap_5272.h>
|
||||
#include <asm/m5272.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_M5282
|
||||
#include <asm/m5282.h>
|
||||
#include <asm/immap_5282.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_M5249
|
||||
#include <asm/m5249.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_M5271
|
||||
/*
|
||||
* Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
|
||||
* determine which one we are running on, based on the Chip Identification
|
||||
* Register (CIR).
|
||||
*/
|
||||
int checkcpu (void)
|
||||
int checkcpu(void)
|
||||
{
|
||||
char buf[32];
|
||||
unsigned short cir; /* Chip Identification Register */
|
||||
|
|
@ -80,156 +62,194 @@ int checkcpu (void)
|
|||
|
||||
if (cpu_model)
|
||||
printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
|
||||
cpu_model, prn, strmhz(buf, CFG_CLK));
|
||||
cpu_model, prn, strmhz(buf, CFG_CLK));
|
||||
else
|
||||
printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
|
||||
" (PIN: 0x%x) rev. %hu, at %s MHz\n",
|
||||
pin, prn, strmhz(buf, CFG_CLK));
|
||||
" (PIN: 0x%x) rev. %hu, at %s MHz\n",
|
||||
pin, prn, strmhz(buf, CFG_CLK));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
|
||||
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
|
||||
{
|
||||
mbar_writeByte(MCF_RCM_RCR,
|
||||
MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
|
||||
MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
|
||||
return 0;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
void watchdog_reset (void)
|
||||
void watchdog_reset(void)
|
||||
{
|
||||
mbar_writeShort(MCF_WTM_WSR, 0x5555);
|
||||
mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
|
||||
}
|
||||
|
||||
int watchdog_disable (void)
|
||||
int watchdog_disable(void)
|
||||
{
|
||||
mbar_writeShort(MCF_WTM_WCR, 0);
|
||||
return (0);
|
||||
}
|
||||
|
||||
int watchdog_init (void)
|
||||
int watchdog_init(void)
|
||||
{
|
||||
mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
|
||||
return (0);
|
||||
}
|
||||
#endif /* #ifdef CONFIG_WATCHDOG */
|
||||
#endif /* #ifdef CONFIG_WATCHDOG */
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_M5272
|
||||
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
|
||||
volatile wdog_t * wdp = (wdog_t *)(CFG_MBAR + MCFSIM_WRRR);
|
||||
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
|
||||
{
|
||||
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
|
||||
|
||||
wdp->wdog_wrrr = 0;
|
||||
udelay (1000);
|
||||
udelay(1000);
|
||||
|
||||
/* enable watchdog, set timeout to 0 and wait */
|
||||
wdp->wdog_wrrr = 1;
|
||||
while (1);
|
||||
while (1) ;
|
||||
|
||||
/* we don't return! */
|
||||
return 0;
|
||||
};
|
||||
|
||||
int checkcpu(void) {
|
||||
ulong *dirp = (ulong *)(CFG_MBAR + MCFSIM_DIR);
|
||||
int checkcpu(void)
|
||||
{
|
||||
volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
|
||||
uchar msk;
|
||||
char *suf;
|
||||
char *suf;
|
||||
|
||||
puts ("CPU: ");
|
||||
msk = (*dirp > 28) & 0xf;
|
||||
puts("CPU: ");
|
||||
msk = (sysctrl->sc_dir > 28) & 0xf;
|
||||
switch (msk) {
|
||||
case 0x2: suf = "1K75N"; break;
|
||||
case 0x4: suf = "3K75N"; break;
|
||||
default:
|
||||
suf = NULL;
|
||||
printf ("Freescale MCF5272 (Mask:%01x)\n", msk);
|
||||
break;
|
||||
}
|
||||
case 0x2:
|
||||
suf = "1K75N";
|
||||
break;
|
||||
case 0x4:
|
||||
suf = "3K75N";
|
||||
break;
|
||||
default:
|
||||
suf = NULL;
|
||||
printf("Freescale MCF5272 (Mask:%01x)\n", msk);
|
||||
break;
|
||||
}
|
||||
|
||||
if (suf)
|
||||
printf ("Freescale MCF5272 %s\n", suf);
|
||||
printf("Freescale MCF5272 %s\n", suf);
|
||||
return 0;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
/* Called by macro WATCHDOG_RESET */
|
||||
void watchdog_reset (void)
|
||||
void watchdog_reset(void)
|
||||
{
|
||||
volatile immap_t * regp = (volatile immap_t *)CFG_MBAR;
|
||||
regp->wdog_reg.wdog_wcr = 0;
|
||||
volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
|
||||
wdt->wdog_wcr = 0;
|
||||
}
|
||||
|
||||
int watchdog_disable (void)
|
||||
int watchdog_disable(void)
|
||||
{
|
||||
volatile immap_t *regp = (volatile immap_t *)CFG_MBAR;
|
||||
volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
|
||||
|
||||
regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */
|
||||
regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */
|
||||
regp->wdog_reg.wdog_wrrr = 0; /* disable watchdog timer */
|
||||
wdt->wdog_wcr = 0; /* reset watchdog counter */
|
||||
wdt->wdog_wirr = 0; /* disable watchdog interrupt */
|
||||
wdt->wdog_wrrr = 0; /* disable watchdog timer */
|
||||
|
||||
puts ("WATCHDOG:disabled\n");
|
||||
puts("WATCHDOG:disabled\n");
|
||||
return (0);
|
||||
}
|
||||
|
||||
int watchdog_init (void)
|
||||
int watchdog_init(void)
|
||||
{
|
||||
volatile immap_t *regp = (volatile immap_t *)CFG_MBAR;
|
||||
volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
|
||||
|
||||
regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */
|
||||
wdt->wdog_wirr = 0; /* disable watchdog interrupt */
|
||||
|
||||
/* set timeout and enable watchdog */
|
||||
regp->wdog_reg.wdog_wrrr = ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
|
||||
regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */
|
||||
wdt->wdog_wrrr =
|
||||
((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
|
||||
wdt->wdog_wcr = 0; /* reset watchdog counter */
|
||||
|
||||
puts ("WATCHDOG:enabled\n");
|
||||
puts("WATCHDOG:enabled\n");
|
||||
return (0);
|
||||
}
|
||||
#endif /* #ifdef CONFIG_WATCHDOG */
|
||||
|
||||
#endif /* #ifdef CONFIG_M5272 */
|
||||
#endif /* #ifdef CONFIG_WATCHDOG */
|
||||
|
||||
#endif /* #ifdef CONFIG_M5272 */
|
||||
|
||||
#ifdef CONFIG_M5282
|
||||
int checkcpu (void)
|
||||
int checkcpu(void)
|
||||
{
|
||||
unsigned char resetsource = MCFRESET_RSR;
|
||||
|
||||
printf ("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
|
||||
MCFCCM_CIR>>8,MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
|
||||
printf ("Reset:%s%s%s%s%s%s%s\n",
|
||||
(resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
|
||||
(resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
|
||||
(resetsource & MCFRESET_RSR_EXT) ? " External" : "",
|
||||
(resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
|
||||
(resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
|
||||
(resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
|
||||
(resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : ""
|
||||
);
|
||||
printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
|
||||
MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
|
||||
printf("Reset:%s%s%s%s%s%s%s\n",
|
||||
(resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
|
||||
(resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
|
||||
(resetsource & MCFRESET_RSR_EXT) ? " External" : "",
|
||||
(resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
|
||||
(resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
|
||||
(resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
|
||||
(resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
|
||||
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
|
||||
{
|
||||
MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
|
||||
return 0;
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_M5249 /* test-only: todo... */
|
||||
int checkcpu (void)
|
||||
#ifdef CONFIG_M5249
|
||||
int checkcpu(void)
|
||||
{
|
||||
char buf[32];
|
||||
|
||||
printf ("CPU: Freescale Coldfire MCF5249 at %s MHz\n", strmhz(buf, CFG_CLK));
|
||||
printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
|
||||
strmhz(buf, CFG_CLK));
|
||||
return 0;
|
||||
}
|
||||
|
||||
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
|
||||
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
|
||||
{
|
||||
/* enable watchdog, set timeout to 0 and wait */
|
||||
mbar_writeByte(MCFSIM_SYPCR, 0xc0);
|
||||
while (1);
|
||||
while (1) ;
|
||||
|
||||
/* we don't return! */
|
||||
return 0;
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_M5253
|
||||
int checkcpu(void)
|
||||
{
|
||||
char buf[32];
|
||||
|
||||
unsigned char resetsource = mbar_readLong(SIM_RSR);
|
||||
printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
|
||||
strmhz(buf, CFG_CLK));
|
||||
|
||||
if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
|
||||
printf("Reset:%s%s\n",
|
||||
(resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
|
||||
: "",
|
||||
(resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
|
||||
"");
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
|
||||
{
|
||||
/* enable watchdog, set timeout to 0 and wait */
|
||||
mbar_writeByte(SIM_SYPCR, 0xc0);
|
||||
while (1) ;
|
||||
|
||||
/* we don't return! */
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -6,6 +6,10 @@
|
|||
* (C) Copyright 2005
|
||||
* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
* Hayden Fraser (Hayden.Fraser@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
|
|
@ -27,28 +31,78 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <watchdog.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#ifdef CONFIG_M5271
|
||||
#include <asm/m5271.h>
|
||||
#include <asm/immap_5271.h>
|
||||
#endif
|
||||
#if defined(CONFIG_M5253)
|
||||
/*
|
||||
* Breath some life into the CPU...
|
||||
*
|
||||
* Set up the memory map,
|
||||
* initialize a bunch of registers,
|
||||
* initialize the UPM's
|
||||
*/
|
||||
void cpu_init_f(void)
|
||||
{
|
||||
mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */
|
||||
mbar_writeByte(MCFSIM_SYPCR, 0x00);
|
||||
mbar_writeByte(MCFSIM_SWIVR, 0x0f);
|
||||
mbar_writeByte(MCFSIM_SWSR, 0x00);
|
||||
mbar_writeByte(MCFSIM_SWDICR, 0x00);
|
||||
mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
|
||||
mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
|
||||
mbar_writeByte(MCFSIM_I2CICR, 0x00);
|
||||
mbar_writeByte(MCFSIM_UART1ICR, 0x00);
|
||||
mbar_writeByte(MCFSIM_UART2ICR, 0x00);
|
||||
mbar_writeByte(MCFSIM_ICR6, 0x00);
|
||||
mbar_writeByte(MCFSIM_ICR7, 0x00);
|
||||
mbar_writeByte(MCFSIM_ICR8, 0x00);
|
||||
mbar_writeByte(MCFSIM_ICR9, 0x00);
|
||||
mbar_writeByte(MCFSIM_QSPIICR, 0x00);
|
||||
|
||||
#ifdef CONFIG_M5272
|
||||
#include <asm/m5272.h>
|
||||
#include <asm/immap_5272.h>
|
||||
#endif
|
||||
mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
|
||||
mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
|
||||
mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
|
||||
|
||||
#ifdef CONFIG_M5282
|
||||
#include <asm/m5282.h>
|
||||
#include <asm/immap_5282.h>
|
||||
#endif
|
||||
/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
|
||||
|
||||
#ifdef CONFIG_M5249
|
||||
#include <asm/m5249.h>
|
||||
#endif
|
||||
/*
|
||||
* Setup chip selects...
|
||||
*/
|
||||
|
||||
mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
|
||||
mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
|
||||
mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
|
||||
|
||||
mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
|
||||
mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
|
||||
mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
|
||||
|
||||
/* enable instruction cache now */
|
||||
icache_enable();
|
||||
}
|
||||
|
||||
/*initialize higher level parts of CPU like timers */
|
||||
int cpu_init_r(void)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
void uart_port_conf(void)
|
||||
{
|
||||
/* Setup Ports: */
|
||||
switch (CFG_UART_PORT) {
|
||||
case 0:
|
||||
break;
|
||||
case 1:
|
||||
break;
|
||||
case 2:
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif /* #if defined(CONFIG_M5253) */
|
||||
|
||||
#if defined(CONFIG_M5271)
|
||||
void cpu_init_f (void)
|
||||
void cpu_init_f(void)
|
||||
{
|
||||
#ifndef CONFIG_WATCHDOG
|
||||
/* Disable the watchdog if we aren't using it */
|
||||
|
|
@ -58,25 +112,35 @@ void cpu_init_f (void)
|
|||
/* Set clockspeed to 100MHz */
|
||||
mbar_writeShort(MCF_FMPLL_SYNCR,
|
||||
MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
|
||||
while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK);
|
||||
|
||||
/* Enable UART pins */
|
||||
mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
|
||||
MCF_GPIO_PAR_UART_U0RXD |
|
||||
MCF_GPIO_PAR_UART_U1RXD_UART1 |
|
||||
MCF_GPIO_PAR_UART_U1TXD_UART1);
|
||||
|
||||
/* Enable Ethernet pins */
|
||||
mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
|
||||
while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
|
||||
}
|
||||
|
||||
/*
|
||||
* initialize higher level parts of CPU like timers
|
||||
*/
|
||||
int cpu_init_r (void)
|
||||
int cpu_init_r(void)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
void uart_port_conf(void)
|
||||
{
|
||||
/* Setup Ports: */
|
||||
switch (CFG_UART_PORT) {
|
||||
case 0:
|
||||
mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
|
||||
MCF_GPIO_PAR_UART_U0RXD);
|
||||
break;
|
||||
case 1:
|
||||
mbar_writeShort(MCF_GPIO_PAR_UART,
|
||||
MCF_GPIO_PAR_UART_U1RXD_UART1 |
|
||||
MCF_GPIO_PAR_UART_U1TXD_UART1);
|
||||
break;
|
||||
case 2:
|
||||
mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_M5272)
|
||||
|
|
@ -87,69 +151,68 @@ int cpu_init_r (void)
|
|||
* initialize a bunch of registers,
|
||||
* initialize the UPM's
|
||||
*/
|
||||
void cpu_init_f (void)
|
||||
void cpu_init_f(void)
|
||||
{
|
||||
/* if we come from RAM we assume the CPU is
|
||||
* already initialized.
|
||||
*/
|
||||
#ifndef CONFIG_MONITOR_IS_IN_RAM
|
||||
volatile immap_t *regp = (immap_t *)CFG_MBAR;
|
||||
volatile sysctrl_t *sysctrl = (sysctrl_t *) (CFG_MBAR);
|
||||
volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
|
||||
volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
|
||||
|
||||
volatile unsigned char *mbar;
|
||||
mbar = (volatile unsigned char *) CFG_MBAR;
|
||||
|
||||
regp->sysctrl_reg.sc_scr = CFG_SCR;
|
||||
regp->sysctrl_reg.sc_spr = CFG_SPR;
|
||||
sysctrl->sc_scr = CFG_SCR;
|
||||
sysctrl->sc_spr = CFG_SPR;
|
||||
|
||||
/* Setup Ports: */
|
||||
regp->gpio_reg.gpio_pacnt = CFG_PACNT;
|
||||
regp->gpio_reg.gpio_paddr = CFG_PADDR;
|
||||
regp->gpio_reg.gpio_padat = CFG_PADAT;
|
||||
regp->gpio_reg.gpio_pbcnt = CFG_PBCNT;
|
||||
regp->gpio_reg.gpio_pbddr = CFG_PBDDR;
|
||||
regp->gpio_reg.gpio_pbdat = CFG_PBDAT;
|
||||
regp->gpio_reg.gpio_pdcnt = CFG_PDCNT;
|
||||
gpio->gpio_pacnt = CFG_PACNT;
|
||||
gpio->gpio_paddr = CFG_PADDR;
|
||||
gpio->gpio_padat = CFG_PADAT;
|
||||
gpio->gpio_pbcnt = CFG_PBCNT;
|
||||
gpio->gpio_pbddr = CFG_PBDDR;
|
||||
gpio->gpio_pbdat = CFG_PBDAT;
|
||||
gpio->gpio_pdcnt = CFG_PDCNT;
|
||||
|
||||
/* Memory Controller: */
|
||||
regp->csctrl_reg.cs_br0 = CFG_BR0_PRELIM;
|
||||
regp->csctrl_reg.cs_or0 = CFG_OR0_PRELIM;
|
||||
csctrl->cs_br0 = CFG_BR0_PRELIM;
|
||||
csctrl->cs_or0 = CFG_OR0_PRELIM;
|
||||
|
||||
#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
|
||||
regp->csctrl_reg.cs_br1 = CFG_BR1_PRELIM;
|
||||
regp->csctrl_reg.cs_or1 = CFG_OR1_PRELIM;
|
||||
csctrl->cs_br1 = CFG_BR1_PRELIM;
|
||||
csctrl->cs_or1 = CFG_OR1_PRELIM;
|
||||
#endif
|
||||
|
||||
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
|
||||
regp->csctrl_reg.cs_br2 = CFG_BR2_PRELIM;
|
||||
regp->csctrl_reg.cs_or2 = CFG_OR2_PRELIM;
|
||||
csctrl->cs_br2 = CFG_BR2_PRELIM;
|
||||
csctrl->cs_or2 = CFG_OR2_PRELIM;
|
||||
#endif
|
||||
|
||||
#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
|
||||
regp->csctrl_reg.cs_br3 = CFG_BR3_PRELIM;
|
||||
regp->csctrl_reg.cs_or3 = CFG_OR3_PRELIM;
|
||||
csctrl->cs_br3 = CFG_BR3_PRELIM;
|
||||
csctrl->cs_or3 = CFG_OR3_PRELIM;
|
||||
#endif
|
||||
|
||||
#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
|
||||
regp->csctrl_reg.cs_br4 = CFG_BR4_PRELIM;
|
||||
regp->csctrl_reg.cs_or4 = CFG_OR4_PRELIM;
|
||||
csctrl->cs_br4 = CFG_BR4_PRELIM;
|
||||
csctrl->cs_or4 = CFG_OR4_PRELIM;
|
||||
#endif
|
||||
|
||||
#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
|
||||
regp->csctrl_reg.cs_br5 = CFG_BR5_PRELIM;
|
||||
regp->csctrl_reg.cs_or5 = CFG_OR5_PRELIM;
|
||||
csctrl->cs_br5 = CFG_BR5_PRELIM;
|
||||
csctrl->cs_or5 = CFG_OR5_PRELIM;
|
||||
#endif
|
||||
|
||||
#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
|
||||
regp->csctrl_reg.cs_br6 = CFG_BR6_PRELIM;
|
||||
regp->csctrl_reg.cs_or6 = CFG_OR6_PRELIM;
|
||||
csctrl->cs_br6 = CFG_BR6_PRELIM;
|
||||
csctrl->cs_or6 = CFG_OR6_PRELIM;
|
||||
#endif
|
||||
|
||||
#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
|
||||
regp->csctrl_reg.cs_br7 = CFG_BR7_PRELIM;
|
||||
regp->csctrl_reg.cs_or7 = CFG_OR7_PRELIM;
|
||||
csctrl->cs_br7 = CFG_BR7_PRELIM;
|
||||
csctrl->cs_or7 = CFG_OR7_PRELIM;
|
||||
#endif
|
||||
|
||||
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
|
||||
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
|
||||
|
||||
/* enable instruction cache now */
|
||||
icache_enable();
|
||||
|
|
@ -159,14 +222,30 @@ void cpu_init_f (void)
|
|||
/*
|
||||
* initialize higher level parts of CPU like timers
|
||||
*/
|
||||
int cpu_init_r (void)
|
||||
int cpu_init_r(void)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
#endif /* #if defined(CONFIG_M5272) */
|
||||
|
||||
void uart_port_conf(void)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
#ifdef CONFIG_M5282
|
||||
/* Setup Ports: */
|
||||
switch (CFG_UART_PORT) {
|
||||
case 0:
|
||||
gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
|
||||
gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
|
||||
break;
|
||||
case 1:
|
||||
gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
|
||||
gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif /* #if defined(CONFIG_M5272) */
|
||||
|
||||
#if defined(CONFIG_M5282)
|
||||
/*
|
||||
* Breath some life into the CPU...
|
||||
*
|
||||
|
|
@ -174,7 +253,7 @@ int cpu_init_r (void)
|
|||
* initialize a bunch of registers,
|
||||
* initialize the UPM's
|
||||
*/
|
||||
void cpu_init_f (void)
|
||||
void cpu_init_f(void)
|
||||
{
|
||||
#ifndef CONFIG_WATCHDOG
|
||||
/* disable watchdog if we aren't using it */
|
||||
|
|
@ -183,7 +262,11 @@ void cpu_init_f (void)
|
|||
|
||||
#ifndef CONFIG_MONITOR_IS_IN_RAM
|
||||
/* Set speed /PLL */
|
||||
MCFCLOCK_SYNCR = MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
|
||||
MCFCLOCK_SYNCR =
|
||||
MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
|
||||
while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
|
||||
|
||||
MCFGPIO_PBCDPAR = 0xc0;
|
||||
|
||||
/* Set up the GPIO ports */
|
||||
#ifdef CFG_PEPAR
|
||||
|
|
@ -228,29 +311,28 @@ void cpu_init_f (void)
|
|||
defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \
|
||||
defined(CFG_CS0_WS)
|
||||
|
||||
MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
|
||||
MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
|
||||
|
||||
#if (CFG_CS0_WIDTH == 8)
|
||||
#define CFG_CS0_PS MCFCSM_CSCR_PS_8
|
||||
#elif (CFG_CS0_WIDTH == 16)
|
||||
#define CFG_CS0_PS MCFCSM_CSCR_PS_16
|
||||
#elif (CFG_CS0_WIDTH == 32)
|
||||
#define CFG_CS0_PS MCFCSM_CSCR_PS_32
|
||||
#else
|
||||
#error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
|
||||
#endif
|
||||
MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
|
||||
|CFG_CS0_PS
|
||||
|MCFCSM_CSCR_AA;
|
||||
|
||||
#if (CFG_CS0_RO != 0)
|
||||
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)
|
||||
|MCFCSM_CSMR_WP|MCFCSM_CSMR_V;
|
||||
#else
|
||||
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)|MCFCSM_CSMR_V;
|
||||
#endif
|
||||
#if (CFG_CS0_WIDTH == 8)
|
||||
#define CFG_CS0_PS MCFCSM_CSCR_PS_8
|
||||
#elif (CFG_CS0_WIDTH == 16)
|
||||
#define CFG_CS0_PS MCFCSM_CSCR_PS_16
|
||||
#elif (CFG_CS0_WIDTH == 32)
|
||||
#define CFG_CS0_PS MCFCSM_CSCR_PS_32
|
||||
#else
|
||||
#waring "Chip Select 0 are not initialized/used"
|
||||
#error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
|
||||
#endif
|
||||
MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
|
||||
| CFG_CS0_PS | MCFCSM_CSCR_AA;
|
||||
|
||||
#if (CFG_CS0_RO != 0)
|
||||
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1)
|
||||
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
|
||||
#else
|
||||
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V;
|
||||
#endif
|
||||
#else
|
||||
#waring "Chip Select 0 are not initialized/used"
|
||||
#endif
|
||||
|
||||
#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
|
||||
|
|
@ -259,29 +341,27 @@ void cpu_init_f (void)
|
|||
|
||||
MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
|
||||
|
||||
#if (CFG_CS1_WIDTH == 8)
|
||||
#define CFG_CS1_PS MCFCSM_CSCR_PS_8
|
||||
#elif (CFG_CS1_WIDTH == 16)
|
||||
#define CFG_CS1_PS MCFCSM_CSCR_PS_16
|
||||
#elif (CFG_CS1_WIDTH == 32)
|
||||
#define CFG_CS1_PS MCFCSM_CSCR_PS_32
|
||||
#else
|
||||
#error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
|
||||
#endif
|
||||
MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
|
||||
|CFG_CS1_PS
|
||||
|MCFCSM_CSCR_AA;
|
||||
|
||||
#if (CFG_CS1_RO != 0)
|
||||
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
|
||||
|MCFCSM_CSMR_WP
|
||||
|MCFCSM_CSMR_V;
|
||||
#else
|
||||
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
|
||||
|MCFCSM_CSMR_V;
|
||||
#endif
|
||||
#if (CFG_CS1_WIDTH == 8)
|
||||
#define CFG_CS1_PS MCFCSM_CSCR_PS_8
|
||||
#elif (CFG_CS1_WIDTH == 16)
|
||||
#define CFG_CS1_PS MCFCSM_CSCR_PS_16
|
||||
#elif (CFG_CS1_WIDTH == 32)
|
||||
#define CFG_CS1_PS MCFCSM_CSCR_PS_32
|
||||
#else
|
||||
#warning "Chip Select 1 are not initialized/used"
|
||||
#error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
|
||||
#endif
|
||||
MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
|
||||
| CFG_CS1_PS | MCFCSM_CSCR_AA;
|
||||
|
||||
#if (CFG_CS1_RO != 0)
|
||||
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
|
||||
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
|
||||
#else
|
||||
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
|
||||
| MCFCSM_CSMR_V;
|
||||
#endif
|
||||
#else
|
||||
#warning "Chip Select 1 are not initialized/used"
|
||||
#endif
|
||||
|
||||
#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
|
||||
|
|
@ -290,29 +370,27 @@ void cpu_init_f (void)
|
|||
|
||||
MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
|
||||
|
||||
#if (CFG_CS2_WIDTH == 8)
|
||||
#define CFG_CS2_PS MCFCSM_CSCR_PS_8
|
||||
#elif (CFG_CS2_WIDTH == 16)
|
||||
#define CFG_CS2_PS MCFCSM_CSCR_PS_16
|
||||
#elif (CFG_CS2_WIDTH == 32)
|
||||
#define CFG_CS2_PS MCFCSM_CSCR_PS_32
|
||||
#else
|
||||
#error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
|
||||
#endif
|
||||
MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
|
||||
|CFG_CS2_PS
|
||||
|MCFCSM_CSCR_AA;
|
||||
|
||||
#if (CFG_CS2_RO != 0)
|
||||
MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
|
||||
|MCFCSM_CSMR_WP
|
||||
|MCFCSM_CSMR_V;
|
||||
#else
|
||||
MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
|
||||
|MCFCSM_CSMR_V;
|
||||
#endif
|
||||
#if (CFG_CS2_WIDTH == 8)
|
||||
#define CFG_CS2_PS MCFCSM_CSCR_PS_8
|
||||
#elif (CFG_CS2_WIDTH == 16)
|
||||
#define CFG_CS2_PS MCFCSM_CSCR_PS_16
|
||||
#elif (CFG_CS2_WIDTH == 32)
|
||||
#define CFG_CS2_PS MCFCSM_CSCR_PS_32
|
||||
#else
|
||||
#warning "Chip Select 2 are not initialized/used"
|
||||
#error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
|
||||
#endif
|
||||
MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
|
||||
| CFG_CS2_PS | MCFCSM_CSCR_AA;
|
||||
|
||||
#if (CFG_CS2_RO != 0)
|
||||
MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
|
||||
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
|
||||
#else
|
||||
MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
|
||||
| MCFCSM_CSMR_V;
|
||||
#endif
|
||||
#else
|
||||
#warning "Chip Select 2 are not initialized/used"
|
||||
#endif
|
||||
|
||||
#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
|
||||
|
|
@ -321,32 +399,30 @@ void cpu_init_f (void)
|
|||
|
||||
MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
|
||||
|
||||
#if (CFG_CS3_WIDTH == 8)
|
||||
#define CFG_CS3_PS MCFCSM_CSCR_PS_8
|
||||
#elif (CFG_CS3_WIDTH == 16)
|
||||
#define CFG_CS3_PS MCFCSM_CSCR_PS_16
|
||||
#elif (CFG_CS3_WIDTH == 32)
|
||||
#define CFG_CS3_PS MCFCSM_CSCR_PS_32
|
||||
#else
|
||||
#error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
|
||||
#endif
|
||||
MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
|
||||
|CFG_CS3_PS
|
||||
|MCFCSM_CSCR_AA;
|
||||
|
||||
#if (CFG_CS3_RO != 0)
|
||||
MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
|
||||
|MCFCSM_CSMR_WP
|
||||
|MCFCSM_CSMR_V;
|
||||
#else
|
||||
MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
|
||||
|MCFCSM_CSMR_V;
|
||||
#endif
|
||||
#if (CFG_CS3_WIDTH == 8)
|
||||
#define CFG_CS3_PS MCFCSM_CSCR_PS_8
|
||||
#elif (CFG_CS3_WIDTH == 16)
|
||||
#define CFG_CS3_PS MCFCSM_CSCR_PS_16
|
||||
#elif (CFG_CS3_WIDTH == 32)
|
||||
#define CFG_CS3_PS MCFCSM_CSCR_PS_32
|
||||
#else
|
||||
#warning "Chip Select 3 are not initialized/used"
|
||||
#error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
|
||||
#endif
|
||||
MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
|
||||
| CFG_CS3_PS | MCFCSM_CSCR_AA;
|
||||
|
||||
#if (CFG_CS3_RO != 0)
|
||||
MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
|
||||
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
|
||||
#else
|
||||
MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
|
||||
| MCFCSM_CSMR_V;
|
||||
#endif
|
||||
#else
|
||||
#warning "Chip Select 3 are not initialized/used"
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_MONITOR_IS_IN_RAM */
|
||||
#endif /* CONFIG_MONITOR_IS_IN_RAM */
|
||||
|
||||
/* defer enabling cache until boot (see do_go) */
|
||||
/* icache_enable(); */
|
||||
|
|
@ -355,10 +431,29 @@ void cpu_init_f (void)
|
|||
/*
|
||||
* initialize higher level parts of CPU like timers
|
||||
*/
|
||||
int cpu_init_r (void)
|
||||
int cpu_init_r(void)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
void uart_port_conf(void)
|
||||
{
|
||||
/* Setup Ports: */
|
||||
switch (CFG_UART_PORT) {
|
||||
case 0:
|
||||
MCFGPIO_PUAPAR &= 0xFc;
|
||||
MCFGPIO_PUAPAR |= 0x03;
|
||||
break;
|
||||
case 1:
|
||||
MCFGPIO_PUAPAR &= 0xF3;
|
||||
MCFGPIO_PUAPAR |= 0x0C;
|
||||
break;
|
||||
case 2:
|
||||
MCFGPIO_PASPAR &= 0xFF0F;
|
||||
MCFGPIO_PASPAR |= 0x00A0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_M5249)
|
||||
|
|
@ -369,33 +464,13 @@ int cpu_init_r (void)
|
|||
* initialize a bunch of registers,
|
||||
* initialize the UPM's
|
||||
*/
|
||||
void cpu_init_f (void)
|
||||
void cpu_init_f(void)
|
||||
{
|
||||
#ifndef CFG_PLL_BYPASS
|
||||
/*
|
||||
* Setup the PLL to run at the specified speed
|
||||
*
|
||||
*/
|
||||
volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
|
||||
unsigned long pllcr;
|
||||
#ifdef CFG_FAST_CLK
|
||||
pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
|
||||
#else
|
||||
pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
|
||||
#endif
|
||||
cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
|
||||
mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
|
||||
mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
|
||||
pllcr ^= 0x00000001; /* Set pll bypass to 1 */
|
||||
mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
|
||||
udelay(0x20); /* Wait for a lock ... */
|
||||
#endif /* #ifndef CFG_PLL_BYPASS */
|
||||
|
||||
/*
|
||||
* NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
|
||||
* (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
|
||||
* which is their primary function.
|
||||
* ~Jeremy
|
||||
* (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
|
||||
* which is their primary function.
|
||||
* ~Jeremy
|
||||
*/
|
||||
mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
|
||||
mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
|
||||
|
|
@ -411,7 +486,7 @@ void cpu_init_f (void)
|
|||
* ~Jeremy
|
||||
*
|
||||
*/
|
||||
mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
|
||||
mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
|
||||
mbar_writeByte(MCFSIM_SYPCR, 0x00);
|
||||
mbar_writeByte(MCFSIM_SWIVR, 0x0f);
|
||||
mbar_writeByte(MCFSIM_SWSR, 0x00);
|
||||
|
|
@ -431,7 +506,7 @@ void cpu_init_f (void)
|
|||
mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
|
||||
mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
|
||||
mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
|
||||
mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
|
||||
mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
|
||||
|
||||
/* Setup interrupt priorities for gpio7 */
|
||||
/* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
|
||||
|
|
@ -459,8 +534,19 @@ void cpu_init_f (void)
|
|||
/*
|
||||
* initialize higher level parts of CPU like timers
|
||||
*/
|
||||
int cpu_init_r (void)
|
||||
int cpu_init_r(void)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
#endif /* #if defined(CONFIG_M5249) */
|
||||
|
||||
void uart_port_conf(void)
|
||||
{
|
||||
/* Setup Ports: */
|
||||
switch (CFG_UART_PORT) {
|
||||
case 0:
|
||||
break;
|
||||
case 1:
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif /* #if defined(CONFIG_M5249) */
|
||||
|
|
|
|||
|
|
@ -1,605 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <malloc.h>
|
||||
#include <asm/fec.h>
|
||||
|
||||
#ifdef CONFIG_M5271
|
||||
#include <asm/m5271.h>
|
||||
#include <asm/immap_5271.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_M5272
|
||||
#include <asm/m5272.h>
|
||||
#include <asm/immap_5272.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_M5282
|
||||
#include <asm/m5282.h>
|
||||
#include <asm/immap_5282.h>
|
||||
#endif
|
||||
|
||||
#include <net.h>
|
||||
#include <command.h>
|
||||
|
||||
#ifdef CONFIG_M5272
|
||||
#define FEC_ADDR (CFG_MBAR + 0x840)
|
||||
#endif
|
||||
#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
|
||||
#define FEC_ADDR (CFG_MBAR + 0x1000)
|
||||
#endif
|
||||
|
||||
#undef ET_DEBUG
|
||||
#undef MII_DEBUG
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(FEC_ENET)
|
||||
|
||||
#ifdef CFG_DISCOVER_PHY
|
||||
#include <miiphy.h>
|
||||
static void mii_discover_phy (void);
|
||||
#endif
|
||||
|
||||
/* Ethernet Transmit and Receive Buffers */
|
||||
#define DBUF_LENGTH 1520
|
||||
|
||||
#define TX_BUF_CNT 2
|
||||
|
||||
#define TOUT_LOOP 100
|
||||
|
||||
#define PKT_MAXBUF_SIZE 1518
|
||||
#define PKT_MINBUF_SIZE 64
|
||||
#define PKT_MAXBLR_SIZE 1520
|
||||
|
||||
|
||||
static char txbuf[DBUF_LENGTH];
|
||||
|
||||
static uint rxIdx; /* index of the current RX buffer */
|
||||
static uint txIdx; /* index of the current TX buffer */
|
||||
|
||||
/*
|
||||
* FEC Ethernet Tx and Rx buffer descriptors allocated at the
|
||||
* immr->udata_bd address on Dual-Port RAM
|
||||
* Provide for Double Buffering
|
||||
*/
|
||||
|
||||
typedef volatile struct CommonBufferDescriptor {
|
||||
cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
|
||||
cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
|
||||
} RTXBD;
|
||||
|
||||
static RTXBD *rtx = NULL;
|
||||
|
||||
int eth_send (volatile void *packet, int length)
|
||||
{
|
||||
int j, rc;
|
||||
volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
|
||||
|
||||
/* section 16.9.23.3
|
||||
* Wait for ready
|
||||
*/
|
||||
j = 0;
|
||||
while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
|
||||
&& (j < TOUT_LOOP)) {
|
||||
udelay (1);
|
||||
j++;
|
||||
}
|
||||
if (j >= TOUT_LOOP) {
|
||||
printf ("TX not ready\n");
|
||||
}
|
||||
|
||||
rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
|
||||
rtx->txbd[txIdx].cbd_datlen = length;
|
||||
rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
|
||||
|
||||
/* Activate transmit Buffer Descriptor polling */
|
||||
fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
|
||||
|
||||
j = 0;
|
||||
while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
|
||||
&& (j < TOUT_LOOP)) {
|
||||
udelay (1);
|
||||
j++;
|
||||
}
|
||||
if (j >= TOUT_LOOP) {
|
||||
printf ("TX timeout\n");
|
||||
}
|
||||
#ifdef ET_DEBUG
|
||||
printf ("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, j, rtx->txbd[txIdx].cbd_sc,
|
||||
(rtx->txbd[txIdx].cbd_sc & 0x003C) >> 2);
|
||||
#endif
|
||||
|
||||
/* return only status bits */ ;
|
||||
rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
|
||||
|
||||
txIdx = (txIdx + 1) % TX_BUF_CNT;
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
int eth_rx (void)
|
||||
{
|
||||
int length;
|
||||
volatile fec_t *fecp = (fec_t *) FEC_ADDR;
|
||||
|
||||
for (;;) {
|
||||
/* section 16.9.23.2 */
|
||||
if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
|
||||
length = -1;
|
||||
break; /* nothing received - leave for() loop */
|
||||
}
|
||||
|
||||
length = rtx->rxbd[rxIdx].cbd_datlen;
|
||||
|
||||
if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
|
||||
#ifdef ET_DEBUG
|
||||
printf ("%s[%d] err: %x\n",
|
||||
__FUNCTION__, __LINE__,
|
||||
rtx->rxbd[rxIdx].cbd_sc);
|
||||
#endif
|
||||
} else {
|
||||
/* Pass the packet up to the protocol layers. */
|
||||
NetReceive (NetRxPackets[rxIdx], length - 4);
|
||||
}
|
||||
|
||||
/* Give the buffer back to the FEC. */
|
||||
rtx->rxbd[rxIdx].cbd_datlen = 0;
|
||||
|
||||
/* wrap around buffer index when necessary */
|
||||
if ((rxIdx + 1) >= PKTBUFSRX) {
|
||||
rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
|
||||
(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
|
||||
rxIdx = 0;
|
||||
} else {
|
||||
rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
|
||||
rxIdx++;
|
||||
}
|
||||
|
||||
/* Try to fill Buffer Descriptors */
|
||||
fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
|
||||
}
|
||||
|
||||
return length;
|
||||
}
|
||||
|
||||
/**************************************************************
|
||||
*
|
||||
* FEC Ethernet Initialization Routine
|
||||
*
|
||||
*************************************************************/
|
||||
#define FEC_ECNTRL_ETHER_EN 0x00000002
|
||||
#define FEC_ECNTRL_RESET 0x00000001
|
||||
|
||||
#define FEC_RCNTRL_BC_REJ 0x00000010
|
||||
#define FEC_RCNTRL_PROM 0x00000008
|
||||
#define FEC_RCNTRL_MII_MODE 0x00000004
|
||||
#define FEC_RCNTRL_DRT 0x00000002
|
||||
#define FEC_RCNTRL_LOOP 0x00000001
|
||||
|
||||
#define FEC_TCNTRL_FDEN 0x00000004
|
||||
#define FEC_TCNTRL_HBC 0x00000002
|
||||
#define FEC_TCNTRL_GTS 0x00000001
|
||||
|
||||
#define FEC_RESET_DELAY 50000
|
||||
|
||||
int eth_init (bd_t * bd)
|
||||
{
|
||||
#ifndef CFG_ENET_BD_BASE
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
#endif
|
||||
int i;
|
||||
volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
|
||||
|
||||
/* Whack a reset.
|
||||
* A delay is required between a reset of the FEC block and
|
||||
* initialization of other FEC registers because the reset takes
|
||||
* some time to complete. If you don't delay, subsequent writes
|
||||
* to FEC registers might get killed by the reset routine which is
|
||||
* still in progress.
|
||||
*/
|
||||
fecp->fec_ecntrl = FEC_ECNTRL_RESET;
|
||||
for (i = 0;
|
||||
(fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
|
||||
++i) {
|
||||
udelay (1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf ("FEC_RESET_DELAY timeout\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* We use strictly polling mode only
|
||||
*/
|
||||
fecp->fec_imask = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->fec_ievent = 0xffffffff;
|
||||
|
||||
/* Set station address */
|
||||
#define ea bd->bi_enetaddr
|
||||
fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) |
|
||||
(ea[2] << 8) | (ea[3]);
|
||||
fecp->fec_addr_high = (ea[4] << 24) | (ea[5] << 16);
|
||||
#ifdef ET_DEBUG
|
||||
printf ("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n",
|
||||
ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]);
|
||||
#endif
|
||||
#undef ea
|
||||
|
||||
#ifdef CONFIG_M5271
|
||||
/* Clear multicast address hash table
|
||||
*/
|
||||
fecp->fec_ghash_table_high = 0;
|
||||
fecp->fec_ghash_table_low = 0;
|
||||
|
||||
/* Clear individual address hash table
|
||||
*/
|
||||
fecp->fec_ihash_table_high = 0;
|
||||
fecp->fec_ihash_table_low = 0;
|
||||
#else
|
||||
/* Clear multicast address hash table
|
||||
*/
|
||||
#ifdef CONFIG_M5282
|
||||
fecp->fec_ihash_table_high = 0;
|
||||
fecp->fec_ihash_table_low = 0;
|
||||
#else
|
||||
fecp->fec_hash_table_high = 0;
|
||||
fecp->fec_hash_table_low = 0;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Set maximum receive buffer size.
|
||||
*/
|
||||
fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
|
||||
|
||||
/*
|
||||
* Setup Buffers and Buffer Desriptors
|
||||
*/
|
||||
rxIdx = 0;
|
||||
txIdx = 0;
|
||||
|
||||
if (!rtx) {
|
||||
#ifdef CFG_ENET_BD_BASE
|
||||
rtx = (RTXBD *) CFG_ENET_BD_BASE;
|
||||
#else
|
||||
rtx = (RTXBD *) (CFG_MONITOR_BASE+gd->reloc_off -
|
||||
(((PKTBUFSRX+TX_BUF_CNT)*+sizeof(cbd_t)
|
||||
+0xFF)
|
||||
& ~0xFF)
|
||||
);
|
||||
debug("set ENET_DB_BASE to %lX\n",(long) rtx);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup Receiver Buffer Descriptors (13.14.24.18)
|
||||
* Settings:
|
||||
* Empty, Wrap
|
||||
*/
|
||||
for (i = 0; i < PKTBUFSRX; i++) {
|
||||
rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
|
||||
rtx->rxbd[i].cbd_datlen = 0; /* Reset */
|
||||
rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
|
||||
}
|
||||
rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
|
||||
|
||||
/*
|
||||
* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
|
||||
* Settings:
|
||||
* Last, Tx CRC
|
||||
*/
|
||||
for (i = 0; i < TX_BUF_CNT; i++) {
|
||||
rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
|
||||
rtx->txbd[i].cbd_datlen = 0; /* Reset */
|
||||
rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
|
||||
}
|
||||
rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
|
||||
|
||||
/* Set receive and transmit descriptor base
|
||||
*/
|
||||
fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
|
||||
fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
|
||||
|
||||
/* Enable MII mode
|
||||
*/
|
||||
|
||||
#if 0 /* Full duplex mode */
|
||||
fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
|
||||
fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
|
||||
#else /* Half duplex mode */
|
||||
fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16); /* set max frame length */
|
||||
fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
|
||||
fecp->fec_x_cntrl = 0;
|
||||
#endif
|
||||
/* Set MII speed */
|
||||
fecp->fec_mii_speed = (((CFG_CLK / 2) / (2500000 / 10)) + 5) / 10;
|
||||
fecp->fec_mii_speed *= 2;
|
||||
|
||||
/* Configure port B for MII.
|
||||
*/
|
||||
/* port initialization was already made in cpu_init_f() */
|
||||
|
||||
/* Now enable the transmit and receive processing
|
||||
*/
|
||||
fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
|
||||
|
||||
#ifdef CFG_DISCOVER_PHY
|
||||
/* wait for the PHY to wake up after reset */
|
||||
mii_discover_phy ();
|
||||
#endif
|
||||
|
||||
/* And last, try to fill Rx Buffer Descriptors */
|
||||
fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void eth_halt (void)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) FEC_ADDR;
|
||||
|
||||
fecp->fec_ecntrl = 0;
|
||||
}
|
||||
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
|
||||
static int phyaddr = -1; /* didn't find a PHY yet */
|
||||
static uint phytype;
|
||||
|
||||
/* Make MII read/write commands for the FEC.
|
||||
*/
|
||||
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
|
||||
(REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
|
||||
(REG & 0x1f) << 18) | \
|
||||
(VAL & 0xffff))
|
||||
|
||||
/* Interrupt events/masks.
|
||||
*/
|
||||
#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
|
||||
#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
|
||||
#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
|
||||
#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
|
||||
#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
|
||||
#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
|
||||
#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
|
||||
#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
|
||||
#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
|
||||
#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
|
||||
|
||||
/* PHY identification
|
||||
*/
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
static uint mii_send (uint mii_cmd)
|
||||
{
|
||||
uint mii_reply;
|
||||
volatile fec_t *ep = (fec_t *) (FEC_ADDR);
|
||||
|
||||
ep->fec_mii_data = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->fec_ievent & FEC_ENET_MII)); /* spin until done */
|
||||
mii_reply = ep->fec_mii_data; /* result from phy */
|
||||
ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf ("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CFG_DISCOVER_PHY)
|
||||
static void mii_discover_phy (void)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
uint phyno;
|
||||
int pass;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay (10000); /* wait 10ms */
|
||||
}
|
||||
for (phyno = 1; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf ("PHY type 0x%x pass %d type ", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |= mii_send (mk_mii_read (phyno,
|
||||
PHY_PHYIDR2));
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf ("PHY @ 0x%x pass %d type ", phyno,
|
||||
pass);
|
||||
switch (phytype & 0xfffffff0) {
|
||||
case PHY_ID_LXT970:
|
||||
printf ("LXT970\n");
|
||||
break;
|
||||
case PHY_ID_LXT971:
|
||||
printf ("LXT971\n");
|
||||
break;
|
||||
case PHY_ID_82555:
|
||||
printf ("82555\n");
|
||||
break;
|
||||
case PHY_ID_QS6612:
|
||||
printf ("QS6612\n");
|
||||
break;
|
||||
case PHY_ID_AMD79C784:
|
||||
printf ("AMD79C784\n");
|
||||
break;
|
||||
case PHY_ID_LSI80225B:
|
||||
printf ("LSI L80225/B\n");
|
||||
break;
|
||||
default:
|
||||
printf ("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0) {
|
||||
printf ("No PHY device found.\n");
|
||||
}
|
||||
}
|
||||
#endif /* CFG_DISCOVER_PHY */
|
||||
|
||||
#if defined(CONFIG_CMD_MII) && !defined(CONFIG_BITBANGMII)
|
||||
|
||||
static int mii_init_done = 0;
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_init (void)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
|
||||
|
||||
int i;
|
||||
|
||||
if (mii_init_done != 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* Whack a reset.
|
||||
* A delay is required between a reset of the FEC block and
|
||||
* initialization of other FEC registers because the reset takes
|
||||
* some time to complete. If you don't delay, subsequent writes
|
||||
* to FEC registers might get killed by the reset routine which is
|
||||
* still in progress.
|
||||
*/
|
||||
|
||||
fecp->fec_ecntrl = FEC_ECNTRL_RESET;
|
||||
for (i = 0;
|
||||
(fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
|
||||
++i) {
|
||||
udelay (1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf ("FEC_RESET_DELAY timeout\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* We use strictly polling mode only
|
||||
*/
|
||||
fecp->fec_imask = 0;
|
||||
|
||||
/* Clear any pending interrupt
|
||||
*/
|
||||
fecp->fec_ievent = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
fecp->fec_mii_speed = 0x0e;
|
||||
|
||||
/* Configure port B for MII.
|
||||
*/
|
||||
/* port initialization was already made in cpu_init_f() */
|
||||
|
||||
/* Now enable the transmit and receive processing */
|
||||
fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
|
||||
|
||||
mii_init_done = 1;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcf52x2_miiphy_read (char *devname, unsigned char addr,
|
||||
unsigned char reg, unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send (mk_mii_read (addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf ("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcf52x2_miiphy_write (char *devname, unsigned char addr,
|
||||
unsigned char reg, unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send (mk_mii_write (addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf ("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
int mcf52x2_miiphy_initialize(bd_t *bis)
|
||||
{
|
||||
#if defined(CONFIG_CMD_NET) && defined(FEC_ENET)
|
||||
#if defined(CONFIG_CMD_MII) && !defined(CONFIG_BITBANGMII)
|
||||
miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write);
|
||||
#endif
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,9 +1,10 @@
|
|||
/*
|
||||
* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
|
|
@ -26,140 +27,12 @@
|
|||
#include <common.h>
|
||||
#include <watchdog.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
#ifdef CONFIG_M5271
|
||||
#include <asm/m5271.h>
|
||||
#include <asm/immap_5271.h>
|
||||
#endif
|
||||
#include <asm/immap.h>
|
||||
|
||||
#ifdef CONFIG_M5272
|
||||
#include <asm/m5272.h>
|
||||
#include <asm/immap_5272.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_M5282
|
||||
#include <asm/m5282.h>
|
||||
#include <asm/immap_5282.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_M5249
|
||||
#include <asm/m5249.h>
|
||||
#endif
|
||||
|
||||
|
||||
#define NR_IRQS 31
|
||||
|
||||
/*
|
||||
* Interrupt vector functions.
|
||||
*/
|
||||
struct interrupt_action {
|
||||
interrupt_handler_t *handler;
|
||||
void *arg;
|
||||
};
|
||||
|
||||
static struct interrupt_action irq_vecs[NR_IRQS];
|
||||
|
||||
static __inline__ unsigned short get_sr (void)
|
||||
int interrupt_init(void)
|
||||
{
|
||||
unsigned short sr;
|
||||
|
||||
asm volatile ("move.w %%sr,%0":"=r" (sr):);
|
||||
|
||||
return sr;
|
||||
}
|
||||
|
||||
static __inline__ void set_sr (unsigned short sr)
|
||||
{
|
||||
asm volatile ("move.w %0,%%sr"::"r" (sr));
|
||||
}
|
||||
|
||||
/************************************************************************/
|
||||
/*
|
||||
* Install and free an interrupt handler
|
||||
*/
|
||||
void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
|
||||
{
|
||||
#ifdef CONFIG_M5272
|
||||
volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
|
||||
#endif
|
||||
int vec_base = 0;
|
||||
|
||||
#ifdef CONFIG_M5272
|
||||
vec_base = intp->int_pivr & 0xe0;
|
||||
#endif
|
||||
|
||||
if ((vec < vec_base) || (vec > vec_base + NR_IRQS)) {
|
||||
printf ("irq_install_handler: wrong interrupt vector %d\n",
|
||||
vec);
|
||||
return;
|
||||
}
|
||||
|
||||
irq_vecs[vec - vec_base].handler = handler;
|
||||
irq_vecs[vec - vec_base].arg = arg;
|
||||
}
|
||||
|
||||
void irq_free_handler (int vec)
|
||||
{
|
||||
#ifdef CONFIG_M5272
|
||||
volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
|
||||
#endif
|
||||
int vec_base = 0;
|
||||
|
||||
#ifdef CONFIG_M5272
|
||||
vec_base = intp->int_pivr & 0xe0;
|
||||
#endif
|
||||
|
||||
if ((vec < vec_base) || (vec > vec_base + NR_IRQS)) {
|
||||
return;
|
||||
}
|
||||
|
||||
irq_vecs[vec - vec_base].handler = NULL;
|
||||
irq_vecs[vec - vec_base].arg = NULL;
|
||||
}
|
||||
|
||||
void enable_interrupts (void)
|
||||
{
|
||||
unsigned short sr;
|
||||
|
||||
sr = get_sr ();
|
||||
set_sr (sr & ~0x0700);
|
||||
}
|
||||
|
||||
int disable_interrupts (void)
|
||||
{
|
||||
unsigned short sr;
|
||||
|
||||
sr = get_sr ();
|
||||
set_sr (sr | 0x0700);
|
||||
|
||||
return ((sr & 0x0700) == 0); /* return TRUE, if interrupts were enabled before */
|
||||
}
|
||||
|
||||
void int_handler (struct pt_regs *fp)
|
||||
{
|
||||
#ifdef CONFIG_M5272
|
||||
volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
|
||||
#endif
|
||||
int vec, vec_base = 0;
|
||||
|
||||
vec = (fp->vector >> 2) & 0xff;
|
||||
#ifdef CONFIG_M5272
|
||||
vec_base = intp->int_pivr & 0xe0;
|
||||
#endif
|
||||
|
||||
if (irq_vecs[vec - vec_base].handler != NULL) {
|
||||
irq_vecs[vec -
|
||||
vec_base].handler (irq_vecs[vec - vec_base].arg);
|
||||
} else {
|
||||
printf ("\nBogus External Interrupt Vector %d\n", vec);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_M5272
|
||||
int interrupt_init (void)
|
||||
{
|
||||
volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
|
||||
volatile intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
|
||||
|
||||
/* disable all external interrupts */
|
||||
intp->int_icr1 = 0x88888888;
|
||||
|
|
@ -170,24 +43,59 @@ int interrupt_init (void)
|
|||
/* initialize vector register */
|
||||
intp->int_pivr = 0x40;
|
||||
|
||||
enable_interrupts ();
|
||||
enable_interrupts();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MCFTMR)
|
||||
void dtimer_intr_setup(void)
|
||||
{
|
||||
volatile intctrl_t *intp = (intctrl_t *) (CFG_INTR_BASE);
|
||||
|
||||
intp->int_icr1 &= ~INT_ICR1_TMR3MASK;
|
||||
intp->int_icr1 |= CFG_TMRINTR_PRI;
|
||||
}
|
||||
#endif /* CONFIG_MCFTMR */
|
||||
#endif /* CONFIG_M5272 */
|
||||
|
||||
#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
|
||||
int interrupt_init (void)
|
||||
int interrupt_init(void)
|
||||
{
|
||||
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
|
||||
|
||||
/* Make sure all interrupts are disabled */
|
||||
intp->imrl0 |= 0x1;
|
||||
|
||||
enable_interrupts();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_M5249
|
||||
int interrupt_init (void)
|
||||
#if defined(CONFIG_MCFTMR)
|
||||
void dtimer_intr_setup(void)
|
||||
{
|
||||
enable_interrupts ();
|
||||
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
|
||||
|
||||
intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
|
||||
intp->imrl0 &= ~0xFFFFFFFE;
|
||||
intp->imrl0 &= ~CFG_TMRINTR_MASK;
|
||||
}
|
||||
#endif /* CONFIG_MCFTMR */
|
||||
#endif /* CONFIG_M5282 | CONFIG_M5271 */
|
||||
|
||||
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
|
||||
int interrupt_init(void)
|
||||
{
|
||||
enable_interrupts();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MCFTMR)
|
||||
void dtimer_intr_setup(void)
|
||||
{
|
||||
mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
|
||||
mbar_writeByte(MCFSIM_TIMER2ICR, CFG_TMRINTR_PRI);
|
||||
}
|
||||
#endif /* CONFIG_MCFTMR */
|
||||
#endif /* CONFIG_M5249 || CONFIG_M5253 */
|
||||
|
|
|
|||
|
|
@ -1,215 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <watchdog.h>
|
||||
|
||||
#include <asm/mcfuart.h>
|
||||
|
||||
#ifdef CONFIG_M5271
|
||||
#include <asm/m5271.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_M5272
|
||||
#include <asm/m5272.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_M5282
|
||||
#include <asm/m5282.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_M5249
|
||||
#include <asm/m5249.h>
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_M5249) || defined(CONFIG_M5271)
|
||||
#define DoubleClock(a) ((double)(CFG_CLK/2) / 32.0 / (double)(a))
|
||||
#else
|
||||
#define DoubleClock(a) ((double)(CFG_CLK) / 32.0 / (double)(a))
|
||||
#endif
|
||||
|
||||
void rs_serial_setbaudrate(int port,int baudrate)
|
||||
{
|
||||
#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5271)
|
||||
volatile unsigned char *uartp;
|
||||
# ifndef CONFIG_M5271
|
||||
double fraction;
|
||||
# endif
|
||||
double clock;
|
||||
|
||||
if (port == 0)
|
||||
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
|
||||
else
|
||||
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
|
||||
|
||||
clock = DoubleClock(baudrate); /* Set baud above */
|
||||
|
||||
uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */
|
||||
uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */
|
||||
|
||||
# ifndef CONFIG_M5271
|
||||
fraction = ((clock - (int)clock) * 16.0) + 0.5;
|
||||
uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_M5282)
|
||||
volatile unsigned char *uartp;
|
||||
long clock;
|
||||
|
||||
switch (port) {
|
||||
case 1:
|
||||
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
|
||||
break;
|
||||
case 2:
|
||||
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3);
|
||||
break;
|
||||
default:
|
||||
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
|
||||
}
|
||||
|
||||
clock = (long) CFG_CLK / ((long) 32 * baudrate); /* Set baud above */
|
||||
|
||||
uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */
|
||||
uartp[MCFUART_UBG2] = ((int) clock & 0xff); /* set lsb baud */
|
||||
|
||||
#endif
|
||||
};
|
||||
|
||||
void rs_serial_init (int port, int baudrate)
|
||||
{
|
||||
volatile unsigned char *uartp;
|
||||
|
||||
/*
|
||||
* Reset UART, get it into known state...
|
||||
*/
|
||||
switch (port) {
|
||||
case 1:
|
||||
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
|
||||
break;
|
||||
#if defined(CONFIG_M5282)
|
||||
case 2:
|
||||
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
|
||||
}
|
||||
|
||||
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */
|
||||
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */
|
||||
|
||||
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR; /* reset MR pointer */
|
||||
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR; /* reset Error pointer */
|
||||
|
||||
/*
|
||||
* Set port for CONSOLE_BAUD_RATE, 8 data bits, 1 stop bit, no parity.
|
||||
*/
|
||||
uartp[MCFUART_UMR] = MCFUART_MR1_PARITYNONE | MCFUART_MR1_CS8;
|
||||
uartp[MCFUART_UMR] = MCFUART_MR2_STOP1;
|
||||
|
||||
/* Mask UART interrupts */
|
||||
uartp[MCFUART_UIMR] = 0;
|
||||
|
||||
/* Set clock Select Register: Tx/Rx clock is timer */
|
||||
uartp[MCFUART_UCSR] = MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER;
|
||||
|
||||
rs_serial_setbaudrate (port, baudrate);
|
||||
|
||||
/* Enable Tx/Rx */
|
||||
uartp[MCFUART_UCR] = MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/*
|
||||
* Output a single character, using UART polled mode.
|
||||
* This is used for console output.
|
||||
*/
|
||||
|
||||
void rs_put_char(char ch)
|
||||
{
|
||||
volatile unsigned char *uartp;
|
||||
int i;
|
||||
|
||||
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
|
||||
|
||||
for (i = 0; (i < 0x10000); i++) {
|
||||
if (uartp[MCFUART_USR] & MCFUART_USR_TXREADY)
|
||||
break;
|
||||
}
|
||||
uartp[MCFUART_UTB] = ch;
|
||||
return;
|
||||
}
|
||||
|
||||
int rs_is_char(void)
|
||||
{
|
||||
volatile unsigned char *uartp;
|
||||
|
||||
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
|
||||
return((uartp[MCFUART_USR] & MCFUART_USR_RXREADY) ? 1 : 0);
|
||||
}
|
||||
|
||||
int rs_get_char(void)
|
||||
{
|
||||
volatile unsigned char *uartp;
|
||||
|
||||
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
|
||||
return(uartp[MCFUART_URB]);
|
||||
}
|
||||
|
||||
void serial_setbrg(void) {
|
||||
rs_serial_setbaudrate(0,gd->bd->bi_baudrate);
|
||||
}
|
||||
|
||||
int serial_init(void) {
|
||||
rs_serial_init(0,gd->baudrate);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void serial_putc(const char c) {
|
||||
if (c == '\n')
|
||||
serial_putc ('\r');
|
||||
rs_put_char(c);
|
||||
}
|
||||
|
||||
void serial_puts (const char *s) {
|
||||
while (*s)
|
||||
serial_putc(*s++);
|
||||
}
|
||||
|
||||
int serial_getc(void) {
|
||||
while(!rs_is_char())
|
||||
WATCHDOG_RESET();
|
||||
|
||||
return rs_get_char();
|
||||
}
|
||||
|
||||
int serial_tstc() {
|
||||
return rs_is_char();
|
||||
}
|
||||
|
|
@ -2,6 +2,9 @@
|
|||
* (C) Copyright 2003
|
||||
* Josef Baumgartner <josef.baumgartner@telex.de>
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* Hayden Fraser (Hayden.Fraser@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
|
|
@ -23,6 +26,7 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
@ -31,8 +35,37 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
*/
|
||||
int get_clocks (void)
|
||||
{
|
||||
gd->cpu_clk = CFG_CLK;
|
||||
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
|
||||
volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
|
||||
unsigned long pllcr;
|
||||
|
||||
#ifndef CFG_PLL_BYPASS
|
||||
|
||||
#ifdef CONFIG_M5249
|
||||
/* Setup the PLL to run at the specified speed */
|
||||
#ifdef CFG_FAST_CLK
|
||||
pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
|
||||
#else
|
||||
pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
|
||||
#endif
|
||||
#endif /* CONFIG_M5249 */
|
||||
|
||||
#ifdef CONFIG_M5253
|
||||
pllcr = CFG_PLLCR;
|
||||
#endif /* CONFIG_M5253 */
|
||||
|
||||
cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
|
||||
mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
|
||||
mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
|
||||
pllcr ^= 0x00000001; /* Set pll bypass to 1 */
|
||||
mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
|
||||
udelay(0x20); /* Wait for a lock ... */
|
||||
#endif /* #ifndef CFG_PLL_BYPASS */
|
||||
|
||||
#endif /* CONFIG_M5249 || CONFIG_M5253 */
|
||||
|
||||
gd->cpu_clk = CFG_CLK;
|
||||
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
|
||||
gd->bus_clk = gd->cpu_clk / 2;
|
||||
#else
|
||||
gd->bus_clk = gd->cpu_clk;
|
||||
|
|
|
|||
|
|
@ -121,7 +121,7 @@ _start:
|
|||
nop
|
||||
move.w #0x2700,%sr
|
||||
|
||||
#if defined(CONFIG_M5272) || defined(CONFIG_M5249)
|
||||
#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
|
||||
move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */
|
||||
move.c %d0, %MBAR
|
||||
|
||||
|
|
@ -133,7 +133,7 @@ _start:
|
|||
|
||||
move.l #(CFG_INIT_RAM_ADDR + 1), %d0
|
||||
movec %d0, %RAMBAR0
|
||||
#endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */
|
||||
#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
|
||||
|
||||
#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
|
||||
/* Initialize IPSBAR */
|
||||
|
|
@ -159,7 +159,7 @@ _copy_flash:
|
|||
|
||||
_flashbar_setup:
|
||||
/* Initialize FLASHBAR: locate internal Flash and validate it */
|
||||
move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
|
||||
move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
|
||||
movec %d0, %RAMBAR0
|
||||
jmp _after_flashbar_copy.L /* Force jump to absolute address */
|
||||
_flashbar_setup_end:
|
||||
|
|
@ -167,7 +167,7 @@ _flashbar_setup_end:
|
|||
_after_flashbar_copy:
|
||||
#else
|
||||
/* Setup code to initialize FLASHBAR, if start from external Memory */
|
||||
move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
|
||||
move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
|
||||
movec %d0, %RAMBAR0
|
||||
#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
|
||||
|
||||
|
|
@ -326,10 +326,10 @@ clear_bss:
|
|||
/* set parameters for board_init_r */
|
||||
move.l %a0,-(%sp) /* dest_addr */
|
||||
move.l %d0,-(%sp) /* gd */
|
||||
#if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
|
||||
defined(CFG_HALT_BEFOR_RAM_JUMP)
|
||||
halt
|
||||
#endif
|
||||
#if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
|
||||
defined(CFG_HALT_BEFOR_RAM_JUMP)
|
||||
halt
|
||||
#endif
|
||||
jsr (%a1)
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
|
|
@ -356,6 +356,24 @@ _int_handler:
|
|||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* cache functions */
|
||||
#ifdef CONFIG_M5271
|
||||
.globl icache_enable
|
||||
icache_enable:
|
||||
move.l #0x01000000, %d0 /* Invalidate cache cmd */
|
||||
movec %d0, %CACR /* Invalidate cache */
|
||||
move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
|
||||
movec %d0, %ACR0 /* Enable cache */
|
||||
|
||||
move.l #0x80000200, %d0 /* Setup cache mask */
|
||||
movec %d0, %CACR /* Enable cache */
|
||||
nop
|
||||
|
||||
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
|
||||
moveq #1, %d0
|
||||
move.l %d0, (%a1)
|
||||
rts
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_M5272
|
||||
.globl icache_enable
|
||||
icache_enable:
|
||||
|
|
@ -389,7 +407,7 @@ icache_state_access_1:
|
|||
rts
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_M5249
|
||||
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
|
||||
.globl icache_enable
|
||||
icache_enable:
|
||||
/*
|
||||
|
|
@ -426,13 +444,29 @@ icache_state_access_2:
|
|||
.globl icache_status
|
||||
icache_status:
|
||||
icache_state_access_3:
|
||||
move.l icache_state, %d0
|
||||
move.l #(icache_state), %a0
|
||||
move.l (%a0), %d0
|
||||
rts
|
||||
|
||||
.data
|
||||
icache_state:
|
||||
.long 0 /* cache is diabled on inirialization */
|
||||
|
||||
.globl dcache_enable
|
||||
dcache_enable:
|
||||
/* dummy function */
|
||||
rts
|
||||
|
||||
.globl dcache_disable
|
||||
dcache_disable:
|
||||
/* dummy function */
|
||||
rts
|
||||
|
||||
.globl dcache_status
|
||||
dcache_status:
|
||||
/* dummy function */
|
||||
rts
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
|
||||
.globl version_string
|
||||
|
|
|
|||
48
cpu/mcf532x/Makefile
Normal file
48
cpu/mcf532x/Makefile
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
# CFLAGS += -DET_DEBUG
|
||||
|
||||
LIB = lib$(CPU).a
|
||||
|
||||
START =
|
||||
COBJS = cpu.o speed.o cpu_init.o interrupts.o
|
||||
|
||||
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
START := $(addprefix $(obj),$(START))
|
||||
|
||||
all: $(obj).depend $(START) $(LIB)
|
||||
|
||||
$(LIB): $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
27
cpu/mcf532x/config.mk
Normal file
27
cpu/mcf532x/config.mk
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
#
|
||||
# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
|
||||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
|
||||
PLATFORM_CPPFLAGS += -m5307 -fPIC
|
||||
119
cpu/mcf532x/cpu.c
Normal file
119
cpu/mcf532x/cpu.c
Normal file
|
|
@ -0,0 +1,119 @@
|
|||
/*
|
||||
*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <watchdog.h>
|
||||
#include <command.h>
|
||||
|
||||
#include <asm/immap.h>
|
||||
|
||||
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
|
||||
{
|
||||
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
|
||||
|
||||
wdp->cr = 0;
|
||||
udelay(1000);
|
||||
|
||||
/* enable watchdog, set timeout to 0 and wait */
|
||||
wdp->cr = WTM_WCR_EN;
|
||||
while (1) ;
|
||||
|
||||
/* we don't return! */
|
||||
return 0;
|
||||
};
|
||||
|
||||
int checkcpu(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
|
||||
u16 msk;
|
||||
u16 id = 0;
|
||||
u8 ver;
|
||||
|
||||
puts("CPU: ");
|
||||
msk = (ccm->cir >> 6);
|
||||
ver = (ccm->cir & 0x003f);
|
||||
switch (msk) {
|
||||
case 0x54:
|
||||
id = 5329;
|
||||
break;
|
||||
case 0x59:
|
||||
id = 5328;
|
||||
break;
|
||||
case 0x61:
|
||||
id = 5327;
|
||||
break;
|
||||
}
|
||||
|
||||
if (id) {
|
||||
printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
|
||||
ver);
|
||||
printf(" CPU CLK %d Mhz BUS CLK %d Mhz\n",
|
||||
(int)(gd->cpu_clk / 1000000),
|
||||
(int)(gd->bus_clk / 1000000));
|
||||
}
|
||||
|
||||
return 0;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
/* Called by macro WATCHDOG_RESET */
|
||||
void watchdog_reset(void)
|
||||
{
|
||||
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
|
||||
|
||||
wdp->sr = 0x5555; /* Count register */
|
||||
}
|
||||
|
||||
int watchdog_disable(void)
|
||||
{
|
||||
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
|
||||
|
||||
/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
|
||||
wdp->cr |= WTM_WCR_HALTED; /* halted watchdog timer */
|
||||
|
||||
puts("WATCHDOG:disabled\n");
|
||||
return (0);
|
||||
}
|
||||
|
||||
int watchdog_init(void)
|
||||
{
|
||||
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
|
||||
u32 wdog_module = 0;
|
||||
|
||||
/* set timeout and enable watchdog */
|
||||
wdog_module = ((CFG_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
|
||||
wdog_module |= (wdog_module / 8192);
|
||||
wdp->mr = wdog_module;
|
||||
|
||||
wdp->cr = WTM_WCR_EN;
|
||||
puts("WATCHDOG:enabled\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
#endif /* CONFIG_WATCHDOG */
|
||||
141
cpu/mcf532x/cpu_init.c
Normal file
141
cpu/mcf532x/cpu_init.c
Normal file
|
|
@ -0,0 +1,141 @@
|
|||
/*
|
||||
*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* (C) Copyright 2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <watchdog.h>
|
||||
|
||||
#include <asm/immap.h>
|
||||
|
||||
/*
|
||||
* Breath some life into the CPU...
|
||||
*
|
||||
* Set up the memory map,
|
||||
* initialize a bunch of registers,
|
||||
* initialize the UPM's
|
||||
*/
|
||||
void cpu_init_f(void)
|
||||
{
|
||||
volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
|
||||
volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
|
||||
volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
|
||||
|
||||
/* watchdog is enabled by default - disable the watchdog */
|
||||
#ifndef CONFIG_WATCHDOG
|
||||
wdog->cr = 0;
|
||||
#endif
|
||||
|
||||
scm1->mpr0 = 0x77777777;
|
||||
scm2->pacra = 0;
|
||||
scm2->pacrb = 0;
|
||||
scm2->pacrc = 0;
|
||||
scm2->pacrd = 0;
|
||||
scm2->pacre = 0;
|
||||
scm2->pacrf = 0;
|
||||
scm2->pacrg = 0;
|
||||
scm1->pacrh = 0;
|
||||
|
||||
/* Port configuration */
|
||||
gpio->par_cs = 0;
|
||||
|
||||
#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
|
||||
fbcs->csar0 = CFG_CS0_BASE;
|
||||
fbcs->cscr0 = CFG_CS0_CTRL;
|
||||
fbcs->csmr0 = CFG_CS0_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
|
||||
/* Latch chipselect */
|
||||
gpio->par_cs |= GPIO_PAR_CS1;
|
||||
fbcs->csar1 = CFG_CS1_BASE;
|
||||
fbcs->cscr1 = CFG_CS1_CTRL;
|
||||
fbcs->csmr1 = CFG_CS1_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
|
||||
gpio->par_cs |= GPIO_PAR_CS2;
|
||||
fbcs->csar2 = CFG_CS2_BASE;
|
||||
fbcs->cscr2 = CFG_CS2_CTRL;
|
||||
fbcs->csmr2 = CFG_CS2_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
|
||||
gpio->par_cs |= GPIO_PAR_CS3;
|
||||
fbcs->csar3 = CFG_CS3_BASE;
|
||||
fbcs->cscr3 = CFG_CS3_CTRL;
|
||||
fbcs->csmr3 = CFG_CS3_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
|
||||
gpio->par_cs |= GPIO_PAR_CS4;
|
||||
fbcs->csar4 = CFG_CS4_BASE;
|
||||
fbcs->cscr4 = CFG_CS4_CTRL;
|
||||
fbcs->csmr4 = CFG_CS4_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
|
||||
gpio->par_cs |= GPIO_PAR_CS5;
|
||||
fbcs->csar5 = CFG_CS5_BASE;
|
||||
fbcs->cscr5 = CFG_CS5_CTRL;
|
||||
fbcs->csmr5 = CFG_CS5_MASK;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_I2C
|
||||
gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
|
||||
#endif
|
||||
|
||||
icache_enable();
|
||||
}
|
||||
|
||||
/*
|
||||
* initialize higher level parts of CPU like timers
|
||||
*/
|
||||
int cpu_init_r(void)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
void uart_port_conf(void)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
/* Setup Ports: */
|
||||
switch (CFG_UART_PORT) {
|
||||
case 0:
|
||||
gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
|
||||
break;
|
||||
case 1:
|
||||
gpio->par_uart =
|
||||
(GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
|
||||
break;
|
||||
case 2:
|
||||
gpio->par_timer &= 0x0F;
|
||||
gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
|
||||
break;
|
||||
}
|
||||
}
|
||||
49
cpu/mcf532x/interrupts.c
Normal file
49
cpu/mcf532x/interrupts.c
Normal file
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* CPU specific interrupt routine */
|
||||
#include <common.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
int interrupt_init(void)
|
||||
{
|
||||
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
|
||||
|
||||
/* Make sure all interrupts are disabled */
|
||||
intp->imrh0 |= 0xFFFFFFFF;
|
||||
intp->imrl0 |= 0xFFFFFFFF;
|
||||
|
||||
enable_interrupts();
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MCFTMR)
|
||||
void dtimer_intr_setup(void)
|
||||
{
|
||||
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
|
||||
|
||||
intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
|
||||
intp->imrh0 &= ~CFG_TMRINTR_MASK;
|
||||
}
|
||||
#endif
|
||||
216
cpu/mcf532x/speed.c
Normal file
216
cpu/mcf532x/speed.c
Normal file
|
|
@ -0,0 +1,216 @@
|
|||
/*
|
||||
*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
#include <asm/immap.h>
|
||||
|
||||
/* PLL min/max specifications */
|
||||
#define MAX_FVCO 500000 /* KHz */
|
||||
#define MAX_FSYS 80000 /* KHz */
|
||||
#define MIN_FSYS 58333 /* KHz */
|
||||
#define FREF 16000 /* KHz */
|
||||
#define MAX_MFD 135 /* Multiplier */
|
||||
#define MIN_MFD 88 /* Multiplier */
|
||||
#define BUSDIV 6 /* Divider */
|
||||
/*
|
||||
* Low Power Divider specifications
|
||||
*/
|
||||
#define MIN_LPD (1 << 0) /* Divider (not encoded) */
|
||||
#define MAX_LPD (1 << 15) /* Divider (not encoded) */
|
||||
#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
|
||||
|
||||
/*
|
||||
* Get the value of the current system clock
|
||||
*
|
||||
* Parameters:
|
||||
* none
|
||||
*
|
||||
* Return Value:
|
||||
* The current output system frequency
|
||||
*/
|
||||
int get_sys_clock(void)
|
||||
{
|
||||
volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
|
||||
volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
|
||||
int divider;
|
||||
|
||||
/* Test to see if device is in LIMP mode */
|
||||
if (ccm->misccr & CCM_MISCCR_LIMP) {
|
||||
divider = ccm->cdr & CCM_CDR_LPDIV(0xF);
|
||||
return (FREF / (2 << divider));
|
||||
} else {
|
||||
return ((FREF * pll->pfdr) / (BUSDIV * 4));
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize the Low Power Divider circuit
|
||||
*
|
||||
* Parameters:
|
||||
* div Desired system frequency divider
|
||||
*
|
||||
* Return Value:
|
||||
* The resulting output system frequency
|
||||
*/
|
||||
int clock_limp(int div)
|
||||
{
|
||||
volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
|
||||
u32 temp;
|
||||
|
||||
/* Check bounds of divider */
|
||||
if (div < MIN_LPD)
|
||||
div = MIN_LPD;
|
||||
if (div > MAX_LPD)
|
||||
div = MAX_LPD;
|
||||
|
||||
/* Save of the current value of the SSIDIV so we don't overwrite the value */
|
||||
temp = (ccm->cdr & CCM_CDR_SSIDIV(0xF));
|
||||
|
||||
/* Apply the divider to the system clock */
|
||||
ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
|
||||
|
||||
ccm->misccr |= CCM_MISCCR_LIMP;
|
||||
|
||||
return (FREF / (3 * (1 << div)));
|
||||
}
|
||||
|
||||
/*
|
||||
* Exit low power LIMP mode
|
||||
*
|
||||
* Parameters:
|
||||
* div Desired system frequency divider
|
||||
*
|
||||
* Return Value:
|
||||
* The resulting output system frequency
|
||||
*/
|
||||
int clock_exit_limp(void)
|
||||
{
|
||||
volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
|
||||
int fout;
|
||||
|
||||
/* Exit LIMP mode */
|
||||
ccm->misccr &= (~CCM_MISCCR_LIMP);
|
||||
|
||||
/* Wait for PLL to lock */
|
||||
while (!(ccm->misccr & CCM_MISCCR_PLL_LOCK)) ;
|
||||
|
||||
fout = get_sys_clock();
|
||||
|
||||
return fout;
|
||||
}
|
||||
|
||||
/* Initialize the PLL
|
||||
*
|
||||
* Parameters:
|
||||
* fref PLL reference clock frequency in KHz
|
||||
* fsys Desired PLL output frequency in KHz
|
||||
* flags Operating parameters
|
||||
*
|
||||
* Return Value:
|
||||
* The resulting output system frequency
|
||||
*/
|
||||
int clock_pll(int fsys, int flags)
|
||||
{
|
||||
volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80);
|
||||
volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
|
||||
int fref, temp, fout, mfd;
|
||||
u32 i;
|
||||
|
||||
fref = FREF;
|
||||
|
||||
if (fsys == 0) {
|
||||
/* Return current PLL output */
|
||||
mfd = pll->pfdr;
|
||||
|
||||
return (fref * mfd / (BUSDIV * 4));
|
||||
}
|
||||
|
||||
/* Check bounds of requested system clock */
|
||||
if (fsys > MAX_FSYS)
|
||||
fsys = MAX_FSYS;
|
||||
|
||||
if (fsys < MIN_FSYS)
|
||||
fsys = MIN_FSYS;
|
||||
|
||||
/* Multiplying by 100 when calculating the temp value,
|
||||
and then dividing by 100 to calculate the mfd allows
|
||||
for exact values without needing to include floating
|
||||
point libraries. */
|
||||
temp = (100 * fsys) / fref;
|
||||
mfd = (4 * BUSDIV * temp) / 100;
|
||||
|
||||
/* Determine the output frequency for selected values */
|
||||
fout = ((fref * mfd) / (BUSDIV * 4));
|
||||
|
||||
/*
|
||||
* Check to see if the SDRAM has already been initialized.
|
||||
* If it has then the SDRAM needs to be put into self refresh
|
||||
* mode before reprogramming the PLL.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Initialize the PLL to generate the new system clock frequency.
|
||||
* The device must be put into LIMP mode to reprogram the PLL.
|
||||
*/
|
||||
|
||||
/* Enter LIMP mode */
|
||||
clock_limp(DEFAULT_LPD);
|
||||
|
||||
/* Reprogram PLL for desired fsys */
|
||||
pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
|
||||
|
||||
pll->pfdr = mfd;
|
||||
|
||||
/* Exit LIMP mode */
|
||||
clock_exit_limp();
|
||||
|
||||
/*
|
||||
* Return the SDRAM to normal operation if it is in use.
|
||||
*/
|
||||
|
||||
/* software workaround for SDRAM opeartion after exiting LIMP mode errata */
|
||||
*sdram_workaround = CFG_SDRAM_BASE;
|
||||
|
||||
/* wait for DQS logic to relock */
|
||||
for (i = 0; i < 0x200; i++) ;
|
||||
|
||||
return fout;
|
||||
}
|
||||
|
||||
/*
|
||||
* get_clocks() fills in gd->cpu_clock and gd->bus_clk
|
||||
*/
|
||||
int get_clocks(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gd->bus_clk = clock_pll(CFG_CLK / 1000, 0) * 1000;
|
||||
gd->cpu_clk = (gd->bus_clk * 3);
|
||||
return (0);
|
||||
}
|
||||
335
cpu/mcf532x/start.S
Normal file
335
cpu/mcf532x/start.S
Normal file
|
|
@ -0,0 +1,335 @@
|
|||
/*
|
||||
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
|
||||
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include "version.h"
|
||||
|
||||
#ifndef CONFIG_IDENT_STRING
|
||||
#define CONFIG_IDENT_STRING ""
|
||||
#endif
|
||||
|
||||
#define _START _start
|
||||
#define _FAULT _fault
|
||||
|
||||
#define SAVE_ALL \
|
||||
move.w #0x2700,%sr; /* disable intrs */ \
|
||||
subl #60,%sp; /* space for 15 regs */ \
|
||||
moveml %d0-%d7/%a0-%a6,%sp@;
|
||||
|
||||
#define RESTORE_ALL \
|
||||
moveml %sp@,%d0-%d7/%a0-%a6; \
|
||||
addl #60,%sp; /* space for 15 regs */ \
|
||||
rte;
|
||||
|
||||
.text
|
||||
/*
|
||||
* Vector table. This is used for initial platform startup.
|
||||
* These vectors are to catch any un-intended traps.
|
||||
*/
|
||||
_vectors:
|
||||
|
||||
INITSP: .long 0x00000000 /* Initial SP */
|
||||
INITPC: .long _START /* Initial PC */
|
||||
vector02: .long _FAULT /* Access Error */
|
||||
vector03: .long _FAULT /* Address Error */
|
||||
vector04: .long _FAULT /* Illegal Instruction */
|
||||
vector05: .long _FAULT /* Reserved */
|
||||
vector06: .long _FAULT /* Reserved */
|
||||
vector07: .long _FAULT /* Reserved */
|
||||
vector08: .long _FAULT /* Privilege Violation */
|
||||
vector09: .long _FAULT /* Trace */
|
||||
vector0A: .long _FAULT /* Unimplemented A-Line */
|
||||
vector0B: .long _FAULT /* Unimplemented F-Line */
|
||||
vector0C: .long _FAULT /* Debug Interrupt */
|
||||
vector0D: .long _FAULT /* Reserved */
|
||||
vector0E: .long _FAULT /* Format Error */
|
||||
vector0F: .long _FAULT /* Unitialized Int. */
|
||||
|
||||
/* Reserved */
|
||||
vector10_17:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
|
||||
vector18: .long _FAULT /* Spurious Interrupt */
|
||||
vector19: .long _FAULT /* Autovector Level 1 */
|
||||
vector1A: .long _FAULT /* Autovector Level 2 */
|
||||
vector1B: .long _FAULT /* Autovector Level 3 */
|
||||
vector1C: .long _FAULT /* Autovector Level 4 */
|
||||
vector1D: .long _FAULT /* Autovector Level 5 */
|
||||
vector1E: .long _FAULT /* Autovector Level 6 */
|
||||
vector1F: .long _FAULT /* Autovector Level 7 */
|
||||
|
||||
/* TRAP #0 - #15 */
|
||||
vector20_2F:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
|
||||
/* Reserved */
|
||||
vector30_3F:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
|
||||
vector64_127:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
|
||||
vector128_191:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
|
||||
vector192_255:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
|
||||
.text
|
||||
|
||||
.globl _start
|
||||
_start:
|
||||
nop
|
||||
nop
|
||||
move.w #0x2700,%sr /* Mask off Interrupt */
|
||||
|
||||
/* Set vector base register at the beginning of the Flash */
|
||||
move.l #CFG_FLASH_BASE, %d0
|
||||
movec %d0, %VBR
|
||||
|
||||
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
|
||||
movec %d0, %RAMBAR0
|
||||
|
||||
/* invalidate and disable cache */
|
||||
move.l #0x01000000, %d0 /* Invalidate cache cmd */
|
||||
movec %d0, %CACR /* Invalidate cache */
|
||||
move.l #0, %d0
|
||||
movec %d0, %ACR0
|
||||
movec %d0, %ACR1
|
||||
|
||||
/* initialize general use internal ram */
|
||||
move.l #0, %d0
|
||||
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
|
||||
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a2
|
||||
move.l %d0, (%a1)
|
||||
move.l %d0, (%a2)
|
||||
|
||||
/* set stackpointer to end of internal ram to get some stackspace for the
|
||||
first c-code */
|
||||
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
|
||||
clr.l %sp@-
|
||||
|
||||
move.l #__got_start, %a5 /* put relocation table address to a5 */
|
||||
|
||||
bsr cpu_init_f /* run low-level CPU init code (from flash) */
|
||||
bsr board_init_f /* run low-level board init code (from flash) */
|
||||
|
||||
/* board_init_f() does not return */
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* void relocate_code (addr_sp, gd, addr_moni)
|
||||
*
|
||||
* This "function" does not return, instead it continues in RAM
|
||||
* after relocating the monitor code.
|
||||
*
|
||||
* r3 = dest
|
||||
* r4 = src
|
||||
* r5 = length in bytes
|
||||
* r6 = cachelinesize
|
||||
*/
|
||||
.globl relocate_code
|
||||
relocate_code:
|
||||
link.w %a6,#0
|
||||
move.l 8(%a6), %sp /* set new stack pointer */
|
||||
|
||||
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
|
||||
move.l 16(%a6), %a0 /* Save copy of Destination Address */
|
||||
|
||||
move.l #CFG_MONITOR_BASE, %a1
|
||||
move.l #__init_end, %a2
|
||||
move.l %a0, %a3
|
||||
|
||||
/* copy the code to RAM */
|
||||
1:
|
||||
move.l (%a1)+, (%a3)+
|
||||
cmp.l %a1,%a2
|
||||
bgt.s 1b
|
||||
|
||||
/*
|
||||
* We are done. Do not return, instead branch to second part of board
|
||||
* initialization, now running from RAM.
|
||||
*/
|
||||
move.l %a0, %a1
|
||||
add.l #(in_ram - CFG_MONITOR_BASE), %a1
|
||||
jmp (%a1)
|
||||
|
||||
in_ram:
|
||||
|
||||
clear_bss:
|
||||
/*
|
||||
* Now clear BSS segment
|
||||
*/
|
||||
move.l %a0, %a1
|
||||
add.l #(_sbss - CFG_MONITOR_BASE),%a1
|
||||
move.l %a0, %d1
|
||||
add.l #(_ebss - CFG_MONITOR_BASE),%d1
|
||||
6:
|
||||
clr.l (%a1)+
|
||||
cmp.l %a1,%d1
|
||||
bgt.s 6b
|
||||
|
||||
/*
|
||||
* fix got table in RAM
|
||||
*/
|
||||
move.l %a0, %a1
|
||||
add.l #(__got_start - CFG_MONITOR_BASE),%a1
|
||||
move.l %a1,%a5 /* * fix got pointer register a5 */
|
||||
|
||||
move.l %a0, %a2
|
||||
add.l #(__got_end - CFG_MONITOR_BASE),%a2
|
||||
|
||||
7:
|
||||
move.l (%a1),%d1
|
||||
sub.l #_start,%d1
|
||||
add.l %a0,%d1
|
||||
move.l %d1,(%a1)+
|
||||
cmp.l %a2, %a1
|
||||
bne 7b
|
||||
|
||||
/* calculate relative jump to board_init_r in ram */
|
||||
move.l %a0, %a1
|
||||
add.l #(board_init_r - CFG_MONITOR_BASE), %a1
|
||||
|
||||
/* set parameters for board_init_r */
|
||||
move.l %a0,-(%sp) /* dest_addr */
|
||||
move.l %d0,-(%sp) /* gd */
|
||||
jsr (%a1)
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* exception code */
|
||||
.globl _fault
|
||||
_fault:
|
||||
jmp _fault
|
||||
.globl _exc_handler
|
||||
|
||||
_exc_handler:
|
||||
SAVE_ALL
|
||||
movel %sp,%sp@-
|
||||
bsr exc_handler
|
||||
addql #4,%sp
|
||||
RESTORE_ALL
|
||||
|
||||
.globl _int_handler
|
||||
_int_handler:
|
||||
SAVE_ALL
|
||||
movel %sp,%sp@-
|
||||
bsr int_handler
|
||||
addql #4,%sp
|
||||
RESTORE_ALL
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* cache functions */
|
||||
.globl icache_enable
|
||||
icache_enable:
|
||||
move.l #0x01000000, %d0 /* Invalidate cache cmd */
|
||||
movec %d0, %CACR /* Invalidate cache */
|
||||
move.l #(CFG_SDRAM_BASE + 0xc000 + ((CFG_SDRAM_SIZE & 0x1fe0) << 11)), %d0
|
||||
movec %d0, %ACR0 /* Enable cache */
|
||||
|
||||
move.l #0x80000200, %d0 /* Setup cache mask */
|
||||
movec %d0, %CACR /* Enable cache */
|
||||
nop
|
||||
|
||||
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
|
||||
moveq #1, %d0
|
||||
move.l %d0, (%a1)
|
||||
rts
|
||||
|
||||
.globl icache_disable
|
||||
icache_disable:
|
||||
move.l #0x01000000, %d0 /* Setup cache mask */
|
||||
movec %d0, %CACR /* Disable cache */
|
||||
clr.l %d0 /* Setup cache mask */
|
||||
movec %d0, %ACR0
|
||||
movec %d0, %ACR1
|
||||
|
||||
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
|
||||
moveq #0, %d0
|
||||
move.l %d0, (%a1)
|
||||
rts
|
||||
|
||||
.globl icache_status
|
||||
icache_status:
|
||||
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
|
||||
move.l (%a1), %d0
|
||||
rts
|
||||
|
||||
.globl icache_invalid
|
||||
icache_invalid:
|
||||
move.l #0x81000200, %d0 /* Setup cache mask */
|
||||
movec %d0, %CACR /* Enable cache */
|
||||
rts
|
||||
|
||||
.globl dcache_enable
|
||||
dcache_enable:
|
||||
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
|
||||
moveq #1, %d0
|
||||
move.l %d0, (%a1)
|
||||
rts
|
||||
|
||||
/* No dcache, just a dummy function */
|
||||
.globl dcache_disable
|
||||
dcache_disable:
|
||||
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
|
||||
moveq #0, %d0
|
||||
move.l %d0, (%a1)
|
||||
rts
|
||||
|
||||
.globl dcache_status
|
||||
dcache_status:
|
||||
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
|
||||
move.l (%a1), %d0
|
||||
rts
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
|
||||
.globl version_string
|
||||
version_string:
|
||||
.ascii U_BOOT_VERSION
|
||||
.ascii " (", __DATE__, " - ", __TIME__, ")"
|
||||
.ascii CONFIG_IDENT_STRING, "\0"
|
||||
48
cpu/mcf5445x/Makefile
Normal file
48
cpu/mcf5445x/Makefile
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
# CFLAGS += -DET_DEBUG
|
||||
|
||||
LIB = lib$(CPU).a
|
||||
|
||||
START = start.o
|
||||
COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o
|
||||
|
||||
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
START := $(addprefix $(obj),$(START))
|
||||
|
||||
all: $(obj).depend $(START) $(LIB)
|
||||
|
||||
$(LIB): $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
27
cpu/mcf5445x/config.mk
Normal file
27
cpu/mcf5445x/config.mk
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
#
|
||||
# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
|
||||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
|
||||
PLATFORM_CPPFLAGS += -m5407 -fPIC
|
||||
97
cpu/mcf5445x/cpu.c
Normal file
97
cpu/mcf5445x/cpu.c
Normal file
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <watchdog.h>
|
||||
#include <command.h>
|
||||
|
||||
#include <asm/immap.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
|
||||
{
|
||||
volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
|
||||
udelay(1000);
|
||||
rcm->rcr |= RCM_RCR_SOFTRST;
|
||||
|
||||
/* we don't return! */
|
||||
return 0;
|
||||
};
|
||||
|
||||
int checkcpu(void)
|
||||
{
|
||||
volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
|
||||
u16 msk;
|
||||
u16 id = 0;
|
||||
u8 ver;
|
||||
|
||||
puts("CPU: ");
|
||||
msk = (ccm->cir >> 6);
|
||||
ver = (ccm->cir & 0x003f);
|
||||
switch (msk) {
|
||||
case 0x48:
|
||||
id = 54455;
|
||||
break;
|
||||
case 0x49:
|
||||
id = 54454;
|
||||
break;
|
||||
case 0x4a:
|
||||
id = 54453;
|
||||
break;
|
||||
case 0x4b:
|
||||
id = 54452;
|
||||
break;
|
||||
case 0x4d:
|
||||
id = 54451;
|
||||
break;
|
||||
case 0x4f:
|
||||
id = 54450;
|
||||
break;
|
||||
}
|
||||
|
||||
if (id) {
|
||||
printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
|
||||
ver);
|
||||
printf(" CPU CLK %d Mhz BUS CLK %d Mhz FLB CLK %d Mhz\n",
|
||||
(int)(gd->cpu_clk / 1000000),
|
||||
(int)(gd->bus_clk / 1000000),
|
||||
(int)(gd->flb_clk / 1000000));
|
||||
#ifdef CONFIG_PCI
|
||||
printf(" PCI CLK %d Mhz INP CLK %d Mhz VCO CLK %d Mhz\n",
|
||||
(int)(gd->pci_clk / 1000000),
|
||||
(int)(gd->inp_clk / 1000000),
|
||||
(int)(gd->vco_clk / 1000000));
|
||||
#else
|
||||
printf(" INP CLK %d Mhz VCO CLK %d Mhz\n",
|
||||
(int)(gd->inp_clk / 1000000),
|
||||
(int)(gd->vco_clk / 1000000));
|
||||
#endif
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
140
cpu/mcf5445x/cpu_init.c
Normal file
140
cpu/mcf5445x/cpu_init.c
Normal file
|
|
@ -0,0 +1,140 @@
|
|||
/*
|
||||
*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <watchdog.h>
|
||||
|
||||
#include <asm/immap.h>
|
||||
#include <asm/rtc.h>
|
||||
|
||||
/*
|
||||
* Breath some life into the CPU...
|
||||
*
|
||||
* Set up the memory map,
|
||||
* initialize a bunch of registers,
|
||||
* initialize the UPM's
|
||||
*/
|
||||
void cpu_init_f(void)
|
||||
{
|
||||
volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
|
||||
|
||||
scm1->mpr = 0x77777777;
|
||||
scm1->pacra = 0;
|
||||
scm1->pacrb = 0;
|
||||
scm1->pacrc = 0;
|
||||
scm1->pacrd = 0;
|
||||
scm1->pacre = 0;
|
||||
scm1->pacrf = 0;
|
||||
scm1->pacrg = 0;
|
||||
|
||||
/* FlexBus */
|
||||
gpio->par_be =
|
||||
GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 |
|
||||
GPIO_PAR_BE_BE0_BE0;
|
||||
gpio->par_fbctl =
|
||||
GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW |
|
||||
GPIO_PAR_FBCTL_TS_TS;
|
||||
|
||||
#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
|
||||
fbcs->csar0 = CFG_CS0_BASE;
|
||||
fbcs->cscr0 = CFG_CS0_CTRL;
|
||||
fbcs->csmr0 = CFG_CS0_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
|
||||
/* Latch chipselect */
|
||||
fbcs->csar1 = CFG_CS1_BASE;
|
||||
fbcs->cscr1 = CFG_CS1_CTRL;
|
||||
fbcs->csmr1 = CFG_CS1_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
|
||||
fbcs->csar2 = CFG_CS2_BASE;
|
||||
fbcs->cscr2 = CFG_CS2_CTRL;
|
||||
fbcs->csmr2 = CFG_CS2_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
|
||||
fbcs->csar3 = CFG_CS3_BASE;
|
||||
fbcs->cscr3 = CFG_CS3_CTRL;
|
||||
fbcs->csmr3 = CFG_CS3_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
|
||||
fbcs->csar4 = CFG_CS4_BASE;
|
||||
fbcs->cscr4 = CFG_CS4_CTRL;
|
||||
fbcs->csmr4 = CFG_CS4_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
|
||||
fbcs->csar5 = CFG_CS5_BASE;
|
||||
fbcs->cscr5 = CFG_CS5_CTRL;
|
||||
fbcs->csmr5 = CFG_CS5_MASK;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_I2C
|
||||
gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
|
||||
#endif
|
||||
|
||||
icache_enable();
|
||||
}
|
||||
|
||||
/*
|
||||
* initialize higher level parts of CPU like timers
|
||||
*/
|
||||
int cpu_init_r(void)
|
||||
{
|
||||
#ifdef CONFIG_MCFTMR
|
||||
volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
|
||||
volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
|
||||
u32 oscillator = CFG_RTC_OSCILLATOR;
|
||||
|
||||
rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF;
|
||||
rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF;
|
||||
#endif
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
void uart_port_conf(void)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
/* Setup Ports: */
|
||||
switch (CFG_UART_PORT) {
|
||||
case 0:
|
||||
gpio->par_uart =
|
||||
(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
|
||||
break;
|
||||
case 1:
|
||||
gpio->par_uart =
|
||||
(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
|
||||
break;
|
||||
}
|
||||
}
|
||||
52
cpu/mcf5445x/interrupts.c
Normal file
52
cpu/mcf5445x/interrupts.c
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* CPU specific interrupt routine */
|
||||
#include <common.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
int interrupt_init(void)
|
||||
{
|
||||
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
|
||||
|
||||
/* Make sure all interrupts are disabled */
|
||||
intp->imrh0 |= 0xFFFFFFFF;
|
||||
intp->imrl0 |= 0xFFFFFFFF;
|
||||
|
||||
enable_interrupts();
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MCFTMR)
|
||||
void dtimer_intr_setup(void)
|
||||
{
|
||||
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
|
||||
|
||||
intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
|
||||
intp->imrh0 &= ~CFG_TMRINTR_MASK;
|
||||
}
|
||||
#endif
|
||||
189
cpu/mcf5445x/pci.c
Normal file
189
cpu/mcf5445x/pci.c
Normal file
|
|
@ -0,0 +1,189 @@
|
|||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* PCI Configuration space access support
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <pci.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
/* System RAM mapped over PCI */
|
||||
#define CFG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
|
||||
#define CFG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
|
||||
#define CFG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
|
||||
|
||||
#define cfg_read(val, addr, type, op) *val = op((type)(addr));
|
||||
#define cfg_write(val, addr, type, op) op((type *)(addr), (val));
|
||||
|
||||
#define PCI_OP(rw, size, type, op, mask) \
|
||||
int pci_##rw##_cfg_##size(struct pci_controller *hose, \
|
||||
pci_dev_t dev, int offset, type val) \
|
||||
{ \
|
||||
u32 addr = 0; \
|
||||
u16 cfg_type = 0; \
|
||||
addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \
|
||||
out_be32(hose->cfg_addr, addr); \
|
||||
__asm__ __volatile__("nop"); \
|
||||
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
|
||||
out_be32(hose->cfg_addr, addr & 0x7fffffff); \
|
||||
__asm__ __volatile__("nop"); \
|
||||
return 0; \
|
||||
}
|
||||
|
||||
PCI_OP(read, byte, u8 *, in_8, 3)
|
||||
PCI_OP(read, word, u16 *, in_le16, 2)
|
||||
PCI_OP(write, byte, u8, out_8, 3)
|
||||
PCI_OP(write, word, u16, out_le16, 2)
|
||||
PCI_OP(write, dword, u32, out_le32, 0)
|
||||
|
||||
int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev,
|
||||
int offset, u32 * val)
|
||||
{
|
||||
u32 addr;
|
||||
u32 tmpv;
|
||||
u32 mask = 2; /* word access */
|
||||
/* Read lower 16 bits */
|
||||
addr = ((offset & 0xfc) | (dev) | 0x80000000);
|
||||
out_be32(hose->cfg_addr, addr);
|
||||
__asm__ __volatile__("nop");
|
||||
*val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
|
||||
out_be32(hose->cfg_addr, addr & 0x7fffffff);
|
||||
__asm__ __volatile__("nop");
|
||||
|
||||
/* Read upper 16 bits */
|
||||
offset += 2;
|
||||
addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000);
|
||||
out_be32(hose->cfg_addr, addr);
|
||||
__asm__ __volatile__("nop");
|
||||
tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
|
||||
out_be32(hose->cfg_addr, addr & 0x7fffffff);
|
||||
__asm__ __volatile__("nop");
|
||||
|
||||
/* combine results into dword value */
|
||||
*val = (tmpv << 16) | *val;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void pci_mcf5445x_init(struct pci_controller *hose)
|
||||
{
|
||||
volatile pci_t *pci = (volatile pci_t *)MMAP_PCI;
|
||||
volatile pciarb_t *pciarb = (volatile pciarb_t *)MMAP_PCIARB;
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
u32 barEn = 0;
|
||||
|
||||
pciarb->acr = 0x001f001f;
|
||||
|
||||
/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
|
||||
PCIREQ2, PCIGNT2 */
|
||||
gpio->par_pci =
|
||||
GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | GPIO_PAR_PCI_GNT1 |
|
||||
GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
|
||||
GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0;
|
||||
|
||||
pci->tcr1 |= PCI_TCR1_P;
|
||||
|
||||
/* Initiator windows */
|
||||
pci->iw0btar = CFG_PCI_MEM_PHYS;
|
||||
pci->iw1btar = CFG_PCI_IO_PHYS;
|
||||
pci->iw2btar = CFG_PCI_CFG_PHYS;
|
||||
|
||||
pci->iwcr =
|
||||
PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
|
||||
PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
|
||||
|
||||
/* Enable bus master and mem access */
|
||||
pci->scr = PCI_SCR_MW | PCI_SCR_B | PCI_SCR_M;
|
||||
|
||||
/* Cache line size and master latency */
|
||||
pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xFF);
|
||||
pci->cr2 = 0;
|
||||
|
||||
#ifdef CFG_PCI_BAR0
|
||||
pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0);
|
||||
pci->tbatr0 = CFG_PCI_TBATR0 | PCI_TBATR_EN;
|
||||
barEn |= PCI_TCR1_B0E;
|
||||
#endif
|
||||
#ifdef CFG_PCI_BAR1
|
||||
pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1);
|
||||
pci->tbatr1 = CFG_PCI_TBATR1 | PCI_TBATR_EN;
|
||||
barEn |= PCI_TCR1_B1E;
|
||||
#endif
|
||||
#ifdef CFG_PCI_BAR2
|
||||
pci->bar2 = PCI_BAR_BAR2(CFG_PCI_BAR2);
|
||||
pci->tbatr2 = CFG_PCI_TBATR2 | PCI_TBATR_EN;
|
||||
barEn |= PCI_TCR1_B2E;
|
||||
#endif
|
||||
#ifdef CFG_PCI_BAR3
|
||||
pci->bar3 = PCI_BAR_BAR3(CFG_PCI_BAR3);
|
||||
pci->tbatr3 = CFG_PCI_TBATR3 | PCI_TBATR_EN;
|
||||
barEn |= PCI_TCR1_B3E;
|
||||
#endif
|
||||
#ifdef CFG_PCI_BAR4
|
||||
pci->bar4 = PCI_BAR_BAR4(CFG_PCI_BAR4);
|
||||
pci->tbatr4 = CFG_PCI_TBATR4 | PCI_TBATR_EN;
|
||||
barEn |= PCI_TCR1_B4E;
|
||||
#endif
|
||||
#ifdef CFG_PCI_BAR5
|
||||
pci->bar5 = PCI_BAR_BAR5(CFG_PCI_BAR5);
|
||||
pci->tbatr5 = CFG_PCI_TBATR5 | PCI_TBATR_EN;
|
||||
barEn |= PCI_TCR1_B5E;
|
||||
#endif
|
||||
|
||||
pci->tcr2 = barEn;
|
||||
|
||||
/* Deassert reset bit */
|
||||
pci->gscr &= ~PCI_GSCR_PR;
|
||||
udelay(1000);
|
||||
|
||||
/* Enable PCI bus master support */
|
||||
hose->first_busno = 0;
|
||||
hose->last_busno = 0xff;
|
||||
|
||||
pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS,
|
||||
CFG_PCI_MEM_SIZE, PCI_REGION_MEM);
|
||||
|
||||
pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS,
|
||||
CFG_PCI_IO_SIZE, PCI_REGION_IO);
|
||||
|
||||
pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS,
|
||||
CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
|
||||
hose->region_count = 3;
|
||||
|
||||
hose->cfg_addr = &(pci->car);
|
||||
hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS;
|
||||
|
||||
pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
|
||||
pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
|
||||
pci_write_cfg_dword);
|
||||
|
||||
/* Hose scan */
|
||||
pci_register_hose(hose);
|
||||
hose->last_busno = pci_hose_scan(hose);
|
||||
}
|
||||
#endif /* CONFIG_PCI */
|
||||
186
cpu/mcf5445x/speed.c
Normal file
186
cpu/mcf5445x/speed.c
Normal file
|
|
@ -0,0 +1,186 @@
|
|||
/*
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
#include <asm/immap.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Low Power Divider specifications
|
||||
*/
|
||||
#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
|
||||
#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
|
||||
|
||||
#define CLOCK_PLL_FVCO_MAX 540000000
|
||||
#define CLOCK_PLL_FVCO_MIN 300000000
|
||||
|
||||
#define CLOCK_PLL_FSYS_MAX 266666666
|
||||
#define CLOCK_PLL_FSYS_MIN 100000000
|
||||
#define MHZ 1000000
|
||||
|
||||
void clock_enter_limp(int lpdiv)
|
||||
{
|
||||
volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
|
||||
int i, j;
|
||||
|
||||
/* Check bounds of divider */
|
||||
if (lpdiv < CLOCK_LPD_MIN)
|
||||
lpdiv = CLOCK_LPD_MIN;
|
||||
if (lpdiv > CLOCK_LPD_MAX)
|
||||
lpdiv = CLOCK_LPD_MAX;
|
||||
|
||||
/* Round divider down to nearest power of two */
|
||||
for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
|
||||
|
||||
/* Apply the divider to the system clock */
|
||||
ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i);
|
||||
|
||||
/* Enable Limp Mode */
|
||||
ccm->misccr |= CCM_MISCCR_LIMP;
|
||||
}
|
||||
|
||||
/*
|
||||
* brief Exit Limp mode
|
||||
* warning The PLL should be set and locked prior to exiting Limp mode
|
||||
*/
|
||||
void clock_exit_limp(void)
|
||||
{
|
||||
volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
|
||||
volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
|
||||
|
||||
/* Exit Limp mode */
|
||||
ccm->misccr &= ~CCM_MISCCR_LIMP;
|
||||
|
||||
/* Wait for the PLL to lock */
|
||||
while (!(pll->psr & PLL_PSR_LOCK)) ;
|
||||
}
|
||||
|
||||
/*
|
||||
* get_clocks() fills in gd->cpu_clock and gd->bus_clk
|
||||
*/
|
||||
int get_clocks(void)
|
||||
{
|
||||
volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
|
||||
volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
|
||||
volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3);
|
||||
volatile u8 *fpga = (volatile u8 *)(CFG_CS3_BASE + 14);
|
||||
int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
|
||||
int pllmult_pci[] = { 12, 6, 16, 8 };
|
||||
int vco, bPci, temp, fbtemp, pcrvalue;
|
||||
int *pPllmult = NULL;
|
||||
u16 fbpll_mask;
|
||||
u8 cpldmode;
|
||||
|
||||
/* To determine PCI is present or not */
|
||||
if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
|
||||
((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
|
||||
pPllmult = &pllmult_pci[0];
|
||||
fbpll_mask = 3;
|
||||
bPci = 1;
|
||||
} else {
|
||||
pPllmult = &pllmult_nopci[0];
|
||||
fbpll_mask = 7;
|
||||
#ifdef CONFIG_PCI
|
||||
gd->pci_clk = 0;
|
||||
#endif
|
||||
bPci = 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_M54455EVB
|
||||
/* Temporary place here, belongs in board/freescale/... */
|
||||
/* Temporary read from CCR- fixed fb issue, must be the same clock
|
||||
as pci or input clock, causing cpld/fpga read inconsistancy */
|
||||
fbtemp = pPllmult[ccm->ccr & fbpll_mask];
|
||||
|
||||
/* Break down into small pieces, code still in flex bus */
|
||||
pcrvalue = pll->pcr & 0xFFFFF0FF;
|
||||
temp = fbtemp - 1;
|
||||
pcrvalue |= PLL_PCR_OUTDIV3(temp);
|
||||
|
||||
pll->pcr = pcrvalue;
|
||||
|
||||
cpldmode = *cpld & 0x03;
|
||||
if (cpldmode == 0) {
|
||||
/* RCON mode */
|
||||
vco = pPllmult[ccm->rcon & fbpll_mask] * CFG_INPUT_CLKSRC;
|
||||
|
||||
if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
|
||||
/* invaild range, re-set in PCR */
|
||||
int temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
|
||||
int i, j, bus;
|
||||
|
||||
j = (pll->pcr & 0xFF000000) >> 24;
|
||||
for (i = j; i < 0xFF; i++) {
|
||||
vco = i * CFG_INPUT_CLKSRC;
|
||||
if (vco >= CLOCK_PLL_FVCO_MIN) {
|
||||
bus = vco / temp;
|
||||
if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
|
||||
continue;
|
||||
else
|
||||
break;
|
||||
}
|
||||
}
|
||||
pcrvalue = pll->pcr & 0x00FF00FF;
|
||||
fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
|
||||
pcrvalue |= ((i << 24) | fbtemp);
|
||||
|
||||
pll->pcr = pcrvalue;
|
||||
}
|
||||
gd->vco_clk = vco; /* Vco clock */
|
||||
} else if (cpldmode == 2) {
|
||||
/* Normal mode */
|
||||
vco = pPllmult[ccm->ccr & fbpll_mask] * CFG_INPUT_CLKSRC;
|
||||
gd->vco_clk = vco; /* Vco clock */
|
||||
} else if (cpldmode == 3) {
|
||||
/* serial mode */
|
||||
}
|
||||
#endif /* CONFIG_M54455EVB */
|
||||
|
||||
if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
|
||||
/* Limp mode */
|
||||
} else {
|
||||
gd->inp_clk = CFG_INPUT_CLKSRC; /* Input clock */
|
||||
|
||||
temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
|
||||
gd->cpu_clk = vco / temp; /* cpu clock */
|
||||
|
||||
temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
|
||||
gd->bus_clk = vco / temp; /* bus clock */
|
||||
|
||||
temp = ((pll->pcr & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
|
||||
gd->flb_clk = vco / temp; /* FlexBus clock */
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
if (bPci) {
|
||||
temp = ((pll->pcr & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
|
||||
gd->pci_clk = vco / temp; /* PCI clock */
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
388
cpu/mcf5445x/start.S
Normal file
388
cpu/mcf5445x/start.S
Normal file
|
|
@ -0,0 +1,388 @@
|
|||
/*
|
||||
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
|
||||
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include "version.h"
|
||||
|
||||
#ifndef CONFIG_IDENT_STRING
|
||||
#define CONFIG_IDENT_STRING ""
|
||||
#endif
|
||||
|
||||
/* last three long word reserved for cache status */
|
||||
#define CACR_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12)
|
||||
#define ICACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8)
|
||||
#define DCACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4)
|
||||
|
||||
#define _START _start
|
||||
#define _FAULT _fault
|
||||
|
||||
#define SAVE_ALL \
|
||||
move.w #0x2700,%sr; /* disable intrs */ \
|
||||
subl #60,%sp; /* space for 15 regs */ \
|
||||
moveml %d0-%d7/%a0-%a6,%sp@;
|
||||
|
||||
#define RESTORE_ALL \
|
||||
moveml %sp@,%d0-%d7/%a0-%a6; \
|
||||
addl #60,%sp; /* space for 15 regs */ \
|
||||
rte;
|
||||
|
||||
.text
|
||||
/*
|
||||
* Vector table. This is used for initial platform startup.
|
||||
* These vectors are to catch any un-intended traps.
|
||||
*/
|
||||
_vectors:
|
||||
|
||||
INITSP: .long 0x00000000 /* Initial SP */
|
||||
INITPC: .long _START /* Initial PC */
|
||||
vector02: .long _FAULT /* Access Error */
|
||||
vector03: .long _FAULT /* Address Error */
|
||||
vector04: .long _FAULT /* Illegal Instruction */
|
||||
vector05: .long _FAULT /* Reserved */
|
||||
vector06: .long _FAULT /* Reserved */
|
||||
vector07: .long _FAULT /* Reserved */
|
||||
vector08: .long _FAULT /* Privilege Violation */
|
||||
vector09: .long _FAULT /* Trace */
|
||||
vector0A: .long _FAULT /* Unimplemented A-Line */
|
||||
vector0B: .long _FAULT /* Unimplemented F-Line */
|
||||
vector0C: .long _FAULT /* Debug Interrupt */
|
||||
vector0D: .long _FAULT /* Reserved */
|
||||
vector0E: .long _FAULT /* Format Error */
|
||||
vector0F: .long _FAULT /* Unitialized Int. */
|
||||
|
||||
/* Reserved */
|
||||
vector10_17:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
|
||||
vector18: .long _FAULT /* Spurious Interrupt */
|
||||
vector19: .long _FAULT /* Autovector Level 1 */
|
||||
vector1A: .long _FAULT /* Autovector Level 2 */
|
||||
vector1B: .long _FAULT /* Autovector Level 3 */
|
||||
vector1C: .long _FAULT /* Autovector Level 4 */
|
||||
vector1D: .long _FAULT /* Autovector Level 5 */
|
||||
vector1E: .long _FAULT /* Autovector Level 6 */
|
||||
vector1F: .long _FAULT /* Autovector Level 7 */
|
||||
|
||||
/* TRAP #0 - #15 */
|
||||
vector20_2F:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
|
||||
/* Reserved */
|
||||
vector30_3F:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
|
||||
vector64_127:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
|
||||
vector128_191:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
|
||||
vector192_255:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
|
||||
.text
|
||||
|
||||
.globl _start
|
||||
_start:
|
||||
nop
|
||||
nop
|
||||
move.w #0x2700,%sr /* Mask off Interrupt */
|
||||
|
||||
/* Set vector base register at the beginning of the Flash */
|
||||
move.l #CFG_FLASH_BASE, %d0
|
||||
movec %d0, %VBR
|
||||
|
||||
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
|
||||
movec %d0, %RAMBAR0
|
||||
|
||||
/* initialize general use internal ram */
|
||||
move.l #0, %d0
|
||||
move.l #(CACR_STATUS), %a1 /* CACR */
|
||||
move.l #(ICACHE_STATUS), %a2 /* icache */
|
||||
move.l #(DCACHE_STATUS), %a3 /* dcache */
|
||||
move.l %d0, (%a1)
|
||||
move.l %d0, (%a2)
|
||||
move.l %d0, (%a3)
|
||||
|
||||
/* invalidate and disable cache */
|
||||
move.l #0x01004100, %d0 /* Invalidate cache cmd */
|
||||
movec %d0, %CACR /* Invalidate cache */
|
||||
move.l #0, %d0
|
||||
movec %d0, %ACR0
|
||||
movec %d0, %ACR1
|
||||
movec %d0, %ACR2
|
||||
movec %d0, %ACR3
|
||||
|
||||
/* set stackpointer to end of internal ram to get some stackspace for
|
||||
the first c-code */
|
||||
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
|
||||
clr.l %sp@-
|
||||
|
||||
move.l #__got_start, %a5 /* put relocation table address to a5 */
|
||||
|
||||
bsr cpu_init_f /* run low-level CPU init code (from flash) */
|
||||
bsr board_init_f /* run low-level board init code (from flash) */
|
||||
|
||||
/* board_init_f() does not return */
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* void relocate_code (addr_sp, gd, addr_moni)
|
||||
*
|
||||
* This "function" does not return, instead it continues in RAM
|
||||
* after relocating the monitor code.
|
||||
*
|
||||
* r3 = dest
|
||||
* r4 = src
|
||||
* r5 = length in bytes
|
||||
* r6 = cachelinesize
|
||||
*/
|
||||
.globl relocate_code
|
||||
relocate_code:
|
||||
link.w %a6,#0
|
||||
move.l 8(%a6), %sp /* set new stack pointer */
|
||||
|
||||
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
|
||||
move.l 16(%a6), %a0 /* Save copy of Destination Address */
|
||||
|
||||
move.l #CFG_MONITOR_BASE, %a1
|
||||
move.l #__init_end, %a2
|
||||
move.l %a0, %a3
|
||||
|
||||
/* copy the code to RAM */
|
||||
1:
|
||||
move.l (%a1)+, (%a3)+
|
||||
cmp.l %a1,%a2
|
||||
bgt.s 1b
|
||||
|
||||
/*
|
||||
* We are done. Do not return, instead branch to second part of board
|
||||
* initialization, now running from RAM.
|
||||
*/
|
||||
move.l %a0, %a1
|
||||
add.l #(in_ram - CFG_MONITOR_BASE), %a1
|
||||
jmp (%a1)
|
||||
|
||||
in_ram:
|
||||
|
||||
clear_bss:
|
||||
/*
|
||||
* Now clear BSS segment
|
||||
*/
|
||||
move.l %a0, %a1
|
||||
add.l #(_sbss - CFG_MONITOR_BASE),%a1
|
||||
move.l %a0, %d1
|
||||
add.l #(_ebss - CFG_MONITOR_BASE),%d1
|
||||
6:
|
||||
clr.l (%a1)+
|
||||
cmp.l %a1,%d1
|
||||
bgt.s 6b
|
||||
|
||||
/*
|
||||
* fix got table in RAM
|
||||
*/
|
||||
move.l %a0, %a1
|
||||
add.l #(__got_start - CFG_MONITOR_BASE),%a1
|
||||
move.l %a1,%a5 /* * fix got pointer register a5 */
|
||||
|
||||
move.l %a0, %a2
|
||||
add.l #(__got_end - CFG_MONITOR_BASE),%a2
|
||||
|
||||
7:
|
||||
move.l (%a1),%d1
|
||||
sub.l #_start,%d1
|
||||
add.l %a0,%d1
|
||||
move.l %d1,(%a1)+
|
||||
cmp.l %a2, %a1
|
||||
bne 7b
|
||||
|
||||
/* calculate relative jump to board_init_r in ram */
|
||||
move.l %a0, %a1
|
||||
add.l #(board_init_r - CFG_MONITOR_BASE), %a1
|
||||
|
||||
/* set parameters for board_init_r */
|
||||
move.l %a0,-(%sp) /* dest_addr */
|
||||
move.l %d0,-(%sp) /* gd */
|
||||
jsr (%a1)
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* exception code */
|
||||
.globl _fault
|
||||
_fault:
|
||||
jmp _fault
|
||||
.globl _exc_handler
|
||||
|
||||
_exc_handler:
|
||||
SAVE_ALL
|
||||
movel %sp,%sp@-
|
||||
bsr exc_handler
|
||||
addql #4,%sp
|
||||
RESTORE_ALL
|
||||
|
||||
.globl _int_handler
|
||||
_int_handler:
|
||||
SAVE_ALL
|
||||
movel %sp,%sp@-
|
||||
bsr int_handler
|
||||
addql #4,%sp
|
||||
RESTORE_ALL
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* cache functions */
|
||||
.globl icache_enable
|
||||
icache_enable:
|
||||
move.l #(CACR_STATUS), %a1 /* read CACR Status */
|
||||
move.l (%a1), %d1
|
||||
|
||||
move.l #0x00040100, %d0 /* Invalidate icache */
|
||||
or.l %d1, %d0
|
||||
movec %d0, %CACR
|
||||
|
||||
move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup icache */
|
||||
movec %d0, %ACR2
|
||||
|
||||
or.l #0x00088400, %d1 /* Enable bcache and icache */
|
||||
movec %d1, %CACR
|
||||
|
||||
move.l #(ICACHE_STATUS), %a1
|
||||
moveq #1, %d0
|
||||
move.l %d0, (%a1)
|
||||
rts
|
||||
|
||||
.globl icache_disable
|
||||
icache_disable:
|
||||
move.l #(CACR_STATUS), %a1 /* read CACR Status */
|
||||
move.l (%a1), %d0
|
||||
|
||||
and.l #0xFFF77BFF, %d0
|
||||
or.l #0x00040100, %d0 /* Setup cache mask */
|
||||
movec %d0, %CACR /* Invalidate icache */
|
||||
clr.l %d0
|
||||
movec %d0, %ACR2
|
||||
movec %d0, %ACR3
|
||||
|
||||
move.l #(ICACHE_STATUS), %a1
|
||||
moveq #0, %d0
|
||||
move.l %d0, (%a1)
|
||||
rts
|
||||
|
||||
.globl icache_status
|
||||
icache_status:
|
||||
move.l #(ICACHE_STATUS), %a1
|
||||
move.l (%a1), %d0
|
||||
rts
|
||||
|
||||
.globl icache_invalid
|
||||
icache_invalid:
|
||||
move.l #(CACR_STATUS), %a1 /* read CACR Status */
|
||||
move.l (%a1), %d0
|
||||
|
||||
or.l #0x00040100, %d0 /* Invalidate icache */
|
||||
movec %d0, %CACR /* Enable and invalidate cache */
|
||||
rts
|
||||
|
||||
.globl dcache_enable
|
||||
dcache_enable:
|
||||
move.l #(CACR_STATUS), %a1 /* read CACR Status */
|
||||
move.l (%a1), %d1
|
||||
|
||||
move.l #0x01000000, %d0
|
||||
or.l %d1, %d0
|
||||
movec %d0, %CACR /* Invalidate dcache */
|
||||
|
||||
move.l #(CFG_SDRAM_BASE + 0xc000), %d0
|
||||
movec %d0, %ACR0
|
||||
move.l #0, %d0
|
||||
movec %d0, %ACR1
|
||||
|
||||
or.l #0x80000000, %d1 /* Enable bcache and icache */
|
||||
movec %d1, %CACR
|
||||
|
||||
move.l #(DCACHE_STATUS), %a1
|
||||
moveq #1, %d0
|
||||
move.l %d0, (%a1)
|
||||
rts
|
||||
|
||||
.globl dcache_disable
|
||||
dcache_disable:
|
||||
move.l #(CACR_STATUS), %a1 /* read CACR Status */
|
||||
move.l (%a1), %d0
|
||||
|
||||
and.l #0x7FFFFFFF, %d0
|
||||
or.l #0x01000000, %d0 /* Setup cache mask */
|
||||
movec %d0, %CACR /* Disable dcache */
|
||||
clr.l %d0
|
||||
movec %d0, %ACR0
|
||||
movec %d0, %ACR1
|
||||
|
||||
move.l #(DCACHE_STATUS), %a1
|
||||
moveq #0, %d0
|
||||
move.l %d0, (%a1)
|
||||
rts
|
||||
|
||||
.globl dcache_invalid
|
||||
dcache_invalid:
|
||||
move.l #(CACR_STATUS), %a1 /* read CACR Status */
|
||||
move.l (%a1), %d0
|
||||
|
||||
or.l #0x01000000, %d0 /* Setup cache mask */
|
||||
movec %d0, %CACR /* Enable and invalidate cache */
|
||||
rts
|
||||
|
||||
.globl dcache_status
|
||||
dcache_status:
|
||||
move.l #(DCACHE_STATUS), %a1
|
||||
move.l (%a1), %d0
|
||||
rts
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
|
||||
.globl version_string
|
||||
version_string:
|
||||
.ascii U_BOOT_VERSION
|
||||
.ascii " (", __DATE__, " - ", __TIME__, ")"
|
||||
.ascii CONFIG_IDENT_STRING, "\0"
|
||||
103
doc/README.m5253evbe
Normal file
103
doc/README.m5253evbe
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
Freescale Amadeus Plus M5253EVBE board
|
||||
======================================
|
||||
|
||||
Hayden Fraser(Hayden.Fraser@freescale.com)
|
||||
Created 06/05/2007
|
||||
===========================================
|
||||
|
||||
|
||||
1. SWITCH SETTINGS
|
||||
==================
|
||||
1.1 N/A
|
||||
|
||||
|
||||
2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
|
||||
===========================================
|
||||
2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and
|
||||
linux kernel, you can customize it based on your system requirements:
|
||||
SDR: 0x00000000-0x00ffffff
|
||||
SRAM0: 0x20010000-0x20017fff
|
||||
SRAM1: 0x20000000-0x2000ffff
|
||||
MBAR1: 0x10000000-0x4fffffff
|
||||
MBAR2: 0x80000000-0xCfffffff
|
||||
Flash: 0xffe00000-0xffffffff
|
||||
|
||||
3. DEFINITIONS AND COMPILATION
|
||||
==============================
|
||||
3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h
|
||||
CONFIG_MCF52x2 Processor family
|
||||
CONFIG_MCF5253 MCF5253 specific
|
||||
CONFIG_M5253EVBE Amadeus Plus board specific
|
||||
CFG_CLK Define Amadeus Plus CPU Clock
|
||||
CFG_MBAR MBAR base address
|
||||
CFG_MBAR2 MBAR2 base address
|
||||
|
||||
3.2 Compilation
|
||||
export CROSS_COMPILE=/usr/local/freescale-coldfire-4.1-elf/bin/m68k-elf-
|
||||
cd u-boot-1-2-x
|
||||
make distclean
|
||||
make M5253EVBE_config
|
||||
make
|
||||
|
||||
|
||||
4. SCREEN DUMP
|
||||
==============
|
||||
4.1 U-Boot 1.2.0 (Jun 18 2007 - 18:20:00)
|
||||
|
||||
CPU: Freescale Coldfire MCF5253 at 62 MHz
|
||||
Board: Freescale MCF5253 EVBE
|
||||
DRAM: 16 MB
|
||||
FLASH: 2 MB
|
||||
In: serial
|
||||
Out: serial
|
||||
Err: serial
|
||||
=> flinfo
|
||||
|
||||
Bank # 1: CFI conformant FLASH (16 x 16) Size: 2 MB in 35 Sectors
|
||||
AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x49
|
||||
Erase timeout: 16384 ms, write timeout: 1 ms
|
||||
|
||||
Sector Start Addresses:
|
||||
FFE00000 RO FFE04000 RO FFE06000 RO FFE08000 RO FFE10000 RO
|
||||
FFE20000 FFE30000 FFE40000 FFE50000 FFE60000
|
||||
FFE70000 FFE80000 FFE90000 FFEA0000 FFEB0000
|
||||
FFEC0000 FFED0000 FFEE0000 FFEF0000 FFF00000
|
||||
FFF10000 FFF20000 FFF30000 FFF40000 FFF50000
|
||||
FFF60000 FFF70000 FFF80000 FFF90000 FFFA0000
|
||||
FFFB0000 FFFC0000 FFFD0000 FFFE0000 FFFF0000
|
||||
|
||||
=> bdinfo
|
||||
boot_params = 0x00F62F90
|
||||
memstart = 0x00000000
|
||||
memsize = 0x01000000
|
||||
flashstart = 0xFFE00000
|
||||
flashsize = 0x00200000
|
||||
flashoffset = 0x00000000
|
||||
baudrate = 19200 bps
|
||||
|
||||
=> printenv
|
||||
bootdelay=5
|
||||
baudrate=19200
|
||||
stdin=serial
|
||||
stdout=serial
|
||||
stderr=serial
|
||||
|
||||
Environment size: 134/8188 bytes
|
||||
=> saveenv
|
||||
Saving Environment to Flash...
|
||||
Un-Protected 1 sectors
|
||||
Erasing Flash...
|
||||
. done
|
||||
Erased 1 sectors
|
||||
Writing to Flash... done
|
||||
Protected 1 sectors
|
||||
=>
|
||||
|
||||
5. COMPILER
|
||||
-----------
|
||||
To create U-Boot the CodeSourcery's version of the GNU Toolchain for the ColdFire architecture
|
||||
compiler set (freescale-coldfire-4.1-elf) from www.codesourcery.com was used.
|
||||
You can download it from:http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
|
||||
|
||||
compiler that you used - for example, codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M
|
||||
codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M
|
||||
416
doc/README.m54455evb
Normal file
416
doc/README.m54455evb
Normal file
|
|
@ -0,0 +1,416 @@
|
|||
Freescale MCF54455EVB ColdFire Development Board
|
||||
================================================
|
||||
|
||||
TsiChung Liew(Tsi-Chung.Liew@freescale.com)
|
||||
Created 4/08/07
|
||||
===========================================
|
||||
|
||||
|
||||
Changed files:
|
||||
==============
|
||||
|
||||
- board/freescale/m54455evb/m54455evb.c Dram setup, IDE pre init, and PCI init
|
||||
- board/freescale/m54455evb/flash.c Atmel and INTEL flash support
|
||||
- board/freescale/m54455evb/Makefile Makefile
|
||||
- board/freescale/m54455evb/config.mk config make
|
||||
- board/freescale/m54455evb/u-boot.lds Linker description
|
||||
|
||||
- common/cmd_bdinfo.c Clock frequencies output
|
||||
- common/cmd_mii.c mii support
|
||||
|
||||
- cpu/mcf5445x/cpu.c cpu specific code
|
||||
- cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
|
||||
- cpu/mcf5445x/interrupts.c cpu specific interrupt support
|
||||
- cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock
|
||||
- cpu/mcf5445x/Makefile Makefile
|
||||
- cpu/mcf5445x/config.mk config make
|
||||
- cpu/mcf5445x/start.S start up assembly code
|
||||
|
||||
- doc/README.m54455evb This readme file
|
||||
|
||||
- drivers/net/mcffec.c ColdFire common FEC driver
|
||||
- drivers/serial/mcfuart.c ColdFire common UART driver
|
||||
|
||||
- include/asm-m68k/bitops.h Bit operation function export
|
||||
- include/asm-m68k/byteorder.h Byte order functions
|
||||
- include/asm-m68k/fec.h FEC structure and definition
|
||||
- include/asm-m68k/fsl_i2c.h I2C structure and definition
|
||||
- include/asm-m68k/global_data.h Global data structure
|
||||
- include/asm-m68k/immap.h ColdFire specific header file and driver macros
|
||||
- include/asm-m68k/immap_5445x.h mcf5445x specific header file
|
||||
- include/asm-m68k/io.h io functions
|
||||
- include/asm-m68k/m5445x.h mcf5445x specific header file
|
||||
- include/asm-m68k/posix_types.h Posix
|
||||
- include/asm-m68k/processor.h header file
|
||||
- include/asm-m68k/ptrace.h Exception structure
|
||||
- include/asm-m68k/rtc.h Realtime clock header file
|
||||
- include/asm-m68k/string.h String function export
|
||||
- include/asm-m68k/timer.h Timer structure and definition
|
||||
- include/asm-m68k/types.h Data types definition
|
||||
- include/asm-m68k/uart.h Uart structure and definition
|
||||
- include/asm-m68k/u-boot.h u-boot structure
|
||||
|
||||
- include/configs/M54455EVB.h Board specific configuration file
|
||||
|
||||
- lib_m68k/board.c board init function
|
||||
- lib_m68k/cache.c
|
||||
- lib_m68k/interrupts Coldfire common interrupt functions
|
||||
- lib_m68k/m68k_linux.c
|
||||
- lib_m68k/time.c Timer functions (Dma timer and PIT)
|
||||
- lib_m68k/traps.c Exception init code
|
||||
|
||||
- rtc/mcfrtc.c Realtime clock Driver
|
||||
|
||||
1 MCF5445x specific Options/Settings
|
||||
====================================
|
||||
1.1 pre-loader is no longer suppoer in thie coldfire family
|
||||
|
||||
1.2 Configuration settings for M54455EVB Development Board
|
||||
CONFIG_MCF5445x -- define for all MCF5445x CPUs
|
||||
CONFIG_M54455 -- define for all Freescale MCF54455 CPUs
|
||||
CONFIG_M54455EVB -- define for M54455EVB board
|
||||
|
||||
CONFIG_MCFUART -- define to use common CF Uart driver
|
||||
CFG_UART_PORT -- define UART port number, start with 0, 1 and 2
|
||||
CONFIG_BAUDRATE -- define UART baudrate
|
||||
|
||||
CONFIG_MCFRTC -- define to use common CF RTC driver
|
||||
CFG_MCFRTC_BASE -- provide base address for RTC in immap.h
|
||||
CFG_RTC_OSCILLATOR -- define RTC clock frequency
|
||||
RTC_DEBUG -- define to show RTC debug message
|
||||
CONFIG_CMD_DATE -- enable to use date feature in u-boot
|
||||
|
||||
CONFIG_MCFFEC -- define to use common CF FEC driver
|
||||
CONFIG_NET_MULTI -- define to use multi FEC in u-boot
|
||||
CONFIG_MII -- enable to use MII driver
|
||||
CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
|
||||
CFG_DISCOVER_PHY -- enable PHY discovery
|
||||
CFG_RX_ETH_BUFFER -- Set FEC Receive buffer
|
||||
CFG_FAULT_ECHO_LINK_DOWN--
|
||||
CFG_FEC0_PINMUX -- Set FEC0 Pin configuration
|
||||
CFG_FEC1_PINMUX -- Set FEC1 Pin configuration
|
||||
CFG_FEC0_MIIBASE -- Set FEC0 MII base register
|
||||
CFG_FEC1_MIIBASE -- Set FEC0 MII base register
|
||||
MCFFEC_TOUT_LOOP -- set FEC timeout loop
|
||||
CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot
|
||||
|
||||
CONFIG_ISO_PARTITION -- enable ISO read/write
|
||||
CONFIG_DOS_PARTITION -- enable DOS read/write
|
||||
CONFIG_IDE_RESET -- define ide_reset()
|
||||
CONFIG_IDE_PREINIT -- define ide_preinit()
|
||||
CONFIG_ATAPI -- define ATAPI support
|
||||
CONFIG_LBA48 -- define LBA48 (larger than 120GB) support
|
||||
CFG_IDE_MAXBUS -- define max channel
|
||||
CFG_IDE_MAXDEVICE -- define max devices per channel
|
||||
CFG_ATA_BASE_ADDR -- define ATA base address
|
||||
CFG_ATA_IDE0_OFFSET -- define ATA IDE0 offset
|
||||
CFG_ATA_DATA_OFFSET -- define ATA data IO
|
||||
CFG_ATA_REG_OFFSET -- define for normal register accesses
|
||||
CFG_ATA_ALT_OFFSET -- define for alternate registers
|
||||
CFG_ATA_STRIDE -- define for Interval between registers
|
||||
_IO_BASE -- define for IO base address
|
||||
|
||||
CONFIG_MCFTMR -- define to use DMA timer
|
||||
CONFIG_MCFPIT -- define to use PIT timer
|
||||
|
||||
CONFIG_FSL_I2C -- define to use FSL common I2C driver
|
||||
CONFIG_HARD_I2C -- define for I2C hardware support
|
||||
CONFIG_SOFT_I2C -- define for I2C bit-banged
|
||||
CFG_I2C_SPEED -- define for I2C speed
|
||||
CFG_I2C_SLAVE -- define for I2C slave address
|
||||
CFG_I2C_OFFSET -- define for I2C base address offset
|
||||
CFG_IMMR -- define for MBAR offset
|
||||
|
||||
CONFIG_PCI -- define for PCI support
|
||||
CONFIG_PCI_PNP -- define for Plug n play support
|
||||
CFG_PCI_MEM_BUS -- PCI memory logical offset
|
||||
CFG_PCI_MEM_PHYS -- PCI memory physical offset
|
||||
CFG_PCI_MEM_SIZE -- PCI memory size
|
||||
CFG_PCI_IO_BUS -- PCI IO logical offset
|
||||
CFG_PCI_IO_PHYS -- PCI IO physical offset
|
||||
CFG_PCI_IO_SIZE -- PCI IO size
|
||||
CFG_PCI_CFG_BUS -- PCI Configuration logical offset
|
||||
CFG_PCI_CFG_PHYS -- PCI Configuration physical offset
|
||||
CFG_PCI_CFG_SIZE -- PCI Configuration size
|
||||
|
||||
CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc
|
||||
|
||||
CFG_MBAR -- define MBAR offset
|
||||
|
||||
CFG_ATMEL_BOOT -- To determine the u-boot is booted from Atmel or Intel
|
||||
|
||||
CONFIG_MONITOR_IS_IN_RAM -- Not support
|
||||
|
||||
CFG_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM
|
||||
|
||||
CFG_CSn_BASE -- defines the Chip Select Base register
|
||||
CFG_CSn_MASK -- defines the Chip Select Mask register
|
||||
CFG_CSn_CTRL -- defines the Chip Select Control register
|
||||
|
||||
CFG_ATMEL_BASE -- defines the Atmel Flash base
|
||||
CFG_INTEL_BASE -- defines the Intel Flash base
|
||||
|
||||
CFG_SDRAM_BASE -- defines the DRAM Base
|
||||
CFG_SDRAM_BASE1 -- defines the DRAM Base 1
|
||||
|
||||
2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
|
||||
===========================================
|
||||
2.1. System memory map:
|
||||
Flash: 0x00000000-0x3FFFFFFF (1024MB)
|
||||
DDR: 0x40000000-0x7FFFFFFF (1024MB)
|
||||
SRAM: 0x80000000-0x8FFFFFFF (256MB)
|
||||
ATA: 0x90000000-0x9FFFFFFF (256MB)
|
||||
PCI: 0xA0000000-0xBFFFFFFF (512MB)
|
||||
FlexBus: 0xC0000000-0xDFFFFFFF (512MB)
|
||||
IP: 0xF0000000-0xFFFFFFFF (256MB)
|
||||
|
||||
2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
|
||||
linux kernel, you can customize it based on your system requirements:
|
||||
Atmel boot:
|
||||
Flash0: 0x00000000-0x0007FFFF (512KB)
|
||||
Flash1: 0x04000000-0x05FFFFFF (32MB)
|
||||
Intel boot:
|
||||
Flash0: 0x00000000-0x01FFFFFF (32MB)
|
||||
Flash1: 0x04000000-0x0407FFFF (512KB)
|
||||
|
||||
CPLD: 0x08000000-0x08FFFFFF (16MB)
|
||||
FPGA: 0x09000000-0x09FFFFFF (16MB)
|
||||
DDR: 0x40000000-0x4FFFFFFF (256MB)
|
||||
SRAM: 0x80000000-0x80007FFF (32KB)
|
||||
IP: 0xFC000000-0xFC0FFFFF (64KB)
|
||||
|
||||
3. SWITCH SETTINGS
|
||||
==================
|
||||
3.1 SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL
|
||||
SW1 Pin4: 0 - ULPI chip not in reset state or 1 - ULPI chip in reset state
|
||||
SW1 Pin5: 0 - Full ATA Bus enabled, FEC Phy1 powered down
|
||||
1 - Upper 8 bits ATA data bus disabled, FEC PHY1 active
|
||||
SW1 Pin6: 0 - FEC Phy0 active or 1 - FEC Phy0 powered down
|
||||
SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL
|
||||
|
||||
4. COMPILATION
|
||||
==============
|
||||
4.1 To create U-Boot the gcc-4.1-32 compiler set (ColdFire ELF version)
|
||||
from codesourcery.com was used. Download it from:
|
||||
http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
|
||||
|
||||
4.2 Compilation
|
||||
export CROSS_COMPILE=cross-compile-prefix
|
||||
cd u-boot-1.x.x
|
||||
make distclean
|
||||
make M54455EVB_config, or - default to atmel 33Mhz input clock
|
||||
make M54455EVB_atmel_config, or - default to atmel 33Mhz input clock
|
||||
make M54455EVB_a33_config, or - default to atmel 33Mhz input clock
|
||||
make M54455EVB_a66_config, or - default to atmel 66Mhz input clock
|
||||
make M54455EVB_intel_config, or - default to intel 33Mhz input clock
|
||||
make M54455EVB_i33_config, or - default to intel 33Mhz input clock
|
||||
make M54455EVB_i66_config, or - default to intel 66Mhz input clock
|
||||
make
|
||||
|
||||
5. SCREEN DUMP
|
||||
==============
|
||||
5.1 M54455EVB Development board
|
||||
Boot from Atmel (NOTE: May not show exactly the same)
|
||||
|
||||
U-Boot 1.2.0-g98c80b46-dirty (Jul 26 2007 - 12:44:08)
|
||||
|
||||
CPU: Freescale MCF54455 (Mask:48 Version:1)
|
||||
CPU CLK 266 Mhz BUS CLK 133 Mhz FLB CLK 66 Mhz
|
||||
PCI CLK 33 Mhz INP CLK 33 Mhz VCO CLK 533 Mhz
|
||||
Board: Freescale M54455 EVB
|
||||
I2C: ready
|
||||
DRAM: 256 MB
|
||||
FLASH: 16.5 MB
|
||||
In: serial
|
||||
Out: serial
|
||||
Err: serial
|
||||
Net: FEC0, FEC1
|
||||
IDE: Bus 0: not available
|
||||
-> print
|
||||
bootargs=root=/dev/ram rw
|
||||
bootdelay=1
|
||||
baudrate=115200
|
||||
ethaddr=00:e0:0c:bc:e5:60
|
||||
eth1addr=00:e0:0c:bc:e5:61
|
||||
hostname=M54455EVB
|
||||
netdev=eth0
|
||||
inpclk=33333333
|
||||
loadaddr=40010000
|
||||
load=tftp ${loadaddr) ${u-boot}
|
||||
upd=run load; run prog
|
||||
prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save
|
||||
ethact=FEC0
|
||||
mtdids=nor0=M54455EVB-1
|
||||
mtdparts=M54455EVB-1:16m(user)
|
||||
u-boot=u-boot54455.bin
|
||||
filesize=292b4
|
||||
fileaddr=40010000
|
||||
gatewayip=192.168.1.1
|
||||
netmask=255.255.255.0
|
||||
ipaddr=192.168.1.3
|
||||
serverip=192.168.1.2
|
||||
stdin=serial
|
||||
stdout=serial
|
||||
stderr=serial
|
||||
mem=261632k
|
||||
|
||||
Environment size: 563/8188 bytes
|
||||
-> bdinfo
|
||||
memstart = 0x40000000
|
||||
memsize = 0x10000000
|
||||
flashstart = 0x00000000
|
||||
flashsize = 0x01080000
|
||||
flashoffset = 0x00000000
|
||||
sramstart = 0x80000000
|
||||
sramsize = 0x00008000
|
||||
mbar = 0xFC000000
|
||||
busfreq = 133.333 MHz
|
||||
pcifreq = 33.333 MHz
|
||||
flbfreq = 66.666 MHz
|
||||
inpfreq = 33.333 MHz
|
||||
vcofreq = 533.333 MHz
|
||||
ethaddr = 00:E0:0C:BC:E5:60
|
||||
eth1addr = 00:E0:0C:BC:E5:61
|
||||
ip_addr = 192.168.1.3
|
||||
baudrate = 115200 bps
|
||||
->
|
||||
-> help
|
||||
? - alias for 'help'
|
||||
autoscr - run script from memory
|
||||
base - print or set address offset
|
||||
bdinfo - print Board Info structure
|
||||
boot - boot default, i.e., run 'bootcmd'
|
||||
bootd - boot default, i.e., run 'bootcmd'
|
||||
bootelf - Boot from an ELF image in memory
|
||||
bootm - boot application image from memory
|
||||
bootp - boot image via network using BootP/TFTP protocol
|
||||
bootvx - Boot vxWorks from an ELF image
|
||||
cmp - memory compare
|
||||
coninfo - print console devices and information
|
||||
cp - memory copy
|
||||
crc32 - checksum calculation
|
||||
date - get/set/reset date & time
|
||||
dcache - enable or disable data cache
|
||||
diskboot- boot from IDE device
|
||||
echo - echo args to console
|
||||
erase - erase FLASH memory
|
||||
ext2load- load binary file from a Ext2 filesystem
|
||||
ext2ls - list files in a directory (default /)
|
||||
fatinfo - print information about filesystem
|
||||
fatload - load binary file from a dos filesystem
|
||||
fatls - list files in a directory (default /)
|
||||
flinfo - print FLASH memory information
|
||||
fsinfo - print information about filesystems
|
||||
fsload - load binary file from a filesystem image
|
||||
go - start application at address 'addr'
|
||||
help - print online help
|
||||
icache - enable or disable instruction cache
|
||||
icrc32 - checksum calculation
|
||||
ide - IDE sub-system
|
||||
iloop - infinite loop on address range
|
||||
imd - i2c memory display
|
||||
iminfo - print header information for application image
|
||||
imls - list all images found in flash
|
||||
imm - i2c memory modify (auto-incrementing)
|
||||
imw - memory write (fill)
|
||||
inm - memory modify (constant address)
|
||||
iprobe - probe to discover valid I2C chip addresses
|
||||
itest - return true/false on integer compare
|
||||
loadb - load binary file over serial line (kermit mode)
|
||||
loads - load S-Record file over serial line
|
||||
loady - load binary file over serial line (ymodem mode)
|
||||
loop - infinite loop on address range
|
||||
ls - list files in a directory (default /)
|
||||
md - memory display
|
||||
mii - MII utility commands
|
||||
mm - memory modify (auto-incrementing)
|
||||
mtest - simple RAM test
|
||||
mw - memory write (fill)
|
||||
nfs - boot image via network using NFS protocol
|
||||
nm - memory modify (constant address)
|
||||
pci - list and access PCI Configuration Space
|
||||
ping - send ICMP ECHO_REQUEST to network host
|
||||
printenv- print environment variables
|
||||
protect - enable or disable FLASH write protection
|
||||
rarpboot- boot image via network using RARP/TFTP protocol
|
||||
reset - Perform RESET of the CPU
|
||||
run - run commands in an environment variable
|
||||
saveenv - save environment variables to persistent storage
|
||||
setenv - set environment variables
|
||||
sleep - delay execution for some time
|
||||
tftpboot- boot image via network using TFTP protocol
|
||||
version - print monitor version
|
||||
->bootm 4000000
|
||||
|
||||
## Booting image at 04000000 ...
|
||||
Image Name: Linux Kernel Image
|
||||
Created: 2007-08-14 15:13:00 UTC
|
||||
Image Type: M68K Linux Kernel Image (uncompressed)
|
||||
Data Size: 2301952 Bytes = 2.2 MB
|
||||
Load Address: 40020000
|
||||
Entry Point: 40020000
|
||||
Verifying Checksum ... OK
|
||||
OK
|
||||
Linux version 2.6.20-gfe5136d6-dirty (mattw@kea) (gcc version 4.2.0 20070318 (pr
|
||||
erelease) (Sourcery G++ Lite 4.2-20)) #108 Mon Aug 13 13:00:13 MDT 2007
|
||||
starting up linux startmem 0xc0254000, endmem 0xcfffffff, size 253MB
|
||||
Built 1 zonelists. Total pages: 32624
|
||||
Kernel command line: root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=ph
|
||||
ysmap-flash.0:5M(kernel)ro,-(jffs2)
|
||||
PID hash table entries: 1024 (order: 10, 4096 bytes)
|
||||
Console: colour dummy device 80x25
|
||||
Dentry cache hash table entries: 32768 (order: 4, 131072 bytes)
|
||||
Inode-cache hash table entries: 16384 (order: 3, 65536 bytes)
|
||||
Memory: 257496k/262136k available (1864k kernel code, 2440k data, 88k init)
|
||||
Mount-cache hash table entries: 1024
|
||||
NET: Registered protocol family 16
|
||||
SCSI subsystem initialized
|
||||
NET: Registered protocol family 2
|
||||
IP route cache hash table entries: 2048 (order: 0, 8192 bytes)
|
||||
TCP established hash table entries: 8192 (order: 2, 32768 bytes)
|
||||
TCP bind hash table entries: 4096 (order: 1, 16384 bytes)
|
||||
TCP: Hash tables configured (established 8192 bind 4096)
|
||||
TCP reno registered
|
||||
JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc.
|
||||
io scheduler noop registered
|
||||
io scheduler anticipatory registered
|
||||
io scheduler deadline registered
|
||||
io scheduler cfq registered (default)
|
||||
ColdFire internal UART serial driver version 1.00
|
||||
ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART
|
||||
ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART
|
||||
ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART
|
||||
RAMDISK driver initialized: 16 RAM disks of 64000K size 1024 blocksize
|
||||
loop: loaded (max 8 devices)
|
||||
FEC ENET Version 0.2
|
||||
fec: PHY @ 0x0, ID 0x20005ca2 -- DP83849
|
||||
eth0: ethernet 00:08:ee:00:e4:19
|
||||
physmap platform flash device: 01000000 at 04000000
|
||||
physmap-flash.0: Found 1 x16 devices at 0x0 in 8-bit bank
|
||||
Intel/Sharp Extended Query Table at 0x0031
|
||||
Using buffer write method
|
||||
cfi_cmdset_0001: Erase suspend on write enabled
|
||||
2 cmdlinepart partitions found on MTD device physmap-flash.0
|
||||
Creating 2 MTD partitions on "physmap-flash.0":
|
||||
0x00000000-0x00500000 : "kernel"
|
||||
mtd: Giving out device 0 to kernel
|
||||
0x00500000-0x01000000 : "jffs2"
|
||||
mtd: Giving out device 1 to jffs2
|
||||
mice: PS/2 mouse device common for all mice
|
||||
i2c /dev entries driver
|
||||
TCP cubic registered
|
||||
NET: Registered protocol family 1
|
||||
NET: Registered protocol family 17
|
||||
NET: Registered protocol family 15
|
||||
VFS: Mounted root (jffs2 filesystem).
|
||||
Setting the hostname to freescale
|
||||
Mounting filesystems
|
||||
mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory
|
||||
Starting syslogd and klogd
|
||||
Setting up networking on loopback device:
|
||||
Setting up networking on eth0:
|
||||
eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX.
|
||||
Adding static route for default gateway to 172.27.255.254:
|
||||
Setting nameserver to 172.27.0.1 in /etc/resolv.conf:
|
||||
Starting inetd:
|
||||
/ #
|
||||
45
drivers/net/Makefile
Normal file
45
drivers/net/Makefile
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB := $(obj)libnet.a
|
||||
|
||||
COBJS := mcffec.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
all: $(LIB)
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
597
drivers/net/mcffec.c
Normal file
597
drivers/net/mcffec.c
Normal file
|
|
@ -0,0 +1,597 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* (C) Copyright 2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <malloc.h>
|
||||
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <command.h>
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
#include <miiphy.h>
|
||||
|
||||
#ifdef CONFIG_MCFFEC
|
||||
#undef ET_DEBUG
|
||||
#undef MII_DEBUG
|
||||
|
||||
/* Ethernet Transmit and Receive Buffers */
|
||||
#define DBUF_LENGTH 1520
|
||||
#define TX_BUF_CNT 2
|
||||
#define PKT_MAXBUF_SIZE 1518
|
||||
#define PKT_MINBUF_SIZE 64
|
||||
#define PKT_MAXBLR_SIZE 1520
|
||||
#define LAST_PKTBUFSRX PKTBUFSRX - 1
|
||||
#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
|
||||
#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
|
||||
struct fec_info_s fec_info[] = {
|
||||
#ifdef CFG_FEC0_IOBASE
|
||||
{
|
||||
0, /* index */
|
||||
CFG_FEC0_IOBASE, /* io base */
|
||||
CFG_FEC0_PINMUX, /* gpio pin muxing */
|
||||
CFG_FEC0_MIIBASE, /* mii base */
|
||||
-1, /* phy_addr */
|
||||
0, /* duplex and speed */
|
||||
0, /* phy name */
|
||||
0, /* phyname init */
|
||||
0, /* RX BD */
|
||||
0, /* TX BD */
|
||||
0, /* rx Index */
|
||||
0, /* tx Index */
|
||||
0, /* tx buffer */
|
||||
0, /* initialized flag */
|
||||
},
|
||||
#endif
|
||||
#ifdef CFG_FEC1_IOBASE
|
||||
{
|
||||
1, /* index */
|
||||
CFG_FEC1_IOBASE, /* io base */
|
||||
CFG_FEC1_PINMUX, /* gpio pin muxing */
|
||||
CFG_FEC1_MIIBASE, /* mii base */
|
||||
-1, /* phy_addr */
|
||||
0, /* duplex and speed */
|
||||
0, /* phy name */
|
||||
0, /* phy name init */
|
||||
0, /* RX BD */
|
||||
0, /* TX BD */
|
||||
0, /* rx Index */
|
||||
0, /* tx Index */
|
||||
0, /* tx buffer */
|
||||
0, /* initialized flag */
|
||||
}
|
||||
#endif
|
||||
};
|
||||
|
||||
int fec_send(struct eth_device *dev, volatile void *packet, int length);
|
||||
int fec_recv(struct eth_device *dev);
|
||||
int fec_init(struct eth_device *dev, bd_t * bd);
|
||||
void fec_halt(struct eth_device *dev);
|
||||
void fec_reset(struct eth_device *dev);
|
||||
|
||||
extern int fecpin_setclear(struct eth_device *dev, int setclear);
|
||||
|
||||
#ifdef CFG_DISCOVER_PHY
|
||||
extern void __mii_init(void);
|
||||
extern uint mii_send(uint mii_cmd);
|
||||
extern int mii_discover_phy(struct eth_device *dev);
|
||||
extern int mcffec_miiphy_read(char *devname, unsigned char addr,
|
||||
unsigned char reg, unsigned short *value);
|
||||
extern int mcffec_miiphy_write(char *devname, unsigned char addr,
|
||||
unsigned char reg, unsigned short value);
|
||||
#endif
|
||||
|
||||
void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
|
||||
{
|
||||
if ((dup_spd >> 16) == FULL) {
|
||||
/* Set maximum frame length */
|
||||
fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
|
||||
FEC_RCR_PROM | 0x100;
|
||||
fecp->tcr = FEC_TCR_FDEN;
|
||||
} else {
|
||||
/* Half duplex mode */
|
||||
fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
|
||||
FEC_RCR_MII_MODE | FEC_RCR_DRT;
|
||||
fecp->tcr &= ~FEC_TCR_FDEN;
|
||||
}
|
||||
|
||||
if ((dup_spd & 0xFFFF) == _100BASET) {
|
||||
#ifdef MII_DEBUG
|
||||
printf("100Mbps\n");
|
||||
#endif
|
||||
bd->bi_ethspeed = 100;
|
||||
} else {
|
||||
#ifdef MII_DEBUG
|
||||
printf("10Mbps\n");
|
||||
#endif
|
||||
bd->bi_ethspeed = 10;
|
||||
}
|
||||
}
|
||||
|
||||
int fec_send(struct eth_device *dev, volatile void *packet, int length)
|
||||
{
|
||||
struct fec_info_s *info = dev->priv;
|
||||
volatile fec_t *fecp = (fec_t *) (info->iobase);
|
||||
int j, rc;
|
||||
u16 phyStatus;
|
||||
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus);
|
||||
|
||||
/* section 16.9.23.3
|
||||
* Wait for ready
|
||||
*/
|
||||
j = 0;
|
||||
while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
|
||||
(j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("TX not ready\n");
|
||||
}
|
||||
|
||||
info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
|
||||
info->txbd[info->txIdx].cbd_datlen = length;
|
||||
info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST;
|
||||
|
||||
/* Activate transmit Buffer Descriptor polling */
|
||||
fecp->tdar = 0x01000000; /* Descriptor polling active */
|
||||
|
||||
#ifdef CFG_UNIFY_CACHE
|
||||
icache_invalid();
|
||||
#endif
|
||||
j = 0;
|
||||
while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
|
||||
(j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("TX timeout\n");
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, j,
|
||||
info->txbd[info->txIdx].cbd_sc,
|
||||
(info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2);
|
||||
#endif
|
||||
|
||||
/* return only status bits */
|
||||
rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
|
||||
info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
int fec_recv(struct eth_device *dev)
|
||||
{
|
||||
struct fec_info_s *info = dev->priv;
|
||||
volatile fec_t *fecp = (fec_t *) (info->iobase);
|
||||
int length;
|
||||
|
||||
for (;;) {
|
||||
#ifdef CFG_UNIFY_CACHE
|
||||
icache_invalid();
|
||||
#endif
|
||||
/* section 16.9.23.2 */
|
||||
if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
|
||||
length = -1;
|
||||
break; /* nothing received - leave for() loop */
|
||||
}
|
||||
|
||||
length = info->rxbd[info->rxIdx].cbd_datlen;
|
||||
|
||||
if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) {
|
||||
printf("%s[%d] err: %x\n",
|
||||
__FUNCTION__, __LINE__,
|
||||
info->rxbd[info->rxIdx].cbd_sc);
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] err: %x\n",
|
||||
__FUNCTION__, __LINE__,
|
||||
info->rxbd[info->rxIdx].cbd_sc);
|
||||
#endif
|
||||
} else {
|
||||
|
||||
length -= 4;
|
||||
/* Pass the packet up to the protocol layers. */
|
||||
NetReceive(NetRxPackets[info->rxIdx], length);
|
||||
|
||||
fecp->eir |= FEC_EIR_RXF;
|
||||
}
|
||||
|
||||
/* Give the buffer back to the FEC. */
|
||||
info->rxbd[info->rxIdx].cbd_datlen = 0;
|
||||
|
||||
/* wrap around buffer index when necessary */
|
||||
if (info->rxIdx == LAST_PKTBUFSRX) {
|
||||
info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E;
|
||||
info->rxIdx = 0;
|
||||
} else {
|
||||
info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
|
||||
info->rxIdx++;
|
||||
}
|
||||
|
||||
/* Try to fill Buffer Descriptors */
|
||||
fecp->rdar = 0x01000000; /* Descriptor polling active */
|
||||
}
|
||||
|
||||
return length;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
void dbgFecRegs(struct eth_device *dev)
|
||||
{
|
||||
struct fec_info_s *info = dev->priv;
|
||||
volatile fec_t *fecp = (fec_t *) (info->iobase);
|
||||
|
||||
printf("=====\n");
|
||||
printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
|
||||
printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
|
||||
printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar);
|
||||
printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar);
|
||||
printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
|
||||
printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
|
||||
printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
|
||||
printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
|
||||
printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
|
||||
printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
|
||||
printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
|
||||
printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
|
||||
printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
|
||||
printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
|
||||
printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
|
||||
printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
|
||||
printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
|
||||
printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
|
||||
printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr);
|
||||
printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr);
|
||||
printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr);
|
||||
printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr);
|
||||
printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr);
|
||||
|
||||
printf("\n");
|
||||
printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop,
|
||||
fecp->rmon_t_drop);
|
||||
printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets,
|
||||
fecp->rmon_t_packets);
|
||||
printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt,
|
||||
fecp->rmon_t_bc_pkt);
|
||||
printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt,
|
||||
fecp->rmon_t_mc_pkt);
|
||||
printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align,
|
||||
fecp->rmon_t_crc_align);
|
||||
printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize,
|
||||
fecp->rmon_t_undersize);
|
||||
printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize,
|
||||
fecp->rmon_t_oversize);
|
||||
printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag,
|
||||
fecp->rmon_t_frag);
|
||||
printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab,
|
||||
fecp->rmon_t_jab);
|
||||
printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col,
|
||||
fecp->rmon_t_col);
|
||||
printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64,
|
||||
fecp->rmon_t_p64);
|
||||
printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127,
|
||||
fecp->rmon_t_p65to127);
|
||||
printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255,
|
||||
fecp->rmon_t_p128to255);
|
||||
printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511,
|
||||
fecp->rmon_t_p256to511);
|
||||
printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023,
|
||||
fecp->rmon_t_p512to1023);
|
||||
printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047,
|
||||
fecp->rmon_t_p1024to2047);
|
||||
printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048,
|
||||
fecp->rmon_t_p_gte2048);
|
||||
printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets,
|
||||
fecp->rmon_t_octets);
|
||||
|
||||
printf("\n");
|
||||
printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop,
|
||||
fecp->ieee_t_drop);
|
||||
printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok,
|
||||
fecp->ieee_t_frame_ok);
|
||||
printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col,
|
||||
fecp->ieee_t_1col);
|
||||
printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol,
|
||||
fecp->ieee_t_mcol);
|
||||
printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def,
|
||||
fecp->ieee_t_def);
|
||||
printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol,
|
||||
fecp->ieee_t_lcol);
|
||||
printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol,
|
||||
fecp->ieee_t_excol);
|
||||
printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr,
|
||||
fecp->ieee_t_macerr);
|
||||
printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr,
|
||||
fecp->ieee_t_cserr);
|
||||
printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe,
|
||||
fecp->ieee_t_sqe);
|
||||
printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc,
|
||||
fecp->ieee_t_fdxfc);
|
||||
printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok,
|
||||
fecp->ieee_t_octets_ok);
|
||||
|
||||
printf("\n");
|
||||
printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop,
|
||||
fecp->rmon_r_drop);
|
||||
printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets,
|
||||
fecp->rmon_r_packets);
|
||||
printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt,
|
||||
fecp->rmon_r_bc_pkt);
|
||||
printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt,
|
||||
fecp->rmon_r_mc_pkt);
|
||||
printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align,
|
||||
fecp->rmon_r_crc_align);
|
||||
printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize,
|
||||
fecp->rmon_r_undersize);
|
||||
printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize,
|
||||
fecp->rmon_r_oversize);
|
||||
printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag,
|
||||
fecp->rmon_r_frag);
|
||||
printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab,
|
||||
fecp->rmon_r_jab);
|
||||
printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64,
|
||||
fecp->rmon_r_p64);
|
||||
printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127,
|
||||
fecp->rmon_r_p65to127);
|
||||
printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255,
|
||||
fecp->rmon_r_p128to255);
|
||||
printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511,
|
||||
fecp->rmon_r_p256to511);
|
||||
printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023,
|
||||
fecp->rmon_r_p512to1023);
|
||||
printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047,
|
||||
fecp->rmon_r_p1024to2047);
|
||||
printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048,
|
||||
fecp->rmon_r_p_gte2048);
|
||||
printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets,
|
||||
fecp->rmon_r_octets);
|
||||
|
||||
printf("\n");
|
||||
printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop,
|
||||
fecp->ieee_r_drop);
|
||||
printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok,
|
||||
fecp->ieee_r_frame_ok);
|
||||
printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc,
|
||||
fecp->ieee_r_crc);
|
||||
printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align,
|
||||
fecp->ieee_r_align);
|
||||
printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr,
|
||||
fecp->ieee_r_macerr);
|
||||
printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc,
|
||||
fecp->ieee_r_fdxfc);
|
||||
printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok,
|
||||
fecp->ieee_r_octets_ok);
|
||||
|
||||
printf("\n\n\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
int fec_init(struct eth_device *dev, bd_t * bd)
|
||||
{
|
||||
struct fec_info_s *info = dev->priv;
|
||||
volatile fec_t *fecp = (fec_t *) (info->iobase);
|
||||
int i;
|
||||
u8 *ea = NULL;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
fec_reset(dev);
|
||||
|
||||
#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
|
||||
defined (CFG_DISCOVER_PHY)
|
||||
|
||||
mii_init();
|
||||
|
||||
setFecDuplexSpeed(fecp, bd, info->dup_spd);
|
||||
#else
|
||||
#ifndef CFG_DISCOVER_PHY
|
||||
setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
|
||||
#endif /* ifndef CFG_DISCOVER_PHY */
|
||||
#endif /* CONFIG_CMD_MII || CONFIG_MII */
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set station address */
|
||||
if ((u32) fecp == CFG_FEC0_IOBASE) {
|
||||
#ifdef CFG_FEC1_IOBASE
|
||||
volatile fec_t *fecp1 = (fec_t *) (CFG_FEC1_IOBASE);
|
||||
ea = &bd->bi_enet1addr[0];
|
||||
fecp1->palr =
|
||||
(ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
|
||||
fecp1->paur = (ea[4] << 24) | (ea[5] << 16);
|
||||
#endif
|
||||
ea = &bd->bi_enetaddr[0];
|
||||
fecp->palr =
|
||||
(ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
|
||||
fecp->paur = (ea[4] << 24) | (ea[5] << 16);
|
||||
} else {
|
||||
#ifdef CFG_FEC0_IOBASE
|
||||
volatile fec_t *fecp0 = (fec_t *) (CFG_FEC0_IOBASE);
|
||||
ea = &bd->bi_enetaddr[0];
|
||||
fecp0->palr =
|
||||
(ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
|
||||
fecp0->paur = (ea[4] << 24) | (ea[5] << 16);
|
||||
#endif
|
||||
#ifdef CFG_FEC1_IOBASE
|
||||
ea = &bd->bi_enet1addr[0];
|
||||
fecp->palr =
|
||||
(ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
|
||||
fecp->paur = (ea[4] << 24) | (ea[5] << 16);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Clear unicast address hash table */
|
||||
fecp->iaur = 0;
|
||||
fecp->ialr = 0;
|
||||
|
||||
/* Clear multicast address hash table */
|
||||
fecp->gaur = 0;
|
||||
fecp->galr = 0;
|
||||
|
||||
/* Set maximum receive buffer size. */
|
||||
fecp->emrbr = PKT_MAXBLR_SIZE;
|
||||
|
||||
/*
|
||||
* Setup Buffers and Buffer Desriptors
|
||||
*/
|
||||
info->rxIdx = 0;
|
||||
info->txIdx = 0;
|
||||
|
||||
/*
|
||||
* Setup Receiver Buffer Descriptors (13.14.24.18)
|
||||
* Settings:
|
||||
* Empty, Wrap
|
||||
*/
|
||||
for (i = 0; i < PKTBUFSRX; i++) {
|
||||
info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
|
||||
info->rxbd[i].cbd_datlen = 0; /* Reset */
|
||||
info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
|
||||
}
|
||||
info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
|
||||
|
||||
/*
|
||||
* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
|
||||
* Settings:
|
||||
* Last, Tx CRC
|
||||
*/
|
||||
for (i = 0; i < TX_BUF_CNT; i++) {
|
||||
info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
|
||||
info->txbd[i].cbd_datlen = 0; /* Reset */
|
||||
info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
|
||||
}
|
||||
info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
|
||||
|
||||
/* Set receive and transmit descriptor base */
|
||||
fecp->erdsr = (unsigned int)(&info->rxbd[0]);
|
||||
fecp->etdsr = (unsigned int)(&info->txbd[0]);
|
||||
|
||||
/* Now enable the transmit and receive processing */
|
||||
fecp->ecr |= FEC_ECR_ETHER_EN;
|
||||
|
||||
/* And last, try to fill Rx Buffer Descriptors */
|
||||
fecp->rdar = 0x01000000; /* Descriptor polling active */
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void fec_reset(struct eth_device *dev)
|
||||
{
|
||||
struct fec_info_s *info = dev->priv;
|
||||
volatile fec_t *fecp = (fec_t *) (info->iobase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
void fec_halt(struct eth_device *dev)
|
||||
{
|
||||
struct fec_info_s *info = dev->priv;
|
||||
|
||||
fec_reset(dev);
|
||||
|
||||
fecpin_setclear(dev, 0);
|
||||
|
||||
info->rxIdx = info->txIdx = 0;
|
||||
memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t));
|
||||
memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
|
||||
memset(info->txbuf, 0, DBUF_LENGTH);
|
||||
}
|
||||
|
||||
int mcffec_initialize(bd_t * bis)
|
||||
{
|
||||
struct eth_device *dev;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) {
|
||||
|
||||
dev =
|
||||
(struct eth_device *)memalign(CFG_CACHELINE_SIZE,
|
||||
sizeof *dev);
|
||||
if (dev == NULL)
|
||||
hang();
|
||||
|
||||
memset(dev, 0, sizeof(*dev));
|
||||
|
||||
sprintf(dev->name, "FEC%d", fec_info[i].index);
|
||||
|
||||
dev->priv = &fec_info[i];
|
||||
dev->init = fec_init;
|
||||
dev->halt = fec_halt;
|
||||
dev->send = fec_send;
|
||||
dev->recv = fec_recv;
|
||||
|
||||
/* setup Receive and Transmit buffer descriptor */
|
||||
fec_info[i].rxbd =
|
||||
(cbd_t *) memalign(CFG_CACHELINE_SIZE,
|
||||
(PKTBUFSRX * sizeof(cbd_t)));
|
||||
fec_info[i].txbd =
|
||||
(cbd_t *) memalign(CFG_CACHELINE_SIZE,
|
||||
(TX_BUF_CNT * sizeof(cbd_t)));
|
||||
fec_info[i].txbuf =
|
||||
(char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH);
|
||||
#ifdef ET_DEBUG
|
||||
printf("rxbd %x txbd %x\n",
|
||||
(int)fec_info[i].rxbd, (int)fec_info[i].txbd);
|
||||
#endif
|
||||
|
||||
fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32);
|
||||
|
||||
eth_register(dev);
|
||||
|
||||
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
|
||||
miiphy_register(dev->name,
|
||||
mcffec_miiphy_read, mcffec_miiphy_write);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* default speed */
|
||||
bis->bi_ethspeed = 10;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
#endif /* CONFIG_MCFFEC */
|
||||
45
drivers/serial/Makefile
Normal file
45
drivers/serial/Makefile
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB := $(obj)libserial.a
|
||||
|
||||
COBJS := mcfuart.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
all: $(LIB)
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
131
drivers/serial/mcfuart.c
Normal file
131
drivers/serial/mcfuart.c
Normal file
|
|
@ -0,0 +1,131 @@
|
|||
/*
|
||||
* (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew, Tsi-Chung.Liew@freescale.com.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Minimal serial functions needed to use one of the uart ports
|
||||
* as serial console interface.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/immap.h>
|
||||
#include <asm/uart.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifdef CONFIG_MCFUART
|
||||
extern void uart_port_conf(void);
|
||||
|
||||
int serial_init(void)
|
||||
{
|
||||
volatile uart_t *uart;
|
||||
u32 counter;
|
||||
|
||||
uart = (volatile uart_t *)(CFG_UART_BASE);
|
||||
|
||||
uart_port_conf();
|
||||
|
||||
/* write to SICR: SIM2 = uart mode,dcd does not affect rx */
|
||||
uart->ucr = UART_UCR_RESET_RX;
|
||||
uart->ucr = UART_UCR_RESET_TX;
|
||||
uart->ucr = UART_UCR_RESET_ERROR;
|
||||
uart->ucr = UART_UCR_RESET_MR;
|
||||
__asm__("nop");
|
||||
|
||||
uart->uimr = 0;
|
||||
|
||||
/* write to CSR: RX/TX baud rate from timers */
|
||||
uart->ucsr = (UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK);
|
||||
|
||||
uart->umr = (UART_UMR_BC_8 | UART_UMR_PM_NONE);
|
||||
uart->umr = UART_UMR_SB_STOP_BITS_1;
|
||||
|
||||
/* Setting up BaudRate */
|
||||
counter = (u32) (gd->bus_clk / (gd->baudrate));
|
||||
counter >>= 5;
|
||||
|
||||
/* write to CTUR: divide counter upper byte */
|
||||
uart->ubg1 = (u8) ((counter & 0xff00) >> 8);
|
||||
/* write to CTLR: divide counter lower byte */
|
||||
uart->ubg2 = (u8) (counter & 0x00ff);
|
||||
|
||||
uart->ucr = (UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
void serial_putc(const char c)
|
||||
{
|
||||
volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE);
|
||||
|
||||
if (c == '\n')
|
||||
serial_putc('\r');
|
||||
|
||||
/* Wait for last character to go. */
|
||||
while (!(uart->usr & UART_USR_TXRDY)) ;
|
||||
|
||||
uart->utb = c;
|
||||
}
|
||||
|
||||
void serial_puts(const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
serial_putc(*s++);
|
||||
}
|
||||
}
|
||||
|
||||
int serial_getc(void)
|
||||
{
|
||||
volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE);
|
||||
|
||||
/* Wait for a character to arrive. */
|
||||
while (!(uart->usr & UART_USR_RXRDY)) ;
|
||||
return uart->urb;
|
||||
}
|
||||
|
||||
int serial_tstc(void)
|
||||
{
|
||||
volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE);
|
||||
|
||||
return (uart->usr & UART_USR_RXRDY);
|
||||
}
|
||||
|
||||
void serial_setbrg(void)
|
||||
{
|
||||
volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE);
|
||||
u32 counter;
|
||||
|
||||
counter = ((gd->bus_clk / gd->baudrate)) >> 5;
|
||||
counter++;
|
||||
|
||||
/* write to CTUR: divide counter upper byte */
|
||||
uart->ubg1 = ((counter & 0xff00) >> 8);
|
||||
/* write to CTLR: divide counter lower byte */
|
||||
uart->ubg2 = (counter & 0x00ff);
|
||||
|
||||
uart->ucr = UART_UCR_RESET_RX;
|
||||
uart->ucr = UART_UCR_RESET_TX;
|
||||
|
||||
uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED;
|
||||
}
|
||||
#endif /* CONFIG_MCFUART */
|
||||
|
|
@ -15,4 +15,43 @@ extern int test_and_set_bit(int nr, volatile void *addr);
|
|||
extern int test_and_clear_bit(int nr, volatile void *addr);
|
||||
extern int test_and_change_bit(int nr, volatile void *addr);
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
/*
|
||||
* ffs: find first bit set. This is defined the same way as
|
||||
* the libc and compiler builtin ffs routines, therefore
|
||||
* differs in spirit from the above ffz (man ffs).
|
||||
*/
|
||||
extern __inline__ int ffs(int x)
|
||||
{
|
||||
int r = 1;
|
||||
|
||||
if (!x)
|
||||
return 0;
|
||||
if (!(x & 0xffff)) {
|
||||
x >>= 16;
|
||||
r += 16;
|
||||
}
|
||||
if (!(x & 0xff)) {
|
||||
x >>= 8;
|
||||
r += 8;
|
||||
}
|
||||
if (!(x & 0xf)) {
|
||||
x >>= 4;
|
||||
r += 4;
|
||||
}
|
||||
if (!(x & 3)) {
|
||||
x >>= 2;
|
||||
r += 2;
|
||||
}
|
||||
if (!(x & 1)) {
|
||||
x >>= 1;
|
||||
r += 1;
|
||||
}
|
||||
return r;
|
||||
}
|
||||
#define __ffs(x) (ffs(x) - 1)
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* _M68K_BITOPS_H */
|
||||
|
|
|
|||
|
|
@ -1,7 +1,107 @@
|
|||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _M68K_BYTEORDER_H
|
||||
#define _M68K_BYTEORDER_H
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
#ifdef __GNUC__
|
||||
#define __sw16(x) \
|
||||
((__u16)( \
|
||||
(((__u16)(x) & (__u16)0x00ffU) << 8) | \
|
||||
(((__u16)(x) & (__u16)0xff00U) >> 8) ))
|
||||
#define __sw32(x) \
|
||||
((__u32)( \
|
||||
(((__u32)(x)) << 24) | \
|
||||
(((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \
|
||||
(((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \
|
||||
(((__u32)(x)) >> 24) ))
|
||||
|
||||
extern __inline__ unsigned ld_le16(const volatile unsigned short *addr)
|
||||
{
|
||||
unsigned result = *addr;
|
||||
return __sw16(result);
|
||||
}
|
||||
|
||||
extern __inline__ void st_le16(volatile unsigned short *addr,
|
||||
const unsigned val)
|
||||
{
|
||||
*addr = __sw16(val);
|
||||
}
|
||||
|
||||
extern __inline__ unsigned ld_le32(const volatile unsigned *addr)
|
||||
{
|
||||
unsigned result = *addr;
|
||||
return __sw32(result);
|
||||
}
|
||||
|
||||
extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
|
||||
{
|
||||
*addr = __sw32(val);
|
||||
}
|
||||
|
||||
#if 0
|
||||
/* alas, egcs sounds like it has a bug in this code that doesn't use the
|
||||
inline asm correctly, and can cause file corruption. Until I hear that
|
||||
it's fixed, I can live without the extra speed. I hope. */
|
||||
#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90)
|
||||
#if 0
|
||||
# define __arch_swab16(x) ld_le16(&x)
|
||||
# define __arch_swab32(x) ld_le32(&x)
|
||||
#else
|
||||
static __inline__ __attribute__ ((const))
|
||||
__u16 ___arch__swab16(__u16 value)
|
||||
{
|
||||
return __sw16(value);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__ ((const))
|
||||
__u32 ___arch__swab32(__u32 value)
|
||||
{
|
||||
return __sw32(value);
|
||||
}
|
||||
|
||||
#define __arch__swab32(x) ___arch__swab32(x)
|
||||
#define __arch__swab16(x) ___arch__swab16(x)
|
||||
#endif /* 0 */
|
||||
|
||||
#endif
|
||||
|
||||
/* The same, but returns converted value from the location pointer by addr. */
|
||||
#define __arch__swab16p(addr) ld_le16(addr)
|
||||
#define __arch__swab32p(addr) ld_le32(addr)
|
||||
|
||||
/* The same, but do the conversion in situ, ie. put the value back to addr. */
|
||||
#define __arch__swab16s(addr) st_le16(addr,*addr)
|
||||
#define __arch__swab32s(addr) st_le32(addr,*addr)
|
||||
#endif
|
||||
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
|
||||
#define __BYTEORDER_HAS_U64__
|
||||
#endif
|
||||
#include <linux/byteorder/big_endian.h>
|
||||
|
||||
#endif /* _M68K_BYTEORDER_H */
|
||||
#endif /* _M68K_BYTEORDER_H */
|
||||
|
|
|
|||
138
include/asm-m68k/errno.h
Normal file
138
include/asm-m68k/errno.h
Normal file
|
|
@ -0,0 +1,138 @@
|
|||
#ifndef _PPC_ERRNO_H
|
||||
#define _PPC_ERRNO_H
|
||||
|
||||
#define EPERM 1 /* Operation not permitted */
|
||||
#define ENOENT 2 /* No such file or directory */
|
||||
#define ESRCH 3 /* No such process */
|
||||
#define EINTR 4 /* Interrupted system call */
|
||||
#define EIO 5 /* I/O error */
|
||||
#define ENXIO 6 /* No such device or address */
|
||||
#define E2BIG 7 /* Arg list too long */
|
||||
#define ENOEXEC 8 /* Exec format error */
|
||||
#define EBADF 9 /* Bad file number */
|
||||
#define ECHILD 10 /* No child processes */
|
||||
#define EAGAIN 11 /* Try again */
|
||||
#define ENOMEM 12 /* Out of memory */
|
||||
#define EACCES 13 /* Permission denied */
|
||||
#define EFAULT 14 /* Bad address */
|
||||
#define ENOTBLK 15 /* Block device required */
|
||||
#define EBUSY 16 /* Device or resource busy */
|
||||
#define EEXIST 17 /* File exists */
|
||||
#define EXDEV 18 /* Cross-device link */
|
||||
#define ENODEV 19 /* No such device */
|
||||
#define ENOTDIR 20 /* Not a directory */
|
||||
#define EISDIR 21 /* Is a directory */
|
||||
#define EINVAL 22 /* Invalid argument */
|
||||
#define ENFILE 23 /* File table overflow */
|
||||
#define EMFILE 24 /* Too many open files */
|
||||
#define ENOTTY 25 /* Not a typewriter */
|
||||
#define ETXTBSY 26 /* Text file busy */
|
||||
#define EFBIG 27 /* File too large */
|
||||
#define ENOSPC 28 /* No space left on device */
|
||||
#define ESPIPE 29 /* Illegal seek */
|
||||
#define EROFS 30 /* Read-only file system */
|
||||
#define EMLINK 31 /* Too many links */
|
||||
#define EPIPE 32 /* Broken pipe */
|
||||
#define EDOM 33 /* Math argument out of domain of func */
|
||||
#define ERANGE 34 /* Math result not representable */
|
||||
#define EDEADLK 35 /* Resource deadlock would occur */
|
||||
#define ENAMETOOLONG 36 /* File name too long */
|
||||
#define ENOLCK 37 /* No record locks available */
|
||||
#define ENOSYS 38 /* Function not implemented */
|
||||
#define ENOTEMPTY 39 /* Directory not empty */
|
||||
#define ELOOP 40 /* Too many symbolic links encountered */
|
||||
#define EWOULDBLOCK EAGAIN /* Operation would block */
|
||||
#define ENOMSG 42 /* No message of desired type */
|
||||
#define EIDRM 43 /* Identifier removed */
|
||||
#define ECHRNG 44 /* Channel number out of range */
|
||||
#define EL2NSYNC 45 /* Level 2 not synchronized */
|
||||
#define EL3HLT 46 /* Level 3 halted */
|
||||
#define EL3RST 47 /* Level 3 reset */
|
||||
#define ELNRNG 48 /* Link number out of range */
|
||||
#define EUNATCH 49 /* Protocol driver not attached */
|
||||
#define ENOCSI 50 /* No CSI structure available */
|
||||
#define EL2HLT 51 /* Level 2 halted */
|
||||
#define EBADE 52 /* Invalid exchange */
|
||||
#define EBADR 53 /* Invalid request descriptor */
|
||||
#define EXFULL 54 /* Exchange full */
|
||||
#define ENOANO 55 /* No anode */
|
||||
#define EBADRQC 56 /* Invalid request code */
|
||||
#define EBADSLT 57 /* Invalid slot */
|
||||
#define EDEADLOCK 58 /* File locking deadlock error */
|
||||
#define EBFONT 59 /* Bad font file format */
|
||||
#define ENOSTR 60 /* Device not a stream */
|
||||
#define ENODATA 61 /* No data available */
|
||||
#define ETIME 62 /* Timer expired */
|
||||
#define ENOSR 63 /* Out of streams resources */
|
||||
#define ENONET 64 /* Machine is not on the network */
|
||||
#define ENOPKG 65 /* Package not installed */
|
||||
#define EREMOTE 66 /* Object is remote */
|
||||
#define ENOLINK 67 /* Link has been severed */
|
||||
#define EADV 68 /* Advertise error */
|
||||
#define ESRMNT 69 /* Srmount error */
|
||||
#define ECOMM 70 /* Communication error on send */
|
||||
#define EPROTO 71 /* Protocol error */
|
||||
#define EMULTIHOP 72 /* Multihop attempted */
|
||||
#define EDOTDOT 73 /* RFS specific error */
|
||||
#define EBADMSG 74 /* Not a data message */
|
||||
#define EOVERFLOW 75 /* Value too large for defined data type */
|
||||
#define ENOTUNIQ 76 /* Name not unique on network */
|
||||
#define EBADFD 77 /* File descriptor in bad state */
|
||||
#define EREMCHG 78 /* Remote address changed */
|
||||
#define ELIBACC 79 /* Can not access a needed shared library */
|
||||
#define ELIBBAD 80 /* Accessing a corrupted shared library */
|
||||
#define ELIBSCN 81 /* .lib section in a.out corrupted */
|
||||
#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
|
||||
#define ELIBEXEC 83 /* Cannot exec a shared library directly */
|
||||
#define EILSEQ 84 /* Illegal byte sequence */
|
||||
#define ERESTART 85 /* Interrupted system call should be restarted */
|
||||
#define ESTRPIPE 86 /* Streams pipe error */
|
||||
#define EUSERS 87 /* Too many users */
|
||||
#define ENOTSOCK 88 /* Socket operation on non-socket */
|
||||
#define EDESTADDRREQ 89 /* Destination address required */
|
||||
#define EMSGSIZE 90 /* Message too long */
|
||||
#define EPROTOTYPE 91 /* Protocol wrong type for socket */
|
||||
#define ENOPROTOOPT 92 /* Protocol not available */
|
||||
#define EPROTONOSUPPORT 93 /* Protocol not supported */
|
||||
#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
|
||||
#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
|
||||
#define EPFNOSUPPORT 96 /* Protocol family not supported */
|
||||
#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
|
||||
#define EADDRINUSE 98 /* Address already in use */
|
||||
#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
|
||||
#define ENETDOWN 100 /* Network is down */
|
||||
#define ENETUNREACH 101 /* Network is unreachable */
|
||||
#define ENETRESET 102 /* Network dropped connection because of reset */
|
||||
#define ECONNABORTED 103 /* Software caused connection abort */
|
||||
#define ECONNRESET 104 /* Connection reset by peer */
|
||||
#define ENOBUFS 105 /* No buffer space available */
|
||||
#define EISCONN 106 /* Transport endpoint is already connected */
|
||||
#define ENOTCONN 107 /* Transport endpoint is not connected */
|
||||
#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
|
||||
#define ETOOMANYREFS 109 /* Too many references: cannot splice */
|
||||
#define ETIMEDOUT 110 /* Connection timed out */
|
||||
#define ECONNREFUSED 111 /* Connection refused */
|
||||
#define EHOSTDOWN 112 /* Host is down */
|
||||
#define EHOSTUNREACH 113 /* No route to host */
|
||||
#define EALREADY 114 /* Operation already in progress */
|
||||
#define EINPROGRESS 115 /* Operation now in progress */
|
||||
#define ESTALE 116 /* Stale NFS file handle */
|
||||
#define EUCLEAN 117 /* Structure needs cleaning */
|
||||
#define ENOTNAM 118 /* Not a XENIX named type file */
|
||||
#define ENAVAIL 119 /* No XENIX semaphores available */
|
||||
#define EISNAM 120 /* Is a named type file */
|
||||
#define EREMOTEIO 121 /* Remote I/O error */
|
||||
#define EDQUOT 122 /* Quota exceeded */
|
||||
|
||||
#define ENOMEDIUM 123 /* No medium found */
|
||||
#define EMEDIUMTYPE 124 /* Wrong medium type */
|
||||
|
||||
/* Should never be seen by user programs */
|
||||
#define ERESTARTSYS 512
|
||||
#define ERESTARTNOINTR 513
|
||||
#define ERESTARTNOHAND 514 /* restart if no handler.. */
|
||||
#define ENOIOCTLCMD 515 /* No ioctl command */
|
||||
|
||||
#define _LAST_ERRNO 515
|
||||
|
||||
#endif
|
||||
|
|
@ -5,6 +5,10 @@
|
|||
* MPC8xx Communication Processor Module.
|
||||
* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
|
||||
*
|
||||
* Add FEC Structure and definitions
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
|
|
@ -30,9 +34,9 @@
|
|||
/* Buffer descriptors used FEC.
|
||||
*/
|
||||
typedef struct cpm_buf_desc {
|
||||
ushort cbd_sc; /* Status and Control */
|
||||
ushort cbd_datlen; /* Data length in buffer */
|
||||
uint cbd_bufaddr; /* Buffer address in host memory */
|
||||
ushort cbd_sc; /* Status and Control */
|
||||
ushort cbd_datlen; /* Data length in buffer */
|
||||
uint cbd_bufaddr; /* Buffer address in host memory */
|
||||
} cbd_t;
|
||||
|
||||
#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
|
||||
|
|
@ -53,28 +57,36 @@ typedef struct cpm_buf_desc {
|
|||
/* Buffer descriptor control/status used by Ethernet receive.
|
||||
*/
|
||||
#define BD_ENET_RX_EMPTY ((ushort)0x8000)
|
||||
#define BD_ENET_RX_RO1 ((ushort)0x4000)
|
||||
#define BD_ENET_RX_WRAP ((ushort)0x2000)
|
||||
#define BD_ENET_RX_INTR ((ushort)0x1000)
|
||||
#define BD_ENET_RX_RO2 BD_ENET_RX_INTR
|
||||
#define BD_ENET_RX_LAST ((ushort)0x0800)
|
||||
#define BD_ENET_RX_FIRST ((ushort)0x0400)
|
||||
#define BD_ENET_RX_MISS ((ushort)0x0100)
|
||||
#define BD_ENET_RX_BC ((ushort)0x0080)
|
||||
#define BD_ENET_RX_MC ((ushort)0x0040)
|
||||
#define BD_ENET_RX_LG ((ushort)0x0020)
|
||||
#define BD_ENET_RX_NO ((ushort)0x0010)
|
||||
#define BD_ENET_RX_SH ((ushort)0x0008)
|
||||
#define BD_ENET_RX_CR ((ushort)0x0004)
|
||||
#define BD_ENET_RX_OV ((ushort)0x0002)
|
||||
#define BD_ENET_RX_CL ((ushort)0x0001)
|
||||
#define BD_ENET_RX_TR BD_ENET_RX_CL
|
||||
#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
|
||||
|
||||
/* Buffer descriptor control/status used by Ethernet transmit.
|
||||
*/
|
||||
#define BD_ENET_TX_READY ((ushort)0x8000)
|
||||
#define BD_ENET_TX_PAD ((ushort)0x4000)
|
||||
#define BD_ENET_TX_TO1 BD_ENET_TX_PAD
|
||||
#define BD_ENET_TX_WRAP ((ushort)0x2000)
|
||||
#define BD_ENET_TX_INTR ((ushort)0x1000)
|
||||
#define BD_ENET_TX_TO2 BD_ENET_TX_INTR_
|
||||
#define BD_ENET_TX_LAST ((ushort)0x0800)
|
||||
#define BD_ENET_TX_TC ((ushort)0x0400)
|
||||
#define BD_ENET_TX_DEF ((ushort)0x0200)
|
||||
#define BD_ENET_TX_ABC BD_ENET_TX_DEF
|
||||
#define BD_ENET_TX_HB ((ushort)0x0100)
|
||||
#define BD_ENET_TX_LC ((ushort)0x0080)
|
||||
#define BD_ENET_TX_RL ((ushort)0x0040)
|
||||
|
|
@ -83,4 +95,261 @@ typedef struct cpm_buf_desc {
|
|||
#define BD_ENET_TX_CSL ((ushort)0x0001)
|
||||
#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
|
||||
|
||||
#endif /* fec_h */
|
||||
#ifdef CONFIG_MCFFEC
|
||||
/*********************************************************************
|
||||
*
|
||||
* Fast Ethernet Controller (FEC)
|
||||
*
|
||||
*********************************************************************/
|
||||
/* FEC private information */
|
||||
struct fec_info_s {
|
||||
int index;
|
||||
u32 iobase;
|
||||
u32 pinmux;
|
||||
u32 miibase;
|
||||
int phy_addr;
|
||||
int dup_spd;
|
||||
char *phy_name;
|
||||
int phyname_init;
|
||||
cbd_t *rxbd; /* Rx BD */
|
||||
cbd_t *txbd; /* Tx BD */
|
||||
uint rxIdx;
|
||||
uint txIdx;
|
||||
char *txbuf;
|
||||
int initialized;
|
||||
};
|
||||
|
||||
/* Register read/write struct */
|
||||
typedef struct fec {
|
||||
#ifdef CONFIG_M5272
|
||||
u32 ecr; /* 0x00 */
|
||||
u32 eir; /* 0x04 */
|
||||
u32 eimr; /* 0x08 */
|
||||
u32 ivsr; /* 0x0C */
|
||||
u32 rdar; /* 0x10 */
|
||||
u32 tdar; /* 0x14 */
|
||||
u8 resv1[0x28]; /* 0x18 */
|
||||
u32 mmfr; /* 0x40 */
|
||||
u32 mscr; /* 0x44 */
|
||||
u8 resv2[0x44]; /* 0x48 */
|
||||
u32 frbr; /* 0x8C */
|
||||
u32 frsr; /* 0x90 */
|
||||
u8 resv3[0x10]; /* 0x94 */
|
||||
u32 tfwr; /* 0xA4 */
|
||||
u32 res4; /* 0xA8 */
|
||||
u32 tfsr; /* 0xAC */
|
||||
u8 resv4[0x50]; /* 0xB0 */
|
||||
u32 opd; /* 0x100 - dummy */
|
||||
u32 rcr; /* 0x104 */
|
||||
u32 mibc; /* 0x108 */
|
||||
u8 resv5[0x38]; /* 0x10C */
|
||||
u32 tcr; /* 0x144 */
|
||||
u8 resv6[0x270]; /* 0x148 */
|
||||
u32 iaur; /* 0x3B8 - dummy */
|
||||
u32 ialr; /* 0x3BC - dummy */
|
||||
u32 palr; /* 0x3C0 */
|
||||
u32 paur; /* 0x3C4 */
|
||||
u32 gaur; /* 0x3C8 */
|
||||
u32 galr; /* 0x3CC */
|
||||
u32 erdsr; /* 0x3D0 */
|
||||
u32 etdsr; /* 0x3D4 */
|
||||
u32 emrbr; /* 0x3D8 */
|
||||
u8 resv12[0x74]; /* 0x18C */
|
||||
#else
|
||||
u8 resv0[0x4];
|
||||
u32 eir;
|
||||
u32 eimr;
|
||||
u8 resv1[0x4];
|
||||
u32 rdar;
|
||||
u32 tdar;
|
||||
u8 resv2[0xC];
|
||||
u32 ecr;
|
||||
u8 resv3[0x18];
|
||||
u32 mmfr;
|
||||
u32 mscr;
|
||||
u8 resv4[0x1C];
|
||||
u32 mibc;
|
||||
u8 resv5[0x1C];
|
||||
u32 rcr;
|
||||
u8 resv6[0x3C];
|
||||
u32 tcr;
|
||||
u8 resv7[0x1C];
|
||||
u32 palr;
|
||||
u32 paur;
|
||||
u32 opd;
|
||||
u8 resv8[0x28];
|
||||
u32 iaur;
|
||||
u32 ialr;
|
||||
u32 gaur;
|
||||
u32 galr;
|
||||
u8 resv9[0x1C];
|
||||
u32 tfwr;
|
||||
u8 resv10[0x4];
|
||||
u32 frbr;
|
||||
u32 frsr;
|
||||
u8 resv11[0x2C];
|
||||
u32 erdsr;
|
||||
u32 etdsr;
|
||||
u32 emrbr;
|
||||
u8 resv12[0x74];
|
||||
#endif
|
||||
|
||||
u32 rmon_t_drop;
|
||||
u32 rmon_t_packets;
|
||||
u32 rmon_t_bc_pkt;
|
||||
u32 rmon_t_mc_pkt;
|
||||
u32 rmon_t_crc_align;
|
||||
u32 rmon_t_undersize;
|
||||
u32 rmon_t_oversize;
|
||||
u32 rmon_t_frag;
|
||||
u32 rmon_t_jab;
|
||||
u32 rmon_t_col;
|
||||
u32 rmon_t_p64;
|
||||
u32 rmon_t_p65to127;
|
||||
u32 rmon_t_p128to255;
|
||||
u32 rmon_t_p256to511;
|
||||
u32 rmon_t_p512to1023;
|
||||
u32 rmon_t_p1024to2047;
|
||||
u32 rmon_t_p_gte2048;
|
||||
u32 rmon_t_octets;
|
||||
|
||||
u32 ieee_t_drop;
|
||||
u32 ieee_t_frame_ok;
|
||||
u32 ieee_t_1col;
|
||||
u32 ieee_t_mcol;
|
||||
u32 ieee_t_def;
|
||||
u32 ieee_t_lcol;
|
||||
u32 ieee_t_excol;
|
||||
u32 ieee_t_macerr;
|
||||
u32 ieee_t_cserr;
|
||||
u32 ieee_t_sqe;
|
||||
u32 ieee_t_fdxfc;
|
||||
u32 ieee_t_octets_ok;
|
||||
u8 resv13[0x8];
|
||||
|
||||
u32 rmon_r_drop;
|
||||
u32 rmon_r_packets;
|
||||
u32 rmon_r_bc_pkt;
|
||||
u32 rmon_r_mc_pkt;
|
||||
u32 rmon_r_crc_align;
|
||||
u32 rmon_r_undersize;
|
||||
u32 rmon_r_oversize;
|
||||
u32 rmon_r_frag;
|
||||
u32 rmon_r_jab;
|
||||
u32 rmon_r_resvd_0;
|
||||
u32 rmon_r_p64;
|
||||
u32 rmon_r_p65to127;
|
||||
u32 rmon_r_p128to255;
|
||||
u32 rmon_r_p256to511;
|
||||
u32 rmon_r_p512to1023;
|
||||
u32 rmon_r_p1024to2047;
|
||||
u32 rmon_r_p_gte2048;
|
||||
u32 rmon_r_octets;
|
||||
|
||||
u32 ieee_r_drop;
|
||||
u32 ieee_r_frame_ok;
|
||||
u32 ieee_r_crc;
|
||||
u32 ieee_r_align;
|
||||
u32 ieee_r_macerr;
|
||||
u32 ieee_r_fdxfc;
|
||||
u32 ieee_r_octets_ok;
|
||||
} fec_t;
|
||||
|
||||
/*********************************************************************
|
||||
* Fast Ethernet Controller (FEC)
|
||||
*********************************************************************/
|
||||
/* Bit definitions and macros for FEC_EIR */
|
||||
#define FEC_EIR_CLEAR_ALL (0xFFF80000)
|
||||
#define FEC_EIR_HBERR (0x80000000)
|
||||
#define FEC_EIR_BABR (0x40000000)
|
||||
#define FEC_EIR_BABT (0x20000000)
|
||||
#define FEC_EIR_GRA (0x10000000)
|
||||
#define FEC_EIR_TXF (0x08000000)
|
||||
#define FEC_EIR_TXB (0x04000000)
|
||||
#define FEC_EIR_RXF (0x02000000)
|
||||
#define FEC_EIR_RXB (0x01000000)
|
||||
#define FEC_EIR_MII (0x00800000)
|
||||
#define FEC_EIR_EBERR (0x00400000)
|
||||
#define FEC_EIR_LC (0x00200000)
|
||||
#define FEC_EIR_RL (0x00100000)
|
||||
#define FEC_EIR_UN (0x00080000)
|
||||
|
||||
/* Bit definitions and macros for FEC_RDAR */
|
||||
#define FEC_RDAR_R_DES_ACTIVE (0x01000000)
|
||||
|
||||
/* Bit definitions and macros for FEC_TDAR */
|
||||
#define FEC_TDAR_X_DES_ACTIVE (0x01000000)
|
||||
|
||||
/* Bit definitions and macros for FEC_ECR */
|
||||
#define FEC_ECR_ETHER_EN (0x00000002)
|
||||
#define FEC_ECR_RESET (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for FEC_MMFR */
|
||||
#define FEC_MMFR_DATA(x) (((x)&0xFFFF))
|
||||
#define FEC_MMFR_ST(x) (((x)&0x03)<<30)
|
||||
#define FEC_MMFR_ST_01 (0x40000000)
|
||||
#define FEC_MMFR_OP_RD (0x20000000)
|
||||
#define FEC_MMFR_OP_WR (0x10000000)
|
||||
#define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
|
||||
#define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
|
||||
#define FEC_MMFR_TA(x) (((x)&0x03)<<16)
|
||||
#define FEC_MMFR_TA_10 (0x00020000)
|
||||
|
||||
/* Bit definitions and macros for FEC_MSCR */
|
||||
#define FEC_MSCR_DIS_PREAMBLE (0x00000080)
|
||||
#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
|
||||
|
||||
/* Bit definitions and macros for FEC_MIBC */
|
||||
#define FEC_MIBC_MIB_DISABLE (0x80000000)
|
||||
#define FEC_MIBC_MIB_IDLE (0x40000000)
|
||||
|
||||
/* Bit definitions and macros for FEC_RCR */
|
||||
#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
|
||||
#define FEC_RCR_FCE (0x00000020)
|
||||
#define FEC_RCR_BC_REJ (0x00000010)
|
||||
#define FEC_RCR_PROM (0x00000008)
|
||||
#define FEC_RCR_MII_MODE (0x00000004)
|
||||
#define FEC_RCR_DRT (0x00000002)
|
||||
#define FEC_RCR_LOOP (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for FEC_TCR */
|
||||
#define FEC_TCR_RFC_PAUSE (0x00000010)
|
||||
#define FEC_TCR_TFC_PAUSE (0x00000008)
|
||||
#define FEC_TCR_FDEN (0x00000004)
|
||||
#define FEC_TCR_HBC (0x00000002)
|
||||
#define FEC_TCR_GTS (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for FEC_PAUR */
|
||||
#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
|
||||
#define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
|
||||
|
||||
/* Bit definitions and macros for FEC_OPD */
|
||||
#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
|
||||
#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
|
||||
|
||||
/* Bit definitions and macros for FEC_TFWR */
|
||||
#define FEC_TFWR_X_WMRK(x) ((x)&0x03)
|
||||
#define FEC_TFWR_X_WMRK_64 (0x01)
|
||||
#define FEC_TFWR_X_WMRK_128 (0x02)
|
||||
#define FEC_TFWR_X_WMRK_192 (0x03)
|
||||
|
||||
/* Bit definitions and macros for FEC_FRBR */
|
||||
#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
|
||||
|
||||
/* Bit definitions and macros for FEC_FRSR */
|
||||
#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
|
||||
|
||||
/* Bit definitions and macros for FEC_ERDSR */
|
||||
#define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
|
||||
|
||||
/* Bit definitions and macros for FEC_ETDSR */
|
||||
#define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
|
||||
|
||||
/* Bit definitions and macros for FEC_EMRBR */
|
||||
#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4)
|
||||
|
||||
#define FEC_RESET_DELAY 100
|
||||
#define FEC_RX_TOUT 100
|
||||
|
||||
#endif /* CONFIG_MCFFEC */
|
||||
#endif /* fec_h */
|
||||
|
|
|
|||
86
include/asm-m68k/fsl_i2c.h
Normal file
86
include/asm-m68k/fsl_i2c.h
Normal file
|
|
@ -0,0 +1,86 @@
|
|||
/*
|
||||
* Freescale I2C Controller
|
||||
*
|
||||
* Copyright 2006 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
|
||||
* Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
|
||||
* and Jeff Brown.
|
||||
* Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
|
||||
*
|
||||
* This software may be used and distributed according to the
|
||||
* terms of the GNU Public License, Version 2, incorporated
|
||||
* herein by reference.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* Version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _ASM_FSL_I2C_H_
|
||||
#define _ASM_FSL_I2C_H_
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
typedef struct fsl_i2c {
|
||||
|
||||
u8 adr; /* I2C slave address */
|
||||
u8 res0[3];
|
||||
#define I2C_ADR 0xFE
|
||||
#define I2C_ADR_SHIFT 1
|
||||
#define I2C_ADR_RES ~(I2C_ADR)
|
||||
|
||||
u8 fdr; /* I2C frequency divider register */
|
||||
u8 res1[3];
|
||||
#define IC2_FDR 0x3F
|
||||
#define IC2_FDR_SHIFT 0
|
||||
#define IC2_FDR_RES ~(IC2_FDR)
|
||||
|
||||
u8 cr; /* I2C control redister */
|
||||
u8 res2[3];
|
||||
#define I2C_CR_MEN 0x80
|
||||
#define I2C_CR_MIEN 0x40
|
||||
#define I2C_CR_MSTA 0x20
|
||||
#define I2C_CR_MTX 0x10
|
||||
#define I2C_CR_TXAK 0x08
|
||||
#define I2C_CR_RSTA 0x04
|
||||
#define I2C_CR_BCST 0x01
|
||||
|
||||
u8 sr; /* I2C status register */
|
||||
u8 res3[3];
|
||||
#define I2C_SR_MCF 0x80
|
||||
#define I2C_SR_MAAS 0x40
|
||||
#define I2C_SR_MBB 0x20
|
||||
#define I2C_SR_MAL 0x10
|
||||
#define I2C_SR_BCSTM 0x08
|
||||
#define I2C_SR_SRW 0x04
|
||||
#define I2C_SR_MIF 0x02
|
||||
#define I2C_SR_RXAK 0x01
|
||||
|
||||
u8 dr; /* I2C data register */
|
||||
u8 res4[3];
|
||||
#define I2C_DR 0xFF
|
||||
#define I2C_DR_SHIFT 0
|
||||
#define I2C_DR_RES ~(I2C_DR)
|
||||
|
||||
u8 dfsrr; /* I2C digital filter sampling rate register */
|
||||
u8 res5[3];
|
||||
#define I2C_DFSRR 0x3F
|
||||
#define I2C_DFSRR_SHIFT 0
|
||||
#define I2C_DFSRR_RES ~(I2C_DR)
|
||||
|
||||
/* Fill out the reserved block */
|
||||
u8 res6[0xE8];
|
||||
} fsl_i2c_t;
|
||||
|
||||
#endif /* _ASM_I2C_H_ */
|
||||
|
|
@ -39,6 +39,14 @@ typedef struct global_data {
|
|||
unsigned long baudrate;
|
||||
unsigned long cpu_clk; /* CPU clock in Hz! */
|
||||
unsigned long bus_clk;
|
||||
#ifdef CONFIG_PCI
|
||||
unsigned long pci_clk;
|
||||
#endif
|
||||
#ifdef CONFIG_EXTRA_CLOCK
|
||||
unsigned long inp_clk;
|
||||
unsigned long vco_clk;
|
||||
unsigned long flb_clk;
|
||||
#endif
|
||||
unsigned long ram_size; /* RAM size */
|
||||
unsigned long reloc_off; /* Relocation Offset */
|
||||
unsigned long reset_status; /* reset status register at boot */
|
||||
|
|
|
|||
242
include/asm-m68k/immap.h
Normal file
242
include/asm-m68k/immap.h
Normal file
|
|
@ -0,0 +1,242 @@
|
|||
/*
|
||||
* ColdFire Internal Memory Map and Defines
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __IMMAP_H
|
||||
#define __IMMAP_H
|
||||
|
||||
#ifdef CONFIG_M5235
|
||||
#include <asm/immap_5235.h>
|
||||
#include <asm/m5235.h>
|
||||
|
||||
#define CFG_FEC0_IOBASE (MMAP_FEC)
|
||||
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
|
||||
|
||||
/* Timer */
|
||||
#ifdef CONFIG_MCFTMR
|
||||
#define CFG_UDELAY_BASE (MMAP_DTMR0)
|
||||
#define CFG_TMR_BASE (MMAP_DTMR3)
|
||||
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
|
||||
#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
|
||||
#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
|
||||
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
|
||||
#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
|
||||
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MCFPIT
|
||||
#define CFG_UDELAY_BASE (MMAP_PIT0)
|
||||
#define CFG_PIT_BASE (MMAP_PIT1)
|
||||
#define CFG_PIT_PRESCALE (6)
|
||||
#endif
|
||||
|
||||
#define CFG_INTR_BASE (MMAP_INTC0)
|
||||
#define CFG_NUM_IRQS (128)
|
||||
#endif /* CONFIG_M5235 */
|
||||
|
||||
#ifdef CONFIG_M5249
|
||||
#include <asm/immap_5249.h>
|
||||
#include <asm/m5249.h>
|
||||
|
||||
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
|
||||
|
||||
#define CFG_INTR_BASE (MMAP_INTC)
|
||||
#define CFG_NUM_IRQS (64)
|
||||
|
||||
/* Timer */
|
||||
#ifdef CONFIG_MCFTMR
|
||||
#define CFG_UDELAY_BASE (MMAP_DTMR0)
|
||||
#define CFG_TMR_BASE (MMAP_DTMR1)
|
||||
#define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
|
||||
#define CFG_TMRINTR_NO (31)
|
||||
#define CFG_TMRINTR_MASK (0x00000400)
|
||||
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
|
||||
#define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
|
||||
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
|
||||
#endif
|
||||
#endif /* CONFIG_M5249 */
|
||||
|
||||
#ifdef CONFIG_M5253
|
||||
#include <asm/immap_5253.h>
|
||||
#include <asm/m5249.h>
|
||||
#include <asm/m5253.h>
|
||||
|
||||
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
|
||||
|
||||
#define CFG_INTR_BASE (MMAP_INTC)
|
||||
#define CFG_NUM_IRQS (64)
|
||||
|
||||
/* Timer */
|
||||
#ifdef CONFIG_MCFTMR
|
||||
#define CFG_UDELAY_BASE (MMAP_DTMR0)
|
||||
#define CFG_TMR_BASE (MMAP_DTMR1)
|
||||
#define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
|
||||
#define CFG_TMRINTR_NO (27)
|
||||
#define CFG_TMRINTR_MASK (0x00000400)
|
||||
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
|
||||
#define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
|
||||
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
|
||||
#endif
|
||||
#endif /* CONFIG_M5253 */
|
||||
|
||||
#ifdef CONFIG_M5271
|
||||
#include <asm/immap_5271.h>
|
||||
#include <asm/m5271.h>
|
||||
|
||||
#define CFG_FEC0_IOBASE (MMAP_FEC)
|
||||
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
|
||||
|
||||
/* Timer */
|
||||
#ifdef CONFIG_MCFTMR
|
||||
#define CFG_UDELAY_BASE (MMAP_DTMR0)
|
||||
#define CFG_TMR_BASE (MMAP_DTMR3)
|
||||
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
|
||||
#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
|
||||
#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
|
||||
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
|
||||
#define CFG_TMRINTR_PRI (0) /* Level must include inorder to work */
|
||||
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
|
||||
#endif
|
||||
|
||||
#define CFG_INTR_BASE (MMAP_INTC0)
|
||||
#define CFG_NUM_IRQS (128)
|
||||
#endif /* CONFIG_M5271 */
|
||||
|
||||
#ifdef CONFIG_M5272
|
||||
#include <asm/immap_5272.h>
|
||||
#include <asm/m5272.h>
|
||||
|
||||
#define CFG_FEC0_IOBASE (MMAP_FEC)
|
||||
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
|
||||
|
||||
#define CFG_INTR_BASE (MMAP_INTC)
|
||||
#define CFG_NUM_IRQS (64)
|
||||
|
||||
/* Timer */
|
||||
#ifdef CONFIG_MCFTMR
|
||||
#define CFG_UDELAY_BASE (MMAP_TMR0)
|
||||
#define CFG_TMR_BASE (MMAP_TMR3)
|
||||
#define CFG_TMRPND_REG (((volatile intctrl_t *)(CFG_INTR_BASE))->int_isr)
|
||||
#define CFG_TMRINTR_NO (INT_TMR3)
|
||||
#define CFG_TMRINTR_MASK (INT_ISR_INT24)
|
||||
#define CFG_TMRINTR_PEND (0)
|
||||
#define CFG_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
|
||||
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
|
||||
#endif
|
||||
#endif /* CONFIG_M5272 */
|
||||
|
||||
#ifdef CONFIG_M5282
|
||||
#include <asm/immap_5282.h>
|
||||
#include <asm/m5282.h>
|
||||
|
||||
#define CFG_FEC0_IOBASE (MMAP_FEC)
|
||||
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
|
||||
|
||||
#define CFG_INTR_BASE (MMAP_INTC0)
|
||||
#define CFG_NUM_IRQS (128)
|
||||
|
||||
/* Timer */
|
||||
#ifdef CONFIG_MCFTMR
|
||||
#define CFG_UDELAY_BASE (MMAP_DTMR0)
|
||||
#define CFG_TMR_BASE (MMAP_DTMR3)
|
||||
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
|
||||
#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
|
||||
#define CFG_TMRINTR_MASK (1 << INT0_LO_DTMR3)
|
||||
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
|
||||
#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
|
||||
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
|
||||
#endif
|
||||
#endif /* CONFIG_M5282 */
|
||||
|
||||
#ifdef CONFIG_M5329
|
||||
#include <asm/immap_5329.h>
|
||||
#include <asm/m5329.h>
|
||||
|
||||
#define CFG_FEC0_IOBASE (MMAP_FEC)
|
||||
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
|
||||
#define CFG_MCFRTC_BASE (MMAP_RTC)
|
||||
|
||||
/* Timer */
|
||||
#ifdef CONFIG_MCFTMR
|
||||
#define CFG_UDELAY_BASE (MMAP_DTMR0)
|
||||
#define CFG_TMR_BASE (MMAP_DTMR1)
|
||||
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
|
||||
#define CFG_TMRINTR_NO (INT0_HI_DTMR1)
|
||||
#define CFG_TMRINTR_MASK (INTC_IPRH_INT33)
|
||||
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
|
||||
#define CFG_TMRINTR_PRI (6)
|
||||
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MCFPIT
|
||||
#define CFG_UDELAY_BASE (MMAP_PIT0)
|
||||
#define CFG_PIT_BASE (MMAP_PIT1)
|
||||
#define CFG_PIT_PRESCALE (6)
|
||||
#endif
|
||||
|
||||
#define CFG_INTR_BASE (MMAP_INTC0)
|
||||
#define CFG_NUM_IRQS (128)
|
||||
#endif /* CONFIG_M5329 */
|
||||
|
||||
#ifdef CONFIG_M54455
|
||||
#include <asm/immap_5445x.h>
|
||||
#include <asm/m5445x.h>
|
||||
|
||||
#define CFG_FEC0_IOBASE (MMAP_FEC0)
|
||||
#define CFG_FEC1_IOBASE (MMAP_FEC1)
|
||||
|
||||
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
|
||||
|
||||
#define CFG_MCFRTC_BASE (MMAP_RTC)
|
||||
|
||||
/* Timer */
|
||||
#ifdef CONFIG_MCFTMR
|
||||
#define CFG_UDELAY_BASE (MMAP_DTMR0)
|
||||
#define CFG_TMR_BASE (MMAP_DTMR1)
|
||||
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
|
||||
#define CFG_TMRINTR_NO (INT0_HI_DTMR1)
|
||||
#define CFG_TMRINTR_MASK (INTC_IPRH_INT33)
|
||||
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
|
||||
#define CFG_TMRINTR_PRI (6)
|
||||
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MCFPIT
|
||||
#define CFG_UDELAY_BASE (MMAP_PIT0)
|
||||
#define CFG_PIT_BASE (MMAP_PIT1)
|
||||
#define CFG_PIT_PRESCALE (6)
|
||||
#endif
|
||||
|
||||
#define CFG_INTR_BASE (MMAP_INTC0)
|
||||
#define CFG_NUM_IRQS (128)
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define CFG_PCI_BAR0 CFG_SDRAM_BASE
|
||||
#define CFG_PCI_BAR4 CFG_SDRAM_BASE
|
||||
#define CFG_PCI_TBATR0 (CFG_SDRAM_BASE)
|
||||
#define CFG_PCI_TBATR4 (CFG_SDRAM_BASE)
|
||||
#endif
|
||||
#endif /* CONFIG_M54455 */
|
||||
|
||||
#endif /* __IMMAP_H */
|
||||
378
include/asm-m68k/immap_5235.h
Normal file
378
include/asm-m68k/immap_5235.h
Normal file
|
|
@ -0,0 +1,378 @@
|
|||
/*
|
||||
* MCF5329 Internal Memory Map
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __IMMAP_5235__
|
||||
#define __IMMAP_5235__
|
||||
|
||||
#define MMAP_SCM (CFG_MBAR + 0x00000000)
|
||||
#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
|
||||
#define MMAP_FBCS (CFG_MBAR + 0x00000080)
|
||||
#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
|
||||
#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
|
||||
#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
|
||||
#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
|
||||
#define MMAP_UART0 (CFG_MBAR + 0x00000200)
|
||||
#define MMAP_UART1 (CFG_MBAR + 0x00000240)
|
||||
#define MMAP_UART2 (CFG_MBAR + 0x00000280)
|
||||
#define MMAP_I2C (CFG_MBAR + 0x00000300)
|
||||
#define MMAP_QSPI (CFG_MBAR + 0x00000340)
|
||||
#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
|
||||
#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
|
||||
#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
|
||||
#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
|
||||
#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
|
||||
#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
|
||||
#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
|
||||
#define MMAP_FEC (CFG_MBAR + 0x00001000)
|
||||
#define MMAP_FECFIFO (CFG_MBAR + 0x00001400)
|
||||
#define MMAP_GPIO (CFG_MBAR + 0x00100000)
|
||||
#define MMAP_CCM (CFG_MBAR + 0x00110000)
|
||||
#define MMAP_PLL (CFG_MBAR + 0x00120000)
|
||||
#define MMAP_EPORT (CFG_MBAR + 0x00130000)
|
||||
#define MMAP_WDOG (CFG_MBAR + 0x00140000)
|
||||
#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
|
||||
#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
|
||||
#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
|
||||
#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
|
||||
#define MMAP_MDHA (CFG_MBAR + 0x00190000)
|
||||
#define MMAP_RNG (CFG_MBAR + 0x001A0000)
|
||||
#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
|
||||
#define MMAP_CAN1 (CFG_MBAR + 0x001C0000)
|
||||
#define MMAP_ETPU (CFG_MBAR + 0x001D0000)
|
||||
#define MMAP_CAN2 (CFG_MBAR + 0x001F0000)
|
||||
|
||||
/* System Control Module register */
|
||||
typedef struct scm_ctrl {
|
||||
u32 ipsbar; /* 0x00 - MBAR */
|
||||
u32 res1; /* 0x04 */
|
||||
u32 rambar; /* 0x08 - RAMBAR */
|
||||
u32 res2; /* 0x0C */
|
||||
u8 crsr; /* 0x10 Core Reset Status Register */
|
||||
u8 cwcr; /* 0x11 Core Watchdog Control Register */
|
||||
u8 lpicr; /* 0x12 Low-Power Interrupt Control Register */
|
||||
u8 cwsr; /* 0x13 Core Watchdog Service Register */
|
||||
u32 dmareqc; /* 0x14 */
|
||||
u32 res3; /* 0x18 */
|
||||
u32 mpark; /* 0x1C */
|
||||
u8 mpr; /* 0x20 */
|
||||
u8 res4[3]; /* 0x21 - 0x23 */
|
||||
u8 pacr0; /* 0x24 */
|
||||
u8 pacr1; /* 0x25 */
|
||||
u8 pacr2; /* 0x26 */
|
||||
u8 pacr3; /* 0x27 */
|
||||
u8 pacr4; /* 0x28 */
|
||||
u32 res5; /* 0x29 */
|
||||
u8 pacr5; /* 0x2a */
|
||||
u8 pacr6; /* 0x2b */
|
||||
u8 pacr7; /* 0x2c */
|
||||
u32 res6; /* 0x2d */
|
||||
u8 pacr8; /* 0x2e */
|
||||
u32 res7; /* 0x2f */
|
||||
u8 gpacr; /* 0x30 */
|
||||
u8 res8[3]; /* 0x31 - 0x33 */
|
||||
} scm_t;
|
||||
|
||||
/* SDRAM controller registers */
|
||||
typedef struct sdram_ctrl {
|
||||
u16 dcr; /* 0x00 Control register */
|
||||
u16 res1[3]; /* 0x02 - 0x07 */
|
||||
u32 dacr0; /* 0x08 address and control register 0 */
|
||||
u32 dmr0; /* 0x0C mask register block 0 */
|
||||
u32 dacr1; /* 0x10 address and control register 1 */
|
||||
u32 dmr1; /* 0x14 mask register block 1 */
|
||||
} sdram_t;
|
||||
|
||||
/* Flexbus module Chip select registers */
|
||||
typedef struct fbcs_ctrl {
|
||||
u16 csar0; /* 0x00 Chip-Select Address Register 0 */
|
||||
u16 res0;
|
||||
u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
|
||||
u16 res1; /* 0x08 */
|
||||
u16 cscr0; /* 0x0A Chip-Select Control Register 0 */
|
||||
|
||||
u16 csar1; /* 0x0C Chip-Select Address Register 1 */
|
||||
u16 res2;
|
||||
u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
|
||||
u16 res3; /* 0x14 */
|
||||
u16 cscr1; /* 0x16 Chip-Select Control Register 1 */
|
||||
|
||||
u16 csar2; /* 0x18 Chip-Select Address Register 2 */
|
||||
u16 res4;
|
||||
u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
|
||||
u16 res5; /* 0x20 */
|
||||
u16 cscr2; /* 0x22 Chip-Select Control Register 2 */
|
||||
|
||||
u16 csar3; /* 0x24 Chip-Select Address Register 3 */
|
||||
u16 res6;
|
||||
u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
|
||||
u16 res7; /* 0x2C */
|
||||
u16 cscr3; /* 0x2E Chip-Select Control Register 3 */
|
||||
|
||||
u16 csar4; /* 0x30 Chip-Select Address Register 4 */
|
||||
u16 res8;
|
||||
u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
|
||||
u16 res9; /* 0x38 */
|
||||
u16 cscr4; /* 0x3A Chip-Select Control Register 4 */
|
||||
|
||||
u16 csar5; /* 0x3C Chip-Select Address Register 5 */
|
||||
u16 res10;
|
||||
u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
|
||||
u16 res11; /* 0x44 */
|
||||
u16 cscr5; /* 0x46 Chip-Select Control Register 5 */
|
||||
|
||||
u16 csar6; /* 0x48 Chip-Select Address Register 5 */
|
||||
u16 res12;
|
||||
u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */
|
||||
u16 res13; /* 0x50 */
|
||||
u16 cscr6; /* 0x52 Chip-Select Control Register 5 */
|
||||
|
||||
u16 csar7; /* 0x54 Chip-Select Address Register 5 */
|
||||
u16 res14;
|
||||
u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */
|
||||
u16 res15; /* 0x5C */
|
||||
u16 cscr7; /* 0x5E Chip-Select Control Register 5 */
|
||||
} fbcs_t;
|
||||
|
||||
/* QSPI module registers */
|
||||
typedef struct qspi_ctrl {
|
||||
u16 qmr; /* Mode register */
|
||||
u16 res1;
|
||||
u16 qdlyr; /* Delay register */
|
||||
u16 res2;
|
||||
u16 qwr; /* Wrap register */
|
||||
u16 res3;
|
||||
u16 qir; /* Interrupt register */
|
||||
u16 res4;
|
||||
u16 qar; /* Address register */
|
||||
u16 res5;
|
||||
u16 qdr; /* Data register */
|
||||
u16 res6;
|
||||
} qspi_t;
|
||||
|
||||
/* Interrupt module registers */
|
||||
typedef struct int0_ctrl {
|
||||
/* Interrupt Controller 0 */
|
||||
u32 iprh0; /* 0x00 Pending Register High */
|
||||
u32 iprl0; /* 0x04 Pending Register Low */
|
||||
u32 imrh0; /* 0x08 Mask Register High */
|
||||
u32 imrl0; /* 0x0C Mask Register Low */
|
||||
u32 frch0; /* 0x10 Force Register High */
|
||||
u32 frcl0; /* 0x14 Force Register Low */
|
||||
u8 irlr; /* 0x18 */
|
||||
u8 iacklpr; /* 0x19 */
|
||||
u16 res1[19]; /* 0x1a - 0x3c */
|
||||
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
|
||||
u32 res3[24]; /* 0x80 - 0xDF */
|
||||
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
|
||||
u8 res4[3]; /* 0xE1 - 0xE3 */
|
||||
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
|
||||
u8 res5[3]; /* 0xE5 - 0xE7 */
|
||||
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
|
||||
u8 res6[3]; /* 0xE9 - 0xEB */
|
||||
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
|
||||
u8 res7[3]; /* 0xED - 0xEF */
|
||||
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
|
||||
u8 res8[3]; /* 0xF1 - 0xF3 */
|
||||
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
|
||||
u8 res9[3]; /* 0xF5 - 0xF7 */
|
||||
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
|
||||
u8 resa[3]; /* 0xF9 - 0xFB */
|
||||
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
|
||||
u8 resb[3]; /* 0xFD - 0xFF */
|
||||
} int0_t;
|
||||
|
||||
typedef struct int1_ctrl {
|
||||
/* Interrupt Controller 1 */
|
||||
u32 iprh1; /* 0x00 Pending Register High */
|
||||
u32 iprl1; /* 0x04 Pending Register Low */
|
||||
u32 imrh1; /* 0x08 Mask Register High */
|
||||
u32 imrl1; /* 0x0C Mask Register Low */
|
||||
u32 frch1; /* 0x10 Force Register High */
|
||||
u32 frcl1; /* 0x14 Force Register Low */
|
||||
u8 irlr; /* 0x18 */
|
||||
u8 iacklpr; /* 0x19 */
|
||||
u16 res1[19]; /* 0x1a - 0x3c */
|
||||
u8 icr1[64]; /* 0x40 - 0x7F */
|
||||
u32 res4[24]; /* 0x80 - 0xDF */
|
||||
u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
|
||||
u8 res5[3]; /* 0xE1 - 0xE3 */
|
||||
u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
|
||||
u8 res6[3]; /* 0xE5 - 0xE7 */
|
||||
u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
|
||||
u8 res7[3]; /* 0xE9 - 0xEB */
|
||||
u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
|
||||
u8 res8[3]; /* 0xED - 0xEF */
|
||||
u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
|
||||
u8 res9[3]; /* 0xF1 - 0xF3 */
|
||||
u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
|
||||
u8 resa[3]; /* 0xF5 - 0xF7 */
|
||||
u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
|
||||
u8 resb[3]; /* 0xF9 - 0xFB */
|
||||
u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
|
||||
u8 resc[3]; /* 0xFD - 0xFF */
|
||||
} int1_t;
|
||||
|
||||
typedef struct intgack_ctrl1 {
|
||||
/* Global IACK Registers */
|
||||
u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */
|
||||
u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
|
||||
} intgack_t;
|
||||
|
||||
/* GPIO port registers */
|
||||
typedef struct gpio_ctrl {
|
||||
/* Port Output Data Registers */
|
||||
u8 podr_addr; /* 0x00 */
|
||||
u8 podr_datah; /* 0x01 */
|
||||
u8 podr_datal; /* 0x02 */
|
||||
u8 podr_busctl; /* 0x03 */
|
||||
u8 podr_bs; /* 0x04 */
|
||||
u8 podr_cs; /* 0x05 */
|
||||
u8 podr_sdram; /* 0x06 */
|
||||
u8 podr_feci2c; /* 0x07 */
|
||||
u8 podr_uarth; /* 0x08 */
|
||||
u8 podr_uartl; /* 0x09 */
|
||||
u8 podr_qspi; /* 0x0A */
|
||||
u8 podr_timer; /* 0x0B */
|
||||
u8 podr_etpu; /* 0x0C */
|
||||
u8 res1[3]; /* 0x0D - 0x0F */
|
||||
|
||||
/* Port Data Direction Registers */
|
||||
u8 pddr_addr; /* 0x10 */
|
||||
u8 pddr_datah; /* 0x11 */
|
||||
u8 pddr_datal; /* 0x12 */
|
||||
u8 pddr_busctl; /* 0x13 */
|
||||
u8 pddr_bs; /* 0x14 */
|
||||
u8 pddr_cs; /* 0x15 */
|
||||
u8 pddr_sdram; /* 0x16 */
|
||||
u8 pddr_feci2c; /* 0x17 */
|
||||
u8 pddr_uarth; /* 0x18 */
|
||||
u8 pddr_uartl; /* 0x19 */
|
||||
u8 pddr_qspi; /* 0x1A */
|
||||
u8 pddr_timer; /* 0x1B */
|
||||
u8 pddr_etpu; /* 0x1C */
|
||||
u8 res2[3]; /* 0x1D - 0x1F */
|
||||
|
||||
/* Port Data Direction Registers */
|
||||
u8 ppdsdr_addr; /* 0x20 */
|
||||
u8 ppdsdr_datah; /* 0x21 */
|
||||
u8 ppdsdr_datal; /* 0x22 */
|
||||
u8 ppdsdr_busctl; /* 0x23 */
|
||||
u8 ppdsdr_bs; /* 0x24 */
|
||||
u8 ppdsdr_cs; /* 0x25 */
|
||||
u8 ppdsdr_sdram; /* 0x26 */
|
||||
u8 ppdsdr_feci2c; /* 0x27 */
|
||||
u8 ppdsdr_uarth; /* 0x28 */
|
||||
u8 ppdsdr_uartl; /* 0x29 */
|
||||
u8 ppdsdr_qspi; /* 0x2A */
|
||||
u8 ppdsdr_timer; /* 0x2B */
|
||||
u8 ppdsdr_etpu; /* 0x2C */
|
||||
u8 res3[3]; /* 0x2D - 0x2F */
|
||||
|
||||
/* Port Clear Output Data Registers */
|
||||
u8 pclrr_addr; /* 0x30 */
|
||||
u8 pclrr_datah; /* 0x31 */
|
||||
u8 pclrr_datal; /* 0x32 */
|
||||
u8 pclrr_busctl; /* 0x33 */
|
||||
u8 pclrr_bs; /* 0x34 */
|
||||
u8 pclrr_cs; /* 0x35 */
|
||||
u8 pclrr_sdram; /* 0x36 */
|
||||
u8 pclrr_feci2c; /* 0x37 */
|
||||
u8 pclrr_uarth; /* 0x38 */
|
||||
u8 pclrr_uartl; /* 0x39 */
|
||||
u8 pclrr_qspi; /* 0x3A */
|
||||
u8 pclrr_timer; /* 0x3B */
|
||||
u8 pclrr_etpu; /* 0x3C */
|
||||
u8 res4[3]; /* 0x3D - 0x3F */
|
||||
|
||||
/* Pin Assignment Registers */
|
||||
u8 par_ad; /* 0x40 */
|
||||
u8 res5; /* 0x41 */
|
||||
u16 par_busctl; /* 0x42 */
|
||||
u8 par_bs; /* 0x44 */
|
||||
u8 par_cs; /* 0x45 */
|
||||
u8 par_sdram; /* 0x46 */
|
||||
u8 par_feci2c; /* 0x47 */
|
||||
u16 par_uart; /* 0x48 */
|
||||
u8 par_qspi; /* 0x4A */
|
||||
u8 res6; /* 0x4B */
|
||||
u16 par_timer; /* 0x4C */
|
||||
u8 par_etpu; /* 0x4E */
|
||||
u8 res7; /* 0x4F */
|
||||
|
||||
/* Drive Strength Control Registers */
|
||||
u8 dscr_eim; /* 0x50 */
|
||||
u8 dscr_etpu; /* 0x51 */
|
||||
u8 dscr_feci2c; /* 0x52 */
|
||||
u8 dscr_uart; /* 0x53 */
|
||||
u8 dscr_qspi; /* 0x54 */
|
||||
u8 dscr_timer; /* 0x55 */
|
||||
u16 res8; /* 0x56 */
|
||||
} gpio_t;
|
||||
|
||||
/*Chip configuration module registers */
|
||||
typedef struct ccm_ctrl {
|
||||
u8 rcr; /* 0x01 */
|
||||
u8 rsr; /* 0x02 */
|
||||
u16 res1; /* 0x03 */
|
||||
u16 ccr; /* 0x04 Chip configuration register */
|
||||
u16 lpcr; /* 0x06 Low-power Control register */
|
||||
u16 rcon; /* 0x08 Rreset configuration register */
|
||||
u16 cir; /* 0x0a Chip identification register */
|
||||
} ccm_t;
|
||||
|
||||
/* Clock Module registers */
|
||||
typedef struct pll_ctrl {
|
||||
u32 syncr; /* 0x00 synthesizer control register */
|
||||
u32 synsr; /* 0x04 synthesizer status register */
|
||||
} pll_t;
|
||||
|
||||
/* Watchdog registers */
|
||||
typedef struct wdog_ctrl {
|
||||
u16 cr; /* 0x00 Control register */
|
||||
u16 mr; /* 0x02 Modulus register */
|
||||
u16 cntr; /* 0x04 Count register */
|
||||
u16 sr; /* 0x06 Service register */
|
||||
} wdog_t;
|
||||
|
||||
/* FlexCan module registers */
|
||||
typedef struct can_ctrl {
|
||||
u32 mcr; /* 0x00 Module Configuration register */
|
||||
u32 ctrl; /* 0x04 Control register */
|
||||
u32 timer; /* 0x08 Free Running Timer */
|
||||
u32 res1; /* 0x0C */
|
||||
u32 rxgmask; /* 0x10 Rx Global Mask */
|
||||
u32 rx14mask; /* 0x14 RxBuffer 14 Mask */
|
||||
u32 rx15mask; /* 0x18 RxBuffer 15 Mask */
|
||||
u32 errcnt; /* 0x1C Error Counter Register */
|
||||
u32 errstat; /* 0x20 Error and status Register */
|
||||
u32 res2; /* 0x24 */
|
||||
u32 imask; /* 0x28 Interrupt Mask Register */
|
||||
u32 res3; /* 0x2C */
|
||||
u32 iflag; /* 0x30 Interrupt Flag Register */
|
||||
u32 res4[19]; /* 0x34 - 0x7F */
|
||||
u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */
|
||||
} can_t;
|
||||
|
||||
#endif /* __IMMAP_5235__ */
|
||||
|
|
@ -25,19 +25,11 @@
|
|||
#ifndef __IMMAP_5249__
|
||||
#define __IMMAP_5249__
|
||||
|
||||
/* Timer module registers
|
||||
*/
|
||||
typedef struct timer_ctrl {
|
||||
ushort timer_tmr;
|
||||
ushort res1;
|
||||
ushort timer_trr;
|
||||
ushort res2;
|
||||
ushort timer_tcap;
|
||||
ushort res3;
|
||||
ushort timer_tcn;
|
||||
ushort res4;
|
||||
ushort timer_ter;
|
||||
uchar res5[14];
|
||||
} timer_t;
|
||||
#define MMAP_INTC (CFG_MBAR + 0x00000040)
|
||||
#define MMAP_DTMR0 (CFG_MBAR + 0x00000140)
|
||||
#define MMAP_DTMR1 (CFG_MBAR + 0x00000180)
|
||||
#define MMAP_UART0 (CFG_MBAR + 0x000001C0)
|
||||
#define MMAP_UART1 (CFG_MBAR + 0x00000200)
|
||||
#define MMAP_QSPI (CFG_MBAR + 0x00000400)
|
||||
|
||||
#endif /* __IMMAP_5249__ */
|
||||
#endif /* __IMMAP_5249__ */
|
||||
|
|
|
|||
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Reference in a new issue