mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi
- add Macronix Octal flash (JaimeLiao)
This commit is contained in:
Tom Rini
commit
905e779b9e
6 changed files with 219 additions and 18 deletions
12
cmd/sf.c
12
cmd/sf.c
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@ -294,6 +294,12 @@ static int do_spi_flash_read_write(int argc, char *const argv[])
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return 1;
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}
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if (strncmp(argv[0], "read", 4) != 0 && flash->flash_is_unlocked &&
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!flash->flash_is_unlocked(flash, offset, len)) {
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printf("ERROR: flash area is locked\n");
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return 1;
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}
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buf = map_physmem(addr, len, MAP_WRBACK);
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if (!buf && addr) {
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puts("Failed to map physical memory\n");
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@ -350,6 +356,12 @@ static int do_spi_flash_erase(int argc, char *const argv[])
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return 1;
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}
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if (flash->flash_is_unlocked &&
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!flash->flash_is_unlocked(flash, offset, len)) {
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printf("ERROR: flash area is locked\n");
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return 1;
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}
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ret = spi_flash_erase(flash, offset, size);
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printf("SF: %zu bytes @ %#x Erased: ", (size_t)size, (u32)offset);
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if (ret)
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@ -172,6 +172,11 @@ static int spl_spi_load_image(struct spl_image_info *spl_image,
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spl_image->size,
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(void *)spl_image->load_addr);
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}
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if (IS_ENABLED(CONFIG_SPI_FLASH_SOFT_RESET)) {
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err = spi_nor_remove(flash);
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if (err)
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return err;
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}
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}
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return err;
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@ -97,6 +97,13 @@ config SPI_FLASH_SMART_HWCAPS
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can support a type of operation in a much more refined way compared
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to using flags like SPI_RX_DUAL, SPI_TX_QUAD, etc.
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config SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT
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bool "Command extension type is INVERT for Software Reset on boot"
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default n
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help
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Because of SFDP information can not be get before boot.
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So define command extension type is INVERT when Software Reset on boot only.
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config SPI_FLASH_SOFT_RESET
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bool "Software Reset support for SPI NOR flashes"
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help
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@ -65,6 +65,10 @@ struct sfdp_parameter_header {
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#define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
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#define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */
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#define SFDP_PROFILE1_ID 0xff05 /* xSPI Profile 1.0 Table */
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#define SFDP_SCCR_MAP_ID 0xff87 /*
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* Status, Control and Configuration
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* Register Map.
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*/
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#define SFDP_SIGNATURE 0x50444653U
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#define SFDP_JESD216_MAJOR 1
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@ -174,6 +178,9 @@ struct sfdp_header {
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#define PROFILE1_DWORD5_DUMMY_100MHZ GENMASK(11, 7)
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#define PROFILE1_DUMMY_DEFAULT 20
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/* Status, Control and Configuration Register Map(SCCR) */
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#define SCCR_DWORD22_OCTAL_DTR_EN_VOLATILE BIT(31)
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struct sfdp_bfpt {
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u32 dwords[BFPT_DWORD_MAX];
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};
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@ -1308,13 +1315,13 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
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}
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/*
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* Check if a region of the flash is (completely) locked. See stm_lock() for
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* Check if a region of the flash is (completely) unlocked. See stm_lock() for
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* more info.
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*
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* Returns 1 if entire region is locked, 0 if any portion is unlocked, and
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* Returns 1 if entire region is unlocked, 0 if any portion is locked, and
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* negative on errors.
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*/
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static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
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static int stm_is_unlocked(struct spi_nor *nor, loff_t ofs, uint64_t len)
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{
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int status;
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@ -1322,7 +1329,7 @@ static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
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if (status < 0)
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return status;
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return stm_is_locked_sr(nor, ofs, len, status);
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return stm_is_unlocked_sr(nor, ofs, len, status);
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}
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#endif /* CONFIG_SPI_FLASH_STMICRO */
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@ -1555,16 +1562,16 @@ static int sst26_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
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}
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/*
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* Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
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* and negative on errors.
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* Returns EACCES (positive value) if region is (partially) locked, 0 if region
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* is completely unlocked, and negative on errors.
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*/
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static int sst26_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
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static int sst26_is_unlocked(struct spi_nor *nor, loff_t ofs, uint64_t len)
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{
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/*
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* is_locked function is used for check before reading or erasing flash
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* region, so offset and length might be not 64k allighned, so adjust
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* them to be 64k allighned as sst26_lock_ctl works only with 64k
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* allighned regions.
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* is_unlocked function is used for check before reading or erasing
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* flash region, so offset and length might be not 64k aligned, so
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* adjust them to be 64k aligned as sst26_lock_ctl works only with 64k
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* aligned regions.
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*/
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ofs -= ofs & (SZ_64K - 1);
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len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
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@ -2456,6 +2463,44 @@ out:
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return ret;
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}
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/**
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* spi_nor_parse_sccr() - Parse the Status, Control and Configuration Register
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* Map.
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* @nor: pointer to a 'struct spi_nor'
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* @sccr_header: pointer to the 'struct sfdp_parameter_header' describing
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* the SCCR Map table length and version.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_parse_sccr(struct spi_nor *nor,
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const struct sfdp_parameter_header *sccr_header)
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{
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u32 *table, addr;
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size_t len;
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int ret, i;
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len = sccr_header->length * sizeof(*table);
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table = kmalloc(len, GFP_KERNEL);
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if (!table)
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return -ENOMEM;
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addr = SFDP_PARAM_HEADER_PTP(sccr_header);
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ret = spi_nor_read_sfdp(nor, addr, len, table);
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if (ret)
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goto out;
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/* Fix endianness of the table DWORDs. */
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for (i = 0; i < sccr_header->length; i++)
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table[i] = le32_to_cpu(table[i]);
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if (FIELD_GET(SCCR_DWORD22_OCTAL_DTR_EN_VOLATILE, table[22]))
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nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE;
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out:
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kfree(table);
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return ret;
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}
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/**
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* spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
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* @nor: pointer to a 'struct spi_nor'
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@ -2562,6 +2607,10 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
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err = spi_nor_parse_profile1(nor, param_header, params);
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break;
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case SFDP_SCCR_MAP_ID:
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err = spi_nor_parse_sccr(nor, param_header);
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break;
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default:
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break;
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}
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@ -3526,6 +3575,84 @@ static struct spi_nor_fixups mt35xu512aba_fixups = {
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};
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#endif /* CONFIG_SPI_FLASH_MT35XU */
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#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
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/**
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* spi_nor_macronix_octal_dtr_enable() - Enable octal DTR on Macronix flashes.
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* @nor: pointer to a 'struct spi_nor'
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*
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* Set Macronix max dummy cycles 20 to allow the flash to run at fastest frequency.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor)
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{
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struct spi_mem_op op;
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int ret;
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u8 buf;
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ret = write_enable(nor);
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if (ret)
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return ret;
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buf = SPINOR_REG_MXIC_DC_20;
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op = (struct spi_mem_op)
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
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SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1),
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_OUT(1, &buf, 1));
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ret = spi_mem_exec_op(nor->spi, &op);
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if (ret)
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return ret;
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ret = spi_nor_wait_till_ready(nor);
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if (ret)
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return ret;
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nor->read_dummy = MXIC_MAX_DC;
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ret = write_enable(nor);
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if (ret)
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return ret;
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buf = SPINOR_REG_MXIC_OPI_DTR_EN;
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op = (struct spi_mem_op)
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
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SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_MODE, 1),
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_OUT(1, &buf, 1));
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ret = spi_mem_exec_op(nor->spi, &op);
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if (ret) {
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dev_err(nor->dev, "Failed to enable octal DTR mode\n");
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return ret;
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}
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nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
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return 0;
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}
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static void macronix_octal_default_init(struct spi_nor *nor)
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{
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nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable;
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}
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static void macronix_octal_post_sfdp_fixup(struct spi_nor *nor,
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struct spi_nor_flash_parameter *params)
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{
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/*
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* Adding SNOR_HWCAPS_PP_8_8_8_DTR in hwcaps.mask when
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* SPI_NOR_OCTAL_DTR_READ flag exists.
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*/
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if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR)
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params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
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}
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static struct spi_nor_fixups macronix_octal_fixups = {
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.default_init = macronix_octal_default_init,
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.post_sfdp = macronix_octal_post_sfdp_fixup,
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};
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#endif /* CONFIG_SPI_FLASH_MACRONIX */
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/** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
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* @nor: pointer to a 'struct spi_nor'
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*
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@ -3542,6 +3669,9 @@ static int spi_nor_octal_dtr_enable(struct spi_nor *nor)
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nor->write_proto == SNOR_PROTO_8_8_8_DTR))
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return 0;
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if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE))
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return 0;
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ret = nor->octal_dtr_enable(nor);
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if (ret)
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return ret;
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@ -3619,7 +3749,12 @@ static int spi_nor_soft_reset(struct spi_nor *nor)
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enum spi_nor_cmd_ext ext;
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ext = nor->cmd_ext_type;
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nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
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if (nor->cmd_ext_type == SPI_NOR_EXT_NONE) {
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nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
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#if CONFIG_IS_ENABLED(SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT)
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nor->cmd_ext_type = SPI_NOR_EXT_INVERT;
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#endif /* SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT */
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}
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op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0),
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SPI_MEM_OP_NO_DUMMY,
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@ -3696,6 +3831,10 @@ void spi_nor_set_fixups(struct spi_nor *nor)
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if (!strcmp(nor->info->name, "mt35xu512aba"))
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nor->fixups = &mt35xu512aba_fixups;
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#endif
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#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
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nor->fixups = ¯onix_octal_fixups;
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#endif /* SPI_FLASH_MACRONIX */
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}
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int spi_nor_scan(struct spi_nor *nor)
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@ -3785,7 +3924,7 @@ int spi_nor_scan(struct spi_nor *nor)
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info->flags & SPI_NOR_HAS_LOCK) {
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nor->flash_lock = stm_lock;
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nor->flash_unlock = stm_unlock;
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nor->flash_is_locked = stm_is_locked;
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nor->flash_is_unlocked = stm_is_unlocked;
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}
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#endif
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@ -3797,7 +3936,7 @@ int spi_nor_scan(struct spi_nor *nor)
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if (info->flags & SPI_NOR_HAS_SST26LOCK) {
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nor->flash_lock = sst26_lock;
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nor->flash_unlock = sst26_unlock;
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nor->flash_is_locked = sst26_is_locked;
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nor->flash_is_unlocked = sst26_is_unlocked;
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}
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#endif
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|
|
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|
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@ -198,7 +198,24 @@ const struct flash_info spi_nor_ids[] = {
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{ INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
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{ INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
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{ INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) },
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{ INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
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{ INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
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{ INFO("mx66lm1g45g", 0xc2853b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
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{ INFO("mx25lm51245g", 0xc2853a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
|
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{ INFO("mx25lw51245g", 0xc2863a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
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{ INFO("mx25lm25645g", 0xc28539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
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{ INFO("mx66uw2g345g", 0xc2843c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
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{ INFO("mx66um1g45g", 0xc2803b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
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{ INFO("mx66uw1g45g", 0xc2813b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
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{ INFO("mx25uw51245g", 0xc2813a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
|
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{ INFO("mx25uw51345g", 0xc2843a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
|
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{ INFO("mx25um25645g", 0xc28039, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
|
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{ INFO("mx25uw25645g", 0xc28139, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
|
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{ INFO("mx25um25345g", 0xc28339, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
|
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{ INFO("mx25uw25345g", 0xc28439, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
|
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{ INFO("mx25uw12845g", 0xc28138, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
|
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{ INFO("mx25uw12345g", 0xc28438, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
|
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{ INFO("mx25uw6445g", 0xc28137, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
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{ INFO("mx25uw6345g", 0xc28437, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
|
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#endif
|
||||
|
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#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
|
||||
|
|
@ -397,6 +414,16 @@ const struct flash_info spi_nor_ids[] = {
|
|||
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
||||
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
|
||||
},
|
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{
|
||||
INFO("w25q512nwq", 0xef6020, 0, 64 * 1024, 1024,
|
||||
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
||||
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
|
||||
},
|
||||
{
|
||||
INFO("w25q512nwm", 0xef8020, 0, 64 * 1024, 1024,
|
||||
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
||||
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
|
||||
},
|
||||
{
|
||||
INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048,
|
||||
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
||||
|
|
|
|||
|
|
@ -119,6 +119,16 @@
|
|||
/* Used for Macronix and Winbond flashes. */
|
||||
#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
|
||||
#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
|
||||
#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
|
||||
#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
|
||||
#define SPINOR_OP_RD_CR2 0x71 /* Read configuration register 2 */
|
||||
#define SPINOR_OP_WR_CR2 0x72 /* Write configuration register 2 */
|
||||
#define SPINOR_OP_MXIC_DTR_RD 0xee /* Fast Read opcode in DTR mode */
|
||||
#define SPINOR_REG_MXIC_CR2_MODE 0x00000000 /* For setting octal DTR mode */
|
||||
#define SPINOR_REG_MXIC_OPI_DTR_EN 0x2 /* Enable Octal DTR */
|
||||
#define SPINOR_REG_MXIC_CR2_DC 0x00000300 /* For setting dummy cycles */
|
||||
#define SPINOR_REG_MXIC_DC_20 0x0 /* Setting dummy cycles to 20 */
|
||||
#define MXIC_MAX_DC 20 /* Maximum value of dummy cycles */
|
||||
|
||||
/* Used for Spansion flashes only. */
|
||||
#define SPINOR_OP_BRWR 0x17 /* Bank register write */
|
||||
|
|
@ -280,6 +290,7 @@ enum spi_nor_option_flags {
|
|||
SNOR_F_USE_CLSR = BIT(5),
|
||||
SNOR_F_BROKEN_RESET = BIT(6),
|
||||
SNOR_F_SOFT_RESET = BIT(7),
|
||||
SNOR_F_IO_MODE_EN_VOLATILE = BIT(8),
|
||||
};
|
||||
|
||||
struct spi_nor;
|
||||
|
|
@ -506,8 +517,8 @@ struct spi_flash {
|
|||
* spi-nor will send the erase opcode via write_reg()
|
||||
* @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
|
||||
* @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
|
||||
* @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
|
||||
* completely locked
|
||||
* @flash_is_unlocked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
|
||||
* completely unlocked
|
||||
* @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
|
||||
* @octal_dtr_enable: [FLASH-SPECIFIC] enables SPI NOR octal DTR mode.
|
||||
* @ready: [FLASH-SPECIFIC] check if the flash is ready
|
||||
|
|
@ -556,7 +567,7 @@ struct spi_nor {
|
|||
|
||||
int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
|
||||
int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
|
||||
int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
|
||||
int (*flash_is_unlocked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
|
||||
int (*quad_enable)(struct spi_nor *nor);
|
||||
int (*octal_dtr_enable)(struct spi_nor *nor);
|
||||
int (*ready)(struct spi_nor *nor);
|
||||
|
|
|
|||
Loading…
Reference in a new issue