mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-22 15:42:04 +00:00
x86: Coding Style Cleanup
Perform some basic code cleanups of the x86 files
This commit is contained in:
Graeme Russ
parent
59c6d0ef9a
commit
8ffb2e8f33
4 changed files with 352 additions and 363 deletions
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@ -41,7 +41,8 @@ volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;
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void init_sc520(void)
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{
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/* Set the UARTxCTL register at it's slower,
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/*
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* Set the UARTxCTL register at it's slower,
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* baud clock giving us a 1.8432 MHz reference
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*/
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writeb(0x07, &sc520_mmcr->uart1ctl);
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@ -50,18 +51,23 @@ void init_sc520(void)
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/* first set the timer pin mapping */
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writeb(0x72, &sc520_mmcr->clksel); /* no clock frequency selected, use 1.1892MHz */
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/* enable PCI bus arbitrer */
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writeb(0x02, &sc520_mmcr->sysarbctl); /* enable concurrent mode */
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/* enable PCI bus arbiter (concurrent mode) */
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writeb(0x02, &sc520_mmcr->sysarbctl);
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writeb(0x1f, &sc520_mmcr->sysarbmenb); /* enable external grants */
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writeb(0x04, &sc520_mmcr->hbctl); /* enable posted-writes */
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/* enable external grants */
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writeb(0x1f, &sc520_mmcr->sysarbmenb);
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/* enable posted-writes */
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writeb(0x04, &sc520_mmcr->hbctl);
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if (CONFIG_SYS_SC520_HIGH_SPEED) {
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writeb(0x02, &sc520_mmcr->cpuctl); /* set it to 133 MHz and write back */
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/* set it to 133 MHz and write back */
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writeb(0x02, &sc520_mmcr->cpuctl);
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gd->cpu_clk = 133000000;
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printf("## CPU Speed set to 133MHz\n");
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} else {
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writeb(0x01, &sc520_mmcr->cpuctl); /* set it to 100 MHz and write back */
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/* set it to 100 MHz and write back */
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writeb(0x01, &sc520_mmcr->cpuctl);
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printf("## CPU Speed set to 100MHz\n");
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gd->cpu_clk = 100000000;
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}
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@ -139,8 +145,10 @@ unsigned long init_sc520_dram(void)
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writeb(val, &c520_mmcr->drctmctl);
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#endif
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/* We read-back the configuration of the dram
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* controller that the assembly code wrote */
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/*
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* We read-back the configuration of the dram
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* controller that the assembly code wrote
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*/
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dram_ctrl = readl(&sc520_mmcr->drcbendadr);
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bd->bi_dram[0].start = 0;
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@ -148,7 +156,6 @@ unsigned long init_sc520_dram(void)
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/* bank 0 enabled */
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dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
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bd->bi_dram[0].size = bd->bi_dram[1].start;
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} else {
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bd->bi_dram[0].size = 0;
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bd->bi_dram[1].start = bd->bi_dram[0].start;
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@ -179,11 +186,6 @@ unsigned long init_sc520_dram(void)
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} else {
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bd->bi_dram[3].size = 0;
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}
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#if 0
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printf("Configured %d bytes of dram\n", dram_present);
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#endif
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gd->ram_size = dram_present;
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return dram_present;
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@ -172,12 +172,9 @@
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.equ ROW11_DATA, 0x07070707 /* 11 row data/also bank switch (MASK) */
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.equ ROW10_DATA, 0xaaaaaaaa /* 10 row data/also bank switch (MASK) */
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/*
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* initialize dram controller registers
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*/
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.globl mem_init
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mem_init:
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/* initialize dram controller registers */
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xorw %ax, %ax
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movl $DBCTL, %edi
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movb %al, (%edi) /* disable write buffer */
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@ -186,12 +183,10 @@ mem_init:
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movb %al, (%edi) /* disable ECC */
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movl $DRCTMCTL, %edi
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movb $0x1E,%al /* Set SDRAM timing for slowest */
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movb $0x1e, %al /* Set SDRAM timing for slowest */
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movb %al, (%edi)
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/*
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* setup loop to do 4 external banks starting with bank 3
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*/
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/* setup loop to do 4 external banks starting with bank 3 */
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movl $0xff000000, %eax /* enable last bank and setup */
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movl $DRCBENDADR, %edi /* ending address register */
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movl %eax, (%edi)
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@ -200,145 +195,123 @@ mem_init:
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movw $0xbbbb, %ax /* dram config register for */
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movw %ax, (%edi)
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/*
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* issue a NOP to all DRAMs
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*/
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/* issue a NOP to all DRAMs */
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movl $DRCCTL, %edi /* setup DRAM control register with */
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movb $0x1,%al /* Disable refresh,disable write buffer */
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movb $0x01, %al /* Disable refresh,disable write buffer */
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movb %al, (%edi)
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movl $CACHELINESZ, %esi /* just a dummy address to write for */
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movw %ax, (%esi)
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/*
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* delay for 100 usec? 200?
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* ******this is a cludge for now *************
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*/
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/* delay for 100 usec? */
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movw $100, %cx
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sizdelay:
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loop sizdelay /* we need 100 usec here */
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/***********************************************/
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loop sizdelay
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/*
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* issue all banks precharge
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*/
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movb $0x2,%al /* All banks precharge */
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/* issue all banks precharge */
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movb $0x02, %al
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movb %al, (%edi)
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movw %ax, (%esi)
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/*
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* issue 2 auto refreshes to all banks
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*/
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movb $0x4,%al /* Auto refresh cmd */
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/* issue 2 auto refreshes to all banks */
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movb $0x04, %al /* Auto refresh cmd */
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movb %al, (%edi)
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movw $2,%cx
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movw $0x02, %cx
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refresh1:
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movw %ax, (%esi)
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loop refresh1
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/*
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* issue LOAD MODE REGISTER command
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*/
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movb $0x3,%al /* Load mode register cmd */
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/* issue LOAD MODE REGISTER command */
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movb $0x03, %al /* Load mode register cmd */
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movb %al, (%edi)
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movw %ax, (%esi)
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/*
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* issue 8 more auto refreshes to all banks
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*/
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movb $0x4,%al /* Auto refresh cmd */
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/* issue 8 more auto refreshes to all banks */
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movb $0x04, %al /* Auto refresh cmd */
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movb %al, (%edi)
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movw $8,%cx
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movw $0x0008, %cx
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refresh2:
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movw %ax, (%esi)
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loop refresh2
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/*
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* set control register to NORMAL mode
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*/
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movb $0x0,%al /* Normal mode value */
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/* set control register to NORMAL mode */
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movb $0x00, %al /* Normal mode value */
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movb %al, (%edi)
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/*
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* size dram starting with external bank 3 moving to external bank 0
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* size dram starting with external bank 3
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* moving to external bank 0
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*/
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movl $0x3, %ecx /* start with external bank 3 */
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nextbank:
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/*
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* write col 11 wrap adr
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*/
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/* write col 11 wrap adr */
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movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
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movl $COL11_DATA, %eax /* pattern for max supported columns(11) */
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movl %eax, (%esi) /* write max col pattern at max col adr */
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movl (%esi), %ebx /* optional read */
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cmpl %ebx, %eax /* to verify write */
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jnz bad_ram /* this ram is bad */
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/*
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* write col 10 wrap adr
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*/
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/* write col 10 wrap adr */
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movl $COL10_ADR, %esi /* set address to 10 col wrap address */
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movl $COL10_DATA, %eax /* pattern for 10 col wrap */
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movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */
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movl (%esi), %ebx /* optional read */
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cmpl %ebx, %eax /* to verify write */
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jnz bad_ram /* this ram is bad */
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/*
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* write col 9 wrap adr
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*/
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/* write col 9 wrap adr */
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movl $COL09_ADR, %esi /* set address to 9 col wrap address */
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movl $COL09_DATA, %eax /* pattern for 9 col wrap */
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movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */
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movl (%esi), %ebx /* optional read */
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cmpl %ebx, %eax /* to verify write */
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jnz bad_ram /* this ram is bad */
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/*
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* write col 8 wrap adr
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*/
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/* write col 8 wrap adr */
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movl $COL08_ADR, %esi /* set address to min(8) col wrap address */
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movl $COL08_DATA, %eax /* pattern for min (8) col wrap */
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movl %eax, (%esi) /* write min col pattern @ min col adr */
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movl (%esi), %ebx /* optional read */
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cmpl %ebx, %eax /* to verify write */
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jnz bad_ram /* this ram is bad */
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/*
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* write row 14 wrap adr
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*/
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/* write row 14 wrap adr */
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movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */
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movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */
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movl %eax, (%esi) /* write max row pattern at max row adr */
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movl (%esi), %ebx /* optional read */
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cmpl %ebx, %eax /* to verify write */
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jnz bad_ram /* this ram is bad */
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/*
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* write row 13 wrap adr
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*/
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/* write row 13 wrap adr */
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movl $ROW13_ADR, %esi /* set address to 13 row wrap address */
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movl $ROW13_DATA, %eax /* pattern for 13 row wrap */
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movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */
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movl (%esi), %ebx /* optional read */
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cmpl %ebx, %eax /* to verify write */
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jnz bad_ram /* this ram is bad */
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/*
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* write row 12 wrap adr
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*/
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/* write row 12 wrap adr */
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movl $ROW12_ADR, %esi /* set address to 12 row wrap address */
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movl $ROW12_DATA, %eax /* pattern for 12 row wrap */
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movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */
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movl (%esi), %ebx /* optional read */
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cmpl %ebx, %eax /* to verify write */
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jnz bad_ram /* this ram is bad */
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/*
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* write row 11 wrap adr
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*/
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/* write row 11 wrap adr */
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movl $ROW11_ADR, %edi /* set address to 11 row wrap address */
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movl $ROW11_DATA, %eax /* pattern for 11 row wrap */
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movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */
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movl (%edi), %ebx /* optional read */
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cmpl %ebx, %eax /* to verify write */
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jnz bad_ram /* this ram is bad */
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/*
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* write row 10 wrap adr --- this write is really to determine number of banks
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* write row 10 wrap adr --- this write is really to determine
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* number of banks
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*/
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movl $ROW10_ADR, %edi /* set address to 10 row wrap address */
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movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */
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@ -346,6 +319,7 @@ nextbank:
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movl (%edi), %ebx /* optional read */
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cmpl %ebx, %eax /* to verify write */
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jnz bad_ram /* this ram is bad */
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/*
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* read data @ row 12 wrap adr to determine * banks,
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* and read data @ row 14 wrap adr to determine * rows.
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@ -354,14 +328,14 @@ nextbank:
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* if data @ row 12 wrap == 11 or 12, we have 4 banks,
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*/
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xorw %di, %di /* value for 2 banks in DI */
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movl (%esi), %ebx /* read from 12 row wrap to check banks
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* (esi is setup from the write to row 12 wrap) */
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movl (%esi), %ebx /* read from 12 row wrap to check banks */
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/* (esi is setup from the write to row 12 wrap) */
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cmpl %ebx, %eax /* check for AA pattern (eax holds the aa pattern) */
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jz only2 /* if pattern == AA, we only have 2 banks */
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/* 4 banks */
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movw $8,%di /* value for 4 banks in DI (BNK_CNT bit) */
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movw $0x008, %di /* value for 4 banks in DI (BNK_CNT bit) */
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cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */
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jz only2
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cmpl $ROW12_DATA, %ebx /* and 12 */
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@ -387,11 +361,13 @@ only2:
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shrl $16, %ebx
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cmpw %bx, %ax
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jnz bad_ram
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/*
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* read col 11 wrap adr for real column data value
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*/
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movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
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movl (%esi), %eax /* read real col number at max col adr */
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/*
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* validate column data
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*/
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@ -409,26 +385,29 @@ only2:
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shrl $16, %edx
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cmpw %dx, %ax
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jnz bad_ram
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/*
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* merge bank and col data together
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*/
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addw %di, %dx /* merge of bank and col info in dl */
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/*
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* fix ending addr mask based upon col info
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*/
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movb $3,%al
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movb $0x03, %al
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subb %dh, %al /* dh contains the overflow from the bank/col merge */
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movb %bl, %dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
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xchgw %cx, %ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */
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shrb %cl,%dh /* */
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shrb %cl, %dh
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incb %dh /* ending addr is 1 greater than real end */
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xchgw %cx, %ax /* cx is bank number again */
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bad_reint:
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/*
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* issue all banks precharge
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*/
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bad_reint:
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movl $DRCCTL, %esi /* setup DRAM control register with */
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movb $0x2,%al /* All banks precharge */
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movb $0x02, %al /* All banks precharge */
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movb %al, (%esi)
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movl $CACHELINESZ, %esi /* address to init read buffer */
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movw %ax, (%esi)
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@ -440,11 +419,12 @@ bad_reint:
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movl %ecx, %ebx
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addl %ebx, %edi
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movb %dh, (%edi)
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/*
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* update CONFIG REGISTER
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*/
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xorb %dh, %dh
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movw $0x00f,%bx
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movw $0x000f, %bx
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movw %cx, %ax
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shlw $2, %ax
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xchgw %cx, %ax
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@ -453,7 +433,7 @@ bad_reint:
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notw %bx
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xchgw %cx, %ax
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movl $DRCCFG, %edi
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mov (%edi), %ax
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movw (%edi), %ax
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andw %bx, %ax
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orw %dx, %ax
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movw %ax, (%edi)
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@ -465,11 +445,12 @@ bad_reint:
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movb $0xff, %al
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addl %ebx, %edi
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movb %al, (%edi)
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/*
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* set control register to NORMAL mode
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*/
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movl $DRCCTL, %esi /* setup DRAM control register with */
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movb $0x0,%al /* Normal mode value */
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movb $0x00, %al /* Normal mode value */
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movb %al, (%esi)
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movl $CACHELINESZ, %esi /* address to init read buffer */
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movw %ax, (%esi)
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@ -477,7 +458,7 @@ bad_reint:
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cleanup:
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movl $DRCBENDADR, %edi /* DRAM ending address register */
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movw $4,%cx
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movw $0x04, %cx
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xorw %ax, %ax
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cleanuplp:
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movb (%edi), %al
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@ -503,8 +484,10 @@ emptybank:
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movb %al, (%edi)
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#else
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#if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T)
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/* set the CAS latency now since it is hard to do
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* when we run from the RAM */
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/*
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* Set the CAS latency now since it is hard to do
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* when we run from the RAM
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*/
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movl $DRCTMCTL, %edi /* DRAM timing register */
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movb (%edi), %al
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#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
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@ -517,7 +500,7 @@ emptybank:
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#endif
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#endif
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movl $DRCCTL, %edi /* DRAM Control register */
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movb $0x3,%al /* Load mode register cmd */
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movb $0x03, %al /* Load mode register cmd */
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movb %al, (%edi)
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movw %ax, (%esi)
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@ -558,10 +541,10 @@ memtest0:
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movb $0xa5, (%edi)
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cmpb $0xa5, (%edi)
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jne out
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shrl $1, %ecx
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shrl $0x1, %ecx
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andl %ecx, %ecx
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jz set_ecc
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shll $1, %edi
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shll $0x1, %edi
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jmp memtest0
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set_ecc:
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@ -570,20 +553,23 @@ set_ecc:
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xorl %esi, %esi
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xorl %edi, %edi
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xorl %eax, %eax
|
||||
shrl $2, %ecx
|
||||
shrl $0x2, %ecx
|
||||
cld
|
||||
rep stosl
|
||||
|
||||
/* enable read, write buffers */
|
||||
movb $0x11, %al
|
||||
movl $DBCTL, %edi
|
||||
movb %al, (%edi)
|
||||
|
||||
/* enable NMI mapping for ECC */
|
||||
movl $ECCINT, %edi
|
||||
mov $0x10, %al
|
||||
movb $0x10, %al
|
||||
movb %al, (%edi)
|
||||
|
||||
/* Turn on ECC */
|
||||
movl $ECCCTL, %edi
|
||||
mov $0x05, %al
|
||||
movb $0x05, %al
|
||||
movb %al,(%edi)
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -31,7 +31,8 @@
|
|||
.code16
|
||||
.globl start16
|
||||
start16:
|
||||
/* First we let the BSP do some early initialization
|
||||
/*
|
||||
* First we let the BSP do some early initialization
|
||||
* this code have to map the flash to its final position
|
||||
*/
|
||||
mov $board_init16_ret, %bp
|
||||
|
|
|
|||
Loading…
Reference in a new issue