mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
Merge branch '2022-08-12-assorted-updates'
- Clean up some code with the DH electronics boards, remove a few boards that have had their removal ack'd, update Azure CI hosts for macOS and Ubuntu, and migrate a few more symbols to Kconfig.
This commit is contained in:
commit
8f9eee8275
179 changed files with 480 additions and 3967 deletions
|
@ -1,7 +1,7 @@
|
|||
variables:
|
||||
windows_vm: windows-2019
|
||||
ubuntu_vm: ubuntu-18.04
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||||
macos_vm: macOS-10.15
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||||
ubuntu_vm: ubuntu-22.04
|
||||
macos_vm: macOS-12
|
||||
ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20220302-15Mar2022
|
||||
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
|
||||
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
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||||
|
|
95
README
95
README
|
@ -294,17 +294,6 @@ The following options need to be configured:
|
|||
the "64" category of the Power ISA). This is necessary for ePAPR
|
||||
compliance, among other possible reasons.
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|
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CONFIG_SYS_FSL_TBCLK_DIV
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||||
|
||||
Defines the core time base clock divider ratio compared to the
|
||||
system clock. On most PQ3 devices this is 8, on newer QorIQ
|
||||
devices it can be 16 or 32. The ratio varies from SoC to Soc.
|
||||
|
||||
CONFIG_SYS_FSL_PCIE_COMPAT
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|
||||
Defines the string to utilize when trying to match PCIe device
|
||||
tree nodes for the given platform.
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|
||||
CONFIG_SYS_FSL_ERRATUM_A004510
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||||
|
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Enables a workaround for erratum A004510. If set,
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||||
|
@ -330,31 +319,12 @@ The following options need to be configured:
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|||
This is the value to write into CCSR offset 0x18600
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||||
according to the A004510 workaround.
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||||
|
||||
CONFIG_SYS_FSL_DSP_DDR_ADDR
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This value denotes start offset of DDR memory which is
|
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connected exclusively to the DSP cores.
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|
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CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
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This value denotes start offset of M2 memory
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||||
which is directly connected to the DSP core.
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|
||||
CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
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||||
This value denotes start offset of M3 memory which is directly
|
||||
connected to the DSP core.
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CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
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This value denotes start offset of DSP CCSR space.
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|
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CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
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Single Source Clock is clocking mode present in some of FSL SoC's.
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In this mode, a single differential clock is used to supply
|
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clocks to the sysclock, ddrclock and usbclock.
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||||
|
||||
- Generic CPU options:
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CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
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|
||||
Defines the endianess of the CPU. Implementation of those
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||||
values is arch specific.
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||||
|
||||
CONFIG_SYS_FSL_DDR
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||||
Freescale DDR driver in use. This type of DDR controller is
|
||||
|
@ -363,68 +333,17 @@ The following options need to be configured:
|
|||
CONFIG_SYS_FSL_DDR_ADDR
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Freescale DDR memory-mapped register base.
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|
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CONFIG_SYS_FSL_DDRC_GEN1
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Freescale DDR1 controller.
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||||
|
||||
CONFIG_SYS_FSL_DDRC_GEN2
|
||||
Freescale DDR2 controller.
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|
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CONFIG_SYS_FSL_DDRC_GEN3
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Freescale DDR3 controller.
|
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|
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CONFIG_SYS_FSL_DDRC_GEN4
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Freescale DDR4 controller.
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|
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CONFIG_SYS_FSL_DDRC_ARM_GEN3
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Freescale DDR3 controller for ARM-based SoCs.
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|
||||
CONFIG_SYS_FSL_DDR1
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Board config to use DDR1. It can be enabled for SoCs with
|
||||
Freescale DDR1 or DDR2 controllers, depending on the board
|
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implemetation.
|
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|
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CONFIG_SYS_FSL_DDR2
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Board config to use DDR2. It can be enabled for SoCs with
|
||||
Freescale DDR2 or DDR3 controllers, depending on the board
|
||||
implementation.
|
||||
|
||||
CONFIG_SYS_FSL_DDR3
|
||||
Board config to use DDR3. It can be enabled for SoCs with
|
||||
Freescale DDR3 or DDR3L controllers.
|
||||
|
||||
CONFIG_SYS_FSL_DDR3L
|
||||
Board config to use DDR3L. It can be enabled for SoCs with
|
||||
DDR3L controllers.
|
||||
|
||||
CONFIG_SYS_FSL_IFC_CLK_DIV
|
||||
Defines divider of platform clock(clock input to IFC controller).
|
||||
|
||||
CONFIG_SYS_FSL_LBC_CLK_DIV
|
||||
Defines divider of platform clock(clock input to eLBC controller).
|
||||
|
||||
CONFIG_SYS_FSL_DDR_BE
|
||||
Defines the DDR controller register space as Big Endian
|
||||
|
||||
CONFIG_SYS_FSL_DDR_LE
|
||||
Defines the DDR controller register space as Little Endian
|
||||
|
||||
CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
|
||||
Physical address from the view of DDR controllers. It is the
|
||||
same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
|
||||
it could be different for ARM SoCs.
|
||||
|
||||
CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
|
||||
Number of controllers used as main memory.
|
||||
|
||||
CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
|
||||
Number of controllers used for other than main memory.
|
||||
|
||||
CONFIG_SYS_FSL_SEC_BE
|
||||
Defines the SEC controller register space as Big Endian
|
||||
|
||||
CONFIG_SYS_FSL_SEC_LE
|
||||
Defines the SEC controller register space as Little Endian
|
||||
|
||||
- MIPS CPU options:
|
||||
CONFIG_XWAY_SWAP_BYTES
|
||||
|
||||
|
@ -646,20 +565,6 @@ The following options need to be configured:
|
|||
CONFIG_LAN91C96_USE_32_BIT
|
||||
Define this to enable 32 bit addressing
|
||||
|
||||
CONFIG_SMC91111
|
||||
Support for SMSC's LAN91C111 chip
|
||||
|
||||
CONFIG_SMC91111_BASE
|
||||
Define this to hold the physical address
|
||||
of the device (I/O space)
|
||||
|
||||
CONFIG_SMC_USE_32_BIT
|
||||
Define this if data bus is 32 bits
|
||||
|
||||
CONFIG_SMC_USE_IOFUNCS
|
||||
Define this to use i/o functions instead of macros
|
||||
(some hardware wont work with macros)
|
||||
|
||||
CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
|
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Define this if you have more then 3 PHYs.
|
||||
|
||||
|
|
|
@ -53,6 +53,8 @@ config ARC
|
|||
select SUPPORT_OF_CONTROL
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select SYS_CACHE_SHIFT_7
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||||
select TIMER
|
||||
select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
|
||||
select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
|
||||
|
||||
config ARM
|
||||
bool "ARM architecture"
|
||||
|
|
|
@ -227,6 +227,12 @@ config VOL_MONITOR_ISL68233_SET
|
|||
|
||||
endif
|
||||
|
||||
config SYS_FSL_NUM_CC_PLLS
|
||||
int "Number of clock control PLLs"
|
||||
depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A
|
||||
default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2
|
||||
default 6 if FSL_LSCH3 || MPC85xx
|
||||
|
||||
config SYS_FSL_ESDHC_BE
|
||||
bool
|
||||
|
||||
|
|
|
@ -2,12 +2,6 @@
|
|||
#
|
||||
# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
|
||||
|
||||
ifndef CONFIG_CPU_BIG_ENDIAN
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CONFIG_SYS_LITTLE_ENDIAN = 1
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||||
else
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CONFIG_SYS_BIG_ENDIAN = 1
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endif
|
||||
|
||||
ifdef CONFIG_SYS_LITTLE_ENDIAN
|
||||
KBUILD_LDFLAGS += -EL
|
||||
PLATFORM_CPPFLAGS += -mlittle-endian
|
||||
|
|
|
@ -13,10 +13,6 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
|
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
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#endif
|
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|
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void get_sys_info(struct sys_info *sys_info)
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||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
|
|
|
@ -85,6 +85,7 @@ config ARCH_LS1043A
|
|||
select SYS_FSL_ERRATUM_A010539
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_DDR4
|
||||
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
|
||||
select ARCH_EARLY_INIT_R
|
||||
select BOARD_EARLY_INIT_F
|
||||
select SYS_I2C_MXC
|
||||
|
@ -123,6 +124,7 @@ config ARCH_LS1046A
|
|||
select SYS_FSL_ERRATUM_A010539
|
||||
select SYS_FSL_HAS_DDR4
|
||||
select SYS_FSL_SRDS_2
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||||
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
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||||
select ARCH_EARLY_INIT_R
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select BOARD_EARLY_INIT_F
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select SYS_I2C_MXC
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|
@ -193,6 +195,7 @@ config ARCH_LS2080A
|
|||
select FSL_IFC
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||||
select FSL_LAYERSCAPE
|
||||
select FSL_LSCH3
|
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select SYS_FSL_OTHER_DDR_NUM_CTRLS
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||||
select GICV3
|
||||
select SKIP_LOWLEVEL_INIT
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||||
select SYS_FSL_SRDS_1
|
||||
|
|
|
@ -18,10 +18,6 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
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||||
|
||||
#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
#endif
|
||||
|
||||
void get_sys_info(struct sys_info *sys_info)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
|
|
|
@ -21,11 +21,6 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
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||||
#endif
|
||||
|
||||
|
||||
void get_sys_info(struct sys_info *sys_info)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
|
|
|
@ -94,12 +94,7 @@
|
|||
#define EPU_EPCTR5 0x700060a14ULL
|
||||
#define EPU_EPGCR 0x700060000ULL
|
||||
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008751
|
||||
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
|
||||
#elif defined(CONFIG_ARCH_LS1088A)
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
|
||||
#define CONFIG_SYS_PAGE_SIZE 0x10000
|
||||
|
||||
|
@ -131,7 +126,6 @@
|
|||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
||||
|
||||
/* DCFG - GUR */
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
|
||||
|
@ -146,7 +140,6 @@
|
|||
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
|
||||
|
||||
#define CONFIG_SYS_PAGE_SIZE 0x10000
|
||||
|
||||
|
@ -167,10 +160,7 @@
|
|||
|
||||
/* DCFG - GUR */
|
||||
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
|
||||
#elif defined(CONFIG_ARCH_LS1028A)
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
|
||||
#define CONFIG_FSL_TZASC_400
|
||||
|
||||
|
@ -206,7 +196,6 @@
|
|||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
||||
|
||||
/* SEC */
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
|
||||
/* DCFG - GUR */
|
||||
|
||||
|
@ -218,12 +207,8 @@
|
|||
#define DCSR_DCFG_SBEESR2 0x20140534
|
||||
#define DCSR_DCFG_MBEESR2 0x20140544
|
||||
|
||||
#define CONFIG_SYS_FSL_WDOG_BE
|
||||
#define CONFIG_SYS_FSL_DSPI_BE
|
||||
|
||||
/* SoC related */
|
||||
#ifdef CONFIG_ARCH_LS1043A
|
||||
#define CONFIG_SYS_FSL_QMAN_V3
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 7
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||
|
@ -263,17 +248,13 @@
|
|||
#define GIC_ADDR_BIT 31
|
||||
#define SCFG_GIC400_ALIGN 0x1570188
|
||||
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
|
||||
#elif defined(CONFIG_ARCH_LS1012A)
|
||||
#define GICD_BASE 0x01401000
|
||||
#define GICC_BASE 0x01402000
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
||||
|
||||
#elif defined(CONFIG_ARCH_LS1046A)
|
||||
#define CONFIG_SYS_FSL_QMAN_V3
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 8
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 2
|
||||
|
@ -286,8 +267,6 @@
|
|||
/* Generic Interrupt Controller Definitions */
|
||||
#define GICD_BASE 0x01410000
|
||||
#define GICC_BASE 0x01420000
|
||||
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
#else
|
||||
#error SoC not defined
|
||||
#endif
|
||||
|
|
|
@ -166,12 +166,6 @@ struct sys_info {
|
|||
};
|
||||
|
||||
#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000
|
||||
#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000
|
||||
#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000
|
||||
#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000
|
||||
#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000
|
||||
#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000
|
||||
#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000
|
||||
|
||||
#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
|
||||
#define CONFIG_SYS_FSL_FM1_ADDR \
|
||||
|
|
|
@ -48,6 +48,5 @@
|
|||
#define USB_PHY0_BASE_ADDR 0x5b100000
|
||||
|
||||
#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
|
||||
#endif /* __ASM_ARCH_IMX8_REGS_H__ */
|
||||
|
|
|
@ -92,7 +92,6 @@
|
|||
#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
|
||||
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
|
||||
CONFIG_SYS_FSL_JR0_OFFSET)
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
#if !defined(__ASSEMBLY__)
|
||||
#include <asm/types.h>
|
||||
#include <linux/bitops.h>
|
||||
|
|
|
@ -79,13 +79,9 @@
|
|||
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FSL_WDOG_BE
|
||||
#define CONFIG_SYS_FSL_DSPI_BE
|
||||
|
||||
#define DCU_LAYER_MAX_NUM 16
|
||||
|
||||
#ifdef CONFIG_ARCH_LS1021A
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
#else
|
||||
#error SoC not defined
|
||||
#endif
|
||||
|
|
|
@ -244,7 +244,6 @@
|
|||
#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
|
||||
#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
|
||||
CONFIG_SYS_FSL_JR0_OFFSET)
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
|
||||
#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
|
||||
#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
|
||||
|
|
|
@ -221,7 +221,6 @@
|
|||
#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
|
||||
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
|
||||
CONFIG_SYS_FSL_JR0_OFFSET)
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
|
||||
#include <asm/mach-imx/regs-lcdif.h>
|
||||
#include <asm/types.h>
|
||||
|
|
|
@ -234,7 +234,6 @@
|
|||
#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
|
||||
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
|
||||
CONFIG_SYS_FSL_JR0_OFFSET)
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
|
||||
#define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32)))
|
||||
#define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33)))
|
||||
|
|
|
@ -79,15 +79,6 @@ config TARGET_ETHERNUT5
|
|||
bool "Ethernut5 board"
|
||||
select AT91SAM9XE
|
||||
|
||||
config TARGET_SNAPPER9260
|
||||
bool "Support snapper9260"
|
||||
select AT91SAM9260
|
||||
select AT91_WANTS_COMMON_PHY
|
||||
select DM
|
||||
select DM_GPIO
|
||||
select DM_SERIAL
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_GURNARD
|
||||
bool "Support gurnard"
|
||||
select AT91SAM9G45
|
||||
|
@ -364,7 +355,6 @@ source "board/atmel/sama5d3xek/Kconfig"
|
|||
source "board/atmel/sama5d4_xplained/Kconfig"
|
||||
source "board/atmel/sama5d4ek/Kconfig"
|
||||
source "board/bluewater/gurnard/Kconfig"
|
||||
source "board/bluewater/snapper9260/Kconfig"
|
||||
source "board/calao/usb_a9263/Kconfig"
|
||||
source "board/egnite/ethernut5/Kconfig"
|
||||
source "board/esd/meesc/Kconfig"
|
||||
|
|
|
@ -303,10 +303,6 @@ clear_bss:
|
|||
/* set parameters for board_init_r */
|
||||
move.l %a0,-(%sp) /* dest_addr */
|
||||
move.l %d0,-(%sp) /* gd */
|
||||
#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \
|
||||
defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
|
||||
halt
|
||||
#endif
|
||||
jsr (%a1)
|
||||
|
||||
/******************************************************************************/
|
||||
|
|
|
@ -226,10 +226,6 @@ clear_bss:
|
|||
/* set parameters for board_init_r */
|
||||
move.l %a0,-(%sp) /* dest_addr */
|
||||
move.l %d0,-(%sp) /* gd */
|
||||
#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE!=CONFIG_SYS_INT_FLASH_BASE) && \
|
||||
defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
|
||||
halt
|
||||
#endif
|
||||
jsr (%a1)
|
||||
|
||||
/******************************************************************************/
|
||||
|
|
|
@ -26,12 +26,6 @@ config TARGET_MPC837XERDB
|
|||
select BOARD_EARLY_INIT_F
|
||||
select SYS_83XX_DDR_USES_CS0
|
||||
|
||||
config TARGET_IDS8313
|
||||
bool "Support ids8313"
|
||||
select ARCH_MPC8313
|
||||
select DM
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_KMETER1
|
||||
bool "Support kmeter1"
|
||||
select VENDOR_KM
|
||||
|
@ -212,7 +206,6 @@ config FSL_ELBC
|
|||
bool
|
||||
|
||||
source "board/freescale/mpc837xerdb/Kconfig"
|
||||
source "board/ids/ids8313/Kconfig"
|
||||
source "board/gdsys/mpc8308/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
|
|
@ -78,6 +78,7 @@ config TARGET_P3041DS
|
|||
select PHYS_64BIT
|
||||
select ARCH_P3041
|
||||
select BOARD_LATE_INIT if CHAIN_OF_TRUST
|
||||
select FSL_NGPIXIS
|
||||
imply CMD_SATA
|
||||
imply PANIC_HANG
|
||||
|
||||
|
@ -86,6 +87,7 @@ config TARGET_P4080DS
|
|||
select PHYS_64BIT
|
||||
select ARCH_P4080
|
||||
select BOARD_LATE_INIT if CHAIN_OF_TRUST
|
||||
select FSL_NGPIXIS
|
||||
imply CMD_SATA
|
||||
imply PANIC_HANG
|
||||
|
||||
|
@ -94,6 +96,8 @@ config TARGET_P5040DS
|
|||
select PHYS_64BIT
|
||||
select ARCH_P5040
|
||||
select BOARD_LATE_INIT if CHAIN_OF_TRUST
|
||||
select FSL_NGPIXIS
|
||||
select SYS_FSL_RAID_ENGINE
|
||||
imply CMD_SATA
|
||||
imply PANIC_HANG
|
||||
|
||||
|
@ -259,8 +263,11 @@ config ARCH_B4420
|
|||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_QORIQ_CHASSIS2
|
||||
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
|
||||
select SYS_FSL_USB1_PHY_ENABLE
|
||||
select SYS_PPC64
|
||||
select FSL_IFC
|
||||
imply CMD_EEPROM
|
||||
|
@ -289,8 +296,12 @@ config ARCH_B4860
|
|||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_QORIQ_CHASSIS2
|
||||
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
select SYS_FSL_SRIO_LIODN
|
||||
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
|
||||
select SYS_FSL_USB1_PHY_ENABLE
|
||||
select SYS_PPC64
|
||||
select FSL_IFC
|
||||
imply CMD_EEPROM
|
||||
|
@ -326,6 +337,7 @@ config ARCH_BSC9132
|
|||
select FSL_PCIE_RESET
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
select SYS_PPC_E500_USE_DEBUG_TLB
|
||||
|
@ -402,6 +414,7 @@ config ARCH_MPC8548
|
|||
select SYS_FSL_HAS_DDR2
|
||||
select SYS_FSL_HAS_DDR1
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_RMU
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_2
|
||||
select SYS_PPC_E500_USE_DEBUG_TLB
|
||||
|
@ -434,8 +447,10 @@ config ARCH_P1010
|
|||
select FSL_PCIE_RESET
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
select SYS_FSL_USB1_PHY_ENABLE
|
||||
select SYS_PPC_E500_USE_DEBUG_TLB
|
||||
select FSL_IFC
|
||||
imply CMD_EEPROM
|
||||
|
@ -515,6 +530,7 @@ config ARCH_P1023
|
|||
select FSL_PCIE_RESET
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
select FSL_ELBC
|
||||
|
@ -530,6 +546,7 @@ config ARCH_P1024
|
|||
select FSL_PCIE_RESET
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_RMU
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_2
|
||||
select SYS_PPC_E500_USE_DEBUG_TLB
|
||||
|
@ -602,8 +619,11 @@ config ARCH_P2041
|
|||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_QORIQ_CHASSIS1
|
||||
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
select SYS_FSL_USB1_PHY_ENABLE
|
||||
select SYS_FSL_USB2_PHY_ENABLE
|
||||
select FSL_ELBC
|
||||
imply CMD_NAND
|
||||
|
||||
|
@ -631,8 +651,11 @@ config ARCH_P3041
|
|||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_QORIQ_CHASSIS1
|
||||
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
select SYS_FSL_USB1_PHY_ENABLE
|
||||
select SYS_FSL_USB2_PHY_ENABLE
|
||||
select FSL_ELBC
|
||||
imply CMD_NAND
|
||||
imply CMD_SATA
|
||||
|
@ -664,6 +687,7 @@ config ARCH_P4080
|
|||
select SYS_FSL_ERRATUM_I2C_A004447
|
||||
select SYS_FSL_ERRATUM_NMG_CPU_A011
|
||||
select SYS_FSL_ERRATUM_SRIO_A004034
|
||||
select SYS_FSL_PCIE_COMPAT_P4080_PCIE
|
||||
select SYS_P4080_ERRATUM_CPU22
|
||||
select SYS_P4080_ERRATUM_PCIE_A003
|
||||
select SYS_P4080_ERRATUM_SERDES8
|
||||
|
@ -673,6 +697,7 @@ config ARCH_P4080
|
|||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_QORIQ_CHASSIS1
|
||||
select SYS_FSL_RMU
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
select FSL_ELBC
|
||||
|
@ -700,8 +725,11 @@ config ARCH_P5040
|
|||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_QORIQ_CHASSIS1
|
||||
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
select SYS_FSL_USB1_PHY_ENABLE
|
||||
select SYS_FSL_USB2_PHY_ENABLE
|
||||
select SYS_PPC64
|
||||
select FSL_ELBC
|
||||
imply CMD_SATA
|
||||
|
@ -730,8 +758,12 @@ config ARCH_T1024
|
|||
select SYS_FSL_HAS_DDR4
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_QORIQ_CHASSIS2
|
||||
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_5
|
||||
select SYS_FSL_SINGLE_SOURCE_CLK
|
||||
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
|
||||
select SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
select FSL_IFC
|
||||
imply CMD_EEPROM
|
||||
imply CMD_NAND
|
||||
|
@ -757,8 +789,12 @@ config ARCH_T1040
|
|||
select SYS_FSL_HAS_DDR4
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_QORIQ_CHASSIS2
|
||||
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_5
|
||||
select SYS_FSL_SINGLE_SOURCE_CLK
|
||||
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
|
||||
select SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
select FSL_IFC
|
||||
imply CMD_MTDPARTS
|
||||
imply CMD_NAND
|
||||
|
@ -783,8 +819,12 @@ config ARCH_T1042
|
|||
select SYS_FSL_HAS_DDR4
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_QORIQ_CHASSIS2
|
||||
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_5
|
||||
select SYS_FSL_SINGLE_SOURCE_CLK
|
||||
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
|
||||
select SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
select FSL_IFC
|
||||
imply CMD_MTDPARTS
|
||||
imply CMD_NAND
|
||||
|
@ -811,8 +851,12 @@ config ARCH_T2080
|
|||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_QORIQ_CHASSIS2
|
||||
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
select SYS_FSL_SRIO_LIODN
|
||||
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
|
||||
select SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
select SYS_PPC64
|
||||
select FSL_IFC
|
||||
imply CMD_SATA
|
||||
|
@ -843,8 +887,12 @@ config ARCH_T4240
|
|||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_QORIQ_CHASSIS2
|
||||
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
select SYS_FSL_SRIO_LIODN
|
||||
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
|
||||
select SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
select SYS_PPC64
|
||||
select FSL_IFC
|
||||
imply CMD_SATA
|
||||
|
@ -1133,6 +1181,12 @@ config FSL_PCIE_DISABLE_ASPM
|
|||
config FSL_PCIE_RESET
|
||||
bool
|
||||
|
||||
config SYS_FSL_RAID_ENGINE
|
||||
bool
|
||||
|
||||
config SYS_FSL_RMU
|
||||
bool
|
||||
|
||||
config SYS_FSL_QORIQ_CHASSIS1
|
||||
bool
|
||||
|
||||
|
@ -1298,6 +1352,9 @@ config FSL_CORENET
|
|||
bool
|
||||
select SYS_FSL_CPC
|
||||
|
||||
config FSL_NGPIXIS
|
||||
bool
|
||||
|
||||
config SYS_CPC_REINIT_F
|
||||
bool
|
||||
help
|
||||
|
@ -1310,6 +1367,56 @@ config SYS_FSL_CPC
|
|||
config SYS_CACHE_STASHING
|
||||
bool "Enable cache stashing"
|
||||
|
||||
config SYS_FSL_PCIE_COMPAT_P4080_PCIE
|
||||
bool
|
||||
|
||||
config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
|
||||
bool
|
||||
|
||||
config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
|
||||
bool
|
||||
|
||||
config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
|
||||
bool
|
||||
|
||||
config SYS_FSL_PCIE_COMPAT
|
||||
string
|
||||
depends on FSL_CORENET
|
||||
default "fsl,p4080-pcie" if SYS_FSL_PCIE_COMPAT_P4080_PCIE
|
||||
default "fsl,qoriq-pcie-v2.2" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
|
||||
default "fsl,qoriq-pcie-v2.4" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
|
||||
default "fsl,qoriq-pcie-v3.0" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
|
||||
help
|
||||
Defines the string to utilize when trying to match PCIe device tree
|
||||
nodes for the given platform.
|
||||
|
||||
config SYS_FSL_SINGLE_SOURCE_CLK
|
||||
bool
|
||||
|
||||
config SYS_FSL_SRIO_LIODN
|
||||
bool
|
||||
|
||||
config SYS_FSL_TBCLK_DIV
|
||||
int
|
||||
default 32 if ARCH_P2041 || ARCH_P3041
|
||||
default 16 if ARCH_P4080 || ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \
|
||||
ARCH_B4420 || ARCH_T1040 || ARCH_T1042 || \
|
||||
ARCH_T1024 || ARCH_T2080
|
||||
default 8
|
||||
help
|
||||
Defines the core time base clock divider ratio compared to the system
|
||||
clock. On most PQ3 devices this is 8, on newer QorIQ devices it can
|
||||
be 16 or 32. The ratio varies from SoC to Soc.
|
||||
|
||||
config SYS_FSL_USB1_PHY_ENABLE
|
||||
bool
|
||||
|
||||
config SYS_FSL_USB2_PHY_ENABLE
|
||||
bool
|
||||
|
||||
config SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
bool
|
||||
|
||||
config SYS_MPC85XX_NO_RESETVEC
|
||||
bool "Discard resetvec section and move bootpg section up"
|
||||
depends on MPC85xx
|
||||
|
|
|
@ -334,9 +334,6 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
|
|||
/*
|
||||
* Get timebase clock frequency
|
||||
*/
|
||||
#ifndef CONFIG_SYS_FSL_TBCLK_DIV
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 8
|
||||
#endif
|
||||
__weak unsigned long get_tbclk(void)
|
||||
{
|
||||
unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
|
||||
|
|
|
@ -20,10 +20,6 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
||||
#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
|
||||
#endif
|
||||
/* --------------------------------------------------------------- */
|
||||
|
||||
void get_sys_info(sys_info_t *sys_info)
|
||||
|
|
|
@ -31,10 +31,6 @@ ulong cpu_init_f(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SYS_FSL_TBCLK_DIV
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 8
|
||||
#endif
|
||||
|
||||
void udelay(unsigned long usec)
|
||||
{
|
||||
u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
|
||||
|
|
|
@ -20,16 +20,12 @@
|
|||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CONFIG_SYS_FSL_RMU
|
||||
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
|
||||
|
||||
#elif defined(CONFIG_ARCH_P1010)
|
||||
#define CONFIG_FSL_SDHC_V2_3
|
||||
#define CONFIG_TSECV2
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
||||
|
||||
/* P1011 is single core version of P1020 */
|
||||
#elif defined(CONFIG_ARCH_P1011)
|
||||
|
@ -50,7 +46,6 @@
|
|||
#define CONFIG_SYS_QMAN_NUM_PORTALS 3
|
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 3
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
||||
|
||||
/* P1024 is lower end variant of P1020 */
|
||||
#elif defined(CONFIG_ARCH_P1024)
|
||||
|
@ -67,93 +62,61 @@
|
|||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CONFIG_SYS_FSL_RMU
|
||||
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
|
||||
|
||||
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 32
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
||||
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
|
||||
|
||||
#elif defined(CONFIG_ARCH_P3041)
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 32
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
||||
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
|
||||
|
||||
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
|
||||
#define CONFIG_SYS_NUM_FMAN 2
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 4
|
||||
#define CONFIG_SYS_NUM_FM2_DTSEC 4
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||
#define CONFIG_SYS_NUM_FM2_10GEC 1
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CONFIG_SYS_FSL_RMU
|
||||
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
|
||||
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
|
||||
|
||||
#elif defined(CONFIG_ARCH_P5040)
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
|
||||
#define CONFIG_SYS_NUM_FMAN 2
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||
#define CONFIG_SYS_NUM_FM2_DTSEC 5
|
||||
#define CONFIG_SYS_NUM_FM2_10GEC 1
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
|
||||
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
|
||||
|
||||
#elif defined(CONFIG_ARCH_BSC9131)
|
||||
#define CONFIG_FSL_SDHC_V2_3
|
||||
#define CONFIG_TSECV2
|
||||
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
|
||||
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
|
||||
|
||||
#elif defined(CONFIG_ARCH_BSC9132)
|
||||
#define CONFIG_FSL_SDHC_V2_3
|
||||
#define CONFIG_TSECV2
|
||||
#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
|
||||
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
|
||||
#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
|
||||
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
|
||||
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
||||
|
||||
#elif defined(CONFIG_ARCH_T4240)
|
||||
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
|
||||
#ifdef CONFIG_ARCH_T4240
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 8
|
||||
|
@ -166,7 +129,6 @@
|
|||
#define CONFIG_SYS_NUM_FM2_DTSEC 8
|
||||
#define CONFIG_SYS_NUM_FM2_10GEC 1
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#define CONFIG_SYS_FSL_SRDS_2
|
||||
#define CONFIG_SYS_FSL_SRDS_3
|
||||
|
@ -177,50 +139,35 @@
|
|||
#define CONFIG_SYS_FM1_CLK 3
|
||||
#define CONFIG_SYS_FM2_CLK 3
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CONFIG_SYS_FSL_SRIO_LIODN
|
||||
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
|
||||
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
|
||||
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#define CONFIG_SYS_FSL_SRDS_2
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_FM1_CLK 0
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
|
||||
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
||||
|
||||
#ifdef CONFIG_ARCH_B4860
|
||||
#define CONFIG_MAX_DSP_CPUS 12
|
||||
#define CONFIG_NUM_DSP_CPUS 6
|
||||
#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 6
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 2
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CONFIG_SYS_FSL_SRIO_LIODN
|
||||
#else
|
||||
#define CONFIG_MAX_DSP_CPUS 2
|
||||
#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 4
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 0
|
||||
#endif
|
||||
|
||||
#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
|
||||
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
|
@ -231,18 +178,12 @@
|
|||
#define CONFIG_FM_PLAT_CLK_DIV 1
|
||||
#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
|
||||
#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
|
||||
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
|
||||
#define QE_MURAM_SIZE 0x6000UL
|
||||
#define MAX_QE_RISC 1
|
||||
#define QE_NUM_OF_SNUM 28
|
||||
|
||||
#elif defined(CONFIG_ARCH_T1024)
|
||||
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLL 2
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
|
@ -254,19 +195,12 @@
|
|||
#define CONFIG_SYS_FM1_CLK 0
|
||||
#define CONFIG_QBMAN_CLK_DIV 1
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
|
||||
#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
|
||||
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
|
||||
#define QE_MURAM_SIZE 0x6000UL
|
||||
#define MAX_QE_RISC 1
|
||||
#define QE_NUM_OF_SNUM 28
|
||||
|
||||
#elif defined(CONFIG_ARCH_T2080)
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
#define CONFIG_SYS_FSL_QMAN_V3
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
|
@ -274,7 +208,6 @@
|
|||
#define CONFIG_SYS_NUM_FM1_DTSEC 8
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 4
|
||||
#define CONFIG_SYS_FSL_SRDS_2
|
||||
#define CONFIG_SYS_FSL_SRIO_LIODN
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
|
@ -284,11 +217,6 @@
|
|||
#define CONFIG_SYS_FM1_CLK 0
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
|
||||
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define CONFIG_SYS_FSL_ISBC_VER 2
|
||||
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
|
||||
|
||||
|
||||
|
@ -296,13 +224,8 @@
|
|||
#define CONFIG_FSL_SDHC_V2_3
|
||||
#define CONFIG_TSECV2_1
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
|
||||
#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
|
||||
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_ARCH_C29X)
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_MPC85xx_CONFIG_H_ */
|
||||
|
|
|
@ -1464,7 +1464,6 @@ typedef struct ccsr_gur {
|
|||
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
|
||||
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
|
||||
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080
|
||||
#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
|
||||
#define PXCKEN_MASK 0x80000000
|
||||
#define PXCK_MASK 0x00FF0000
|
||||
#define PXCK_BITS_START 16
|
||||
|
@ -1477,8 +1476,6 @@ typedef struct ccsr_gur {
|
|||
#define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000
|
||||
#define FSL_CORENET_RCWSR13_EC2 0x0c000000
|
||||
#define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000
|
||||
#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
|
||||
#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00
|
||||
#define PXCKEN_MASK 0x80000000
|
||||
#define PXCK_MASK 0x00FF0000
|
||||
#define PXCK_BITS_START 16
|
||||
|
@ -2576,20 +2573,10 @@ struct ccsr_pman {
|
|||
#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
|
||||
#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
|
||||
|
||||
#if defined(CONFIG_ARCH_BSC9132)
|
||||
#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
|
||||
#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
|
||||
(CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FSL_CPC_ADDR \
|
||||
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
|
||||
#define CONFIG_SYS_FSL_SCFG_ADDR \
|
||||
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
|
||||
#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \
|
||||
(CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
|
||||
#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \
|
||||
(CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET)
|
||||
#define CONFIG_SYS_FSL_QMAN_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
|
||||
#define CONFIG_SYS_FSL_BMAN_ADDR \
|
||||
|
|
|
@ -179,9 +179,6 @@ extern void dram_query(void);
|
|||
int board_eth_init(struct bd_info *bis)
|
||||
{
|
||||
int rc = 0;
|
||||
#ifdef CONFIG_SMC91111
|
||||
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
|
||||
#endif
|
||||
return rc;
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -200,9 +200,6 @@ int board_eth_init(struct bd_info *bis)
|
|||
{
|
||||
int rc = 0;
|
||||
#ifndef CONFIG_DM_ETH
|
||||
#ifdef CONFIG_SMC91111
|
||||
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
|
||||
#endif
|
||||
#ifdef CONFIG_SMC911X
|
||||
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
|
||||
#endif
|
||||
|
|
|
@ -1,12 +0,0 @@
|
|||
if TARGET_SNAPPER9260
|
||||
|
||||
config SYS_BOARD
|
||||
default "snapper9260"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "bluewater"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "snapper9260"
|
||||
|
||||
endif
|
|
@ -1,7 +0,0 @@
|
|||
SNAPPER9260 BOARD
|
||||
M: Simon Glass <sjg@chromium.org>
|
||||
S: Maintained
|
||||
F: board/bluewater/snapper9260/
|
||||
F: include/configs/snapper9260.h
|
||||
F: configs/snapper9260_defconfig
|
||||
F: configs/snapper9g20_defconfig
|
|
@ -1,9 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2003-2008
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# (C) Copyright 2011 Bluewater Systems
|
||||
# Ryan Mallon <ryan@bluewatersys.com>
|
||||
|
||||
obj-y += snapper9260.o
|
|
@ -1,154 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Bluewater Systems Snapper 9260/9G20 modules
|
||||
*
|
||||
* (C) Copyright 2011 Bluewater Systems
|
||||
* Author: Andre Renaud <andre@bluewatersys.com>
|
||||
* Author: Ryan Mallon <ryan@bluewatersys.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <init.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/arch/at91sam9260_matrix.h>
|
||||
#include <asm/arch/at91sam9_smc.h>
|
||||
#include <asm/arch/at91_common.h>
|
||||
#include <asm/arch/clk.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/atmel_serial.h>
|
||||
#include <net.h>
|
||||
#include <netdev.h>
|
||||
#include <i2c.h>
|
||||
#include <pca953x.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* IO Expander pins */
|
||||
#define IO_EXP_ETH_RESET (0 << 1)
|
||||
#define IO_EXP_ETH_POWER (1 << 1)
|
||||
|
||||
static void macb_hw_init(void)
|
||||
{
|
||||
struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
|
||||
|
||||
at91_periph_clk_enable(ATMEL_ID_EMAC0);
|
||||
|
||||
/* Disable pull-ups to prevent PHY going into test mode */
|
||||
writel(pin_to_mask(AT91_PIN_PA14) |
|
||||
pin_to_mask(AT91_PIN_PA15) |
|
||||
pin_to_mask(AT91_PIN_PA18),
|
||||
&pioa->pudr);
|
||||
|
||||
/* Power down ethernet */
|
||||
pca953x_set_dir(0x28, IO_EXP_ETH_POWER, PCA953X_DIR_OUT);
|
||||
pca953x_set_val(0x28, IO_EXP_ETH_POWER, 1);
|
||||
|
||||
/* Hold ethernet in reset */
|
||||
pca953x_set_dir(0x28, IO_EXP_ETH_RESET, PCA953X_DIR_OUT);
|
||||
pca953x_set_val(0x28, IO_EXP_ETH_RESET, 0);
|
||||
|
||||
/* Enable ethernet power */
|
||||
pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);
|
||||
|
||||
at91_phy_reset();
|
||||
|
||||
/* Bring the ethernet out of reset */
|
||||
pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);
|
||||
|
||||
/* The phy internal reset take 21ms */
|
||||
udelay(21 * 1000);
|
||||
|
||||
/* Re-enable pull-up */
|
||||
writel(pin_to_mask(AT91_PIN_PA14) |
|
||||
pin_to_mask(AT91_PIN_PA15) |
|
||||
pin_to_mask(AT91_PIN_PA18),
|
||||
&pioa->puer);
|
||||
|
||||
at91_macb_hw_init();
|
||||
}
|
||||
|
||||
static void nand_hw_init(void)
|
||||
{
|
||||
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
|
||||
struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
|
||||
unsigned long csa;
|
||||
|
||||
/* Enable CS3 as NAND/SmartMedia */
|
||||
csa = readl(&matrix->ebicsa);
|
||||
csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
|
||||
writel(csa, &matrix->ebicsa);
|
||||
|
||||
/* Configure SMC CS3 for NAND/SmartMedia */
|
||||
writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
|
||||
AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
|
||||
&smc->cs[3].setup);
|
||||
writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
|
||||
AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
|
||||
&smc->cs[3].pulse);
|
||||
writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
|
||||
&smc->cs[3].cycle);
|
||||
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
|
||||
AT91_SMC_MODE_EXNW_DISABLE |
|
||||
AT91_SMC_MODE_DBW_8 |
|
||||
AT91_SMC_MODE_TDF_CYCLE(3),
|
||||
&smc->cs[3].mode);
|
||||
|
||||
/* Configure RDY/BSY */
|
||||
gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
|
||||
gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
|
||||
|
||||
/* Enable NandFlash */
|
||||
gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
|
||||
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOA);
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOB);
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOC);
|
||||
|
||||
/* The mach-type is the same for both Snapper 9260 and 9G20 */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
|
||||
|
||||
/* Address of boot parameters */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
/* Initialise peripherals */
|
||||
at91_seriald_hw_init();
|
||||
i2c_set_bus_num(0);
|
||||
nand_hw_init();
|
||||
macb_hw_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(struct bd_info *bis)
|
||||
{
|
||||
return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x1f);
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
|
||||
CONFIG_SYS_SDRAM_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void reset_phy(void)
|
||||
{
|
||||
}
|
||||
|
||||
static struct atmel_serial_plat at91sam9260_serial_plat = {
|
||||
.base_addr = ATMEL_BASE_DBGU,
|
||||
};
|
||||
|
||||
U_BOOT_DRVINFO(at91sam9260_serial) = {
|
||||
.name = "serial_atmel",
|
||||
.plat = &at91sam9260_serial_plat,
|
||||
};
|
10
board/dhelectronics/common/Makefile
Normal file
10
board/dhelectronics/common/Makefile
Normal file
|
@ -0,0 +1,10 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
|
||||
#
|
||||
|
||||
obj-y += dh_common.o
|
||||
|
||||
ifneq (,$(CONFIG_ARCH_MX6)$(CONFIG_ARCH_IMX8M))
|
||||
obj-y += dh_imx.o
|
||||
endif
|
65
board/dhelectronics/common/dh_common.c
Normal file
65
board/dhelectronics/common/dh_common.c
Normal file
|
@ -0,0 +1,65 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2022 Marek Vasut <marex@denx.de>
|
||||
* Copyright 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <i2c_eeprom.h>
|
||||
#include <net.h>
|
||||
|
||||
#include "dh_common.h"
|
||||
|
||||
bool dh_mac_is_in_env(const char *env)
|
||||
{
|
||||
unsigned char enetaddr[6];
|
||||
|
||||
return eth_env_get_enetaddr(env, enetaddr);
|
||||
}
|
||||
|
||||
int dh_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
ofnode node;
|
||||
|
||||
node = ofnode_path(alias);
|
||||
if (!ofnode_valid(node)) {
|
||||
printf("%s: ofnode for %s not found!", __func__, alias);
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, node, &dev);
|
||||
if (ret) {
|
||||
printf("%s: Cannot find EEPROM! ret = %d\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
|
||||
if (ret) {
|
||||
printf("%s: Error reading EEPROM! ret = %d\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (!is_valid_ethaddr(enetaddr)) {
|
||||
printf("%s: Address read from EEPROM is invalid!\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
__weak int dh_setup_mac_address(void)
|
||||
{
|
||||
unsigned char enetaddr[6];
|
||||
|
||||
if (dh_mac_is_in_env("ethaddr"))
|
||||
return 0;
|
||||
|
||||
if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
|
||||
return eth_env_set_enetaddr("ethaddr", enetaddr);
|
||||
|
||||
printf("%s: Unable to set mac address!\n", __func__);
|
||||
return -ENXIO;
|
||||
}
|
28
board/dhelectronics/common/dh_common.h
Normal file
28
board/dhelectronics/common/dh_common.h
Normal file
|
@ -0,0 +1,28 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Copyright 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
|
||||
*/
|
||||
|
||||
/*
|
||||
* dh_mac_is_in_env - Check if MAC address is already set
|
||||
*
|
||||
* @env: name of environment variable
|
||||
* Return: true if MAC is set, false otherwise
|
||||
*/
|
||||
bool dh_mac_is_in_env(const char *env);
|
||||
|
||||
/*
|
||||
* dh_get_mac_from_eeprom - Get MAC address from eeprom and write it to enetaddr
|
||||
*
|
||||
* @enetaddr: buffer where address is to be stored
|
||||
* @alias: alias for EEPROM device tree node
|
||||
* Return: 0 if OK, other value on error
|
||||
*/
|
||||
int dh_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias);
|
||||
|
||||
/*
|
||||
* dh_setup_mac_address - Try to get MAC address from various locations and write it to env
|
||||
*
|
||||
* Return: 0 if OK, other value on error
|
||||
*/
|
||||
int dh_setup_mac_address(void);
|
24
board/dhelectronics/common/dh_imx.c
Normal file
24
board/dhelectronics/common/dh_imx.c
Normal file
|
@ -0,0 +1,24 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2022 Marek Vasut <marex@denx.de>
|
||||
* Copyright 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
|
||||
*/
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <common.h>
|
||||
#include <net.h>
|
||||
#include "dh_imx.h"
|
||||
|
||||
int dh_imx_get_mac_from_fuse(unsigned char *enetaddr)
|
||||
{
|
||||
/*
|
||||
* If IIM fuses contain valid MAC address, use it.
|
||||
* The IIM MAC address fuses are NOT programmed by default.
|
||||
*/
|
||||
imx_get_mac_from_fuse(0, enetaddr);
|
||||
if (!is_valid_ethaddr(enetaddr))
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
12
board/dhelectronics/common/dh_imx.h
Normal file
12
board/dhelectronics/common/dh_imx.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Copyright 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
|
||||
*/
|
||||
|
||||
/*
|
||||
* dh_imx_get_mac_from_fuse - Get MAC address from fuse and write it to env
|
||||
*
|
||||
* @enetaddr: buffer where address is to be stored
|
||||
* Return: 0 if OK, other value on error
|
||||
*/
|
||||
int dh_imx_get_mac_from_fuse(unsigned char *enetaddr);
|
|
@ -36,6 +36,9 @@
|
|||
#include <linux/delay.h>
|
||||
#include <usb/ehci-ci.h>
|
||||
|
||||
#include "../common/dh_common.h"
|
||||
#include "../common/dh_imx.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int dram_init(void)
|
||||
|
@ -82,46 +85,24 @@ int board_usb_phy_mode(int port)
|
|||
}
|
||||
#endif
|
||||
|
||||
static int setup_dhcom_mac_from_fuse(void)
|
||||
int dh_setup_mac_address(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
ofnode eeprom;
|
||||
unsigned char enetaddr[6];
|
||||
int ret;
|
||||
|
||||
ret = eth_env_get_enetaddr("ethaddr", enetaddr);
|
||||
if (ret) /* ethaddr is already set */
|
||||
if (dh_mac_is_in_env("ethaddr"))
|
||||
return 0;
|
||||
|
||||
imx_get_mac_from_fuse(0, enetaddr);
|
||||
if (!dh_imx_get_mac_from_fuse(enetaddr))
|
||||
goto out;
|
||||
|
||||
if (is_valid_ethaddr(enetaddr)) {
|
||||
eth_env_set_enetaddr("ethaddr", enetaddr);
|
||||
return 0;
|
||||
}
|
||||
if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
|
||||
goto out;
|
||||
|
||||
eeprom = ofnode_get_aliases_node("eeprom0");
|
||||
if (!ofnode_valid(eeprom)) {
|
||||
printf("Can't find eeprom0 alias!\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
printf("%s: Unable to get MAC address!\n", __func__);
|
||||
return -ENXIO;
|
||||
|
||||
ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
|
||||
if (ret) {
|
||||
printf("Cannot find EEPROM!\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
|
||||
if (ret) {
|
||||
printf("Error reading configuration EEPROM!\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (is_valid_ethaddr(enetaddr))
|
||||
eth_env_set_enetaddr("ethaddr", enetaddr);
|
||||
|
||||
return 0;
|
||||
out:
|
||||
return eth_env_set_enetaddr("ethaddr", enetaddr);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
|
@ -188,7 +169,7 @@ int board_late_init(void)
|
|||
u32 hw_code;
|
||||
char buf[16];
|
||||
|
||||
setup_dhcom_mac_from_fuse();
|
||||
dh_setup_mac_address();
|
||||
|
||||
hw_code = board_get_hwcode();
|
||||
|
||||
|
|
|
@ -16,6 +16,8 @@
|
|||
#include <miiphy.h>
|
||||
|
||||
#include "lpddr4_timing.h"
|
||||
#include "../common/dh_common.h"
|
||||
#include "../common/dh_imx.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -75,95 +77,68 @@ static void setup_fec(void)
|
|||
set_clk_enet(ENET_125MHZ);
|
||||
}
|
||||
|
||||
static int setup_mac_address_from_eeprom(char *alias, char *env, bool odd)
|
||||
static int dh_imx8_setup_ethaddr(void)
|
||||
{
|
||||
unsigned char enetaddr[6];
|
||||
struct udevice *dev;
|
||||
int ret, offset;
|
||||
|
||||
offset = fdt_path_offset(gd->fdt_blob, alias);
|
||||
if (offset < 0) {
|
||||
printf("%s: No eeprom0 path offset\n", __func__);
|
||||
return offset;
|
||||
}
|
||||
if (dh_mac_is_in_env("ethaddr"))
|
||||
return 0;
|
||||
|
||||
ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, offset, &dev);
|
||||
if (ret) {
|
||||
printf("Cannot find EEPROM!\n");
|
||||
return ret;
|
||||
}
|
||||
if (!dh_imx_get_mac_from_fuse(enetaddr))
|
||||
goto out;
|
||||
|
||||
ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
|
||||
if (ret) {
|
||||
printf("Error reading configuration EEPROM!\n");
|
||||
return ret;
|
||||
}
|
||||
if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
|
||||
goto out;
|
||||
|
||||
return -ENXIO;
|
||||
|
||||
out:
|
||||
return eth_env_set_enetaddr("ethaddr", enetaddr);
|
||||
}
|
||||
|
||||
static int dh_imx8_setup_eth1addr(void)
|
||||
{
|
||||
unsigned char enetaddr[6];
|
||||
|
||||
if (dh_mac_is_in_env("eth1addr"))
|
||||
return 0;
|
||||
|
||||
if (!dh_imx_get_mac_from_fuse(enetaddr))
|
||||
goto increment_out;
|
||||
|
||||
if (!dh_get_mac_from_eeprom(enetaddr, "eeprom1"))
|
||||
goto out;
|
||||
|
||||
/*
|
||||
* Populate second ethernet MAC from first ethernet EEPROM with MAC
|
||||
* address LSByte incremented by 1. This is only used on SoMs without
|
||||
* second ethernet EEPROM, i.e. early prototypes.
|
||||
*/
|
||||
if (odd)
|
||||
enetaddr[5]++;
|
||||
if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
|
||||
goto increment_out;
|
||||
|
||||
eth_env_set_enetaddr(env, enetaddr);
|
||||
return -ENXIO;
|
||||
|
||||
return 0;
|
||||
increment_out:
|
||||
enetaddr[5]++;
|
||||
|
||||
out:
|
||||
return eth_env_set_enetaddr("eth1addr", enetaddr);
|
||||
}
|
||||
|
||||
static void setup_mac_address(void)
|
||||
int dh_setup_mac_address(void)
|
||||
{
|
||||
unsigned char enetaddr[6];
|
||||
bool skip_eth0 = false;
|
||||
bool skip_eth1 = false;
|
||||
int ret;
|
||||
|
||||
ret = eth_env_get_enetaddr("ethaddr", enetaddr);
|
||||
if (ret) /* ethaddr is already set */
|
||||
skip_eth0 = true;
|
||||
ret = dh_imx8_setup_ethaddr();
|
||||
if (ret)
|
||||
printf("%s: Unable to setup ethaddr! ret = %d\n", __func__, ret);
|
||||
|
||||
ret = eth_env_get_enetaddr("eth1addr", enetaddr);
|
||||
if (ret) /* eth1addr is already set */
|
||||
skip_eth1 = true;
|
||||
ret = dh_imx8_setup_eth1addr();
|
||||
if (ret)
|
||||
printf("%s: Unable to setup eth1addr! ret = %d\n", __func__, ret);
|
||||
|
||||
/* Both MAC addresses are already set in U-Boot environment. */
|
||||
if (skip_eth0 && skip_eth1)
|
||||
return;
|
||||
|
||||
/*
|
||||
* If IIM fuses contain valid MAC address, use it.
|
||||
* The IIM MAC address fuses are NOT programmed by default.
|
||||
*/
|
||||
imx_get_mac_from_fuse(0, enetaddr);
|
||||
if (is_valid_ethaddr(enetaddr)) {
|
||||
if (!skip_eth0)
|
||||
eth_env_set_enetaddr("ethaddr", enetaddr);
|
||||
/*
|
||||
* The LSbit of MAC address in fuses is always 0, use the
|
||||
* next consecutive MAC address for the second ethernet.
|
||||
*/
|
||||
enetaddr[5]++;
|
||||
if (!skip_eth1)
|
||||
eth_env_set_enetaddr("eth1addr", enetaddr);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Use on-SoM EEPROMs with pre-programmed MAC address. */
|
||||
if (!skip_eth0) {
|
||||
/* We cannot do much more if this returns -ve . */
|
||||
setup_mac_address_from_eeprom("eeprom0", "ethaddr", false);
|
||||
}
|
||||
|
||||
if (!skip_eth1) {
|
||||
ret = setup_mac_address_from_eeprom("eeprom1", "eth1addr",
|
||||
false);
|
||||
if (ret) { /* Second EEPROM might not be populated. */
|
||||
/* We cannot do much more if this returns -ve . */
|
||||
setup_mac_address_from_eeprom("eeprom0", "eth1addr",
|
||||
true);
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
|
@ -176,7 +151,7 @@ int board_init(void)
|
|||
|
||||
int board_late_init(void)
|
||||
{
|
||||
setup_mac_address();
|
||||
dh_setup_mac_address();
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -42,6 +42,7 @@
|
|||
#include <usb/dwc2_udc.h>
|
||||
#include <watchdog.h>
|
||||
#include <dm/ofnode.h>
|
||||
#include "../common/dh_common.h"
|
||||
#include "../../st/common/stpmic1.h"
|
||||
|
||||
/* SYSCFG registers */
|
||||
|
@ -84,36 +85,17 @@
|
|||
#define KS_CIDER 0xC0
|
||||
#define CIDER_ID 0x8870
|
||||
|
||||
int setup_mac_address(void)
|
||||
static bool dh_stm32_mac_is_in_ks8851(void)
|
||||
{
|
||||
unsigned char enetaddr[6];
|
||||
bool skip_eth0 = false;
|
||||
bool skip_eth1 = false;
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
ofnode node;
|
||||
|
||||
ret = eth_env_get_enetaddr("ethaddr", enetaddr);
|
||||
if (ret) /* ethaddr is already set */
|
||||
skip_eth0 = true;
|
||||
u32 reg, cider, ccr;
|
||||
|
||||
node = ofnode_path("ethernet1");
|
||||
if (!ofnode_valid(node)) {
|
||||
/* ethernet1 is not present in the system */
|
||||
skip_eth1 = true;
|
||||
goto out_set_ethaddr;
|
||||
}
|
||||
if (!ofnode_valid(node))
|
||||
return false;
|
||||
|
||||
ret = eth_env_get_enetaddr("eth1addr", enetaddr);
|
||||
if (ret) {
|
||||
/* eth1addr is already set */
|
||||
skip_eth1 = true;
|
||||
goto out_set_ethaddr;
|
||||
}
|
||||
|
||||
ret = ofnode_device_is_compatible(node, "micrel,ks8851-mll");
|
||||
if (ret)
|
||||
goto out_set_ethaddr;
|
||||
if (ofnode_device_is_compatible(node, "micrel,ks8851-mll"))
|
||||
return false;
|
||||
|
||||
/*
|
||||
* KS8851 with EEPROM may use custom MAC from EEPROM, read
|
||||
|
@ -121,56 +103,62 @@ int setup_mac_address(void)
|
|||
* is present. If EEPROM is present, it must contain valid
|
||||
* MAC address.
|
||||
*/
|
||||
u32 reg, cider, ccr;
|
||||
reg = ofnode_get_addr(node);
|
||||
if (!reg)
|
||||
goto out_set_ethaddr;
|
||||
return false;
|
||||
|
||||
writew(KS_BE0 | KS_BE1 | KS_CIDER, reg + 2);
|
||||
cider = readw(reg);
|
||||
if ((cider & 0xfff0) != CIDER_ID) {
|
||||
skip_eth1 = true;
|
||||
goto out_set_ethaddr;
|
||||
}
|
||||
if ((cider & 0xfff0) != CIDER_ID)
|
||||
return true;
|
||||
|
||||
writew(KS_BE0 | KS_BE1 | KS_CCR, reg + 2);
|
||||
ccr = readw(reg);
|
||||
if (ccr & KS_CCR_EEPROM) {
|
||||
skip_eth1 = true;
|
||||
goto out_set_ethaddr;
|
||||
}
|
||||
if (ccr & KS_CCR_EEPROM)
|
||||
return true;
|
||||
|
||||
out_set_ethaddr:
|
||||
if (skip_eth0 && skip_eth1)
|
||||
return false;
|
||||
}
|
||||
|
||||
static int dh_stm32_setup_ethaddr(void)
|
||||
{
|
||||
unsigned char enetaddr[6];
|
||||
|
||||
if (dh_mac_is_in_env("ethaddr"))
|
||||
return 0;
|
||||
|
||||
node = ofnode_path("eeprom0");
|
||||
if (!ofnode_valid(node)) {
|
||||
printf("%s: No eeprom0 path offset\n", __func__);
|
||||
return -ENOENT;
|
||||
}
|
||||
if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
|
||||
return eth_env_set_enetaddr("ethaddr", enetaddr);
|
||||
|
||||
ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, node, &dev);
|
||||
if (ret) {
|
||||
printf("Cannot find EEPROM!\n");
|
||||
return ret;
|
||||
}
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
|
||||
if (ret) {
|
||||
printf("Error reading configuration EEPROM!\n");
|
||||
return ret;
|
||||
}
|
||||
static int dh_stm32_setup_eth1addr(void)
|
||||
{
|
||||
unsigned char enetaddr[6];
|
||||
|
||||
if (is_valid_ethaddr(enetaddr)) {
|
||||
if (!skip_eth0)
|
||||
eth_env_set_enetaddr("ethaddr", enetaddr);
|
||||
if (dh_mac_is_in_env("eth1addr"))
|
||||
return 0;
|
||||
|
||||
if (dh_stm32_mac_is_in_ks8851())
|
||||
return 0;
|
||||
|
||||
if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0")) {
|
||||
enetaddr[5]++;
|
||||
if (!skip_eth1)
|
||||
eth_env_set_enetaddr("eth1addr", enetaddr);
|
||||
return eth_env_set_enetaddr("eth1addr", enetaddr);
|
||||
}
|
||||
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
int setup_mac_address(void)
|
||||
{
|
||||
if (dh_stm32_setup_ethaddr())
|
||||
log_err("%s: Unable to setup ethaddr!\n", __func__);
|
||||
|
||||
if (dh_stm32_setup_eth1addr())
|
||||
log_err("%s: Unable to setup eth1addr!\n", __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -1,12 +0,0 @@
|
|||
if TARGET_IDS8313
|
||||
|
||||
config SYS_BOARD
|
||||
default "ids8313"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "ids"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "ids8313"
|
||||
|
||||
endif
|
|
@ -1,6 +0,0 @@
|
|||
IDS8313 BOARD
|
||||
M: Heiko Schocher <hs@denx.de>
|
||||
S: Maintained
|
||||
F: board/ids/ids8313/
|
||||
F: include/configs/ids8313.h
|
||||
F: configs/ids8313_defconfig
|
|
@ -1,9 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# (C) Copyright 2013
|
||||
# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
|
||||
|
||||
obj-y = ids8313.o
|
|
@ -1,216 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2013
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* Based on:
|
||||
* Copyright (c) 2011 IDS GmbH, Germany
|
||||
* ids8313.c - ids8313 board support.
|
||||
*
|
||||
* Sergej Stepanov <ste@ids.de>
|
||||
* Based on board/freescale/mpc8313erdb/mpc8313erdb.c
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <fdt_support.h>
|
||||
#include <init.h>
|
||||
#include <mpc83xx.h>
|
||||
#include <spi.h>
|
||||
#include <asm/bitops.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/libfdt.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
/** CPLD contains the info about:
|
||||
* - board type: *pCpld & 0xF0
|
||||
* - hw-revision: *pCpld & 0x0F
|
||||
* - cpld-revision: *pCpld+1
|
||||
*/
|
||||
int checkboard(void)
|
||||
{
|
||||
char *pcpld = (char *)CONFIG_SYS_CPLD_BASE;
|
||||
u8 u8Vers = readb(pcpld);
|
||||
u8 u8Revs = readb(pcpld + 1);
|
||||
|
||||
printf("Board: ");
|
||||
switch (u8Vers & 0xF0) {
|
||||
case '\x40':
|
||||
printf("CU73X");
|
||||
break;
|
||||
case '\x50':
|
||||
printf("CC73X");
|
||||
break;
|
||||
default:
|
||||
printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs);
|
||||
return 0;
|
||||
}
|
||||
printf("\nInfo: HW-Rev: %i, CPLD-Rev: %i\n",
|
||||
u8Vers & 0x0F, u8Revs & 0xFF);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* fixed sdram init
|
||||
*/
|
||||
int fixed_sdram(unsigned long config)
|
||||
{
|
||||
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
||||
u32 msize = CONFIG_SYS_SDRAM_SIZE;
|
||||
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
u32 msize_log2 = __ilog2(msize);
|
||||
|
||||
out_be32(&im->sysconf.ddrlaw[0].bar,
|
||||
(CONFIG_SYS_SDRAM_BASE & 0xfffff000));
|
||||
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
|
||||
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
|
||||
sync();
|
||||
|
||||
/*
|
||||
* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
|
||||
* or the DDR2 controller may fail to initialize correctly.
|
||||
*/
|
||||
udelay(50000);
|
||||
|
||||
out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
|
||||
out_be32(&im->ddr.cs_config[0], config);
|
||||
|
||||
/* currently we use only one CS, so disable the other banks */
|
||||
out_be32(&im->ddr.cs_config[1], 0);
|
||||
out_be32(&im->ddr.cs_config[2], 0);
|
||||
out_be32(&im->ddr.cs_config[3], 0);
|
||||
|
||||
out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
|
||||
out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
|
||||
out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
|
||||
out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
|
||||
|
||||
out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
|
||||
out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
|
||||
|
||||
out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
|
||||
out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
|
||||
|
||||
out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
|
||||
out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
|
||||
sync();
|
||||
udelay(300);
|
||||
|
||||
/* enable DDR controller */
|
||||
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
|
||||
/* now check the real size */
|
||||
disable_addr_trans();
|
||||
msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
|
||||
enable_addr_trans();
|
||||
#endif
|
||||
return msize;
|
||||
}
|
||||
|
||||
static int setup_sdram(void)
|
||||
{
|
||||
u32 msize = CONFIG_SYS_SDRAM_SIZE;
|
||||
long int size_01, size_02;
|
||||
|
||||
size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
|
||||
size_02 = fixed_sdram(CONFIG_SYS_DDR_CONFIG_256);
|
||||
|
||||
if (size_01 > size_02)
|
||||
msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
|
||||
else
|
||||
msize = size_02;
|
||||
|
||||
return msize;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
||||
fsl_lbc_t *lbc = &im->im_lbc;
|
||||
u32 msize = 0;
|
||||
|
||||
if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
|
||||
return -ENXIO;
|
||||
|
||||
msize = setup_sdram();
|
||||
|
||||
out_be32(&lbc->lbcr, (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF));
|
||||
out_be32(&lbc->mrtpr, 0x20000000);
|
||||
sync();
|
||||
|
||||
gd->ram_size = msize;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
||||
{
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* gpio mask for spi_cs */
|
||||
#define IDSCPLD_SPI_CS_MASK 0x00000001
|
||||
/* spi_cs multiplexed through cpld */
|
||||
#define IDSCPLD_SPI_CS_BASE (CONFIG_SYS_CPLD_BASE + 0xf)
|
||||
|
||||
#if defined(CONFIG_MISC_INIT_R)
|
||||
/* srp umcr mask for rts */
|
||||
#define IDSUMCR_RTS_MASK 0x04
|
||||
int misc_init_r(void)
|
||||
{
|
||||
/*srp*/
|
||||
duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0];
|
||||
duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1];
|
||||
|
||||
gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
|
||||
u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
|
||||
|
||||
/* deactivate spi_cs channels */
|
||||
out_8(spi_base, 0);
|
||||
/* deactivate the spi_cs */
|
||||
setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK);
|
||||
/*srp - deactivate rts*/
|
||||
out_8(&uart1->umcr, IDSUMCR_RTS_MASK);
|
||||
out_8(&uart2->umcr, IDSUMCR_RTS_MASK);
|
||||
|
||||
|
||||
gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE;
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MPC8XXX_SPI
|
||||
/*
|
||||
* The following are used to control the SPI chip selects
|
||||
*/
|
||||
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
|
||||
{
|
||||
return bus == 0 && ((cs >= 0) && (cs <= 2));
|
||||
}
|
||||
|
||||
void spi_cs_activate(struct spi_slave *slave)
|
||||
{
|
||||
gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
|
||||
u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
|
||||
|
||||
/* select the spi_cs channel */
|
||||
out_8(spi_base, 1 << slave->cs);
|
||||
/* activate the spi_cs */
|
||||
clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
|
||||
}
|
||||
|
||||
void spi_cs_deactivate(struct spi_slave *slave)
|
||||
{
|
||||
gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
|
||||
u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
|
||||
|
||||
/* select the spi_cs channel */
|
||||
out_8(spi_base, 1 << slave->cs);
|
||||
/* deactivate the spi_cs */
|
||||
setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
|
||||
}
|
||||
#endif
|
|
@ -24,10 +24,6 @@
|
|||
#include <dm/ofnode.h>
|
||||
#include <tee/optee.h>
|
||||
|
||||
#ifndef CONFIG_SYS_FDT_PAD
|
||||
#define CONFIG_SYS_FDT_PAD 0x3000
|
||||
#endif
|
||||
|
||||
/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
|
||||
#define FDT_RAMDISK_OVERHEAD 0x80
|
||||
|
||||
|
|
|
@ -13,6 +13,7 @@ CONFIG_SYS_CACHE_STASHING=y
|
|||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -13,6 +13,7 @@ CONFIG_SYS_CACHE_STASHING=y
|
|||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -14,6 +14,7 @@ CONFIG_SYS_CACHE_STASHING=y
|
|||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -14,6 +14,7 @@ CONFIG_SYS_CACHE_STASHING=y
|
|||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -14,6 +14,7 @@ CONFIG_PCIE1=y
|
|||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -14,6 +14,7 @@ CONFIG_PCIE1=y
|
|||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -15,6 +15,7 @@ CONFIG_PCIE1=y
|
|||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -15,6 +15,7 @@ CONFIG_PCIE1=y
|
|||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -13,6 +13,7 @@ CONFIG_SYS_CACHE_STASHING=y
|
|||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=4
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -14,6 +14,7 @@ CONFIG_SYS_CACHE_STASHING=y
|
|||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=4
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -14,6 +14,7 @@ CONFIG_SYS_CACHE_STASHING=y
|
|||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=4
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -13,6 +13,7 @@ CONFIG_SYS_CACHE_STASHING=y
|
|||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -13,6 +13,7 @@ CONFIG_SYS_CACHE_STASHING=y
|
|||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -14,6 +14,7 @@ CONFIG_SYS_CACHE_STASHING=y
|
|||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -14,6 +14,7 @@ CONFIG_SYS_CACHE_STASHING=y
|
|||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -20,6 +20,7 @@ CONFIG_PCIE1=y
|
|||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -20,6 +20,7 @@ CONFIG_PCIE1=y
|
|||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -22,6 +22,7 @@ CONFIG_PCIE1=y
|
|||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -14,6 +14,7 @@ CONFIG_PCIE1=y
|
|||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -25,6 +25,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_FSL_QIXIS=y
|
||||
# CONFIG_QIXIS_I2C_ACCESS is not set
|
||||
CONFIG_MP=y
|
||||
|
|
|
@ -25,6 +25,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_FSL_QIXIS=y
|
||||
# CONFIG_QIXIS_I2C_ACCESS is not set
|
||||
CONFIG_MP=y
|
||||
|
|
|
@ -19,6 +19,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_FSL_QIXIS=y
|
||||
# CONFIG_QIXIS_I2C_ACCESS is not set
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
|
|
|
@ -27,6 +27,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_FSL_QIXIS=y
|
||||
# CONFIG_QIXIS_I2C_ACCESS is not set
|
||||
CONFIG_MP=y
|
||||
|
|
|
@ -19,6 +19,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_FSL_QIXIS=y
|
||||
# CONFIG_QIXIS_I2C_ACCESS is not set
|
||||
CONFIG_MP=y
|
||||
|
|
|
@ -19,6 +19,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_FSL_QIXIS=y
|
||||
# CONFIG_QIXIS_I2C_ACCESS is not set
|
||||
CONFIG_MP=y
|
||||
|
|
|
@ -24,6 +24,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
|
|
@ -24,6 +24,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
|
|
@ -26,6 +26,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
|
|
@ -18,6 +18,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
|
|
@ -25,6 +25,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
|
|
@ -25,6 +25,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
|
|
@ -27,6 +27,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
|
|
@ -19,6 +19,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
|
|
@ -24,6 +24,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=5
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -18,6 +18,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=5
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -1,216 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0xFFF00000
|
||||
CONFIG_SYS_MALLOC_LEN=0x800000
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_SYS_BOOTCOUNT_ADDR=0x9
|
||||
CONFIG_SYS_CLK_FREQ=66000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x100000
|
||||
CONFIG_ENV_ADDR=0xFFFC0000
|
||||
CONFIG_MPC83xx=y
|
||||
CONFIG_HIGH_BATS=y
|
||||
CONFIG_TARGET_IDS8313=y
|
||||
CONFIG_CORE_PLL_RATIO_2_1=y
|
||||
CONFIG_PCI_HOST_MODE_ENABLE=y
|
||||
CONFIG_BOOT_ROM_INTERFACE_GPCM_8BIT=y
|
||||
CONFIG_BAT0=y
|
||||
CONFIG_BAT0_NAME="SDRAM"
|
||||
CONFIG_BAT0_BASE=0x00000000
|
||||
CONFIG_BAT0_LENGTH_256_MBYTES=y
|
||||
CONFIG_BAT0_ACCESS_RW=y
|
||||
CONFIG_BAT0_USER_MODE_VALID=y
|
||||
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_BAT1=y
|
||||
CONFIG_BAT1_NAME="INITRAM"
|
||||
CONFIG_BAT1_BASE=0xFD000000
|
||||
CONFIG_BAT1_LENGTH_256_KBYTES=y
|
||||
CONFIG_BAT1_ACCESS_RW=y
|
||||
CONFIG_BAT1_ICACHE_GUARDED=y
|
||||
CONFIG_BAT1_DCACHE_GUARDED=y
|
||||
CONFIG_BAT1_USER_MODE_VALID=y
|
||||
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_BAT2=y
|
||||
CONFIG_BAT2_NAME="FLASH"
|
||||
CONFIG_BAT2_BASE=0xFF800000
|
||||
CONFIG_BAT2_LENGTH_8_MBYTES=y
|
||||
CONFIG_BAT2_ACCESS_RW=y
|
||||
CONFIG_BAT2_ICACHE_GUARDED=y
|
||||
CONFIG_BAT2_DCACHE_INHIBITED=y
|
||||
CONFIG_BAT2_DCACHE_GUARDED=y
|
||||
CONFIG_BAT2_USER_MODE_VALID=y
|
||||
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_BAT5=y
|
||||
CONFIG_BAT5_NAME="IMMR"
|
||||
CONFIG_BAT5_BASE=0xF0000000
|
||||
CONFIG_BAT5_LENGTH_128_MBYTES=y
|
||||
CONFIG_BAT5_ACCESS_RW=y
|
||||
CONFIG_BAT5_ICACHE_INHIBITED=y
|
||||
CONFIG_BAT5_ICACHE_GUARDED=y
|
||||
CONFIG_BAT5_DCACHE_INHIBITED=y
|
||||
CONFIG_BAT5_DCACHE_GUARDED=y
|
||||
CONFIG_BAT5_USER_MODE_VALID=y
|
||||
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_BAT6=y
|
||||
CONFIG_BAT6_NAME="NAND_MRAM_CPLD"
|
||||
CONFIG_BAT6_BASE=0xE0000000
|
||||
CONFIG_BAT6_LENGTH_256_MBYTES=y
|
||||
CONFIG_BAT6_ACCESS_RW=y
|
||||
CONFIG_BAT6_ICACHE_GUARDED=y
|
||||
CONFIG_BAT6_DCACHE_GUARDED=y
|
||||
CONFIG_BAT6_USER_MODE_VALID=y
|
||||
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_NAND_LBLAWBAR_PRELIM_1=y
|
||||
CONFIG_LBLAW0=y
|
||||
CONFIG_LBLAW0_BASE=0xFF800000
|
||||
CONFIG_LBLAW0_NAME="FLASH"
|
||||
CONFIG_LBLAW0_LENGTH_8_MBYTES=y
|
||||
CONFIG_LBLAW1=y
|
||||
CONFIG_LBLAW1_BASE=0xE1000000
|
||||
CONFIG_LBLAW1_NAME="NAND"
|
||||
CONFIG_LBLAW1_LENGTH_32_KBYTES=y
|
||||
CONFIG_LBLAW2=y
|
||||
CONFIG_LBLAW2_BASE=0xE2000000
|
||||
CONFIG_LBLAW2_NAME="MRAM"
|
||||
CONFIG_LBLAW2_LENGTH_128_KBYTES=y
|
||||
CONFIG_LBLAW3=y
|
||||
CONFIG_LBLAW3_BASE=0xE3000000
|
||||
CONFIG_LBLAW3_NAME="CPLD"
|
||||
CONFIG_LBLAW3_LENGTH_32_KBYTES=y
|
||||
CONFIG_ELBC_BR0_OR0=y
|
||||
CONFIG_BR0_OR0_NAME="FLASH"
|
||||
CONFIG_BR0_OR0_BASE=0xFF800000
|
||||
CONFIG_OR0_AM_8_MBYTES=y
|
||||
CONFIG_OR0_SCY_10=y
|
||||
CONFIG_OR0_CSNT_EARLIER=y
|
||||
CONFIG_OR0_TRLX_RELAXED=y
|
||||
CONFIG_OR0_EHTR_8_CYCLE=y
|
||||
CONFIG_OR0_EAD_EXTRA=y
|
||||
CONFIG_ELBC_BR1_OR1=y
|
||||
CONFIG_BR1_OR1_NAME="NAND"
|
||||
CONFIG_BR1_OR1_BASE=0xE1000000
|
||||
CONFIG_BR1_ERRORCHECKING_BOTH=y
|
||||
CONFIG_BR1_MACHINE_FCM=y
|
||||
CONFIG_OR1_SCY_4=y
|
||||
CONFIG_OR1_PGS_LARGE=y
|
||||
CONFIG_OR1_CSCT_8_CYCLE=y
|
||||
CONFIG_OR1_CST_ONE_CLOCK=y
|
||||
CONFIG_OR1_CHT_TWO_CLOCK=y
|
||||
CONFIG_OR1_RST_ONE_CLOCK=y
|
||||
CONFIG_OR1_TRLX_RELAXED=y
|
||||
CONFIG_OR1_EHTR_8_CYCLE=y
|
||||
CONFIG_ELBC_BR2_OR2=y
|
||||
CONFIG_BR2_OR2_NAME="MRAM"
|
||||
CONFIG_BR2_OR2_BASE=0xE2000000
|
||||
CONFIG_OR2_AM_128_KBYTES=y
|
||||
CONFIG_OR2_SCY_7=y
|
||||
CONFIG_OR2_CSNT_EARLIER=y
|
||||
CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
|
||||
CONFIG_OR2_TRLX_RELAXED=y
|
||||
CONFIG_ELBC_BR3_OR3=y
|
||||
CONFIG_BR3_OR3_NAME="CPLD"
|
||||
CONFIG_BR3_OR3_BASE=0xE3000000
|
||||
CONFIG_OR3_SCY_1=y
|
||||
CONFIG_OR3_CSNT_EARLIER=y
|
||||
CONFIG_OR3_TRLX_RELAXED=y
|
||||
CONFIG_HID0_FINAL_EMCP=y
|
||||
CONFIG_HID0_FINAL_ICE=y
|
||||
CONFIG_HID2_HBE=y
|
||||
CONFIG_ACR_PIPE_DEP_4=y
|
||||
CONFIG_ACR_RPTCNT_4=y
|
||||
CONFIG_LCRR_EADC_1=y
|
||||
CONFIG_LCRR_CLKDIV_2=y
|
||||
CONFIG_SYS_BARGSIZE=1024
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_SIGNATURE=y
|
||||
CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=1
|
||||
CONFIG_AUTOBOOT_KEYED=y
|
||||
CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n"
|
||||
CONFIG_AUTOBOOT_DELAY_STR="ids"
|
||||
CONFIG_BOOT_RETRY=y
|
||||
CONFIG_BOOT_RETRY_TIME=900
|
||||
CONFIG_BOOT_RETRY_MIN=30
|
||||
CONFIG_RESET_TO_RETRY=y
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="run boot_cramfs"
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_PREBOOT="echo;echo Type \"run nfsboot\" to mount root filesystem over NFS;echo"
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_AUTO_COMPLETE is not set
|
||||
CONFIG_SYS_CBSIZE=1024
|
||||
CONFIG_SYS_BOOTM_LEN=0x800000
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_ENV_FLAGS=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_NAND_TRIMFFS=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_BOOTP_BOOTFILESIZE=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SNTP=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_JFFS2=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nor0=ff800000.flash,nand0=e1000000.flash"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:7m(dum),768k(BOOT-BIN),128k(BOOT-ENV),128k(BOOT-REDENV);e1000000.flash:-(ubi)"
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_ENV_ADDR_REDUND=0xFFFE0000
|
||||
CONFIG_USE_BOOTFILE=y
|
||||
CONFIG_BOOTFILE="ids8313/uImage"
|
||||
CONFIG_USE_ETHPRIME=y
|
||||
CONFIG_ETHPRIME="TSEC1"
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_BOOTCOUNT_I2C=y
|
||||
CONFIG_SYS_BR0_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR0_PRELIM=0xFF800801
|
||||
CONFIG_SYS_OR0_PRELIM=0xFF8008A7
|
||||
CONFIG_SYS_BR1_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR1_PRELIM=0xE1000C21
|
||||
CONFIG_SYS_OR1_PRELIM=0xFFFF87CE
|
||||
CONFIG_SYS_BR2_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR2_PRELIM=0xE2000801
|
||||
CONFIG_SYS_OR2_PRELIM=0xFFFE0C74
|
||||
CONFIG_SYS_BR3_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR3_PRELIM=0xE3000801
|
||||
CONFIG_SYS_OR3_PRELIM=0xFFFF8814
|
||||
CONFIG_SYS_I2C_LEGACY=y
|
||||
CONFIG_SYS_I2C_FSL=y
|
||||
CONFIG_SYS_FSL_I2C_OFFSET=0x3100
|
||||
CONFIG_SYS_I2C_SLAVE=0x7F
|
||||
CONFIG_SYS_I2C_SPEED=400000
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SYS_MAX_FLASH_SECT=128
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_ELBC=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
# CONFIG_PCI is not set
|
||||
CONFIG_RTC_PCF8563=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_JFFS2_NAND=y
|
||||
CONFIG_OF_LIBFDT=y
|
|
@ -15,6 +15,7 @@ CONFIG_SYS_BOOK3E_HV=y
|
|||
CONFIG_SYS_CACHE_STASHING=y
|
||||
# CONFIG_DEEP_SLEEP is not set
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=2
|
||||
CONFIG_KM_DEF_NETDEV="eth2"
|
||||
CONFIG_KM_IVM_BUS=2
|
||||
CONFIG_MP=y
|
||||
|
|
|
@ -24,6 +24,7 @@ CONFIG_ARMV8_PSCI=y
|
|||
CONFIG_ARMV8_PSCI_RELOCATE=y
|
||||
CONFIG_SYS_LOAD_ADDR=0x82000000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800eff0
|
||||
|
|
|
@ -15,6 +15,7 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
|||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NXP_ESBC=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_FSL_QIXIS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
|
|
|
@ -17,6 +17,7 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
|||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_ENV_ADDR=0x20500000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_FSL_QIXIS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
|
|
|
@ -16,6 +16,7 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
|||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_ENV_ADDR=0x20500000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_FSL_QIXIS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
|
|
|
@ -15,6 +15,7 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
|||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NXP_ESBC=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_FSL_QIXIS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
|
|
|
@ -17,6 +17,7 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
|||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_ENV_ADDR=0x20500000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_FSL_QIXIS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
|
|
|
@ -16,6 +16,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_LTC3882_READ=y
|
||||
CONFIG_VOL_MONITOR_LTC3882_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_FSL_QIXIS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
|
|
|
@ -16,6 +16,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_LTC3882_READ=y
|
||||
CONFIG_VOL_MONITOR_LTC3882_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_FSL_QIXIS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
|
|
|
@ -18,6 +18,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_LTC3882_READ=y
|
||||
CONFIG_VOL_MONITOR_LTC3882_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_FSL_QIXIS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
|
|
|
@ -23,6 +23,7 @@ CONFIG_SPL_VID=y
|
|||
CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_LTC3882_READ=y
|
||||
CONFIG_VOL_MONITOR_LTC3882_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_FSL_QIXIS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
|
|
|
@ -23,6 +23,7 @@ CONFIG_SPL_VID=y
|
|||
CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_LTC3882_READ=y
|
||||
CONFIG_VOL_MONITOR_LTC3882_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_FSL_QIXIS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
|
|
|
@ -21,6 +21,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_LTC3882_READ=y
|
||||
CONFIG_VOL_MONITOR_LTC3882_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_FSL_QIXIS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
|
|
|
@ -16,6 +16,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_LTC3882_READ=y
|
||||
CONFIG_VOL_MONITOR_LTC3882_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_FSL_QIXIS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
|
|
|
@ -18,6 +18,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_LTC3882_READ=y
|
||||
CONFIG_VOL_MONITOR_LTC3882_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_FSL_QIXIS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
|
|
|
@ -22,6 +22,7 @@ CONFIG_SPL_VID=y
|
|||
CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_LTC3882_READ=y
|
||||
CONFIG_VOL_MONITOR_LTC3882_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_FSL_QIXIS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
|
|
|
@ -23,6 +23,7 @@ CONFIG_SPL_VID=y
|
|||
CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_LTC3882_READ=y
|
||||
CONFIG_VOL_MONITOR_LTC3882_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_FSL_QIXIS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
|
|
|
@ -19,6 +19,7 @@ CONFIG_VID=y
|
|||
CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_LTC3882_READ=y
|
||||
CONFIG_VOL_MONITOR_LTC3882_SET=y
|
||||
CONFIG_SYS_FSL_NUM_CC_PLLS=3
|
||||
CONFIG_FSL_QIXIS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue