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https://github.com/AsahiLinux/u-boot
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arm: socfpga: Add SPL support for Arria 10
Add SPL support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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1 changed files with 51 additions and 2 deletions
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@ -19,23 +19,32 @@
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#include <asm/arch/sdram.h>
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#include <asm/arch/scu.h>
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#include <asm/arch/nic301.h>
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#include <asm/sections.h>
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#include <fdtdec.h>
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#include <watchdog.h>
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#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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#include <asm/arch/pinmux.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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static struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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static struct scu_registers *scu_regs =
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(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
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static struct nic301_registers *nic301_regs =
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(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
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static struct socfpga_system_manager *sysmgr_regs =
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#endif
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static const struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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u32 spl_boot_device(void)
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{
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const u32 bsel = readl(&sysmgr_regs->bootinfo);
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switch (bsel & 0x7) {
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switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
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case 0x1: /* FPGA (HPS2FPGA Bridge) */
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return BOOT_DEVICE_RAM;
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case 0x2: /* NAND Flash (1.8V) */
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@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
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}
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#endif
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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static void socfpga_nic301_slave_ns(void)
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{
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writel(0x1, &nic301_regs->lwhps2fpgaregs);
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@ -183,3 +193,42 @@ void board_init_f(ulong dummy)
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/* Configure simple malloc base pointer into RAM. */
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gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
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}
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#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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void spl_board_init(void)
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{
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/* configuring the clock based on handoff */
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cm_basic_init(gd->fdt_blob);
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WATCHDOG_RESET();
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config_dedicated_pins(gd->fdt_blob);
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WATCHDOG_RESET();
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/* Release UART from reset */
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socfpga_reset_uart(0);
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/* enable console uart printing */
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preloader_console_init();
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}
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void board_init_f(ulong dummy)
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{
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/*
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* Configure Clock Manager to use intosc clock instead external osc to
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* ensure success watchdog operation. We do it as early as possible.
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*/
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cm_use_intosc();
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socfpga_watchdog_disable();
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arch_early_init_r();
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#ifdef CONFIG_HW_WATCHDOG
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/* release osc1 watchdog timer 0 from reset */
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socfpga_reset_deassert_osc1wd0();
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/* reconfigure and enable the watchdog */
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hw_watchdog_init();
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WATCHDOG_RESET();
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#endif /* CONFIG_HW_WATCHDOG */
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}
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#endif
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