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net: dwc_eth_qos: Add glue driver for GMAC on Rockchip RK3568
Add a new glue driver for Rockchip SoCs, i.e RK3568, with a GMAC based
on Synopsys DWC Ethernet QoS IP.
rk_gmac_ops was ported from linux commit:
3bb3d6b1c195 ("net: stmmac: Add RK3566/RK3568 SoC support")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
This commit is contained in:
Jonas Karlman
Kever Yang
parent
95446f4a4d
commit
8e76ff61a3
5 changed files with 374 additions and 2 deletions
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@ -225,6 +225,14 @@ config DWC_ETH_QOS_IMX
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The Synopsys Designware Ethernet QOS IP block with the specific
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configuration used in IMX soc.
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config DWC_ETH_QOS_ROCKCHIP
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bool "Synopsys DWC Ethernet QOS device support for Rockchip SoCs"
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depends on DWC_ETH_QOS
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select DM_ETH_PHY
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help
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The Synopsys Designware Ethernet QOS IP block with specific
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configuration used in Rockchip SoCs.
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config DWC_ETH_QOS_STM32
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bool "Synopsys DWC Ethernet QOS device support for STM32"
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depends on DWC_ETH_QOS
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@ -20,6 +20,7 @@ obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
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obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
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obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
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obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
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obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o
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obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
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obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o
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obj-$(CONFIG_E1000) += e1000.o
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@ -1708,7 +1708,12 @@ static const struct udevice_id eqos_ids[] = {
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.data = (ulong)&eqos_imx_config
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},
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#endif
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#if IS_ENABLED(CONFIG_DWC_ETH_QOS_ROCKCHIP)
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{
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.compatible = "rockchip,rk3568-gmac",
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.data = (ulong)&eqos_rockchip_config
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},
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#endif
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#if IS_ENABLED(CONFIG_DWC_ETH_QOS_QCOM)
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{
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.compatible = "qcom,qcs404-ethqos",
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@ -1721,7 +1726,6 @@ static const struct udevice_id eqos_ids[] = {
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.data = (ulong)&eqos_jh7110_config
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},
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#endif
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{ }
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};
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@ -82,6 +82,7 @@ struct eqos_mac_regs {
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#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
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#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
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#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
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#define EQOS_MAC_MDIO_ADDRESS_CR_100_150 1
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#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
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#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
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#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
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@ -287,5 +288,6 @@ void eqos_flush_buffer_generic(void *buf, size_t size);
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int eqos_null_ops(struct udevice *dev);
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extern struct eqos_config eqos_imx_config;
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extern struct eqos_config eqos_rockchip_config;
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extern struct eqos_config eqos_qcom_config;
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extern struct eqos_config eqos_jh7110_config;
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357
drivers/net/dwc_eth_qos_rockchip.c
Normal file
357
drivers/net/dwc_eth_qos_rockchip.c
Normal file
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@ -0,0 +1,357 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright Contributors to the U-Boot project.
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*
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* rk_gmac_ops ported from linux drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
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*
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* Ported code is intentionally left as close as possible with linux counter
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* part in order to simplify future porting of fixes and support for other SoCs.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <net.h>
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#include <phy.h>
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#include <regmap.h>
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#include <reset.h>
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#include <syscon.h>
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#include <asm/gpio.h>
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#include <linux/delay.h>
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#include "dwc_eth_qos.h"
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struct rk_gmac_ops {
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const char *compatible;
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int (*set_to_rgmii)(struct udevice *dev,
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int tx_delay, int rx_delay);
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int (*set_to_rmii)(struct udevice *dev);
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int (*set_gmac_speed)(struct udevice *dev);
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u32 regs[3];
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};
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struct rockchip_platform_data {
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struct reset_ctl_bulk resets;
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const struct rk_gmac_ops *ops;
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int id;
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struct regmap *grf;
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};
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#define HIWORD_UPDATE(val, mask, shift) \
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((val) << (shift) | (mask) << ((shift) + 16))
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#define GRF_BIT(nr) (BIT(nr) | BIT((nr) + 16))
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#define GRF_CLR_BIT(nr) (BIT((nr) + 16))
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#define RK3568_GRF_GMAC0_CON0 0x0380
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#define RK3568_GRF_GMAC0_CON1 0x0384
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#define RK3568_GRF_GMAC1_CON0 0x0388
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#define RK3568_GRF_GMAC1_CON1 0x038c
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/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
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#define RK3568_GMAC_PHY_INTF_SEL_RGMII \
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(GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
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#define RK3568_GMAC_PHY_INTF_SEL_RMII \
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(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
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#define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
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#define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
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#define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
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#define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
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#define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
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#define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
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/* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
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#define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
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#define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
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static int rk3568_set_to_rgmii(struct udevice *dev,
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int tx_delay, int rx_delay)
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{
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct rockchip_platform_data *data = pdata->priv_pdata;
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u32 con0, con1;
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con0 = (data->id == 1) ? RK3568_GRF_GMAC1_CON0 :
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RK3568_GRF_GMAC0_CON0;
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con1 = (data->id == 1) ? RK3568_GRF_GMAC1_CON1 :
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RK3568_GRF_GMAC0_CON1;
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regmap_write(data->grf, con0,
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RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
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RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
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regmap_write(data->grf, con1,
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RK3568_GMAC_PHY_INTF_SEL_RGMII |
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RK3568_GMAC_RXCLK_DLY_ENABLE |
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RK3568_GMAC_TXCLK_DLY_ENABLE);
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return 0;
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}
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static int rk3568_set_to_rmii(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct rockchip_platform_data *data = pdata->priv_pdata;
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u32 con1;
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con1 = (data->id == 1) ? RK3568_GRF_GMAC1_CON1 :
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RK3568_GRF_GMAC0_CON1;
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regmap_write(data->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
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return 0;
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}
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static int rk3568_set_gmac_speed(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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ulong rate;
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int ret;
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switch (eqos->phy->speed) {
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case SPEED_10:
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rate = 2500000;
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break;
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case SPEED_100:
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rate = 25000000;
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break;
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case SPEED_1000:
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rate = 125000000;
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break;
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default:
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return -EINVAL;
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}
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ret = clk_set_rate(&eqos->clk_tx, rate);
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if (ret < 0)
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return ret;
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return 0;
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}
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static const struct rk_gmac_ops rk_gmac_ops[] = {
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{
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.compatible = "rockchip,rk3568-gmac",
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.set_to_rgmii = rk3568_set_to_rgmii,
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.set_to_rmii = rk3568_set_to_rmii,
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.set_gmac_speed = rk3568_set_gmac_speed,
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.regs = {
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0xfe2a0000, /* gmac0 */
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0xfe010000, /* gmac1 */
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0x0, /* sentinel */
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},
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},
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{ }
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};
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static const struct rk_gmac_ops *get_rk_gmac_ops(struct udevice *dev)
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{
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const struct rk_gmac_ops *ops = rk_gmac_ops;
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while (ops->compatible) {
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if (device_is_compatible(dev, ops->compatible))
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return ops;
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ops++;
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}
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return NULL;
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}
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static int eqos_probe_resources_rk(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct rockchip_platform_data *data;
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int reset_flags = GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE;
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int ret;
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data = calloc(1, sizeof(struct rockchip_platform_data));
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if (!data)
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return -ENOMEM;
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data->ops = get_rk_gmac_ops(dev);
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if (!data->ops) {
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ret = -EINVAL;
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goto err_free;
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}
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for (int i = 0; data->ops->regs[i]; i++) {
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if (data->ops->regs[i] == (u32)eqos->regs) {
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data->id = i;
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break;
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}
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}
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pdata->priv_pdata = data;
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pdata->phy_interface = eqos->config->interface(dev);
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pdata->max_speed = eqos->max_speed;
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if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) {
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pr_err("Invalid PHY interface\n");
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ret = -EINVAL;
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goto err_free;
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}
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data->grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,grf");
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if (IS_ERR(data->grf)) {
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dev_err(dev, "Missing rockchip,grf property\n");
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ret = -EINVAL;
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goto err_free;
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}
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ret = reset_get_bulk(dev, &data->resets);
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if (ret < 0)
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goto err_free;
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reset_assert_bulk(&data->resets);
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ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
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if (ret) {
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dev_dbg(dev, "clk_get_by_name(stmmaceth) failed: %d", ret);
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goto err_release_resets;
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}
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ret = clk_get_by_name(dev, "clk_mac_speed", &eqos->clk_tx);
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if (ret) {
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dev_dbg(dev, "clk_get_by_name(clk_mac_speed) failed: %d", ret);
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goto err_free_clk_master_bus;
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}
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/* snps,reset props are deprecated, do bare minimum to support them */
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if (dev_read_bool(dev, "snps,reset-active-low"))
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reset_flags |= GPIOD_ACTIVE_LOW;
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dev_read_u32_array(dev, "snps,reset-delays-us", eqos->reset_delays, 3);
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gpio_request_by_name(dev, "snps,reset-gpio", 0,
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&eqos->phy_reset_gpio, reset_flags);
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return 0;
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err_free_clk_master_bus:
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clk_free(&eqos->clk_master_bus);
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err_release_resets:
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reset_release_bulk(&data->resets);
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err_free:
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free(data);
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return ret;
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}
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static int eqos_remove_resources_rk(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct rockchip_platform_data *data = pdata->priv_pdata;
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if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
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dm_gpio_free(dev, &eqos->phy_reset_gpio);
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clk_free(&eqos->clk_tx);
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clk_free(&eqos->clk_master_bus);
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reset_release_bulk(&data->resets);
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free(data);
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return 0;
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}
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static int eqos_stop_resets_rk(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct rockchip_platform_data *data = pdata->priv_pdata;
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return reset_assert_bulk(&data->resets);
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}
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static int eqos_start_resets_rk(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct rockchip_platform_data *data = pdata->priv_pdata;
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return reset_deassert_bulk(&data->resets);
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}
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static int eqos_stop_clks_rk(struct udevice *dev)
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{
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return 0;
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}
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static int eqos_start_clks_rk(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct rockchip_platform_data *data = pdata->priv_pdata;
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int tx_delay, rx_delay, ret;
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if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
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udelay(eqos->reset_delays[1]);
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ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
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if (ret < 0)
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return ret;
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udelay(eqos->reset_delays[2]);
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}
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tx_delay = dev_read_u32_default(dev, "tx_delay", 0x30);
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rx_delay = dev_read_u32_default(dev, "rx_delay", 0x10);
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switch (pdata->phy_interface) {
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case PHY_INTERFACE_MODE_RGMII:
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return data->ops->set_to_rgmii(dev, tx_delay, rx_delay);
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case PHY_INTERFACE_MODE_RGMII_ID:
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return data->ops->set_to_rgmii(dev, 0, 0);
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case PHY_INTERFACE_MODE_RGMII_RXID:
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return data->ops->set_to_rgmii(dev, tx_delay, 0);
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case PHY_INTERFACE_MODE_RGMII_TXID:
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return data->ops->set_to_rgmii(dev, 0, rx_delay);
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case PHY_INTERFACE_MODE_RMII:
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return data->ops->set_to_rmii(dev);
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}
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return -EINVAL;
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}
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static int eqos_set_tx_clk_speed_rk(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct rockchip_platform_data *data = pdata->priv_pdata;
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return data->ops->set_gmac_speed(dev);
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}
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static ulong eqos_get_tick_clk_rate_rk(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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return clk_get_rate(&eqos->clk_master_bus);
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}
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static struct eqos_ops eqos_rockchip_ops = {
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.eqos_inval_desc = eqos_inval_desc_generic,
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.eqos_flush_desc = eqos_flush_desc_generic,
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.eqos_inval_buffer = eqos_inval_buffer_generic,
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.eqos_flush_buffer = eqos_flush_buffer_generic,
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.eqos_probe_resources = eqos_probe_resources_rk,
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.eqos_remove_resources = eqos_remove_resources_rk,
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.eqos_stop_resets = eqos_stop_resets_rk,
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.eqos_start_resets = eqos_start_resets_rk,
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.eqos_stop_clks = eqos_stop_clks_rk,
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.eqos_start_clks = eqos_start_clks_rk,
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.eqos_calibrate_pads = eqos_null_ops,
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.eqos_disable_calibration = eqos_null_ops,
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.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_rk,
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.eqos_get_enetaddr = eqos_null_ops,
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.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_rk,
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};
|
||||
|
||||
struct eqos_config eqos_rockchip_config = {
|
||||
.reg_access_always_ok = false,
|
||||
.mdio_wait = 10,
|
||||
.swr_wait = 50,
|
||||
.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
|
||||
.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150,
|
||||
.axi_bus_width = EQOS_AXI_WIDTH_64,
|
||||
.interface = dev_read_phy_mode,
|
||||
.ops = &eqos_rockchip_ops,
|
||||
};
|
||||
Loading…
Reference in a new issue