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Merge tag 'u-boot-rockchip-20200220' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip

Browse source 
- rk3399: split roc-pc-rk3399 out of evb_rk3399
- sync dts from upstream kernel for rk3399,rk3288,px30
- boot_mode: find the saradc device name
This commit is contained in:
Tom Rini 2020-02-20 22:14:29 -05:00
commit 8e51bf746a
41 changed files with 494 additions and 159 deletions
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182
arch/arm/dts/px30.dtsi
View file

@ -10,6 +10,7 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/px30-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "rockchip,px30";
@ -113,16 +114,11 @@
compatible = "operating-points-v2";
opp-shared;
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000 950000 1350000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000 950000 1350000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
@ -186,6 +182,55 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
thermal_zones: thermal-zones {
soc_thermal: soc-thermal {
polling-delay-passive = <20>;
polling-delay = <1000>;
sustainable-power = <750>;
thermal-sensors = <&tsadc 0>;
trips {
threshold: trip-point-0 {
temperature = <70000>;
hysteresis = <2000>;
type = "passive";
};
target: trip-point-1 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
soc_crit: soc-crit {
temperature = <115000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <4096>;
};
map1 {
trip = <&target>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <4096>;
};
};
};
gpu_thermal: gpu-thermal {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
thermal-sensors = <&tsadc 1>;
};
};
xin24m: xin24m {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -370,6 +415,36 @@
compatible = "rockchip,px30-io-voltage-domain";
status = "disabled";
};
lvds: lvds {
compatible = "rockchip,px30-lvds";
phys = <&dsi_dphy>;
phy-names = "dphy";
rockchip,grf = <&grf>;
rockchip,output = "lvds";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
lvds_vopb_in: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_lvds>;
};
lvds_vopl_in: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_lvds>;
};
};
};
};
};
uart1: serial@ff158000 {
@ -650,6 +725,26 @@
};
};
tsadc: tsadc@ff280000 {
compatible = "rockchip,px30-tsadc";
reg = <0x0 0xff280000 0x0 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&cru SCLK_TSADC>;
assigned-clock-rates = <50000>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
rockchip,grf = <&grf>;
rockchip,hw-tshut-temp = <120000>;
pinctrl-names = "init", "default", "sleep";
pinctrl-0 = <&tsadc_otp_gpio>;
pinctrl-1 = <&tsadc_otp_out>;
pinctrl-2 = <&tsadc_otp_gpio>;
#thermal-sensor-cells = <1>;
status = "disabled";
};
saradc: saradc@ff288000 {
compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
reg = <0x0 0xff288000 0x0 0x100>;
@ -706,12 +801,48 @@
#reset-cells = <1>;
};
usb2phy_grf: syscon@ff2c0000 {
compatible = "rockchip,px30-usb2phy-grf", "syscon",
"simple-mfd";
reg = <0x0 0xff2c0000 0x0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
u2phy: usb2-phy@100 {
compatible = "rockchip,px30-usb2phy";
reg = <0x100 0x20>;
clocks = <&pmucru SCLK_USBPHY_REF>;
clock-names = "phyclk";
#clock-cells = <0>;
assigned-clocks = <&cru USB480M>;
assigned-clock-parents = <&u2phy>;
clock-output-names = "usb480m_phy";
status = "disabled";
u2phy_host: host-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "linestate";
status = "disabled";
};
u2phy_otg: otg-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "otg-bvalid", "otg-id",
"linestate";
status = "disabled";
};
};
};
dsi_dphy: phy@ff2e0000 {
compatible = "rockchip,px30-dsi-dphy";
reg = <0x0 0xff2e0000 0x0 0x10000>;
clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
clock-names = "ref", "pclk";
#clock-cells = <0>;
resets = <&cru SRST_MIPIDSIPHY_P>;
reset-names = "apb";
#phy-cells = <0>;
@ -731,6 +862,8 @@
g-rx-fifo-size = <280>;
g-tx-fifo-size = <256 128 128 64 32 16>;
g-use-dma;
phys = <&u2phy_otg>;
phy-names = "usb2-phy";
power-domains = <&power PX30_PD_USB>;
status = "disabled";
};
@ -741,6 +874,8 @@
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST>;
clock-names = "usbhost";
phys = <&u2phy_host>;
phy-names = "usb";
power-domains = <&power PX30_PD_USB>;
status = "disabled";
};
@ -751,6 +886,8 @@
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST>;
clock-names = "usbhost";
phys = <&u2phy_host>;
phy-names = "usb";
power-domains = <&power PX30_PD_USB>;
status = "disabled";
};
@ -823,17 +960,30 @@
status = "disabled";
};
gpu: gpu@ff400000 {
compatible = "rockchip,px30-mali", "arm,mali-bifrost";
reg = <0x0 0xff400000 0x0 0x4000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu";
clocks = <&cru SCLK_GPU>;
#cooling-cells = <2>;
power-domains = <&power PX30_PD_GPU>;
status = "disabled";
};
dsi: dsi@ff450000 {
compatible = "rockchip,px30-mipi-dsi";
reg = <0x0 0xff450000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_MIPI_DSI>, <&dsi_dphy>;
clock-names = "pclk", "pll";
resets = <&cru SRST_MIPIDSI_HOST_P>;
reset-names = "apb";
clocks = <&cru PCLK_MIPI_DSI>;
clock-names = "pclk";
phys = <&dsi_dphy>;
phy-names = "dphy";
power-domains = <&power PX30_PD_VO>;
resets = <&cru SRST_MIPIDSI_HOST_P>;
reset-names = "apb";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
@ -883,6 +1033,11 @@
reg = <0>;
remote-endpoint = <&dsi_in_vopb>;
};
vopb_out_lvds: endpoint@1 {
reg = <1>;
remote-endpoint = <&lvds_vopb_in>;
};
};
};
@ -920,6 +1075,11 @@
reg = <0>;
remote-endpoint = <&dsi_in_vopl>;
};
vopl_out_lvds: endpoint@1 {
reg = <1>;
remote-endpoint = <&lvds_vopl_in>;
};
};
};

79
arch/arm/dts/rk3288-vyasa.dts
View file

@ -1,43 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@ -115,6 +78,17 @@
vin-supply = <&vcc_io>;
};
vcc50_hdmi: vcc50-hdmi {
compatible = "regulator-fixed";
regulator-name = "vcc50_hdmi";
enable-active-high;
gpio = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>; /* HDMI_EN */
pinctrl-names = "default";
pinctrl-0 = <&vcc50_hdmi_en>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vsus_5v>;
};
vusb1_5v: vusb1-5v {
compatible = "regulator-fixed";
regulator-name = "vusb1_5v";
@ -158,7 +132,6 @@
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
@ -188,7 +161,7 @@
};
&hdmi {
ddc-i2c-bus = <&i2c2>;
ddc-i2c-bus = <&i2c5>;
status = "okay";
};
@ -324,15 +297,15 @@
};
};
vcc10_lcd: LDO_REG6 {
regulator-name = "vcc10_lcd";
vdd10_lcd: LDO_REG6 {
regulator-name = "vdd10_lcd";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
regulator-suspend-microvolt = <1000000>;
};
};
@ -385,7 +358,7 @@
};
};
&i2c2 {
&i2c5 {
status = "okay";
};
@ -402,6 +375,12 @@
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
status = "okay";
};
&uart2 {
status = "okay";
};
@ -463,15 +442,21 @@
};
};
hdmi {
vcc50_hdmi_en: vcc50-hdmi-en {
rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int: pmic-int {
rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb_host {
phy_pwr_en: phy-pwr-en {
rockchip,pins = <RK_GPIO2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>;
rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>;
};
usb2_pwr_en: usb2-pwr-en {
@ -481,7 +466,7 @@
usb_otg {
otg_vbus_drv: otg-vbus-drv {
rockchip,pins = <RK_GPIO0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};

4
arch/arm/dts/rk3399-evb.dts
View file

@ -176,7 +176,7 @@
status = "okay";
};
&dwc3_typec0 {
&usbdrd3_0 {
vbus-supply = <&vcc5v0_typec0>;
status = "okay";
};
@ -189,7 +189,7 @@
status = "okay";
};
&dwc3_typec1 {
&usbdrd3_1 {
vbus-supply = <&vcc5v0_typec1>;
status = "okay";
};

4
arch/arm/dts/rk3399-puma-ddr1333-u-boot.dtsi Normal file
View file

@ -0,0 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+
#include "rk3399-puma-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1333.dtsi"

2
arch/arm/dts/rk3399-puma-ddr1333.dts
View file

@ -6,5 +6,3 @@
/dts-v1/;
#include "rk3399-puma.dtsi"
#include "rk3399-sdram-ddr3-1333.dtsi"

4
arch/arm/dts/rk3399-puma-ddr1600-u-boot.dtsi Normal file
View file

@ -0,0 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+
#include "rk3399-puma-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1600.dtsi"

2
arch/arm/dts/rk3399-puma-ddr1600.dts
View file

@ -7,5 +7,3 @@
#include "rk3399-puma.dtsi"
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1600.dtsi"

4
arch/arm/dts/rk3399-puma-ddr1866-u-boot.dtsi Normal file
View file

@ -0,0 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+
#include "rk3399-puma-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1866.dtsi"

2
arch/arm/dts/rk3399-puma-ddr1866.dts
View file

@ -6,5 +6,3 @@
/dts-v1/;
#include "rk3399-puma.dtsi"
#include "rk3399-sdram-ddr3-1866.dtsi"

24
arch/arm/dts/rk3399-puma-u-boot.dtsi Normal file
View file

@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0+
#include "rk3399-u-boot.dtsi"
/ {
config {
u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */
u-boot,boot-led = "module_led";
sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
};
chosen {
stdout-path = "serial0:115200n8";
u-boot,spl-boot-order = \
"same-as-spl", &spiflash, &sdhci, &sdmmc;
};
aliases {
spi0 = &spi1;
spi1 = &spi5;
};
};

23
arch/arm/dts/rk3399-puma.dtsi
View file

@ -10,25 +10,6 @@
model = "Theobroma Systems RK3399-Q7 SoM";
compatible = "tsd,rk3399-q7", "tsd,puma", "rockchip,rk3399";
config {
u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */
u-boot,boot-led = "module_led";
sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
};
chosen {
stdout-path = "serial0:115200n8";
u-boot,spl-boot-order = \
"same-as-spl", &spiflash, &sdhci, &sdmmc;
};
aliases {
spi0 = &spi1;
spi1 = &spi5;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@ -518,7 +499,7 @@
status = "disabled";
};
&dwc3_typec0 {
&usbdrd3_0 {
status = "okay";
};
@ -530,7 +511,7 @@
status = "disabled";
};
&dwc3_typec1 {
&usbdrd3_1 {
status = "okay";
tsd,usb-port-power = "usbhub_enable";
};

55
arch/arm/dts/rk3399-u-boot.dtsi
View file

@ -2,19 +2,58 @@
/*
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
#define USB_CLASS_HUB 9
/ {
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc;
};
cic: syscon@ff620000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-cic", "syscon";
reg = <0x0 0xff620000 0x0 0x100>;
};
dfi: dfi@ff630000 {
u-boot,dm-pre-reloc;
reg = <0x00 0xff630000 0x00 0x4000>;
compatible = "rockchip,rk3399-dfi";
rockchip,pmu = <&pmugrf>;
clocks = <&cru PCLK_DDR_MON>;
clock-names = "pclk_ddr_mon";
};
dmc: dmc {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-dmc";
devfreq-events = <&dfi>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_DDRCLK>;
clock-names = "dmc_clk";
reg = <0x0 0xffa80000 0x0 0x0800
0x0 0xffa80800 0x0 0x1800
0x0 0xffa82000 0x0 0x2000
0x0 0xffa84000 0x0 0x1000
0x0 0xffa88000 0x0 0x0800
0x0 0xffa88800 0x0 0x1800
0x0 0xffa8a000 0x0 0x2000
0x0 0xffa8c000 0x0 0x1000>;
};
pmusgrf: syscon@ff330000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-pmusgrf", "syscon";
reg = <0x0 0xff330000 0x0 0xe3d4>;
};
&cic {
u-boot,dm-pre-reloc;
};
&cru {
u-boot,dm-pre-reloc;
};
&dmc {
u-boot,dm-pre-reloc;
};
&grf {
u-boot,dm-pre-reloc;
};
@ -39,10 +78,6 @@
u-boot,dm-pre-reloc;
};
&pmusgrf {
u-boot,dm-pre-reloc;
};
&sdhci {
u-boot,dm-pre-reloc;
};

38
arch/arm/dts/rk3399.dtsi
View file

@ -10,7 +10,6 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/rk3399-power.h>
#include <dt-bindings/thermal/thermal.h>
#define USB_CLASS_HUB 9
/ {
compatible = "rockchip,rk3399";
@ -34,8 +33,6 @@
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
mmc0 = &sdhci;
mmc1 = &sdmmc;
};
cpus {
@ -1080,11 +1077,6 @@
};
};
pmusgrf: syscon@ff330000 {
compatible = "rockchip,rk3399-pmusgrf", "syscon";
reg = <0x0 0xff330000 0x0 0xe3d4>;
};
spi3: spi@ff350000 {
compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
reg = <0x0 0xff350000 0x0 0x1000>;
@ -1200,36 +1192,6 @@
status = "disabled";
};
cic: syscon@ff620000 {
compatible = "rockchip,rk3399-cic", "syscon";
reg = <0x0 0xff620000 0x0 0x100>;
};
dfi: dfi@ff630000 {
reg = <0x00 0xff630000 0x00 0x4000>;
compatible = "rockchip,rk3399-dfi";
rockchip,pmu = <&pmugrf>;
clocks = <&cru PCLK_DDR_MON>;
clock-names = "pclk_ddr_mon";
status = "disabled";
};
dmc: dmc {
compatible = "rockchip,rk3399-dmc";
devfreq-events = <&dfi>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_DDRCLK>;
clock-names = "dmc_clk";
reg = <0x0 0xffa80000 0x0 0x0800
0x0 0xffa80800 0x0 0x1800
0x0 0xffa82000 0x0 0x2000
0x0 0xffa84000 0x0 0x1000
0x0 0xffa88000 0x0 0x0800
0x0 0xffa88800 0x0 0x1800
0x0 0xffa8a000 0x0 0x2000
0x0 0xffa8c000 0x0 0x1000>;
};
efuse0: efuse@ff690000 {
compatible = "rockchip,rk3399-efuse";
reg = <0x0 0xff690000 0x0 0x80>;

1
arch/arm/mach-rockchip/Kconfig
View file

@ -102,6 +102,7 @@ config ROCKCHIP_RK3288
select SUPPORT_SPL
select SPL
select SUPPORT_TPL
imply PRE_CONSOLE_BUFFER
imply ROCKCHIP_COMMON_BOARD
imply SPL_ROCKCHIP_COMMON_BOARD
imply TPL_CLK

22
arch/arm/mach-rockchip/boot_mode.c
View file

@ -7,6 +7,8 @@
#include <adc.h>
#include <asm/io.h>
#include <asm/arch-rockchip/boot_mode.h>
#include <dm/device.h>
#include <dm/uclass.h>
#if (CONFIG_ROCKCHIP_BOOT_MODE_REG == 0)
@ -35,8 +37,26 @@ void set_back_to_bootrom_dnl_flag(void)
__weak int rockchip_dnl_key_pressed(void)
{
unsigned int val;
struct udevice *dev;
struct uclass *uc;
int ret;
if (adc_channel_single_shot("saradc", 1, &val)) {
ret = uclass_get(UCLASS_ADC, &uc);
if (ret)
return false;
ret = -ENODEV;
uclass_foreach_dev(dev, uc) {
if (!strncmp(dev->name, "saradc", 6)) {
ret = adc_channel_single_shot(dev->name, 1, &val);
break;
}
}
if (ret == -ENODEV) {
pr_warn("%s: no saradc device found\n", __func__);
return false;
} else if (ret) {
pr_err("%s: adc_channel_single_shot fail!\n", __func__);
return false;
}

2
arch/arm/mach-rockchip/make_fit_atf.py
View file

@ -107,7 +107,7 @@ def append_conf_section(file, cnt, dtname, segments):
file.write(';\n')
if segments <= 1:
file.write(';\n')
file.write('\t\t\tfdt = "fdt_1";\n')
file.write('\t\t\tfdt = "fdt_%d";\n' % cnt)
file.write('\t\t};\n')
file.write('\n')

42
arch/arm/mach-rockchip/rk3399/Kconfig
View file

@ -3,6 +3,15 @@ if ROCKCHIP_RK3399
choice
prompt "RK3399 board select"
config TARGET_CHROMEBOOK_BOB
bool "Asus Flip C101PA Chromebook (RK3399)"
help
Bob is a small RK3299-based device similar in apperance to Minnie.
It has two USB 3.0 type-C ports, 4GB of SDRAM, WiFi and a 10.1",
1280x800 display. It uses its USB ports for both power and external
display. It includes a Chrome OS EC (Cortex-M3) to provide access to
the keyboard and battery functions.
config TARGET_EVB_RK3399
bool "RK3399 evaluation board"
help
@ -53,15 +62,6 @@ config TARGET_ROCK960_RK3399
* 2x USB 3.0 type A, 2x USB 2.0 type A (host mode only),
1x USB 3.0 type C OTG
config TARGET_CHROMEBOOK_BOB
bool "Asus Flip C101PA Chromebook (RK3399)"
help
Bob is a small RK3299-based device similar in apperance to Minnie.
It has two USB 3.0 type-C ports, 4GB of SDRAM, WiFi and a 10.1",
1280x800 display. It uses its USB ports for both power and external
display. It includes a Chrome OS EC (Cortex-M3) to provide access to
the keyboard and battery functions.
config TARGET_ROCKPRO64_RK3399
bool "Pine64 Rockpro64 board"
help
@ -81,6 +81,25 @@ config TARGET_ROCKPRO64_RK3399
* GPIO expansion ports
* DC 12V/2A
config TARGET_ROC_PC_RK3399
bool "Firefly ROC-RK3399-PC board"
help
ROC-RK3399-PC is SBC produced by Firefly. Key features:
* Rockchip RK3399
* 4GB Dual-Channel LPDDR4 64-bit
* SD card slot
* eMMC socket
* 16MB SPI Flash
* Gigabit ethernet
* PCIe
* HDMI In/Out, DP, MIPI DSI/CSI, eDP
* USB 3.0, 2.0
* USB Type C power and data
* GPIO expansion ports
* wide voltage input(5V-15V), dual cell battery
* Wifi/BT accessible via expansion board M.2
endchoice
config ROCKCHIP_BOOT_MODE_REG
@ -123,10 +142,11 @@ config SYS_BOOTCOUNT_ADDR
endif # BOOTCOUNT_LIMIT
source "board/firefly/roc-pc-rk3399/Kconfig"
source "board/google/gru/Kconfig"
source "board/pine64/rockpro64_rk3399/Kconfig"
source "board/rockchip/evb_rk3399/Kconfig"
source "board/theobroma-systems/puma_rk3399/Kconfig"
source "board/vamrs/rock960_rk3399/Kconfig"
source "board/google/gru/Kconfig"
source "board/pine64/rockpro64_rk3399/Kconfig"
endif

2
arch/arm/mach-rockchip/spl.c
View file

@ -147,7 +147,7 @@ void board_init_f(ulong dummy)
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
int __weak board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);

7
arch/arm/mach-rockchip/tpl.c
View file

@ -40,11 +40,18 @@ __weak void rockchip_stimer_init(void)
TIMER_CONTROL_REG);
}
__weak int board_early_init_f(void)
{
return 0;
}
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
board_early_init_f();
#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL_SUPPORT)
/*
* Debug UART can be used from here if required:

16
board/firefly/roc-pc-rk3399/Kconfig Normal file
View file

@ -0,0 +1,16 @@
if TARGET_ROC_PC_RK3399
config SYS_BOARD
default "roc-pc-rk3399"
config SYS_VENDOR
default "firefly"
config SYS_CONFIG_NAME
default "roc-pc-rk3399"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

6
board/firefly/roc-pc-rk3399/MAINTAINERS Normal file
View file

@ -0,0 +1,6 @@
ROC-RK3399-PC
M: Levin Du <djw@t-chip.com.cn>
S: Maintained
F: board/firefly/roc-pc-rk3399
F: include/configs/roc-pc-rk3399.h
F: configs/roc-pc-rk3399_defconfig

7
board/firefly/roc-pc-rk3399/Makefile Normal file
View file

@ -0,0 +1,7 @@
#
# (C) Copyright 2016 Rockchip Electronics Co., Ltd
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += roc-pc-rk3399.o

61
board/firefly/roc-pc-rk3399/roc-pc-rk3399.c Normal file
View file

@ -0,0 +1,61 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <dm.h>
#include <asm/arch-rockchip/periph.h>
#include <power/regulator.h>
#include <spl_gpio.h>
#include <asm/io.h>
#include <asm/arch-rockchip/gpio.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#ifndef CONFIG_SPL_BUILD
int board_early_init_f(void)
{
struct udevice *regulator;
int ret;
ret = regulator_get_by_platname("vcc5v0_host", &regulator);
if (ret) {
debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret);
goto out;
}
ret = regulator_set_enable(regulator, true);
if (ret)
debug("%s vcc5v0-host-en set fail! ret %d\n", __func__, ret);
out:
return 0;
}
#endif
#if defined(CONFIG_TPL_BUILD)
#define PMUGRF_BASE 0xff320000
#define GPIO0_BASE 0xff720000
int board_early_init_f(void)
{
struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE;
struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
/**
* 1. Glow yellow LED, termed as low power
* 2. Poll for on board power key press
* 3. Once 2 done, off yellow and glow red LED, termed as full power
* 4. Continue booting...
*/
spl_gpio_output(gpio0, GPIO(BANK_A, 2), 1);
spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_A, 5), GPIO_PULL_NORMAL);
while (readl(&gpio0->ext_port) & 0x20);
spl_gpio_output(gpio0, GPIO(BANK_A, 2), 0);
spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1);
return 0;
}
#endif

6
board/rockchip/evb_rk3399/MAINTAINERS
View file

@ -55,12 +55,6 @@ F: configs/orangepi-rk3399_defconfig
F: arch/arm/dts/rk3399-u-boot.dtsi
F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi
ROC-RK3399-PC
M: Levin Du <djw@t-chip.com.cn>
S: Maintained
F: configs/roc-pc-rk3399_defconfig
F: arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
ROCK-PI-4
M: Akash Gajjar <akash@openedev.com>
M: Jagan Teki <jagan@amarulasolutions.com>

1
common/Kconfig
View file

@ -567,6 +567,7 @@ config PRE_CON_BUF_ADDR
depends on PRE_CONSOLE_BUFFER
default 0x2f000000 if ARCH_SUNXI && MACH_SUN9I
default 0x4f000000 if ARCH_SUNXI && !MACH_SUN9I
default 0x0f000000 if ROCKCHIP_RK3288
help
This sets the start address of the pre-console buffer. This must
be in available memory and is accessed before relocation and

1
configs/evb-rk3399_defconfig
View file

@ -3,6 +3,7 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000

1
configs/firefly-rk3399_defconfig
View file

@ -3,6 +3,7 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000

3
configs/khadas-edge-captain-rk3399_defconfig
View file

@ -3,11 +3,12 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtbi"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y

1
configs/khadas-edge-rk3399_defconfig
View file

@ -3,6 +3,7 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000

3
configs/khadas-edge-v-rk3399_defconfig
View file

@ -3,11 +3,12 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtbi"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y

1
configs/leez-rk3399_defconfig
View file

@ -3,6 +3,7 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000

1
configs/nanopc-t4-rk3399_defconfig
View file

@ -3,6 +3,7 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000

1
configs/nanopi-m4-rk3399_defconfig
View file

@ -3,6 +3,7 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000

1
configs/nanopi-neo4-rk3399_defconfig
View file

@ -3,6 +3,7 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000

1
configs/orangepi-rk3399_defconfig
View file

@ -3,6 +3,7 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000

2
configs/roc-pc-rk3399_defconfig
View file

@ -3,6 +3,7 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_ROC_PC_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
@ -56,3 +57,4 @@ CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_TPL_GPIO_SUPPORT=y

1
configs/rock-pi-4-rk3399_defconfig
View file

@ -3,6 +3,7 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000

6
configs/tinker-rk3288_defconfig
View file

@ -83,3 +83,9 @@ CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_BPP16=y
CONFIG_VIDEO_BPP32=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y

22
include/configs/roc-pc-rk3399.h Normal file
View file

@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
#ifndef __ROC_PC_RK3399_H
#define __ROC_PC_RK3399_H
#define ROCKCHIP_DEVICE_SETTINGS \
"stdin=serial,cros-ec-keyb\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#include <configs/rk3399_common.h>
#if defined(CONFIG_ENV_IS_IN_MMC)
# define CONFIG_SYS_MMC_ENV_DEV 0
#endif
#define SDRAM_BANK_SIZE (2UL << 30)
#endif

6
include/configs/tinker_rk3288.h
View file

@ -6,7 +6,11 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define ROCKCHIP_DEVICE_SETTINGS
#define ROCKCHIP_DEVICE_SETTINGS \
"stdin=serial,cros-ec-keyb\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#include <configs/rk3288_common.h>
#undef BOOT_TARGET_DEVICES

6
include/configs/vyasa-rk3288.h
View file

@ -8,7 +8,11 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define ROCKCHIP_DEVICE_SETTINGS
#define ROCKCHIP_DEVICE_SETTINGS \
"stdin=serial,cros-ec-keyb\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#include <configs/rk3288_common.h>
#undef BOOT_TARGET_DEVICES