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mx28: fix clearing of IRQs in power init

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There are 2 locations in the power init code for the mx28 where IRQs are not being cleared because incorrect methods to clear those bits were being used.  This was causing my board to get stuck waiting for POWER_CTRL_VDD5V_DROOP_IRQ to clear.  Using the correct method to clear the IRQs fixes it.

Signed-off-by: Zach Sadecki <zach@itwatchdogs.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
This commit is contained in:
Zach Sadecki 2012-01-09 10:22:54 +00:00 committed by Albert ARIBAUD
parent c660a54182
commit 8db9eff6c5
1 changed files with 4 additions and 4 deletions
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8
arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
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@ -240,8 +240,8 @@ void mx28_enable_4p2_dcdc_input(int xfer)
clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO); clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
clrbits_le32(&power_regs->hw_power_ctrl, writel(POWER_CTRL_VBUS_VALID_IRQ,
POWER_CTRL_VBUS_VALID_IRQ); &power_regs->hw_power_ctrl_clr);
if (prev_5v_brnout) { if (prev_5v_brnout) {
writel(POWER_5VCTRL_PWDN_5VBRNOUT, writel(POWER_5VCTRL_PWDN_5VBRNOUT,
@ -256,8 +256,8 @@ void mx28_enable_4p2_dcdc_input(int xfer)
} }
while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ) while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
clrbits_le32(&power_regs->hw_power_ctrl, writel(POWER_CTRL_VDD5V_DROOP_IRQ,
POWER_CTRL_VDD5V_DROOP_IRQ); &power_regs->hw_power_ctrl_clr);
if (prev_5v_droop) if (prev_5v_droop)
clrbits_le32(&power_regs->hw_power_ctrl, clrbits_le32(&power_regs->hw_power_ctrl,