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Merge branch 'master' of git://git.denx.de/u-boot-sh

Browse source 
- RZ/A1 addition.
- Old board removal.
This commit is contained in:
Tom Rini 2019-05-07 09:38:00 -04:00
commit 8d7f06bbbe
58 changed files with 1860 additions and 2164 deletions
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2
arch/arm/Kconfig
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@ -785,7 +785,7 @@ config ARCH_QEMU
config ARCH_RMOBILE config ARCH_RMOBILE
bool "Renesas ARM SoCs" bool "Renesas ARM SoCs"
select BOARD_EARLY_INIT_F select BOARD_EARLY_INIT_F if !RZA1
select DM select DM
select DM_SERIAL select DM_SERIAL
imply CMD_DM imply CMD_DM

3
arch/arm/dts/Makefile
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@ -603,6 +603,9 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a77990-ebisu-u-boot.dtb \ r8a77990-ebisu-u-boot.dtb \
r8a77995-draak-u-boot.dtb r8a77995-draak-u-boot.dtb
dtb-$(CONFIG_RZA1) += \
r7s72100-gr-peach-u-boot.dtb
dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \ keystone-k2l-evm.dtb \
keystone-k2e-evm.dtb \ keystone-k2e-evm.dtb \

78
arch/arm/dts/r7s72100-gr-peach-u-boot.dts Normal file
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@ -0,0 +1,78 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot for the GR Peach board
*
* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
*/
#include "r7s72100-gr-peach.dts"
/ {
aliases {
spi0 = &rpc;
};
soc {
u-boot,dm-pre-reloc;
};
leds {
led1 {
label = "peach:bottom:red";
};
led-red {
label = "peach:tri:red";
gpios = <&port6 13 GPIO_ACTIVE_HIGH>;
};
led-green {
label = "peach:tri:green";
gpios = <&port6 14 GPIO_ACTIVE_HIGH>;
};
led-blue {
label = "peach:tri:blue";
gpios = <&port6 15 GPIO_ACTIVE_HIGH>;
};
};
rpc: rpc@0xee200000 {
compatible = "renesas,rpc-r7s72100", "renesas,rpc";
reg = <0x3fefa000 0x100>, <0x18000000 0x08000000>;
bank-width = <2>;
num-cs = <1>;
status = "okay";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
flash0: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
reg = <0>;
status = "okay";
};
};
};
&ostm0 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&scif2 {
u-boot,dm-pre-reloc;
clock = <66666666>; /* ToDo: Replace by DM clock driver */
};
&scif2_pins {
u-boot,dm-pre-reloc;
};

134
arch/arm/dts/r7s72100-gr-peach.dts Normal file
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@ -0,0 +1,134 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the GR-Peach board
*
* Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
* Copyright (C) 2016 Renesas Electronics
*/
/dts-v1/;
#include "r7s72100.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
/ {
model = "GR-Peach";
compatible = "renesas,gr-peach", "renesas,r7s72100";
aliases {
serial0 = &scif2;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/mtdblock0";
stdout-path = "serial0:115200n8";
};
memory@20000000 {
device_type = "memory";
reg = <0x20000000 0x00a00000>;
};
lbsc {
#address-cells = <1>;
#size-cells = <1>;
};
flash@18000000 {
compatible = "mtd-rom";
probe-type = "map_rom";
reg = <0x18000000 0x00800000>;
bank-width = <4>;
device-width = <1>;
#address-cells = <1>;
#size-cells = <1>;
rootfs@600000 {
label = "rootfs";
reg = <0x00600000 0x00200000>;
};
};
leds {
status = "okay";
compatible = "gpio-leds";
led1 {
gpios = <&port6 12 GPIO_ACTIVE_HIGH>;
};
};
};
&pinctrl {
scif2_pins: serial2 {
/* P6_2 as RxD2; P6_3 as TxD2 */
pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
};
ether_pins: ether {
/* Ethernet on Ports 1,3,5,10 */
pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL */
<RZA1_PINMUX(3, 0, 2)>, /* P3_0 = ET_TXCLK */
<RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */
<RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */
<RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */
<RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */
<RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */
<RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER */
<RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN */
<RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS */
<RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0 */
<RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1 */
<RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2 */
<RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3 */
<RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0 */
<RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1 */
<RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
<RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
};
};
&extal_clk {
clock-frequency = <13333000>;
};
&usb_x1_clk {
clock-frequency = <48000000>;
};
&mtu2 {
status = "okay";
};
&ostm0 {
status = "okay";
};
&ostm1 {
status = "okay";
};
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif2_pins>;
status = "okay";
};
&ether {
pinctrl-names = "default";
pinctrl-0 = <&ether_pins>;
status = "okay";
renesas,no-ether-link;
phy-handle = <&phy0>;
phy0: ethernet-phy@0 {
reg = <0>;
reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
reset-delay-us = <5>;
};
};

705
arch/arm/dts/r7s72100.dtsi Normal file
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@ -0,0 +1,705 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the r7s72100 SoC
*
* Copyright (C) 2013-14 Renesas Solutions Corp.
* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
*/
#include <dt-bindings/clock/r7s72100-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "renesas,r7s72100";
#address-cells = <1>;
#size-cells = <1>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
spi3 = &spi3;
spi4 = &spi4;
};
/* Fixed factor clocks */
b_clk: b {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R7S72100_CLK_PLL>;
clock-mult = <1>;
clock-div = <3>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
clock-frequency = <400000000>;
clocks = <&cpg_clocks R7S72100_CLK_I>;
next-level-cache = <&L2>;
};
};
/* External clocks */
extal_clk: extal {
#clock-cells = <0>;
compatible = "fixed-clock";
/* If clk present, value must be set by board */
clock-frequency = <0>;
};
p0_clk: p0 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R7S72100_CLK_PLL>;
clock-mult = <1>;
clock-div = <12>;
};
p1_clk: p1 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R7S72100_CLK_PLL>;
clock-mult = <1>;
clock-div = <6>;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
rtc_x1_clk: rtc_x1 {
#clock-cells = <0>;
compatible = "fixed-clock";
/* If clk present, value must be set by board to 32678 */
clock-frequency = <0>;
};
rtc_x3_clk: rtc_x3 {
#clock-cells = <0>;
compatible = "fixed-clock";
/* If clk present, value must be set by board to 4000000 */
clock-frequency = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
L2: cache-controller@3ffff000 {
compatible = "arm,pl310-cache";
reg = <0x3ffff000 0x1000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
arm,early-bresp-disable;
arm,full-line-zero-disable;
cache-unified;
cache-level = <2>;
};
scif0: serial@e8007000 {
compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe8007000 64>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
status = "disabled";
};
scif1: serial@e8007800 {
compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe8007800 64>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
status = "disabled";
};
scif2: serial@e8008000 {
compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe8008000 64>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
status = "disabled";
};
scif3: serial@e8008800 {
compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe8008800 64>;
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
status = "disabled";
};
scif4: serial@e8009000 {
compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe8009000 64>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
status = "disabled";
};
scif5: serial@e8009800 {
compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe8009800 64>;
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
status = "disabled";
};
scif6: serial@e800a000 {
compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe800a000 64>;
interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
status = "disabled";
};
scif7: serial@e800a800 {
compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe800a800 64>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
status = "disabled";
};
spi0: spi@e800c800 {
compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
reg = <0xe800c800 0x24>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@e800d000 {
compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
reg = <0xe800d000 0x24>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi2: spi@e800d800 {
compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
reg = <0xe800d800 0x24>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi3: spi@e800e000 {
compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
reg = <0xe800e000 0x24>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi4: spi@e800e800 {
compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
reg = <0xe800e800 0x24>;
interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
usbhs0: usb@e8010000 {
compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
reg = <0xe8010000 0x1a0>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R7S72100_CLK_USB0>;
renesas,buswait = <4>;
power-domains = <&cpg_clocks>;
status = "disabled";
};
usbhs1: usb@e8207000 {
compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
reg = <0xe8207000 0x1a0>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R7S72100_CLK_USB1>;
renesas,buswait = <4>;
power-domains = <&cpg_clocks>;
status = "disabled";
};
mmcif: mmc@e804c800 {
compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
reg = <0xe804c800 0x80>;
interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
power-domains = <&cpg_clocks>;
reg-io-width = <4>;
bus-width = <8>;
status = "disabled";
};
sdhi0: sd@e804e000 {
compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e000 0x100>;
interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
<&mstp12_clks R7S72100_CLK_SDHI01>;
clock-names = "core", "cd";
power-domains = <&cpg_clocks>;
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
};
sdhi1: sd@e804e800 {
compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e800 0x100>;
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
<&mstp12_clks R7S72100_CLK_SDHI11>;
clock-names = "core", "cd";
power-domains = <&cpg_clocks>;
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
};
gic: interrupt-controller@e8201000 {
compatible = "arm,pl390";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0xe8201000 0x1000>,
<0xe8202000 0x1000>;
};
ether: ethernet@e8203000 {
compatible = "renesas,ether-r7s72100";
reg = <0xe8203000 0x800>,
<0xe8204800 0x200>;
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
power-domains = <&cpg_clocks>;
phy-mode = "mii";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ceu: camera@e8210000 {
reg = <0xe8210000 0x3000>;
compatible = "renesas,r7s72100-ceu";
interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp6_clks R7S72100_CLK_CEU>;
power-domains = <&cpg_clocks>;
status = "disabled";
};
wdt: watchdog@fcfe0000 {
compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
reg = <0xfcfe0000 0x6>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&p0_clk>;
};
/* Special CPG clocks */
cpg_clocks: cpg_clocks@fcfe0000 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-cpg-clocks",
"renesas,rz-cpg-clocks";
reg = <0xfcfe0000 0x18>;
clocks = <&extal_clk>, <&usb_x1_clk>;
clock-output-names = "pll", "i", "g";
#power-domain-cells = <0>;
};
/* MSTP clocks */
mstp3_clks: mstp3_clks@fcfe0420 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0420 4>;
clocks = <&p0_clk>;
clock-indices = <R7S72100_CLK_MTU2>;
clock-output-names = "mtu2";
};
mstp4_clks: mstp4_clks@fcfe0424 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0424 4>;
clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
<&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
clock-indices = <
R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
>;
clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
};
mstp5_clks: mstp5_clks@fcfe0428 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0428 4>;
clocks = <&p0_clk>, <&p0_clk>;
clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
clock-output-names = "ostm0", "ostm1";
};
mstp6_clks: mstp6_clks@fcfe042c {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe042c 4>;
clocks = <&b_clk>, <&p0_clk>;
clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>;
clock-output-names = "ceu", "rtc";
};
mstp7_clks: mstp7_clks@fcfe0430 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0430 4>;
clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
clock-output-names = "ether", "usb0", "usb1";
};
mstp8_clks: mstp8_clks@fcfe0434 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0434 4>;
clocks = <&p1_clk>;
clock-indices = <R7S72100_CLK_MMCIF>;
clock-output-names = "mmcif";
};
mstp9_clks: mstp9_clks@fcfe0438 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0438 4>;
clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
clock-indices = <
R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
>;
clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
};
mstp10_clks: mstp10_clks@fcfe043c {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe043c 4>;
clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
<&p1_clk>;
clock-indices = <
R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
R7S72100_CLK_SPI4
>;
clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
};
mstp12_clks: mstp12_clks@fcfe0444 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0444 4>;
clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
clock-indices = <
R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
>;
clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
};
pinctrl: pin-controller@fcfe3000 {
compatible = "renesas,r7s72100-ports";
reg = <0xfcfe3000 0x4230>;
port0: gpio-0 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 6>;
};
port1: gpio-1 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 16 16>;
};
port2: gpio-2 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 32 16>;
};
port3: gpio-3 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 48 16>;
};
port4: gpio-4 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 64 16>;
};
port5: gpio-5 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 80 11>;
};
port6: gpio-6 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 96 16>;
};
port7: gpio-7 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 112 16>;
};
port8: gpio-8 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 128 16>;
};
port9: gpio-9 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 144 8>;
};
port10: gpio-10 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 160 16>;
};
port11: gpio-11 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 176 16>;
};
};
ostm0: timer@fcfec000 {
compatible = "renesas,r7s72100-ostm", "renesas,ostm";
reg = <0xfcfec000 0x30>;
interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
power-domains = <&cpg_clocks>;
status = "disabled";
};
ostm1: timer@fcfec400 {
compatible = "renesas,r7s72100-ostm", "renesas,ostm";
reg = <0xfcfec400 0x30>;
interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
power-domains = <&cpg_clocks>;
status = "disabled";
};
i2c0: i2c@fcfee000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
reg = <0xfcfee000 0x44>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
clock-frequency = <100000>;
power-domains = <&cpg_clocks>;
status = "disabled";
};
i2c1: i2c@fcfee400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
reg = <0xfcfee400 0x44>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
clock-frequency = <100000>;
power-domains = <&cpg_clocks>;
status = "disabled";
};
i2c2: i2c@fcfee800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
reg = <0xfcfee800 0x44>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
clock-frequency = <100000>;
power-domains = <&cpg_clocks>;
status = "disabled";
};
i2c3: i2c@fcfeec00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
reg = <0xfcfeec00 0x44>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
clock-frequency = <100000>;
power-domains = <&cpg_clocks>;
status = "disabled";
};
mtu2: timer@fcff0000 {
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
reg = <0xfcff0000 0x400>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tgi0a";
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
status = "disabled";
};
rtc: rtc@fcff1000 {
compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
reg = <0xfcff1000 0x2e>;
interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "alarm", "period", "carry";
clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
<&rtc_x3_clk>, <&extal_clk>;
clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
power-domains = <&cpg_clocks>;
status = "disabled";
};
};
usb_x1_clk: usb_x1 {
#clock-cells = <0>;
compatible = "fixed-clock";
/* If clk present, value must be set by board */
clock-frequency = <0>;
};
};

5
arch/arm/mach-rmobile/Kconfig
View file

@ -22,9 +22,14 @@ config RCAR_GEN3
imply CMD_MMC_SWRITE if MMC imply CMD_MMC_SWRITE if MMC
imply SUPPORT_EMMC_RPMB if MMC imply SUPPORT_EMMC_RPMB if MMC
config RZA1
prompt "Renesas ARM SoCs RZ/A1 (32bit)"
select CPU_V7A
endchoice endchoice
source "arch/arm/mach-rmobile/Kconfig.32" source "arch/arm/mach-rmobile/Kconfig.32"
source "arch/arm/mach-rmobile/Kconfig.64" source "arch/arm/mach-rmobile/Kconfig.64"
source "arch/arm/mach-rmobile/Kconfig.rza1"
endif endif

28
arch/arm/mach-rmobile/Kconfig.rza1 Normal file
View file

@ -0,0 +1,28 @@
if RZA1
# required by the Ethernet driver
config R7S72100
bool
default y
# required by serial and usb driver
config CPU_RZA1
bool
default y
choice
prompt "Renesas RZ/A1 board select"
# Renesas Supported Boards
config TARGET_GRPEACH
bool "GR-PEACH board"
endchoice
config SYS_SOC
default "rmobile"
# Renesas Supported Boards
source "board/renesas/grpeach/Kconfig"
endif

8
arch/arm/mach-rmobile/cpu_info.c
View file

@ -26,6 +26,7 @@ void enable_caches(void)
#endif #endif
#ifdef CONFIG_DISPLAY_CPUINFO #ifdef CONFIG_DISPLAY_CPUINFO
#ifndef CONFIG_RZA1
static u32 __rmobile_get_cpu_type(void) static u32 __rmobile_get_cpu_type(void)
{ {
return 0x0; return 0x0;
@ -105,4 +106,11 @@ int print_cpuinfo(void)
return 0; return 0;
} }
#else
int print_cpuinfo(void)
{
printf("CPU: Renesas Electronics RZ/A1\n");
return 0;
}
#endif
#endif /* CONFIG_DISPLAY_CPUINFO */ #endif /* CONFIG_DISPLAY_CPUINFO */

1
arch/arm/mach-rmobile/include/mach/rmobile.h
View file

@ -18,6 +18,7 @@
#include <asm/arch/r8a7794.h> #include <asm/arch/r8a7794.h>
#elif defined(CONFIG_RCAR_GEN3) #elif defined(CONFIG_RCAR_GEN3)
#include <asm/arch/rcar-gen3-base.h> #include <asm/arch/rcar-gen3-base.h>
#elif defined(CONFIG_R7S72100)
#else #else
#error "SOC Name not defined" #error "SOC Name not defined"
#endif #endif

10
arch/sh/Kconfig
View file

@ -75,10 +75,6 @@ config TARGET_AP325RXA
bool "Renesas AP-325RXA" bool "Renesas AP-325RXA"
select CPU_SH4 select CPU_SH4
config TARGET_ECOVEC
bool "EcoVec"
select CPU_SH4A
config TARGET_MIGOR config TARGET_MIGOR
bool "Migo-R" bool "Migo-R"
select CPU_SH4 select CPU_SH4
@ -111,10 +107,6 @@ config TARGET_SH7763RDP
bool "SH7763RDP" bool "SH7763RDP"
select CPU_SH4 select CPU_SH4
config TARGET_SH7785LCR
bool "SH7785LCR"
select CPU_SH4A
endchoice endchoice
config SYS_ARCH config SYS_ARCH
@ -135,7 +127,6 @@ source "board/ms7722se/Kconfig"
source "board/ms7750se/Kconfig" source "board/ms7750se/Kconfig"
source "board/renesas/MigoR/Kconfig" source "board/renesas/MigoR/Kconfig"
source "board/renesas/ap325rxa/Kconfig" source "board/renesas/ap325rxa/Kconfig"
source "board/renesas/ecovec/Kconfig"
source "board/renesas/r0p7734/Kconfig" source "board/renesas/r0p7734/Kconfig"
source "board/renesas/r2dplus/Kconfig" source "board/renesas/r2dplus/Kconfig"
source "board/renesas/r7780mp/Kconfig" source "board/renesas/r7780mp/Kconfig"
@ -146,7 +137,6 @@ source "board/renesas/sh7752evb/Kconfig"
source "board/renesas/sh7753evb/Kconfig" source "board/renesas/sh7753evb/Kconfig"
source "board/renesas/sh7757lcr/Kconfig" source "board/renesas/sh7757lcr/Kconfig"
source "board/renesas/sh7763rdp/Kconfig" source "board/renesas/sh7763rdp/Kconfig"
source "board/renesas/sh7785lcr/Kconfig"
source "board/shmin/Kconfig" source "board/shmin/Kconfig"
endmenu endmenu

4
arch/sh/include/asm/cpu_sh4.h
View file

@ -30,8 +30,6 @@
# include <asm/cpu_sh7722.h> # include <asm/cpu_sh7722.h>
#elif defined (CONFIG_CPU_SH7723) #elif defined (CONFIG_CPU_SH7723)
# include <asm/cpu_sh7723.h> # include <asm/cpu_sh7723.h>
#elif defined (CONFIG_CPU_SH7724)
# include <asm/cpu_sh7724.h>
#elif defined (CONFIG_CPU_SH7734) #elif defined (CONFIG_CPU_SH7734)
# include <asm/cpu_sh7734.h> # include <asm/cpu_sh7734.h>
#elif defined (CONFIG_CPU_SH7752) #elif defined (CONFIG_CPU_SH7752)
@ -44,8 +42,6 @@
# include <asm/cpu_sh7763.h> # include <asm/cpu_sh7763.h>
#elif defined (CONFIG_CPU_SH7780) #elif defined (CONFIG_CPU_SH7780)
# include <asm/cpu_sh7780.h> # include <asm/cpu_sh7780.h>
#elif defined (CONFIG_CPU_SH7785)
# include <asm/cpu_sh7785.h>
#else #else
# error "Unknown SH4 variant" # error "Unknown SH4 variant"
#endif #endif

209
arch/sh/include/asm/cpu_sh7724.h
View file

@ -1,209 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2008, 2011 Renesas Solutions Corp.
*
* SH7724 Internal I/O register
*/
#ifndef _ASM_CPU_SH7724_H_
#define _ASM_CPU_SH7724_H_
#define CACHE_OC_NUM_WAYS 4
#define CCR_CACHE_INIT 0x0000090d
/* EXP */
#define TRA 0xFF000020
#define EXPEVT 0xFF000024
#define INTEVT 0xFF000028
/* MMU */
#define PTEH 0xFF000000
#define PTEL 0xFF000004
#define TTB 0xFF000008
#define TEA 0xFF00000C
#define MMUCR 0xFF000010
#define PASCR 0xFF000070
#define IRMCR 0xFF000078
/* CACHE */
#define CCR 0xFF00001C
#define RAMCR 0xFF000074
/* INTC */
/* BSC */
#define MMSELR 0xFF800020
#define CMNCR 0xFEC10000
#define CS0BCR 0xFEC10004
#define CS2BCR 0xFEC10008
#define CS4BCR 0xFEC10010
#define CS5ABCR 0xFEC10014
#define CS5BBCR 0xFEC10018
#define CS6ABCR 0xFEC1001C
#define CS6BBCR 0xFEC10020
#define CS0WCR 0xFEC10024
#define CS2WCR 0xFEC10028
#define CS4WCR 0xFEC10030
#define CS5AWCR 0xFEC10034
#define CS5BWCR 0xFEC10038
#define CS6AWCR 0xFEC1003C
#define CS6BWCR 0xFEC10040
#define RBWTCNT 0xFEC10054
/* SBSC */
#define SBSC_SDCR 0xFE400008
#define SBSC_SDWCR 0xFE40000C
#define SBSC_SDPCR 0xFE400010
#define SBSC_RTCSR 0xFE400014
#define SBSC_RTCNT 0xFE400018
#define SBSC_RTCOR 0xFE40001C
#define SBSC_RFCR 0xFE400020
/* DSBC */
#define DBKIND 0xFD000008
#define DBSTATE 0xFD00000C
#define DBEN 0xFD000010
#define DBCMDCNT 0xFD000014
#define DBCKECNT 0xFD000018
#define DBCONF 0xFD000020
#define DBTR0 0xFD000030
#define DBTR1 0xFD000034
#define DBTR2 0xFD000038
#define DBTR3 0xFD00003C
#define DBRFPDN0 0xFD000040
#define DBRFPDN1 0xFD000044
#define DBRFPDN2 0xFD000048
#define DBRFSTS 0xFD00004C
#define DBMRCNT 0xFD000060
#define DBPDCNT0 0xFD000108
/* DMAC */
/* CPG */
#define FRQCRA 0xA4150000
#define FRQCRB 0xA4150004
#define FRQCR FRQCRA
#define VCLKCR 0xA4150004
#define SCLKACR 0xA4150008
#define SCLKBCR 0xA415000C
#define IRDACLKCR 0xA4150018
#define PLLCR 0xA4150024
#define DLLFRQ 0xA4150050
/* LOW POWER MODE */
#define STBCR 0xA4150020
#define MSTPCR0 0xA4150030
#define MSTPCR1 0xA4150034
#define MSTPCR2 0xA4150038
/* RWDT */
#define RWTCNT 0xA4520000
#define RWTCSR 0xA4520004
#define WTCNT RWTCNT
/* TMU */
#define TMU_BASE 0xFFD80000
/* TPU */
/* CMT */
#define CMSTR 0xA44A0000
#define CMCSR 0xA44A0060
#define CMCNT 0xA44A0064
#define CMCOR 0xA44A0068
/* MSIOF */
/* SCIF */
#define SCIF0_BASE 0xFFE00000
#define SCIF1_BASE 0xFFE10000
#define SCIF2_BASE 0xFFE20000
#define SCIF3_BASE 0xa4e30000
#define SCIF4_BASE 0xa4e40000
#define SCIF5_BASE 0xa4e50000
/* RTC */
/* IrDA */
/* KEYSC */
/* USB */
/* IIC */
/* FLCTL */
/* VPU */
/* VIO(CEU) */
/* VIO(VEU) */
/* VIO(BEU) */
/* 2DG */
/* LCDC */
/* VOU */
/* TSIF */
/* SIU */
/* ATAPI */
/* PFC */
#define PACR 0xA4050100
#define PBCR 0xA4050102
#define PCCR 0xA4050104
#define PDCR 0xA4050106
#define PECR 0xA4050108
#define PFCR 0xA405010A
#define PGCR 0xA405010C
#define PHCR 0xA405010E
#define PJCR 0xA4050110
#define PKCR 0xA4050112
#define PLCR 0xA4050114
#define PMCR 0xA4050116
#define PNCR 0xA4050118
#define PQCR 0xA405011A
#define PRCR 0xA405011C
#define PSCR 0xA405011E
#define PTCR 0xA4050140
#define PUCR 0xA4050142
#define PVCR 0xA4050144
#define PWCR 0xA4050146
#define PXCR 0xA4050148
#define PYCR 0xA405014A
#define PZCR 0xA405014C
#define PSELA 0xA405014E
#define PSELB 0xA4050150
#define PSELC 0xA4050152
#define PSELD 0xA4050154
#define PSELE 0xA4050156
#define HIZCRA 0xA4050158
#define HIZCRB 0xA405015A
#define HIZCRC 0xA405015C
#define HIZCRD 0xA405015E
#define MSELCRA 0xA4050180
#define MSELCRB 0xA4050182
#define PULCR 0xA4050184
#define DRVCRA 0xA405018A
#define DRVCRB 0xA405018C
/* I/O Port */
#define PADR 0xA4050120
#define PBDR 0xA4050122
#define PCDR 0xA4050124
#define PDDR 0xA4050126
#define PEDR 0xA4050128
#define PFDR 0xA405012A
#define PGDR 0xA405012C
#define PHDR 0xA405012E
#define PJDR 0xA4050130
#define PKDR 0xA4050132
#define PLDR 0xA4050134
#define PMDR 0xA4050136
#define PNDR 0xA4050138
#define PQDR 0xA405013A
#define PRDR 0xA405013C
#define PSDR 0xA405013E
#define PTDR 0xA4050160
#define PUDR 0xA4050162
#define PVDR 0xA4050164
#define PWDR 0xA4050166
#define PXDR 0xA4050168
#define PYDR 0xA405016A
#define PZDR 0xA405016C
/* UBC */
/* H-UDI */
#endif /* _ASM_CPU_SH7724_H_ */

119
arch/sh/include/asm/cpu_sh7785.h
View file

@ -1,119 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef _ASM_CPU_SH7785_H_
#define _ASM_CPU_SH7785_H_
/*
* Copyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
* Copyright (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*/
#define CACHE_OC_NUM_WAYS 1
#define CCR_CACHE_INIT 0x0000090b
/* Exceptions */
#define TRA 0xFF000020
#define EXPEVT 0xFF000024
#define INTEVT 0xFF000028
/* Cache Controller */
#define CCR 0xFF00001C
#define QACR0 0xFF000038
#define QACR1 0xFF00003C
#define RAMCR 0xFF000074
/* Watchdog Timer and Reset */
#define WTCNT WDTCNT
#define WDTST 0xFFCC0000
#define WDTCSR 0xFFCC0004
#define WDTBST 0xFFCC0008
#define WDTCNT 0xFFCC0010
#define WDTBCNT 0xFFCC0018
/* Timer Unit */
#define TMU_BASE 0xFFD80000
/* Serial Communication Interface with FIFO */
#define SCIF1_BASE 0xffeb0000
/* LBSC */
#define MMSELR 0xfc400020
#define LBSC_BASE 0xff800000
#define BCR (LBSC_BASE + 0x1000)
#define CS0BCR (LBSC_BASE + 0x2000)
#define CS1BCR (LBSC_BASE + 0x2010)
#define CS2BCR (LBSC_BASE + 0x2020)
#define CS3BCR (LBSC_BASE + 0x2030)
#define CS4BCR (LBSC_BASE + 0x2040)
#define CS5BCR (LBSC_BASE + 0x2050)
#define CS6BCR (LBSC_BASE + 0x2060)
#define CS0WCR (LBSC_BASE + 0x2008)
#define CS1WCR (LBSC_BASE + 0x2018)
#define CS2WCR (LBSC_BASE + 0x2028)
#define CS3WCR (LBSC_BASE + 0x2038)
#define CS4WCR (LBSC_BASE + 0x2048)
#define CS5WCR (LBSC_BASE + 0x2058)
#define CS6WCR (LBSC_BASE + 0x2068)
#define CS5PCR (LBSC_BASE + 0x2070)
#define CS6PCR (LBSC_BASE + 0x2080)
/* PCI Controller */
#define SH7780_PCIECR 0xFE000008
#define SH7780_PCIVID 0xFE040000
#define SH7780_PCIDID 0xFE040002
#define SH7780_PCICMD 0xFE040004
#define SH7780_PCISTATUS 0xFE040006
#define SH7780_PCIRID 0xFE040008
#define SH7780_PCIPIF 0xFE040009
#define SH7780_PCISUB 0xFE04000A
#define SH7780_PCIBCC 0xFE04000B
#define SH7780_PCICLS 0xFE04000C
#define SH7780_PCILTM 0xFE04000D
#define SH7780_PCIHDR 0xFE04000E
#define SH7780_PCIBIST 0xFE04000F
#define SH7780_PCIIBAR 0xFE040010
#define SH7780_PCIMBAR0 0xFE040014
#define SH7780_PCIMBAR1 0xFE040018
#define SH7780_PCISVID 0xFE04002C
#define SH7780_PCISID 0xFE04002E
#define SH7780_PCICP 0xFE040034
#define SH7780_PCIINTLINE 0xFE04003C
#define SH7780_PCIINTPIN 0xFE04003D
#define SH7780_PCIMINGNT 0xFE04003E
#define SH7780_PCIMAXLAT 0xFE04003F
#define SH7780_PCICID 0xFE040040
#define SH7780_PCINIP 0xFE040041
#define SH7780_PCIPMC 0xFE040042
#define SH7780_PCIPMCSR 0xFE040044
#define SH7780_PCIPMCSRBSE 0xFE040046
#define SH7780_PCI_CDD 0xFE040047
#define SH7780_PCICR 0xFE040100
#define SH7780_PCILSR0 0xFE040104
#define SH7780_PCILSR1 0xFE040108
#define SH7780_PCILAR0 0xFE04010C
#define SH7780_PCILAR1 0xFE040110
#define SH7780_PCIIR 0xFE040114
#define SH7780_PCIIMR 0xFE040118
#define SH7780_PCIAIR 0xFE04011C
#define SH7780_PCICIR 0xFE040120
#define SH7780_PCIAINT 0xFE040130
#define SH7780_PCIAINTM 0xFE040134
#define SH7780_PCIBMIR 0xFE040138
#define SH7780_PCIPAR 0xFE0401C0
#define SH7780_PCIPINT 0xFE0401CC
#define SH7780_PCIPINTM 0xFE0401D0
#define SH7780_PCIMBR0 0xFE0401E0
#define SH7780_PCIMBMR0 0xFE0401E4
#define SH7780_PCIMBR1 0xFE0401E8
#define SH7780_PCIMBMR1 0xFE0401EC
#define SH7780_PCIMBR2 0xFE0401F0
#define SH7780_PCIMBMR2 0xFE0401F4
#define SH7780_PCIIOBR 0xFE0401F8
#define SH7780_PCIIOBMR 0xFE0401FC
#define SH7780_PCICSCR0 0xFE040210
#define SH7780_PCICSCR1 0xFE040214
#define SH7780_PCICSAR0 0xFE040218
#define SH7780_PCICSAR1 0xFE04021C
#define SH7780_PCIPDR 0xFE040220
#endif /* _ASM_CPU_SH7780_H_ */

7
board/renesas/ecovec/MAINTAINERS
View file

@ -1,7 +0,0 @@
ECOVEC BOARD
M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
S: Maintained
F: board/renesas/ecovec/
F: include/configs/ecovec.h
F: configs/ecovec_defconfig

8
board/renesas/ecovec/Makefile
View file

@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2011 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
# Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
#
obj-y := ecovec.o
extra-y += lowlevel_init.o

98
board/renesas/ecovec/ecovec.c
View file

@ -1,98 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2009, 2011 Renesas Solutions Corp.
* Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com>
* Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <i2c.h>
#include <netdev.h>
/* USB power management register */
#define UPONCR0 0xA40501D4
int checkboard(void)
{
puts("BOARD: ecovec\n");
return 0;
}
static void debug_led(u8 led)
{
/* PDGR[0-4] is debug LED */
outb((inb(PGDR) & ~0x0F) | (led & 0x0F), PGDR);
}
int board_late_init(void)
{
u8 mac[6];
char env_mac[18];
udelay(1000);
/* SH-Eth (PLCR, PNCR, PXCR, PSELx )*/
outw(inw(PLCR) & ~0xFFF0, PLCR);
outw(inw(PNCR) & ~0x000F, PNCR);
outw(inw(PXCR) & ~0x0FC0, PXCR);
outw((inw(PSELB) & ~0x030F) | 0x020A, PSELB);
outw((inw(PSELC) & ~0x0307) | 0x0207, PSELC);
outw((inw(PSELE) & ~0x00c0) | 0x0080, PSELE);
debug_led(1 << 3);
outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2);
i2c_set_bus_num(1); /* Use I2C 1 */
/* Read MAC address */
i2c_read(0x50, 0x10, 0, mac, 6);
/* Set MAC address */
sprintf(env_mac, "%02X:%02X:%02X:%02X:%02X:%02X",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
env_set("ethaddr", env_mac);
debug_led(0x0F);
return 0;
}
int board_init(void)
{
/* LED (PTG) */
outw((inw(PGCR) & ~0xFF) | 0x55, PGCR);
outw((inw(HIZCRA) & ~0x02), HIZCRA);
debug_led(1 << 0);
/* SCIF0 (PTF, PTM) */
outw(inw(PFCR) & ~0x30, PFCR);
outw(inw(PMCR) & ~0x0C, PMCR);
outw((inw(PSELA) & ~0x40) | 0x40, PSELA);
debug_led(1 << 1);
/* RMII (PTA) */
outw((inw(PACR) & ~0x0C) | 0x04, PACR);
outb((inb(PADR) & ~0x02) | 0x02, PADR);
debug_led(1 << 2);
/* USB host */
outw((inw(PBCR) & ~0x300) | 0x100, PBCR);
outb((inb(PBDR) & ~0x10) | 0x10, PBDR);
outl(inl(MSTPCR2) & ~0x100000, MSTPCR2);
outw(0x0600, UPONCR0);
debug_led(1 << 3);
/* debug switch */
outw((inw(PVCR) & ~0x03) | 0x02 , PVCR);
return 0;
}

196
board/renesas/ecovec/lowlevel_init.S
View file

@ -1,196 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011 Renesas Solutions Corp.
* Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com>
*
* board/renesas/ecovec/lowlevel_init.S
*/
#include <config.h>
#include <asm/processor.h>
#include <asm/macro.h>
#include <configs/ecovec.h>
.global lowlevel_init
.text
.align 2
lowlevel_init:
/* jump to CONFIG_ECOVEC_ROMIMAGE_ADDR if bit 1 of PVDR_A */
mov.l PVDR_A, r1
mov.l PVDR_D, r2
mov.b @r1, r0
tst r0, r2
bt 1f
mov.l JUMP_A, r1
jmp @r1
nop
1:
/* Disable watchdog */
write16 RWTCSR_A, RWTCSR_D
/* MMU Disable */
write32 MMUCR_A, MMUCR_D
/* Setup clocks */
write32 PLLCR_A, PLLCR_D
write32 FRQCRA_A, FRQCRA_D
write32 FRQCRB_A, FRQCRB_D
wait_timer TIMER_D
write32 MMSELR_A, MMSELR_D
/* Srtup BSC */
write32 CMNCR_A, CMNCR_D
write32 CS0BCR_A, CS0BCR_D
write32 CS0WCR_A, CS0WCR_D
wait_timer TIMER_D
/* Setup SDRAM */
write32 DBPDCNT0_A, DBPDCNT0_D0
write32 DBCONF_A, DBCONF_D
write32 DBTR0_A, DBTR0_D
write32 DBTR1_A, DBTR1_D
write32 DBTR2_A, DBTR2_D
write32 DBTR3_A, DBTR3_D
write32 DBKIND_A, DBKIND_D
write32 DBCKECNT_A, DBCKECNT_D
wait_timer TIMER_D
write32 DBCMDCNT_A, DBCMDCNT_D0
write32 DBMRCNT_A, DBMRCNT_D0
write32 DBMRCNT_A, DBMRCNT_D1
write32 DBMRCNT_A, DBMRCNT_D2
write32 DBMRCNT_A, DBMRCNT_D3
write32 DBCMDCNT_A, DBCMDCNT_D0
write32 DBCMDCNT_A, DBCMDCNT_D1
write32 DBCMDCNT_A, DBCMDCNT_D1
write32 DBMRCNT_A, DBMRCNT_D4
write32 DBMRCNT_A, DBMRCNT_D5
write32 DBMRCNT_A, DBMRCNT_D6
wait_timer TIMER_D
write32 DBEN_A, DBEN_D
write32 DBRFPDN1_A, DBRFPDN1_D
write32 DBRFPDN2_A, DBRFPDN2_D
write32 DBCMDCNT_A, DBCMDCNT_D0
/* Dummy read */
mov.l DUMMY_A ,r1
synco
mov.l @r1, r0
synco
mov.l SDRAM_A ,r1
synco
mov.l @r1, r0
synco
wait_timer TIMER_D
add #4, r1
synco
mov.l @r1, r0
synco
wait_timer TIMER_D
add #4, r1
synco
mov.l @r1, r0
synco
wait_timer TIMER_D
add #4, r1
synco
mov.l @r1, r0
synco
wait_timer TIMER_D
write32 DBCMDCNT_A, DBCMDCNT_D0
write32 DBCMDCNT_A, DBCMDCNT_D1
write32 DBPDCNT0_A, DBPDCNT0_D1
write32 DBRFPDN0_A, DBRFPDN0_D
wait_timer TIMER_D
write32 CCR_A, CCR_D
stc sr, r0
mov.l SR_MASK_D, r1
and r1, r0
ldc r0, sr
rts
.align 2
PVDR_A: .long PVDR
PVDR_D: .long 0x00000001
JUMP_A: .long CONFIG_ECOVEC_ROMIMAGE_ADDR
TIMER_D: .long 64
RWTCSR_A: .long RWTCSR
RWTCSR_D: .long 0x0000A507
MMUCR_A: .long MMUCR
MMUCR_D: .long 0x00000004
PLLCR_A: .long PLLCR
PLLCR_D: .long 0x00004000
FRQCRA_A: .long FRQCRA
FRQCRA_D: .long 0x8E003508
FRQCRB_A: .long FRQCRB
FRQCRB_D: .long 0x0
MMSELR_A: .long MMSELR
MMSELR_D: .long 0xA5A50000
CMNCR_A: .long CMNCR
CMNCR_D: .long 0x00000013
CS0BCR_A: .long CS0BCR
CS0BCR_D: .long 0x11110400
CS0WCR_A: .long CS0WCR
CS0WCR_D: .long 0x00000440
DBPDCNT0_A: .long DBPDCNT0
DBPDCNT0_D0: .long 0x00000181
DBPDCNT0_D1: .long 0x00000080
DBCONF_A: .long DBCONF
DBCONF_D: .long 0x015B0002
DBTR0_A: .long DBTR0
DBTR0_D: .long 0x03061502
DBTR1_A: .long DBTR1
DBTR1_D: .long 0x02020102
DBTR2_A: .long DBTR2
DBTR2_D: .long 0x01090305
DBTR3_A: .long DBTR3
DBTR3_D: .long 0x00000002
DBKIND_A: .long DBKIND
DBKIND_D: .long 0x00000005
DBCKECNT_A: .long DBCKECNT
DBCKECNT_D: .long 0x00000001
DBCMDCNT_A: .long DBCMDCNT
DBCMDCNT_D0:.long 0x2
DBCMDCNT_D1:.long 0x4
DBMRCNT_A: .long DBMRCNT
DBMRCNT_D0: .long 0x00020000
DBMRCNT_D1: .long 0x00030000
DBMRCNT_D2: .long 0x00010040
DBMRCNT_D3: .long 0x00000532
DBMRCNT_D4: .long 0x00000432
DBMRCNT_D5: .long 0x000103C0
DBMRCNT_D6: .long 0x00010040
DBEN_A: .long DBEN
DBEN_D: .long 0x01
DBRFPDN0_A: .long DBRFPDN0
DBRFPDN1_A: .long DBRFPDN1
DBRFPDN2_A: .long DBRFPDN2
DBRFPDN0_D: .long 0x00010000
DBRFPDN1_D: .long 0x00000613
DBRFPDN2_D: .long 0x238C003A
SDRAM_A: .long 0xa8000000
DUMMY_A: .long 0x0c400000
CCR_A: .long CCR
CCR_D: .long 0x0000090B
SR_MASK_D: .long 0xEFFFFF0F

6
board/renesas/ecovec/Kconfig → board/renesas/grpeach/Kconfig
View file

@ -1,12 +1,12 @@
if TARGET_ECOVEC if TARGET_GRPEACH
config SYS_BOARD config SYS_BOARD
default "ecovec" default "grpeach"
config SYS_VENDOR config SYS_VENDOR
default "renesas" default "renesas"
config SYS_CONFIG_NAME config SYS_CONFIG_NAME
default "ecovec" default "grpeach"
endif endif

6
board/renesas/grpeach/MAINTAINERS Normal file
View file

@ -0,0 +1,6 @@
GRPEACH BOARD
M: Marek Vasut <marek.vasut@gmail.com>
S: Maintained
F: board/renesas/grpeach/
F: include/configs/grpeach.h
F: configs/grpeach_defconfig

8
board/renesas/grpeach/Makefile Normal file
View file

@ -0,0 +1,8 @@
#
# Copyright (C) 2017 Renesas Electronics
# Copyright (C) 2017 Chris Brandt
#
# SPDX-License-Identifier: GPL-2.0+
obj-y := grpeach.o
obj-y += lowlevel_init.o

52
board/renesas/grpeach/grpeach.c Normal file
View file

@ -0,0 +1,52 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Renesas Electronics
* Copyright (C) Chris Brandt
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#define RZA1_WDT_BASE 0xfcfe0000
#define WTCSR 0x00
#define WTCNT 0x02
#define WRCSR 0x04
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
return 0;
}
int dram_init(void)
{
if (fdtdec_setup_mem_size_base() != 0)
return -EINVAL;
return 0;
}
int dram_init_banksize(void)
{
fdtdec_setup_memory_banksize();
return 0;
}
void reset_cpu(ulong addr)
{
/* Dummy read (must read WRCSR:WOVF at least once before clearing) */
readb(RZA1_WDT_BASE + WRCSR);
writew(0xa500, RZA1_WDT_BASE + WRCSR);
writew(0x5a5f, RZA1_WDT_BASE + WRCSR);
writew(0x5a00, RZA1_WDT_BASE + WTCNT);
writew(0xa578, RZA1_WDT_BASE + WTCSR);
for (;;)
asm volatile("wfi");
}

107
board/renesas/grpeach/lowlevel_init.S Normal file
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@ -0,0 +1,107 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2017 Renesas Electronics
* Copyright (C) 2017 Chris Brandt
*/
#include <config.h>
#include <version.h>
#include <asm/macro.h>
/* Watchdog Registers */
#define RZA1_WDT_BASE 0xFCFE0000
#define WTCSR (RZA1_WDT_BASE + 0x00) /* Watchdog Timer Control Register */
#define WTCNT (RZA1_WDT_BASE + 0x02) /* Watchdog Timer Counter Register */
#define WRCSR (RZA1_WDT_BASE + 0x04) /* Watchdog Reset Control Register */
/* Standby controller registers (chapter 55) */
#define RZA1_STBCR_BASE 0xFCFE0020
#define STBCR1 (RZA1_STBCR_BASE + 0x00)
#define STBCR2 (RZA1_STBCR_BASE + 0x04)
#define STBCR3 (RZA1_STBCR_BASE + 0x400)
#define STBCR4 (RZA1_STBCR_BASE + 0x404)
#define STBCR5 (RZA1_STBCR_BASE + 0x408)
#define STBCR6 (RZA1_STBCR_BASE + 0x40c)
#define STBCR7 (RZA1_STBCR_BASE + 0x410)
#define STBCR8 (RZA1_STBCR_BASE + 0x414)
#define STBCR9 (RZA1_STBCR_BASE + 0x418)
#define STBCR10 (RZA1_STBCR_BASE + 0x41c)
#define STBCR11 (RZA1_STBCR_BASE + 0x420)
#define STBCR12 (RZA1_STBCR_BASE + 0x424)
#define STBCR13 (RZA1_STBCR_BASE + 0x450)
/* Clock Registers */
#define RZA1_FRQCR_BASE 0xFCFE0010
#define FRQCR (RZA1_FRQCR_BASE + 0x00)
#define FRQCR2 (RZA1_FRQCR_BASE + 0x04)
#define SYSCR1 0xFCFE0400 /* System control register 1 */
#define SYSCR2 0xFCFE0404 /* System control register 2 */
#define SYSCR3 0xFCFE0408 /* System control register 3 */
/* Disable WDT */
#define WTCSR_D 0xA518
#define WTCNT_D 0x5A00
/* Enable all peripheral clocks */
#define STBCR3_D 0x00000000
#define STBCR4_D 0x00000000
#define STBCR5_D 0x00000000
#define STBCR6_D 0x00000000
#define STBCR7_D 0x00000024
#define STBCR8_D 0x00000005
#define STBCR9_D 0x00000000
#define STBCR10_D 0x00000000
#define STBCR11_D 0x000000c0
#define STBCR12_D 0x000000f0
/*
* Set all system clocks to full speed.
* On reset, the CPU will be running at 1/2 speed.
* In the Hardware Manual, see Table 6.3 Settable Frequency Ranges
*/
#define FRQCR_D 0x0035
#define FRQCR2_D 0x0001
.global lowlevel_init
.text
.align 2
lowlevel_init:
/* PL310 init */
write32 0x3fffff80, 0x00000001
/* Disable WDT */
write16 WTCSR, WTCSR_D
write16 WTCNT, WTCNT_D
/* Set clocks */
write16 FRQCR, FRQCR_D
write16 FRQCR2, FRQCR2_D
/* Enable all peripherals(Standby Control) */
write8 STBCR3, STBCR3_D
write8 STBCR4, STBCR4_D
write8 STBCR5, STBCR5_D
write8 STBCR6, STBCR6_D
write8 STBCR7, STBCR7_D
write8 STBCR8, STBCR8_D
write8 STBCR9, STBCR9_D
write8 STBCR10, STBCR10_D
write8 STBCR11, STBCR11_D
write8 STBCR12, STBCR12_D
/* For serial booting, enable read ahead caching to speed things up */
#define DRCR_0 0x3FEFA00C
write32 DRCR_0, 0x00010100 /* Read Burst ON, Length=2 */
/* Enable all internal RAM */
write8 SYSCR1, 0xFF
write8 SYSCR2, 0xFF
write8 SYSCR3, 0xFF
nop
/* back to arch calling code */
mov pc, lr
.align 4

2
board/renesas/sh7757lcr/README.sh7757lcr
View file

@ -20,7 +20,7 @@ configuration for This board:
You can select the configuration as follows: You can select the configuration as follows:
- make sh7785lcr_config - make sh7757lcr_config
This board specific command: This board specific command:

12
board/renesas/sh7785lcr/Kconfig
View file

@ -1,12 +0,0 @@
if TARGET_SH7785LCR
config SYS_BOARD
default "sh7785lcr"
config SYS_VENDOR
default "renesas"
config SYS_CONFIG_NAME
default "sh7785lcr"
endif

7
board/renesas/sh7785lcr/MAINTAINERS
View file

@ -1,7 +0,0 @@
SH7785LCR BOARD
#M: -
S: Maintained
F: board/renesas/sh7785lcr/
F: include/configs/sh7785lcr.h
F: configs/sh7785lcr_defconfig
F: configs/sh7785lcr_32bit_defconfig

7
board/renesas/sh7785lcr/Makefile
View file

@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
#
obj-y := sh7785lcr.o selfcheck.o rtl8169_mac.o
extra-y += lowlevel_init.o

123
board/renesas/sh7785lcr/README.sh7785lcr
View file

@ -1,123 +0,0 @@
========================================
Renesas Technology R0P7785LC0011RL board
========================================
This board specification:
=========================
The R0P7785LC0011RL(board config name:sh7785lcr) has the following device:
- SH7785 (SH-4A)
- DDR2-SDRAM 512MB
- NOR Flash 64MB
- 2D Graphic controller
- SATA controller
- Ethernet controller
- USB host/peripheral controller
- SD controller
- I2C controller
- RTC
This board has 2 physical memory maps. It can be changed with DIP switch(S2-5).
phys address | S2-5 = OFF | S2-5 = ON
-------------------------------+---------------+---------------
0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
0x04000000 - 0x05ffffff(CS1) | PLD | PLD
0x06000000 - 0x07ffffff(CS1) | reserved | I2C
0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
0x14000000 - 0x17ffffff(CS5) | I2C | USB
0x18000000 - 0x1bffffff(CS6) | reserved | SD
0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
configuration for This board:
=============================
You can choose configuration as follows:
- make sh7785lcr_config
- make sh7785lcr_32bit_config
When you use "make sh7785lcr_config", there is build U-Boot for 29-bit
address mode. This mode can use 128MB DDR-SDRAM.
When you use "make sh7785lcr_32bit_config", there is build U-Boot for 32-bit
extended address mode. This mode can use 384MB DDR-SDRAM. And if you run
"pmb" command, this mode can use 512MB DDR-SDRAM.
* 32-bit extended address mode PMB mapping *
a) on start-up
virt | phys | size | device
-------------+---------------+---------------+---------------
0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable)
0xa0000000 | 0x00000000 | 64MB | NOR Flash
0xa4000000 | 0x04000000 | 16MB | PLD
0xa6000000 | 0x08000000 | 16MB | USB
0xa8000000 | 0x48000000 | 384MB | DDR-SDRAM (Non-cacheable)
b) after "pmb" command
virt | phys | size | device
-------------+---------------+---------------+---------------
0x80000000 | 0x40000000 | 512MB | DDR-SDRAM (Cacheable)
0xa0000000 | 0x40000000 | 512MB | DDR-SDRAM (Non-cacheable)
This board specific command:
============================
This board has the following its specific command:
- hwtest
- printmac
- setmac
- pmb (sh7785lcr_32bit_config only)
1. hwtest
This is self-check command. This command has the following options:
- all : test all hardware
- pld : output PLD version
- led : turn on LEDs
- dipsw : test DIP switch
- sm107 : output SM107 version
- net : check RTL8110 ID
- sata : check SiI3512 ID
- net : output PCI slot device ID
i.e)
=> hwtest led
turn on LEDs 3, 5, 7, 9
turn on LEDs 4, 6, 8, 10
=> hwtest net
Ethernet OK
2. printmac
This command outputs MAC address of this board.
i.e)
=> printmac
MAC = 00:00:87:**:**:**
3. setmac
This command writes MAC address of this board.
i.e)
=> setmac 00:00:87:**:**:**
4. pmb
This command change PMB for DDR-SDRAM all mapping. However you cannot use
NOR Flash and USB Host on U-Boot when you run this command.
i.e)
=> pmb

361
board/renesas/sh7785lcr/lowlevel_init.S
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@ -1,361 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*/
#include <config.h>
#include <asm/processor.h>
#include <asm/macro.h>
#include <asm/processor.h>
.global lowlevel_init
.text
.align 2
lowlevel_init:
wait_timer WAIT_200US
wait_timer WAIT_200US
/*------- LBSC -------*/
write32 MMSELR_A, MMSELR_D
/*------- DBSC2 -------*/
write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D
write32 DBSC2_DBTR0_A, DBSC2_DBTR0_D
write32 DBSC2_DBTR1_A, DBSC2_DBTR1_D
write32 DBSC2_DBTR2_A, DBSC2_DBTR2_D
write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1
write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2
wait_timer WAIT_200US
write32 DBSC2_DBDICODTOCD_A, DBSC2_DBDICODTOCD_D
write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_CKE_H
wait_timer WAIT_200US
write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS2
write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS3
write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_1
write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_2
wait_timer WAIT_200US
write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_2
write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
write32 DBSC2_DBEN_A, DBSC2_DBEN_D
write32 DBSC2_DBRFCNT1_A, DBSC2_DBRFCNT1_D
write32 DBSC2_DBRFCNT2_A, DBSC2_DBRFCNT2_D
write32 DBSC2_DBRFCNT0_A, DBSC2_DBRFCNT0_D
wait_timer WAIT_200US
/*------- GPIO -------*/
write16 PACR_A, PXCR_D
write16 PBCR_A, PXCR_D
write16 PCCR_A, PXCR_D
write16 PDCR_A, PXCR_D
write16 PECR_A, PXCR_D
write16 PFCR_A, PXCR_D
write16 PGCR_A, PXCR_D
write16 PHCR_A, PHCR_D
write16 PJCR_A, PJCR_D
write16 PKCR_A, PKCR_D
write16 PLCR_A, PXCR_D
write16 PMCR_A, PMCR_D
write16 PNCR_A, PNCR_D
write16 PPCR_A, PXCR_D
write16 PQCR_A, PXCR_D
write16 PRCR_A, PXCR_D
write8 PEPUPR_A, PEPUPR_D
write8 PHPUPR_A, PHPUPR_D
write8 PJPUPR_A, PJPUPR_D
write8 PKPUPR_A, PKPUPR_D
write8 PLPUPR_A, PLPUPR_D
write8 PMPUPR_A, PMPUPR_D
write8 PNPUPR_A, PNPUPR_D
write16 PPUPR1_A, PPUPR1_D
write16 PPUPR2_A, PPUPR2_D
write16 P1MSELR_A, P1MSELR_D
write16 P2MSELR_A, P2MSELR_D
/*------- LBSC -------*/
write32 BCR_A, BCR_D
write32 CS0BCR_A, CS0BCR_D
write32 CS0WCR_A, CS0WCR_D
write32 CS1BCR_A, CS1BCR_D
write32 CS1WCR_A, CS1WCR_D
write32 CS4BCR_A, CS4BCR_D
write32 CS4WCR_A, CS4WCR_D
mov.l PASCR_A, r0
mov.l @r0, r2
mov.l PASCR_32BIT_MODE, r1
tst r1, r2
bt lbsc_29bit
write32 CS2BCR_A, CS_USB_BCR_D
write32 CS2WCR_A, CS_USB_WCR_D
write32 CS3BCR_A, CS_SD_BCR_D
write32 CS3WCR_A, CS_SD_WCR_D
write32 CS5BCR_A, CS_I2C_BCR_D
write32 CS5WCR_A, CS_I2C_WCR_D
write32 CS6BCR_A, CS0BCR_D
write32 CS6WCR_A, CS0WCR_D
bra lbsc_end
nop
lbsc_29bit:
write32 CS5BCR_A, CS_USB_BCR_D
write32 CS5WCR_A, CS_USB_WCR_D
write32 CS6BCR_A, CS_SD_BCR_D
write32 CS6WCR_A, CS_SD_WCR_D
lbsc_end:
#if defined(CONFIG_SH_32BIT)
/*------- set PMB -------*/
write32 PASCR_A, PASCR_29BIT_D
write32 MMUCR_A, MMUCR_D
/*****************************************************************
* ent virt phys v sz c wt
* 0 0xa0000000 0x00000000 1 64M 0 0
* 1 0xa4000000 0x04000000 1 16M 0 0
* 2 0xa6000000 0x08000000 1 16M 0 0
* 9 0x88000000 0x48000000 1 128M 1 1
* 10 0x90000000 0x50000000 1 128M 1 1
* 11 0x98000000 0x58000000 1 128M 1 1
* 13 0xa8000000 0x48000000 1 128M 0 0
* 14 0xb0000000 0x50000000 1 128M 0 0
* 15 0xb8000000 0x58000000 1 128M 0 0
*/
write32 PMB_ADDR_FLASH_A, PMB_ADDR_FLASH_D
write32 PMB_DATA_FLASH_A, PMB_DATA_FLASH_D
write32 PMB_ADDR_CPLD_A, PMB_ADDR_CPLD_D
write32 PMB_DATA_CPLD_A, PMB_DATA_CPLD_D
write32 PMB_ADDR_USB_A, PMB_ADDR_USB_D
write32 PMB_DATA_USB_A, PMB_DATA_USB_D
write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
write32 PMB_ADDR_DDR_C2_A, PMB_ADDR_DDR_C2_D
write32 PMB_DATA_DDR_C2_A, PMB_DATA_DDR_C2_D
write32 PMB_ADDR_DDR_C3_A, PMB_ADDR_DDR_C3_D
write32 PMB_DATA_DDR_C3_A, PMB_DATA_DDR_C3_D
write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
write32 PMB_ADDR_DDR_N2_A, PMB_ADDR_DDR_N2_D
write32 PMB_DATA_DDR_N2_A, PMB_DATA_DDR_N2_D
write32 PMB_ADDR_DDR_N3_A, PMB_ADDR_DDR_N3_D
write32 PMB_DATA_DDR_N3_A, PMB_DATA_DDR_N3_D
write32 PASCR_A, PASCR_INIT
mov.l DUMMY_ADDR, r0
icbi @r0
#endif
write32 CCR_A, CCR_D
rts
nop
.align 4
/*------- GPIO -------*/
/* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */
PXCR_D: .word 0x0000
PHCR_D: .word 0x00c0
PJCR_D: .word 0xc3fc
PKCR_D: .word 0x03ff
PMCR_D: .word 0xffff
PNCR_D: .word 0xf0c3
PEPUPR_D: .long 0xff
PHPUPR_D: .long 0x00
PJPUPR_D: .long 0x00
PKPUPR_D: .long 0x00
PLPUPR_D: .long 0x00
PMPUPR_D: .long 0xfc
PNPUPR_D: .long 0x00
PPUPR1_D: .word 0xffbf
PPUPR2_D: .word 0xff00
P1MSELR_D: .word 0x3780
P2MSELR_D: .word 0x0000
#define GPIO_BASE 0xffe70000
PACR_A: .long GPIO_BASE + 0x00
PBCR_A: .long GPIO_BASE + 0x02
PCCR_A: .long GPIO_BASE + 0x04
PDCR_A: .long GPIO_BASE + 0x06
PECR_A: .long GPIO_BASE + 0x08
PFCR_A: .long GPIO_BASE + 0x0a
PGCR_A: .long GPIO_BASE + 0x0c
PHCR_A: .long GPIO_BASE + 0x0e
PJCR_A: .long GPIO_BASE + 0x10
PKCR_A: .long GPIO_BASE + 0x12
PLCR_A: .long GPIO_BASE + 0x14
PMCR_A: .long GPIO_BASE + 0x16
PNCR_A: .long GPIO_BASE + 0x18
PPCR_A: .long GPIO_BASE + 0x1a
PQCR_A: .long GPIO_BASE + 0x1c
PRCR_A: .long GPIO_BASE + 0x1e
PEPUPR_A: .long GPIO_BASE + 0x48
PHPUPR_A: .long GPIO_BASE + 0x4e
PJPUPR_A: .long GPIO_BASE + 0x50
PKPUPR_A: .long GPIO_BASE + 0x52
PLPUPR_A: .long GPIO_BASE + 0x54
PMPUPR_A: .long GPIO_BASE + 0x56
PNPUPR_A: .long GPIO_BASE + 0x58
PPUPR1_A: .long GPIO_BASE + 0x60
PPUPR2_A: .long GPIO_BASE + 0x62
P1MSELR_A: .long GPIO_BASE + 0x80
P2MSELR_A: .long GPIO_BASE + 0x82
MMSELR_A: .long 0xfc400020
#if defined(CONFIG_SH_32BIT)
MMSELR_D: .long 0xa5a50005
#else
MMSELR_D: .long 0xa5a50002
#endif
/*------- DBSC2 -------*/
#define DBSC2_BASE 0xfe800000
DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c
DBSC2_DBEN_A: .long DBSC2_BASE + 0x10
DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14
DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20
DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30
DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34
DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38
DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40
DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44
DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48
DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c
DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50
DBSC2_DBDICODTOCD_A:.long DBSC2_BASE + 0x54
DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60
DDR_DUMMY_ACCESS_A: .long 0x40000000
DBSC2_DBCONF_D: .long 0x00630002
DBSC2_DBTR0_D: .long 0x050b1f04
DBSC2_DBTR1_D: .long 0x00040204
DBSC2_DBTR2_D: .long 0x02100308
DBSC2_DBFREQ_D1: .long 0x00000000
DBSC2_DBFREQ_D2: .long 0x00000100
DBSC2_DBDICODTOCD_D:.long 0x000f0907
DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003
DBSC2_DBCMDCNT_D_PALL: .long 0x00000002
DBSC2_DBCMDCNT_D_REF: .long 0x00000004
DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000
DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000
DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006
DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386
DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952
DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852
DBSC2_DBEN_D: .long 0x00000001
DBSC2_DBPDCNT0_D3: .long 0x00000080
DBSC2_DBRFCNT1_D: .long 0x00000926
DBSC2_DBRFCNT2_D: .long 0x00fe00fe
DBSC2_DBRFCNT0_D: .long 0x00010000
WAIT_200US: .long 33333
/*------- LBSC -------*/
PASCR_A: .long 0xff000070
PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */
BCR_A: .long BCR
CS0BCR_A: .long CS0BCR
CS0WCR_A: .long CS0WCR
CS1BCR_A: .long CS1BCR
CS1WCR_A: .long CS1WCR
CS2BCR_A: .long CS2BCR
CS2WCR_A: .long CS2WCR
CS3BCR_A: .long CS3BCR
CS3WCR_A: .long CS3WCR
CS4BCR_A: .long CS4BCR
CS4WCR_A: .long CS4WCR
CS5BCR_A: .long CS5BCR
CS5WCR_A: .long CS5WCR
CS6BCR_A: .long CS6BCR
CS6WCR_A: .long CS6WCR
BCR_D: .long 0x80000003
CS0BCR_D: .long 0x22222340
CS0WCR_D: .long 0x00111118
CS1BCR_D: .long 0x11111100
CS1WCR_D: .long 0x33333303
CS4BCR_D: .long 0x11111300
CS4WCR_D: .long 0x00101012
/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */
CS_USB_BCR_D: .long 0x11111200
CS_USB_WCR_D: .long 0x00020005
/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
CS_SD_BCR_D: .long 0x00000300
CS_SD_WCR_D: .long 0x00030108
/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */
CS_I2C_BCR_D: .long 0x11111100
CS_I2C_WCR_D: .long 0x00000003
#if defined(CONFIG_SH_32BIT)
/*------- set PMB -------*/
PMB_ADDR_FLASH_A: .long PMB_ADDR_BASE(0)
PMB_ADDR_CPLD_A: .long PMB_ADDR_BASE(1)
PMB_ADDR_USB_A: .long PMB_ADDR_BASE(2)
PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(9)
PMB_ADDR_DDR_C2_A: .long PMB_ADDR_BASE(10)
PMB_ADDR_DDR_C3_A: .long PMB_ADDR_BASE(11)
PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(13)
PMB_ADDR_DDR_N2_A: .long PMB_ADDR_BASE(14)
PMB_ADDR_DDR_N3_A: .long PMB_ADDR_BASE(15)
PMB_ADDR_FLASH_D: .long mk_pmb_addr_val(0xa0)
PMB_ADDR_CPLD_D: .long mk_pmb_addr_val(0xa4)
PMB_ADDR_USB_D: .long mk_pmb_addr_val(0xa6)
PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
PMB_ADDR_DDR_C2_D: .long mk_pmb_addr_val(0x90)
PMB_ADDR_DDR_C3_D: .long mk_pmb_addr_val(0x98)
PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
PMB_ADDR_DDR_N2_D: .long mk_pmb_addr_val(0xb0)
PMB_ADDR_DDR_N3_D: .long mk_pmb_addr_val(0xb8)
PMB_DATA_FLASH_A: .long PMB_DATA_BASE(0)
PMB_DATA_CPLD_A: .long PMB_DATA_BASE(1)
PMB_DATA_USB_A: .long PMB_DATA_BASE(2)
PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(9)
PMB_DATA_DDR_C2_A: .long PMB_DATA_BASE(10)
PMB_DATA_DDR_C3_A: .long PMB_DATA_BASE(11)
PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(13)
PMB_DATA_DDR_N2_A: .long PMB_DATA_BASE(14)
PMB_DATA_DDR_N3_A: .long PMB_DATA_BASE(15)
/* ppn ub v s1 s0 c wt */
PMB_DATA_FLASH_D: .long mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1)
PMB_DATA_CPLD_D: .long mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1)
PMB_DATA_USB_D: .long mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1)
PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
PMB_DATA_DDR_C2_D: .long mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1)
PMB_DATA_DDR_C3_D: .long mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1)
PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
PMB_DATA_DDR_N2_D: .long mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1)
PMB_DATA_DDR_N3_D: .long mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1)
DUMMY_ADDR: .long 0xa0000000
PASCR_29BIT_D: .long 0x00000000
PASCR_INIT: .long 0x80000080 /* check booting mode */
MMUCR_A: .long 0xff000010
MMUCR_D: .long 0x00000004 /* clear ITLB */
#endif /* CONFIG_SH_32BIT */
CCR_A: .long 0xff00001c
CCR_D: .long 0x0000090b

43
board/renesas/sh7785lcr/rtl8169.h
View file

@ -1,43 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*/
#define PCIREG_8(_adr) (*(volatile unsigned char *)(_adr))
#define PCIREG_32(_adr) (*(volatile unsigned long *)(_adr))
#define PCI_PAR PCIREG_32(0xfe0401c0)
#define PCI_PDR PCIREG_32(0xfe040220)
#define PCI_CR PCIREG_32(0xfe040100)
#define PCI_CONF1 PCIREG_32(0xfe040004)
#define HIGH 1
#define LOW 0
#define PCI_PROG 0x80
#define PCI_EEP_ADDRESS (unsigned short)0x0007
#define PCI_MAC_ADDRESS_SIZE 3
#define TIME1 100
#define TIME2 20000
#define BIT_DUMMY 0
#define MAC_EEP_READ 1
#define MAC_EEP_WRITE 2
#define MAC_EEP_ERACE 3
#define MAC_EEP_EWEN 4
#define MAC_EEP_EWDS 5
/* RTL8169 */
const unsigned short EEPROM_W_Data_8169_A[] = {
0x8129, 0x10ec, 0x8169, 0x1154, 0x032b,
0x4020, 0xa101
};
const unsigned short EEPROM_W_Data_8169_B[] = {
0x4d15, 0xf7c2, 0x8000, 0x0000, 0x0000, 0x1300,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
};

330
board/renesas/sh7785lcr/rtl8169_mac.c
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@ -1,330 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*/
#include <common.h>
#include "rtl8169.h"
static unsigned char *PCI_MEMR;
static void mac_delay(unsigned int cnt)
{
udelay(cnt);
}
static void mac_pci_setup(void)
{
unsigned long pci_data;
PCI_PAR = 0x00000010;
PCI_PDR = 0x00001000;
PCI_PAR = 0x00000004;
pci_data = PCI_PDR;
PCI_PDR = pci_data | 0x00000007;
PCI_PAR = 0x00000010;
PCI_MEMR = (unsigned char *)((PCI_PDR | 0xFE240050) & 0xFFFFFFF0);
}
static void EECS(int level)
{
unsigned char data = *PCI_MEMR;
if (level)
*PCI_MEMR = data | 0x08;
else
*PCI_MEMR = data & 0xf7;
}
static void EECLK(int level)
{
unsigned char data = *PCI_MEMR;
if (level)
*PCI_MEMR = data | 0x04;
else
*PCI_MEMR = data & 0xfb;
}
static void EEDI(int level)
{
unsigned char data = *PCI_MEMR;
if (level)
*PCI_MEMR = data | 0x02;
else
*PCI_MEMR = data & 0xfd;
}
static inline void sh7785lcr_bitset(unsigned short bit)
{
if (bit)
EEDI(HIGH);
else
EEDI(LOW);
EECLK(LOW);
mac_delay(TIME1);
EECLK(HIGH);
mac_delay(TIME1);
EEDI(LOW);
}
static inline unsigned char sh7785lcr_bitget(void)
{
unsigned char bit;
EECLK(LOW);
mac_delay(TIME1);
bit = *PCI_MEMR & 0x01;
EECLK(HIGH);
mac_delay(TIME1);
return bit;
}
static inline void sh7785lcr_setcmd(unsigned char command)
{
sh7785lcr_bitset(BIT_DUMMY);
switch (command) {
case MAC_EEP_READ:
sh7785lcr_bitset(1);
sh7785lcr_bitset(1);
sh7785lcr_bitset(0);
break;
case MAC_EEP_WRITE:
sh7785lcr_bitset(1);
sh7785lcr_bitset(0);
sh7785lcr_bitset(1);
break;
case MAC_EEP_ERACE:
sh7785lcr_bitset(1);
sh7785lcr_bitset(1);
sh7785lcr_bitset(1);
break;
case MAC_EEP_EWEN:
sh7785lcr_bitset(1);
sh7785lcr_bitset(0);
sh7785lcr_bitset(0);
break;
case MAC_EEP_EWDS:
sh7785lcr_bitset(1);
sh7785lcr_bitset(0);
sh7785lcr_bitset(0);
break;
default:
break;
}
}
static inline unsigned short sh7785lcr_getdt(void)
{
unsigned short data = 0;
int i;
sh7785lcr_bitget(); /* DUMMY */
for (i = 0 ; i < 16 ; i++) {
data <<= 1;
data |= sh7785lcr_bitget();
}
return data;
}
static inline void sh7785lcr_setadd(unsigned short address)
{
sh7785lcr_bitset(address & 0x0020); /* A5 */
sh7785lcr_bitset(address & 0x0010); /* A4 */
sh7785lcr_bitset(address & 0x0008); /* A3 */
sh7785lcr_bitset(address & 0x0004); /* A2 */
sh7785lcr_bitset(address & 0x0002); /* A1 */
sh7785lcr_bitset(address & 0x0001); /* A0 */
}
static inline void sh7785lcr_setdata(unsigned short data)
{
sh7785lcr_bitset(data & 0x8000);
sh7785lcr_bitset(data & 0x4000);
sh7785lcr_bitset(data & 0x2000);
sh7785lcr_bitset(data & 0x1000);
sh7785lcr_bitset(data & 0x0800);
sh7785lcr_bitset(data & 0x0400);
sh7785lcr_bitset(data & 0x0200);
sh7785lcr_bitset(data & 0x0100);
sh7785lcr_bitset(data & 0x0080);
sh7785lcr_bitset(data & 0x0040);
sh7785lcr_bitset(data & 0x0020);
sh7785lcr_bitset(data & 0x0010);
sh7785lcr_bitset(data & 0x0008);
sh7785lcr_bitset(data & 0x0004);
sh7785lcr_bitset(data & 0x0002);
sh7785lcr_bitset(data & 0x0001);
}
static void sh7785lcr_datawrite(const unsigned short *data, unsigned short address,
unsigned int count)
{
unsigned int i;
for (i = 0; i < count; i++) {
EECS(HIGH);
EEDI(LOW);
mac_delay(TIME1);
sh7785lcr_setcmd(MAC_EEP_WRITE);
sh7785lcr_setadd(address++);
sh7785lcr_setdata(*(data + i));
EECLK(LOW);
EEDI(LOW);
EECS(LOW);
mac_delay(TIME2);
}
}
static void sh7785lcr_macerase(void)
{
unsigned int i;
unsigned short pci_address = 7;
for (i = 0; i < 3; i++) {
EECS(HIGH);
EEDI(LOW);
mac_delay(TIME1);
sh7785lcr_setcmd(MAC_EEP_ERACE);
sh7785lcr_setadd(pci_address++);
mac_delay(TIME1);
EECLK(LOW);
EEDI(LOW);
EECS(LOW);
}
mac_delay(TIME2);
printf("\n\nErace End\n");
for (i = 0; i < 10; i++)
mac_delay(TIME2);
}
static void sh7785lcr_macwrite(unsigned short *data)
{
sh7785lcr_macerase();
sh7785lcr_datawrite(EEPROM_W_Data_8169_A, 0x0000, 7);
sh7785lcr_datawrite(data, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE);
sh7785lcr_datawrite(EEPROM_W_Data_8169_B, 0x000a, 54);
}
void sh7785lcr_macdtrd(unsigned char *buf, unsigned short address, unsigned int count)
{
unsigned int i;
unsigned short wk;
for (i = 0 ; i < count; i++) {
EECS(HIGH);
EEDI(LOW);
mac_delay(TIME1);
sh7785lcr_setcmd(MAC_EEP_READ);
sh7785lcr_setadd(address++);
wk = sh7785lcr_getdt();
*buf++ = (unsigned char)(wk & 0xff);
*buf++ = (unsigned char)((wk >> 8) & 0xff);
EECLK(LOW);
EEDI(LOW);
EECS(LOW);
}
}
static void sh7785lcr_macadrd(unsigned char *buf)
{
*PCI_MEMR = PCI_PROG;
sh7785lcr_macdtrd(buf, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE);
}
static void sh7785lcr_eepewen(void)
{
*PCI_MEMR = PCI_PROG;
mac_delay(TIME1);
EECS(LOW);
EECLK(LOW);
EEDI(LOW);
EECS(HIGH);
mac_delay(TIME1);
sh7785lcr_setcmd(MAC_EEP_EWEN);
sh7785lcr_bitset(1);
sh7785lcr_bitset(1);
sh7785lcr_bitset(BIT_DUMMY);
sh7785lcr_bitset(BIT_DUMMY);
sh7785lcr_bitset(BIT_DUMMY);
sh7785lcr_bitset(BIT_DUMMY);
EECLK(LOW);
EEDI(LOW);
EECS(LOW);
mac_delay(TIME1);
}
void mac_write(unsigned short *data)
{
mac_pci_setup();
sh7785lcr_eepewen();
sh7785lcr_macwrite(data);
}
void mac_read(void)
{
unsigned char data[6];
mac_pci_setup();
sh7785lcr_macadrd(data);
printf("Mac = %02x:%02x:%02x:%02x:%02x:%02x\n",
data[0], data[1], data[2], data[3], data[4], data[5]);
}
int do_set_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i;
unsigned char mac[6];
char *s, *e;
if (argc != 2)
return cmd_usage(cmdtp);
s = argv[1];
for (i = 0; i < 6; i++) {
mac[i] = s ? simple_strtoul(s, &e, 16) : 0;
if (s)
s = (*e) ? e + 1 : e;
}
mac_write((unsigned short *)mac);
return 0;
}
U_BOOT_CMD(
setmac, 2, 1, do_set_mac,
"write MAC address for RTL8110SCL",
"\n"
"setmac <mac address> - write MAC address for RTL8110SCL"
);
int do_print_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc != 1)
return cmd_usage(cmdtp);
mac_read();
return 0;
}
U_BOOT_CMD(
printmac, 1, 1, do_print_mac,
"print MAC address for RTL8110",
"\n"
" - print MAC address for RTL8110"
);

150
board/renesas/sh7785lcr/selfcheck.c
View file

@ -1,150 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*/
#include <common.h>
#include <console.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/pci.h>
#if defined(CONFIG_CPU_32BIT)
#define NOCACHE_OFFSET 0x00000000
#else
#define NOCACHE_OFFSET 0xa0000000
#endif
#define PLD_LEDCR (0x04000008 + NOCACHE_OFFSET)
#define PLD_SWSR (0x0400000a + NOCACHE_OFFSET)
#define PLD_VERSR (0x0400000c + NOCACHE_OFFSET)
#define SM107_DEVICEID (0x13e00060 + NOCACHE_OFFSET)
static void test_pld(void)
{
printf("PLD version = %04x\n", readb(PLD_VERSR));
}
static void test_sm107(void)
{
printf("SM107 device ID = %04x\n", readl(SM107_DEVICEID));
}
static void test_led(void)
{
printf("turn on LEDs 3, 5, 7, 9\n");
writeb(0x55, PLD_LEDCR);
mdelay(2000);
printf("turn on LEDs 4, 6, 8, 10\n");
writeb(0xaa, PLD_LEDCR);
mdelay(2000);
writeb(0x00, PLD_LEDCR);
}
static void test_dipsw(void)
{
printf("Please DIPSW set = B'0101\n");
while (readb(PLD_SWSR) != 0x05) {
if (ctrlc())
return;
}
printf("Please DIPSW set = B'1010\n");
while (readb(PLD_SWSR) != 0x0A) {
if (ctrlc())
return;
}
printf("DIPSW OK\n");
}
static void test_net(void)
{
unsigned long data;
writel(0x80000000, 0xfe0401c0);
data = readl(0xfe040220);
if (data == 0x816910ec)
printf("Ethernet OK\n");
else
printf("Ethernet NG, data = %08x\n", (unsigned int)data);
}
static void test_sata(void)
{
unsigned long data;
writel(0x80000800, 0xfe0401c0);
data = readl(0xfe040220);
if (data == 0x35121095)
printf("SATA OK\n");
else
printf("SATA NG, data = %08x\n", (unsigned int)data);
}
static void test_pci(void)
{
writel(0x80001800, 0xfe0401c0);
printf("PCI CN1 ID = %08x\n", readl(0xfe040220));
writel(0x80001000, 0xfe0401c0);
printf("PCI CN2 ID = %08x\n", readl(0xfe040220));
}
int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *cmd;
if (argc != 2)
return cmd_usage(cmdtp);
cmd = argv[1];
switch (cmd[0]) {
case 'a': /* all */
test_pld();
test_led();
test_dipsw();
test_sm107();
test_net();
test_sata();
test_pci();
break;
case 'p': /* pld or pci */
if (cmd[1] == 'l')
test_pld();
else
test_pci();
break;
case 'l': /* led */
test_led();
break;
case 'd': /* dipsw */
test_dipsw();
break;
case 's': /* sm107 or sata */
if (cmd[1] == 'm')
test_sm107();
else
test_sata();
break;
case 'n': /* net */
test_net();
break;
default:
return cmd_usage(cmdtp);
}
return 0;
}
U_BOOT_CMD(
hwtest, 2, 1, do_hw_test,
"hardware test for R0P7785LC0011RL board",
"\n"
"hwtest all - test all hardware\n"
"hwtest pld - output PLD version\n"
"hwtest led - turn on LEDs\n"
"hwtest dipsw - test DIP switch\n"
"hwtest sm107 - output SM107 version\n"
"hwtest net - check RTL8110 ID\n"
"hwtest sata - check SiI3512 ID\n"
"hwtest pci - output PCI slot device ID"
);

63
board/renesas/sh7785lcr/sh7785lcr.c
View file

@ -1,63 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*/
#include <common.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/pci.h>
#include <netdev.h>
int checkboard(void)
{
puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n");
return 0;
}
int board_init(void)
{
return 0;
}
static struct pci_controller hose;
void pci_init_board(void)
{
pci_sh7780_init(&hose);
}
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
}
#if defined(CONFIG_SH_32BIT)
int do_pmb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/* clear ITLB */
writel(0x00000004, 0xff000010);
/* delete PMB for peripheral */
writel(0, PMB_ADDR_BASE(0));
writel(0, PMB_DATA_BASE(0));
writel(0, PMB_ADDR_BASE(1));
writel(0, PMB_DATA_BASE(1));
writel(0, PMB_ADDR_BASE(2));
writel(0, PMB_DATA_BASE(2));
/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(8));
writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(8));
writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(12));
writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(12));
return 0;
}
U_BOOT_CMD(
pmb, 1, 1, do_pmb,
"pmb - PMB setting\n",
"\n"
" - PMB setting for all SDRAM mapping"
);
#endif

40
configs/ecovec_defconfig
View file

@ -1,40 +0,0 @@
CONFIG_SH=y
CONFIG_SYS_TEXT_BASE=0x8FFC0000
CONFIG_TARGET_ECOVEC=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200"
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_SDRAM=y
CONFIG_CMD_USB=y
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SH_ETHER=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USE_PRIVATE_LIBGCC=y

53
configs/grpeach_defconfig Normal file
View file

@ -0,0 +1,53 @@
CONFIG_ARM=y
# CONFIG_SPL_SYS_THUMB_BUILD is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x18000000
CONFIG_RZA1=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_SF=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="r7s72100-gr-peach-u-boot"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=0
CONFIG_USE_ENV_SPI_CS=y
CONFIG_ENV_SPI_CS=0
CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_USE_ENV_SPI_MODE=y
CONFIG_ENV_SPI_MODE=0x0
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_HAVE_BLOCK_DEVICE=y
CONFIG_DM_GPIO=y
CONFIG_RZA1_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
CONFIG_PINCTRL=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_RENESAS_RPC_SPI=y
CONFIG_TIMER=y
CONFIG_RENESAS_OSTM_TIMER=y
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set

40
configs/sh7785lcr_32bit_defconfig
View file

@ -1,40 +0,0 @@
CONFIG_SH=y
CONFIG_SYS_TEXT_BASE=0x8FF80000
CONFIG_SH_32BIT=y
CONFIG_TARGET_SH7785LCR=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC1,115200 root=/dev/nfs ip=dhcp"
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_PCI=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_USB=y
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PCI=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USE_PRIVATE_LIBGCC=y

39
configs/sh7785lcr_defconfig
View file

@ -1,39 +0,0 @@
CONFIG_SH=y
CONFIG_SYS_TEXT_BASE=0x0FF80000
CONFIG_TARGET_SH7785LCR=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC1,115200 root=/dev/nfs ip=dhcp"
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_PCI=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_USB=y
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PCI=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USE_PRIVATE_LIBGCC=y

1
doc/README.sh
View file

@ -94,7 +94,6 @@ U-Boot for Renesas SuperH
I plan to support the following CPUs and boards. I plan to support the following CPUs and boards.
5.1. CPUs 5.1. CPUs
- SH7751R(SH4) - SH7751R(SH4)
- SH7785(SH4)
5.2. Boards 5.2. Boards
- Many boards ;-) - Many boards ;-)

6
drivers/gpio/Kconfig
View file

@ -169,6 +169,12 @@ config RCAR_GPIO
help help
This driver supports the GPIO banks on Renesas RCar SoCs. This driver supports the GPIO banks on Renesas RCar SoCs.
config RZA1_GPIO
bool "Renesas RZ/A1 GPIO driver"
depends on DM_GPIO && RZA1
help
This driver supports the GPIO banks on Renesas RZ/A1 R7S72100 SoCs.
config ROCKCHIP_GPIO config ROCKCHIP_GPIO
bool "Rockchip GPIO driver" bool "Rockchip GPIO driver"
depends on DM_GPIO depends on DM_GPIO

1
drivers/gpio/Makefile
View file

@ -27,6 +27,7 @@ obj-$(CONFIG_PCA953X) += pca953x.o
obj-$(CONFIG_PCA9698) += pca9698.o obj-$(CONFIG_PCA9698) += pca9698.o
obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o
obj-$(CONFIG_RCAR_GPIO) += gpio-rcar.o obj-$(CONFIG_RCAR_GPIO) += gpio-rcar.o
obj-$(CONFIG_RZA1_GPIO) += gpio-rza1.o
obj-$(CONFIG_S5P) += s5p_gpio.o obj-$(CONFIG_S5P) += s5p_gpio.o
obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o
obj-$(CONFIG_SPEAR_GPIO) += spear_gpio.o obj-$(CONFIG_SPEAR_GPIO) += spear_gpio.o

134
drivers/gpio/gpio-rza1.c Normal file
View file

@ -0,0 +1,134 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
#define P(bank) (0x0000 + (bank) * 4)
#define PSR(bank) (0x0100 + (bank) * 4)
#define PPR(bank) (0x0200 + (bank) * 4)
#define PM(bank) (0x0300 + (bank) * 4)
#define PMC(bank) (0x0400 + (bank) * 4)
#define PFC(bank) (0x0500 + (bank) * 4)
#define PFCE(bank) (0x0600 + (bank) * 4)
#define PNOT(bank) (0x0700 + (bank) * 4)
#define PMSR(bank) (0x0800 + (bank) * 4)
#define PMCSR(bank) (0x0900 + (bank) * 4)
#define PFCAE(bank) (0x0A00 + (bank) * 4)
#define PIBC(bank) (0x4000 + (bank) * 4)
#define PBDC(bank) (0x4100 + (bank) * 4)
#define PIPC(bank) (0x4200 + (bank) * 4)
#define RZA1_MAX_GPIO_PER_BANK 16
DECLARE_GLOBAL_DATA_PTR;
struct r7s72100_gpio_priv {
void __iomem *regs;
int bank;
};
static int r7s72100_gpio_get_value(struct udevice *dev, unsigned offset)
{
struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
return !!(readw(priv->regs + PPR(priv->bank)) & BIT(offset));
}
static int r7s72100_gpio_set_value(struct udevice *dev, unsigned line,
int value)
{
struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
writel(BIT(line + 16) | (value ? BIT(line) : 0),
priv->regs + PSR(priv->bank));
return 0;
}
static void r7s72100_gpio_set_direction(struct udevice *dev, unsigned line,
bool output)
{
struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
writel(BIT(line + 16), priv->regs + PMCSR(priv->bank));
writel(BIT(line + 16) | (output ? 0 : BIT(line)),
priv->regs + PMSR(priv->bank));
clrsetbits_le16(priv->regs + PIBC(priv->bank), BIT(line),
output ? 0 : BIT(line));
}
static int r7s72100_gpio_direction_input(struct udevice *dev, unsigned offset)
{
r7s72100_gpio_set_direction(dev, offset, false);
return 0;
}
static int r7s72100_gpio_direction_output(struct udevice *dev, unsigned offset,
int value)
{
/* write GPIO value to output before selecting output mode of pin */
r7s72100_gpio_set_value(dev, offset, value);
r7s72100_gpio_set_direction(dev, offset, true);
return 0;
}
static int r7s72100_gpio_get_function(struct udevice *dev, unsigned offset)
{
struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
if (readw(priv->regs + PM(priv->bank)) & BIT(offset))
return GPIOF_INPUT;
else
return GPIOF_OUTPUT;
}
static const struct dm_gpio_ops r7s72100_gpio_ops = {
.direction_input = r7s72100_gpio_direction_input,
.direction_output = r7s72100_gpio_direction_output,
.get_value = r7s72100_gpio_get_value,
.set_value = r7s72100_gpio_set_value,
.get_function = r7s72100_gpio_get_function,
};
static int r7s72100_gpio_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
struct fdtdec_phandle_args args;
int node = dev_of_offset(dev);
int ret;
fdt_addr_t addr_base;
uc_priv->bank_name = dev->name;
dev = dev_get_parent(dev);
addr_base = devfdt_get_addr(dev);
if (addr_base == FDT_ADDR_T_NONE)
return -EINVAL;
priv->regs = (void __iomem *)addr_base;
ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
NULL, 3, 0, &args);
priv->bank = ret == 0 ? (args.args[1] / RZA1_MAX_GPIO_PER_BANK) : -1;
uc_priv->gpio_count = ret == 0 ? args.args[2] : RZA1_MAX_GPIO_PER_BANK;
return 0;
}
U_BOOT_DRIVER(r7s72100_gpio) = {
.name = "r7s72100-gpio",
.id = UCLASS_GPIO,
.ops = &r7s72100_gpio_ops,
.priv_auto_alloc_size = sizeof(struct r7s72100_gpio_priv),
.probe = r7s72100_gpio_probe,
};

11
drivers/net/sh_eth.c
View file

@ -425,7 +425,7 @@ static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
sh_eth_write(port_info, GECMR_100B, GECMR); sh_eth_write(port_info, GECMR_100B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(port_info, 1, RTRATE); sh_eth_write(port_info, 1, RTRATE);
#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2) #elif defined(CONFIG_RCAR_GEN2)
val = ECMR_RTM; val = ECMR_RTM;
#endif #endif
} else if (phy->speed == 10) { } else if (phy->speed == 10) {
@ -806,9 +806,11 @@ static int sh_ether_probe(struct udevice *udev)
priv->iobase = pdata->iobase; priv->iobase = pdata->iobase;
#if CONFIG_IS_ENABLED(CLK)
ret = clk_get_by_index(udev, 0, &priv->clk); ret = clk_get_by_index(udev, 0, &priv->clk);
if (ret < 0) if (ret < 0)
return ret; return ret;
#endif
ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args); ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args);
if (!ret) { if (!ret) {
@ -843,9 +845,11 @@ static int sh_ether_probe(struct udevice *udev)
eth->port_info[eth->port].iobase = eth->port_info[eth->port].iobase =
(void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port); (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
#if CONFIG_IS_ENABLED(CLK)
ret = clk_enable(&priv->clk); ret = clk_enable(&priv->clk);
if (ret) if (ret)
goto err_mdio_register; goto err_mdio_register;
#endif
ret = sh_eth_phy_config(udev); ret = sh_eth_phy_config(udev);
if (ret) { if (ret) {
@ -856,7 +860,9 @@ static int sh_ether_probe(struct udevice *udev)
return 0; return 0;
err_phy_config: err_phy_config:
#if CONFIG_IS_ENABLED(CLK)
clk_disable(&priv->clk); clk_disable(&priv->clk);
#endif
err_mdio_register: err_mdio_register:
mdio_free(mdiodev); mdio_free(mdiodev);
return ret; return ret;
@ -868,7 +874,9 @@ static int sh_ether_remove(struct udevice *udev)
struct sh_eth_dev *eth = &priv->shdev; struct sh_eth_dev *eth = &priv->shdev;
struct sh_eth_info *port_info = &eth->port_info[eth->port]; struct sh_eth_info *port_info = &eth->port_info[eth->port];
#if CONFIG_IS_ENABLED(CLK)
clk_disable(&priv->clk); clk_disable(&priv->clk);
#endif
free(port_info->phydev); free(port_info->phydev);
mdio_unregister(priv->bus); mdio_unregister(priv->bus);
mdio_free(priv->bus); mdio_free(priv->bus);
@ -917,6 +925,7 @@ int sh_ether_ofdata_to_platdata(struct udevice *dev)
} }
static const struct udevice_id sh_ether_ids[] = { static const struct udevice_id sh_ether_ids[] = {
{ .compatible = "renesas,ether-r7s72100" },
{ .compatible = "renesas,ether-r8a7790" }, { .compatible = "renesas,ether-r8a7790" },
{ .compatible = "renesas,ether-r8a7791" }, { .compatible = "renesas,ether-r8a7791" },
{ .compatible = "renesas,ether-r8a7793" }, { .compatible = "renesas,ether-r8a7793" },

59
drivers/net/sh_eth.h
View file

@ -228,6 +228,60 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
[RMII_MII] = 0x0790, [RMII_MII] = 0x0790,
}; };
static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
[EDSR] = 0x0000,
[EDMR] = 0x0400,
[EDTRR] = 0x0408,
[EDRRR] = 0x0410,
[EESR] = 0x0428,
[EESIPR] = 0x0430,
[TDLAR] = 0x0010,
[TDFAR] = 0x0014,
[TDFXR] = 0x0018,
[TDFFR] = 0x001c,
[RDLAR] = 0x0030,
[RDFAR] = 0x0034,
[RDFXR] = 0x0038,
[RDFFR] = 0x003c,
[TRSCER] = 0x0438,
[RMFCR] = 0x0440,
[TFTR] = 0x0448,
[FDR] = 0x0450,
[RMCR] = 0x0458,
[RPADIR] = 0x0460,
[FCFTR] = 0x0468,
[CSMR] = 0x04E4,
[ECMR] = 0x0500,
[ECSR] = 0x0510,
[ECSIPR] = 0x0518,
[PIR] = 0x0520,
[PSR] = 0x0528,
[PIPR] = 0x052c,
[RFLR] = 0x0508,
[APR] = 0x0554,
[MPR] = 0x0558,
[PFTCR] = 0x055c,
[PFRCR] = 0x0560,
[TPAUSER] = 0x0564,
[GECMR] = 0x05b0,
[BCULR] = 0x05b4,
[MAHR] = 0x05c0,
[MALR] = 0x05c8,
[TROCR] = 0x0700,
[CDCR] = 0x0708,
[LCCR] = 0x0710,
[CEFCR] = 0x0740,
[FRECR] = 0x0748,
[TSFRCR] = 0x0750,
[TLFRCR] = 0x0758,
[RFCR] = 0x0760,
[CERCR] = 0x0768,
[CEECR] = 0x0770,
[MAFCR] = 0x0778,
[RMII_MII] = 0x0790,
};
static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
[ECMR] = 0x0100, [ECMR] = 0x0100,
[RFLR] = 0x0108, [RFLR] = 0x0108,
@ -295,9 +349,6 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
#define SH_ETH_TYPE_ETHER #define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR 0xfef00000 #define BASE_IO_ADDR 0xfef00000
#endif #endif
#elif defined(CONFIG_CPU_SH7724)
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR 0xA4600000
#elif defined(CONFIG_R8A7740) #elif defined(CONFIG_R8A7740)
#define SH_ETH_TYPE_GETHER #define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR 0xE9A00000 #define BASE_IO_ADDR 0xE9A00000
@ -606,6 +657,8 @@ static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port,
const u16 *reg_offset = sh_eth_offset_gigabit; const u16 *reg_offset = sh_eth_offset_gigabit;
#elif defined(SH_ETH_TYPE_ETHER) #elif defined(SH_ETH_TYPE_ETHER)
const u16 *reg_offset = sh_eth_offset_fast_sh4; const u16 *reg_offset = sh_eth_offset_fast_sh4;
#elif defined(SH_ETH_TYPE_RZ)
const u16 *reg_offset = sh_eth_offset_rz;
#else #else
#error #error
#endif #endif

12
drivers/pinctrl/renesas/Kconfig
View file

@ -3,6 +3,7 @@ if ARCH_RMOBILE
config PINCTRL_PFC config PINCTRL_PFC
bool "Renesas pin control drivers" bool "Renesas pin control drivers"
depends on DM && ARCH_RMOBILE depends on DM && ARCH_RMOBILE
default n if CPU_RZA1
help help
Enable support for clock present on Renesas RCar SoCs. Enable support for clock present on Renesas RCar SoCs.
@ -116,4 +117,15 @@ config PINCTRL_PFC_R8A77995
the GPIO definitions and pin control functions for each available the GPIO definitions and pin control functions for each available
multiplex function. multiplex function.
config PINCTRL_PFC_R7S72100
bool "Renesas RZ/A1 R7S72100 pin control driver"
depends on CPU_RZA1
default y if CPU_RZA1
help
Support pin multiplexing control on Renesas RZ/A1 R7S72100 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
endif endif

1
drivers/pinctrl/renesas/Makefile
View file

@ -10,3 +10,4 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o

146
drivers/pinctrl/renesas/pfc-r7s72100.c Normal file
View file

@ -0,0 +1,146 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* R7S72100 processor support
*
* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
*/
#include <common.h>
#include <dm.h>
#include <dm/lists.h>
#include <dm/pinctrl.h>
#include <linux/io.h>
#include <linux/err.h>
#define P(bank) (0x0000 + (bank) * 4)
#define PSR(bank) (0x0100 + (bank) * 4)
#define PPR(bank) (0x0200 + (bank) * 4)
#define PM(bank) (0x0300 + (bank) * 4)
#define PMC(bank) (0x0400 + (bank) * 4)
#define PFC(bank) (0x0500 + (bank) * 4)
#define PFCE(bank) (0x0600 + (bank) * 4)
#define PNOT(bank) (0x0700 + (bank) * 4)
#define PMSR(bank) (0x0800 + (bank) * 4)
#define PMCSR(bank) (0x0900 + (bank) * 4)
#define PFCAE(bank) (0x0A00 + (bank) * 4)
#define PIBC(bank) (0x4000 + (bank) * 4)
#define PBDC(bank) (0x4100 + (bank) * 4)
#define PIPC(bank) (0x4200 + (bank) * 4)
#define RZA1_PINS_PER_PORT 16
DECLARE_GLOBAL_DATA_PTR;
struct r7s72100_pfc_platdata {
void __iomem *base;
};
static void r7s72100_pfc_set_function(struct udevice *dev, u16 bank, u16 line,
u16 func, u16 inbuf, u16 bidir)
{
struct r7s72100_pfc_platdata *plat = dev_get_platdata(dev);
clrsetbits_le16(plat->base + PFCAE(bank), BIT(line),
(func & BIT(2)) ? BIT(line) : 0);
clrsetbits_le16(plat->base + PFCE(bank), BIT(line),
(func & BIT(1)) ? BIT(line) : 0);
clrsetbits_le16(plat->base + PFC(bank), BIT(line),
(func & BIT(0)) ? BIT(line) : 0);
clrsetbits_le16(plat->base + PIBC(bank), BIT(line),
inbuf ? BIT(line) : 0);
clrsetbits_le16(plat->base + PBDC(bank), BIT(line),
bidir ? BIT(line) : 0);
setbits_le32(plat->base + PMCSR(bank), BIT(line + 16) | BIT(line));
setbits_le16(plat->base + PIPC(bank), BIT(line));
}
static int r7s72100_pfc_set_state(struct udevice *dev, struct udevice *config)
{
const void *blob = gd->fdt_blob;
int node = dev_of_offset(config);
u32 cells[32];
u16 bank, line, func;
int i, count, bidir;
count = fdtdec_get_int_array_count(blob, node, "pinmux",
cells, ARRAY_SIZE(cells));
if (count < 0) {
printf("%s: bad pinmux array %d\n", __func__, count);
return -EINVAL;
}
if (count > ARRAY_SIZE(cells)) {
printf("%s: unsupported pinmux array count %d\n",
__func__, count);
return -EINVAL;
}
for (i = 0 ; i < count; i++) {
func = (cells[i] >> 16) & 0xf;
if (func == 0 || func > 8) {
printf("Invalid cell %i in node %s!\n",
count, ofnode_get_name(dev_ofnode(config)));
continue;
}
func = (func - 1) & 0x7;
bank = (cells[i] / RZA1_PINS_PER_PORT) & 0xff;
line = cells[i] % RZA1_PINS_PER_PORT;
bidir = 0;
if (bank == 3 && line == 3 && func == 1)
bidir = 1;
r7s72100_pfc_set_function(dev, bank, line, func, 0, bidir);
}
return 0;
}
const struct pinctrl_ops r7s72100_pfc_ops = {
.set_state = r7s72100_pfc_set_state,
};
static int r7s72100_pfc_probe(struct udevice *dev)
{
struct r7s72100_pfc_platdata *plat = dev_get_platdata(dev);
fdt_addr_t addr_base;
ofnode node;
addr_base = devfdt_get_addr(dev);
if (addr_base == FDT_ADDR_T_NONE)
return -EINVAL;
plat->base = (void __iomem *)addr_base;
dev_for_each_subnode(node, dev) {
struct udevice *cdev;
if (!ofnode_read_bool(node, "gpio-controller"))
continue;
device_bind_driver_to_node(dev, "r7s72100-gpio",
ofnode_get_name(node),
node, &cdev);
}
return 0;
}
static const struct udevice_id r7s72100_pfc_match[] = {
{ .compatible = "renesas,r7s72100-ports" },
{}
};
U_BOOT_DRIVER(r7s72100_pfc) = {
.name = "r7s72100_pfc",
.id = UCLASS_PINCTRL,
.of_match = r7s72100_pfc_match,
.probe = r7s72100_pfc_probe,
.platdata_auto_alloc_size = sizeof(struct r7s72100_pfc_platdata),
.ops = &r7s72100_pfc_ops,
};

4
drivers/serial/serial_sh.c
View file

@ -21,7 +21,6 @@ DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CPU_SH7760) || \ #if defined(CONFIG_CPU_SH7760) || \
defined(CONFIG_CPU_SH7780) || \ defined(CONFIG_CPU_SH7780) || \
defined(CONFIG_CPU_SH7785) || \
defined(CONFIG_CPU_SH7786) defined(CONFIG_CPU_SH7786)
static int scif_rxfill(struct uart_port *port) static int scif_rxfill(struct uart_port *port)
{ {
@ -63,6 +62,9 @@ static void sh_serial_init_generic(struct uart_port *port)
sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST); sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
sci_in(port, SCFCR); sci_in(port, SCFCR);
sci_out(port, SCFCR, 0); sci_out(port, SCFCR, 0);
#if defined(CONFIG_RZA1)
sci_out(port, SCSPTR, 0x0003);
#endif
} }
static void static void

24
drivers/serial/serial_sh.h
View file

@ -107,11 +107,6 @@ struct uart_port {
# define SCSPTR5 0xa4050128 # define SCSPTR5 0xa4050128
# define SCIF_ORER 0x0001 /* overrun error bit */ # define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7724)
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
#elif defined(CONFIG_CPU_SH7734) #elif defined(CONFIG_CPU_SH7734)
# define SCSPTR0 0xFFE40020 # define SCSPTR0 0xFFE40020
# define SCSPTR1 0xFFE41020 # define SCSPTR1 0xFFE41020
@ -175,8 +170,7 @@ struct uart_port {
# define SCSCR_INIT(port) 0x3a # define SCSCR_INIT(port) 0x3a
#endif #endif
#elif defined(CONFIG_CPU_SH7785) || \ #elif defined(CONFIG_CPU_SH7786)
defined(CONFIG_CPU_SH7786)
# define SCSPTR0 0xffea0024 /* 16 bit SCIF */ # define SCSPTR0 0xffea0024 /* 16 bit SCIF */
# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
# define SCSPTR2 0xffec0024 /* 16 bit SCIF */ # define SCSPTR2 0xffec0024 /* 16 bit SCIF */
@ -201,7 +195,7 @@ struct uart_port {
# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
# endif # endif
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7269) #elif defined(CONFIG_CPU_SH7269) || defined(CONFIG_RZA1)
# define SCSPTR0 0xe8007020 /* 16 bit SCIF */ # define SCSPTR0 0xe8007020 /* 16 bit SCIF */
# define SCSPTR1 0xe8007820 /* 16 bit SCIF */ # define SCSPTR1 0xe8007820 /* 16 bit SCIF */
# define SCSPTR2 0xe8008020 /* 16 bit SCIF */ # define SCSPTR2 0xe8008020 /* 16 bit SCIF */
@ -211,6 +205,7 @@ struct uart_port {
# define SCSPTR6 0xe800a020 /* 16 bit SCIF */ # define SCSPTR6 0xe800a020 /* 16 bit SCIF */
# define SCSPTR7 0xe800a820 /* 16 bit SCIF */ # define SCSPTR7 0xe800a820 /* 16 bit SCIF */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
# define SCIF_ORER 0x0001 /* overrun error bit */
#elif defined(CONFIG_CPU_SH7619) #elif defined(CONFIG_CPU_SH7619)
# define SCSPTR0 0xf8400020 /* 16 bit SCIF */ # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
# define SCSPTR1 0xf8410020 /* 16 bit SCIF */ # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
@ -252,12 +247,9 @@ struct uart_port {
defined(CONFIG_CPU_SH7751R) || \ defined(CONFIG_CPU_SH7751R) || \
defined(CONFIG_CPU_SH7763) || \ defined(CONFIG_CPU_SH7763) || \
defined(CONFIG_CPU_SH7780) || \ defined(CONFIG_CPU_SH7780) || \
defined(CONFIG_CPU_SH7785) || \
defined(CONFIG_CPU_SH7786) || \ defined(CONFIG_CPU_SH7786) || \
defined(CONFIG_CPU_SHX3) defined(CONFIG_CPU_SHX3)
#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
#elif defined(CONFIG_CPU_SH7724)
#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
#else #else
#define SCI_CTRL_FLAGS_REIE 0 #define SCI_CTRL_FLAGS_REIE 0
#endif #endif
@ -494,7 +486,7 @@ static inline void sci_##name##_out(struct uart_port *port,\
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
sh4_scif_offset, sh4_scif_size) \ sh4_scif_offset, sh4_scif_size) \
CPU_SCIF_FNS(name) CPU_SCIF_FNS(name)
#elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724) #elif defined(CONFIG_CPU_SH7723)
#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
sh4_scif_offset, sh4_scif_size) \ sh4_scif_offset, sh4_scif_size) \
CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
@ -549,8 +541,7 @@ SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8) SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
SCIF_FNS(SCLSR, 0x00, 0) SCIF_FNS(SCLSR, 0x00, 0)
SCIF_FNS(DL, 0x00, 0) /* dummy */ SCIF_FNS(DL, 0x00, 0) /* dummy */
#elif defined(CONFIG_CPU_SH7723) ||\ #elif defined(CONFIG_CPU_SH7723)
defined(CONFIG_CPU_SH7724)
SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
@ -594,7 +585,6 @@ SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
#if defined(CONFIG_CPU_SH7760) || \ #if defined(CONFIG_CPU_SH7760) || \
defined(CONFIG_CPU_SH7780) || \ defined(CONFIG_CPU_SH7780) || \
defined(CONFIG_CPU_SH7785) || \
defined(CONFIG_CPU_SH7786) defined(CONFIG_CPU_SH7786)
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
@ -734,7 +724,6 @@ static inline int sci_rxd_in(struct uart_port *port)
*/ */
#if (defined(CONFIG_CPU_SH7780) || \ #if (defined(CONFIG_CPU_SH7780) || \
defined(CONFIG_CPU_SH7785) || \
defined(CONFIG_CPU_SH7786)) && \ defined(CONFIG_CPU_SH7786)) && \
!defined(CONFIG_SH_SH2007) !defined(CONFIG_SH_SH2007)
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
@ -747,8 +736,7 @@ static inline int sci_rxd_in(struct uart_port *port)
defined(CONFIG_SH73A0) || \ defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740) defined(CONFIG_R8A7740)
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
#elif defined(CONFIG_CPU_SH7723) ||\ #elif defined(CONFIG_CPU_SH7723)
defined(CONFIG_CPU_SH7724)
static inline int scbrr_calc(struct uart_port *port, int bps, int clk) static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
{ {
if (port->type == PORT_SCIF) if (port->type == PORT_SCIF)

2
drivers/spi/Kconfig
View file

@ -173,7 +173,7 @@ config PL022_SPI
config RENESAS_RPC_SPI config RENESAS_RPC_SPI
bool "Renesas RPC SPI driver" bool "Renesas RPC SPI driver"
depends on RCAR_GEN3 depends on RCAR_GEN3 || RZA1
imply SPI_FLASH_BAR imply SPI_FLASH_BAR
help help
Enable the Renesas RPC SPI driver, used to access SPI NOR flash Enable the Renesas RPC SPI driver, used to access SPI NOR flash

12
drivers/spi/renesas_rpc_spi.c
View file

@ -409,27 +409,30 @@ static int rpc_spi_probe(struct udevice *dev)
priv->regs = plat->regs; priv->regs = plat->regs;
priv->extr = plat->extr; priv->extr = plat->extr;
#if CONFIG_IS_ENABLED(CLK)
clk_enable(&priv->clk); clk_enable(&priv->clk);
#endif
return 0; return 0;
} }
static int rpc_spi_ofdata_to_platdata(struct udevice *bus) static int rpc_spi_ofdata_to_platdata(struct udevice *bus)
{ {
struct rpc_spi_platdata *plat = dev_get_platdata(bus); struct rpc_spi_platdata *plat = dev_get_platdata(bus);
struct rpc_spi_priv *priv = dev_get_priv(bus);
int ret;
plat->regs = dev_read_addr_index(bus, 0); plat->regs = dev_read_addr_index(bus, 0);
plat->extr = dev_read_addr_index(bus, 1); plat->extr = dev_read_addr_index(bus, 1);
#if CONFIG_IS_ENABLED(CLK)
struct rpc_spi_priv *priv = dev_get_priv(bus);
int ret;
ret = clk_get_by_index(bus, 0, &priv->clk); ret = clk_get_by_index(bus, 0, &priv->clk);
if (ret < 0) { if (ret < 0) {
printf("%s: Could not get clock for %s: %d\n", printf("%s: Could not get clock for %s: %d\n",
__func__, bus->name, ret); __func__, bus->name, ret);
return ret; return ret;
} }
#endif
plat->freq = dev_read_u32_default(bus, "spi-max-freq", 50000000); plat->freq = dev_read_u32_default(bus, "spi-max-freq", 50000000);
@ -448,6 +451,7 @@ static const struct udevice_id rpc_spi_ids[] = {
{ .compatible = "renesas,rpc-r8a77965" }, { .compatible = "renesas,rpc-r8a77965" },
{ .compatible = "renesas,rpc-r8a77970" }, { .compatible = "renesas,rpc-r8a77970" },
{ .compatible = "renesas,rpc-r8a77995" }, { .compatible = "renesas,rpc-r8a77995" },
{ .compatible = "renesas,rpc-r7s72100" },
{ } { }
}; };

7
drivers/timer/Kconfig
View file

@ -110,6 +110,13 @@ config MPC83XX_TIMER
Select this to enable support for the timer found on Select this to enable support for the timer found on
devices based on the MPC83xx family of SoCs. devices based on the MPC83xx family of SoCs.
config RENESAS_OSTM_TIMER
bool "Renesas RZ/A1 R7S72100 OSTM Timer"
depends on TIMER
help
Enables support for the Renesas OSTM Timer driver.
This timer is present on Renesas RZ/A1 R7S72100 SoCs.
config X86_TSC_TIMER_EARLY_FREQ config X86_TSC_TIMER_EARLY_FREQ
int "x86 TSC timer frequency in MHz when used as the early timer" int "x86 TSC timer frequency in MHz when used as the early timer"
depends on X86_TSC_TIMER depends on X86_TSC_TIMER

1
drivers/timer/Makefile
View file

@ -13,6 +13,7 @@ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
obj-$(CONFIG_OMAP_TIMER) += omap-timer.o obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o

92
drivers/timer/ostm_timer.c Normal file
View file

@ -0,0 +1,92 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Renesas RZ/A1 R7S72100 OSTM Timer driver
*
* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
*/
#include <common.h>
#include <asm/io.h>
#include <dm.h>
#include <clk.h>
#include <timer.h>
#define OSTM_CMP 0x00
#define OSTM_CNT 0x04
#define OSTM_TE 0x10
#define OSTM_TS 0x14
#define OSTM_TT 0x18
#define OSTM_CTL 0x20
#define OSTM_CTL_D BIT(1)
DECLARE_GLOBAL_DATA_PTR;
struct ostm_priv {
fdt_addr_t regs;
};
static int ostm_get_count(struct udevice *dev, u64 *count)
{
struct ostm_priv *priv = dev_get_priv(dev);
*count = timer_conv_64(readl(priv->regs + OSTM_CNT));
return 0;
}
static int ostm_probe(struct udevice *dev)
{
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct ostm_priv *priv = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(CLK)
struct clk clk;
int ret;
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return ret;
uc_priv->clock_rate = clk_get_rate(&clk);
clk_free(&clk);
#else
uc_priv->clock_rate = CONFIG_SYS_CLK_FREQ / 2;
#endif
readb(priv->regs + OSTM_CTL);
writeb(OSTM_CTL_D, priv->regs + OSTM_CTL);
setbits_8(priv->regs + OSTM_TT, BIT(0));
writel(0xffffffff, priv->regs + OSTM_CMP);
setbits_8(priv->regs + OSTM_TS, BIT(0));
return 0;
}
static int ostm_ofdata_to_platdata(struct udevice *dev)
{
struct ostm_priv *priv = dev_get_priv(dev);
priv->regs = dev_read_addr(dev);
return 0;
}
static const struct timer_ops ostm_ops = {
.get_count = ostm_get_count,
};
static const struct udevice_id ostm_ids[] = {
{ .compatible = "renesas,ostm" },
{}
};
U_BOOT_DRIVER(ostm_timer) = {
.name = "ostm-timer",
.id = UCLASS_TIMER,
.ops = &ostm_ops,
.probe = ostm_probe,
.of_match = ostm_ids,
.ofdata_to_platdata = ostm_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct ostm_priv),
};

133
include/configs/ecovec.h
View file

@ -1,133 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuation settings for the Renesas Solutions ECOVEC board
*
* Copyright (C) 2009 - 2011 Renesas Solutions Corp.
* Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com>
* Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
*/
#ifndef __ECOVEC_H
#define __ECOVEC_H
/*
* Address Interface BusWidth
*-----------------------------------------
* 0x0000_0000 U-Boot 16bit
* 0x0004_0000 Linux romImage 16bit
* 0x0014_0000 MTD for Linux 16bit
* 0x0400_0000 Internal I/O 16/32bit
* 0x0800_0000 DRAM 32bit
* 0x1800_0000 MFI 16bit
*/
#define CONFIG_CPU_SH7724 1
#define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000
#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SH
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2
#define CONFIG_SYS_I2C_SH_BASE0 0xA4470000
#define CONFIG_SYS_I2C_SH_SPEED0 100000
#define CONFIG_SYS_I2C_SH_BASE1 0xA4750000
#define CONFIG_SYS_I2C_SH_SPEED1 100000
#define CONFIG_SH_I2C_DATA_HIGH 4
#define CONFIG_SH_I2C_DATA_LOW 5
#define CONFIG_SH_I2C_CLOCK 41666666
/* Ether */
#define CONFIG_SH_ETHER_USE_PORT (0)
#define CONFIG_SH_ETHER_PHY_ADDR (0x1f)
#define CONFIG_PHY_SMSC 1
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
/* USB / R8A66597 */
#define CONFIG_USB_R8A66597_HCD
#define CONFIG_R8A66597_BASE_ADDR 0xA4D80000
#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
#define CONFIG_SUPERH_ON_CHIP_R8A66597
/* undef to save memory */
/* Monitor Command Prompt */
/* Buffer size for Console output */
#define CONFIG_SYS_PBSIZE 256
/* List of legal baudrate settings for this board */
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
/* SCIF */
#define CONFIG_SCIF 1
#define CONFIG_CONS_SCIF0 1
/* Suppress display of console information at boot */
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE (0x88000000)
#define CONFIG_SYS_SDRAM_SIZE (256 * 1024 * 1024)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 200 * 1024 * 1024)
/* Enable alternate, more extensive, memory test */
/* Scratch address used by the alternate memory test */
#undef CONFIG_SYS_MEMTEST_SCRATCH
/* Enable temporary baudrate change while serial download */
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
/* FLASH */
#undef CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BASE (0xA0000000)
#define CONFIG_SYS_MAX_FLASH_SECT 512
/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
/* Timeout for Flash erase operations (in ms) */
#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
/* Timeout for Flash write operations (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
/* Timeout for Flash set sector lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
/* Timeout for Flash clear lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
/*
* Use hardware flash sectors protection instead
* of U-Boot software protection
*/
#undef CONFIG_SYS_DIRECT_FLASH_TFTP
/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
/* Monitor size */
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* ENV setting */
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 41666666
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#endif /* __ECOVEC_H */

53
include/configs/grpeach.h Normal file
View file

@ -0,0 +1,53 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration settings for the Renesas GRPEACH board
*
* Copyright (C) 2017-2019 Renesas Electronics
*/
#ifndef __GRPEACH_H
#define __GRPEACH_H
/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
#define CONFIG_SYS_CLK_FREQ 66666666
/* Serial Console */
#define CONFIG_BAUDRATE 115200
/* Miscellaneous */
#define CONFIG_SYS_PBSIZE 256
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
#define CONFIG_CMDLINE_TAG
#define CONFIG_ARCH_CPU_INIT
/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024)
#define CONFIG_SYS_LOAD_ADDR \
(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_OFFSET 0xc0000
/* Malloc */
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
/* Kernel Boot */
#define CONFIG_BOOTARGS "ignore_loglevel"
/* Network interface */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#endif /* __GRPEACH_H */

128
include/configs/sh7785lcr.h
View file

@ -1,128 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuation settings for the Renesas Technology R0P7785LC0011RL board
*
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*/
#ifndef __SH7785LCR_H
#define __SH7785LCR_H
#define CONFIG_CPU_SH7785 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootdevice=0:1\0" \
"usbload=usb reset;usbboot;usb stop;bootm\0"
#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
#if defined(CONFIG_SH_32BIT)
/* 0x40000000 - 0x47FFFFFF does not use */
#define CONFIG_SH_SDRAM_OFFSET (0x8000000)
#define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET)
#define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET)
#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024)
#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
#define SH7785LCR_USB_BASE (0xa6000000)
#else
#define SH7785LCR_SDRAM_BASE (0x08000000)
#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024)
#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
#define SH7785LCR_USB_BASE (0xb4000000)
#endif
#define CONFIG_SYS_PBSIZE 256
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
/* SCIF */
#define CONFIG_CONS_SCIF1 1
#define CONFIG_SCIF_EXT_CLOCK 1
#define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
(SH7785LCR_SDRAM_SIZE) - \
4 * 1024 * 1024)
#undef CONFIG_SYS_MEMTEST_SCRATCH
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
#define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE)
#define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
#undef CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1)
#define CONFIG_SYS_MAX_FLASH_SECT 512
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \
(0 * SH7785LCR_FLASH_BANK_SIZE) }
#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
#undef CONFIG_SYS_DIRECT_FLASH_TFTP
/* R8A66597 */
#define CONFIG_USB_R8A66597_HCD
#define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE
#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
/* PCI Controller */
#define CONFIG_SH4_PCI
#define CONFIG_SH7780_PCI
#if defined(CONFIG_SH_32BIT)
#define CONFIG_SH7780_PCI_LSR 0x1ff00001
#define CONFIG_SH7780_PCI_LAR 0x5f000000
#define CONFIG_SH7780_PCI_BAR 0x5f000000
#else
#define CONFIG_SH7780_PCI_LSR 0x07f00001
#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
#endif
#define CONFIG_PCI_SCAN_SHOW 1
#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
#if defined(CONFIG_SH_32BIT)
#define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE
#else
#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
#endif
#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
/* ENV setting */
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ENV_SECT_SIZE (256 * 1024)
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
/* Board Clock */
/* The SCIF used external clock. system clock only used timer. */
#define CONFIG_SYS_CLK_FREQ 50000000
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#endif /* __SH7785LCR_H */

112
include/dt-bindings/clock/r7s72100-clock.h Normal file
View file

@ -0,0 +1,112 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2014 Renesas Solutions Corp.
* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
*/
#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
#define __DT_BINDINGS_CLOCK_R7S72100_H__
#define R7S72100_CLK_PLL 0
#define R7S72100_CLK_I 1
#define R7S72100_CLK_G 2
/* MSTP2 */
#define R7S72100_CLK_CORESIGHT 0
/* MSTP3 */
#define R7S72100_CLK_IEBUS 7
#define R7S72100_CLK_IRDA 6
#define R7S72100_CLK_LIN0 5
#define R7S72100_CLK_LIN1 4
#define R7S72100_CLK_MTU2 3
#define R7S72100_CLK_CAN 2
#define R7S72100_CLK_ADCPWR 1
#define R7S72100_CLK_PWM 0
/* MSTP4 */
#define R7S72100_CLK_SCIF0 7
#define R7S72100_CLK_SCIF1 6
#define R7S72100_CLK_SCIF2 5
#define R7S72100_CLK_SCIF3 4
#define R7S72100_CLK_SCIF4 3
#define R7S72100_CLK_SCIF5 2
#define R7S72100_CLK_SCIF6 1
#define R7S72100_CLK_SCIF7 0
/* MSTP5 */
#define R7S72100_CLK_SCI0 7
#define R7S72100_CLK_SCI1 6
#define R7S72100_CLK_SG0 5
#define R7S72100_CLK_SG1 4
#define R7S72100_CLK_SG2 3
#define R7S72100_CLK_SG3 2
#define R7S72100_CLK_OSTM0 1
#define R7S72100_CLK_OSTM1 0
/* MSTP6 */
#define R7S72100_CLK_ADC 7
#define R7S72100_CLK_CEU 6
#define R7S72100_CLK_DOC0 5
#define R7S72100_CLK_DOC1 4
#define R7S72100_CLK_DRC0 3
#define R7S72100_CLK_DRC1 2
#define R7S72100_CLK_JCU 1
#define R7S72100_CLK_RTC 0
/* MSTP7 */
#define R7S72100_CLK_VDEC0 7
#define R7S72100_CLK_VDEC1 6
#define R7S72100_CLK_ETHER 4
#define R7S72100_CLK_NAND 3
#define R7S72100_CLK_USB0 1
#define R7S72100_CLK_USB1 0
/* MSTP8 */
#define R7S72100_CLK_IMR0 7
#define R7S72100_CLK_IMR1 6
#define R7S72100_CLK_IMRDISP 5
#define R7S72100_CLK_MMCIF 4
#define R7S72100_CLK_MLB 3
#define R7S72100_CLK_ETHAVB 2
#define R7S72100_CLK_SCUX 1
/* MSTP9 */
#define R7S72100_CLK_I2C0 7
#define R7S72100_CLK_I2C1 6
#define R7S72100_CLK_I2C2 5
#define R7S72100_CLK_I2C3 4
#define R7S72100_CLK_SPIBSC0 3
#define R7S72100_CLK_SPIBSC1 2
#define R7S72100_CLK_VDC50 1 /* and LVDS */
#define R7S72100_CLK_VDC51 0
/* MSTP10 */
#define R7S72100_CLK_SPI0 7
#define R7S72100_CLK_SPI1 6
#define R7S72100_CLK_SPI2 5
#define R7S72100_CLK_SPI3 4
#define R7S72100_CLK_SPI4 3
#define R7S72100_CLK_CDROM 2
#define R7S72100_CLK_SPDIF 1
#define R7S72100_CLK_RGPVG2 0
/* MSTP11 */
#define R7S72100_CLK_SSI0 5
#define R7S72100_CLK_SSI1 4
#define R7S72100_CLK_SSI2 3
#define R7S72100_CLK_SSI3 2
#define R7S72100_CLK_SSI4 1
#define R7S72100_CLK_SSI5 0
/* MSTP12 */
#define R7S72100_CLK_SDHI00 3
#define R7S72100_CLK_SDHI01 2
#define R7S72100_CLK_SDHI10 1
#define R7S72100_CLK_SDHI11 0
/* MSTP13 */
#define R7S72100_CLK_PIX1 2
#define R7S72100_CLK_PIX0 1
#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */

18
include/dt-bindings/pinctrl/r7s72100-pinctrl.h Normal file
View file

@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Defines macros and constants for Renesas RZ/A1 pin controller pin
* muxing functions.
*/
#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
#define __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
#define RZA1_PINS_PER_PORT 16
/*
* Create the pin index from its bank and position numbers and store in
* the upper 16 bits the alternate function identifier
*/
#define RZA1_PINMUX(b, p, f) \
((b) * RZA1_PINS_PER_PORT + (p) | ((f) << 16))
#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H */

3
scripts/config_whitelist.txt
View file

@ -277,7 +277,6 @@ CONFIG_CPU_SH7706
CONFIG_CPU_SH7720 CONFIG_CPU_SH7720
CONFIG_CPU_SH7722 CONFIG_CPU_SH7722
CONFIG_CPU_SH7723 CONFIG_CPU_SH7723
CONFIG_CPU_SH7724
CONFIG_CPU_SH7734 CONFIG_CPU_SH7734
CONFIG_CPU_SH7750 CONFIG_CPU_SH7750
CONFIG_CPU_SH7751 CONFIG_CPU_SH7751
@ -286,7 +285,6 @@ CONFIG_CPU_SH7753
CONFIG_CPU_SH7757 CONFIG_CPU_SH7757
CONFIG_CPU_SH7763 CONFIG_CPU_SH7763
CONFIG_CPU_SH7780 CONFIG_CPU_SH7780
CONFIG_CPU_SH7785
CONFIG_CPU_TYPE_R CONFIG_CPU_TYPE_R
CONFIG_CPU_VR41XX CONFIG_CPU_VR41XX
CONFIG_CQSPI_REF_CLK CONFIG_CQSPI_REF_CLK
@ -434,7 +432,6 @@ CONFIG_ECC_MODE_SHIFT
CONFIG_ECC_SRAM_ADDR_MASK CONFIG_ECC_SRAM_ADDR_MASK
CONFIG_ECC_SRAM_ADDR_SHIFT CONFIG_ECC_SRAM_ADDR_SHIFT
CONFIG_ECC_SRAM_REQ_BIT CONFIG_ECC_SRAM_REQ_BIT
CONFIG_ECOVEC_ROMIMAGE_ADDR
CONFIG_EDB9301 CONFIG_EDB9301
CONFIG_EDB9302 CONFIG_EDB9302
CONFIG_EDB9302A CONFIG_EDB9302A