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imx: cleanup bootaux

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Move i.MX6/7 bootaux code to imx_bootaux.c.
The i.MX6/7 has different src layout, so define M4 reg offset
to ease the cleanup. Redefine the M4 related BIT for share
common code.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
This commit is contained in:
Peng Fan 2018-01-10 13:20:32 +08:00 committed by Stefano Babic
parent 6ce8b10b87
commit 8cf223133c
5 changed files with 39 additions and 90 deletions
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9
arch/arm/include/asm/arch-mx6/imx-regs.h
View file

@ -482,10 +482,11 @@ struct src {
#define src_base ((struct src *)SRC_BASE_ADDR)
#define SRC_SCR_M4_ENABLE_OFFSET 22
#define SRC_SCR_M4_ENABLE_MASK (1 << 22)
#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4
#define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 4)
#define SRC_M4_REG_OFFSET 0
#define SRC_M4_ENABLE_OFFSET 22
#define SRC_M4_ENABLE_MASK BIT(22)
#define SRC_M4C_NON_SCLR_RST_OFFSET 4
#define SRC_M4C_NON_SCLR_RST_MASK BIT(4)
/* GPR1 bitfields */
#define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30)

10
arch/arm/include/asm/arch-mx7/imx-regs.h
View file

@ -264,10 +264,12 @@ struct src {
u32 ddrc_rcr;
};
#define SRC_M4RCR_M4C_NON_SCLR_RST_OFFSET 0
#define SRC_M4RCR_M4C_NON_SCLR_RST_MASK (1 << 0)
#define SRC_M4RCR_ENABLE_M4_OFFSET 3
#define SRC_M4RCR_ENABLE_M4_MASK (1 << 3)
#define SRC_M4_REG_OFFSET 0xC
#define SRC_M4C_NON_SCLR_RST_OFFSET 0
#define SRC_M4C_NON_SCLR_RST_MASK BIT(0)
#define SRC_M4_ENABLE_OFFSET 3
#define SRC_M4_ENABLE_MASK BIT(3)
#define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET 1
#define SRC_DDRC_RCR_DDRC_CORE_RST_MASK (1 << 1)

36
arch/arm/mach-imx/imx_bootaux.c
View file

@ -5,21 +5,41 @@
*/
#include <common.h>
#include <asm/io.h>
#include <command.h>
#include <linux/compiler.h>
/* Allow for arch specific config before we boot */
int __weak arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
{
/* please define platform specific arch_auxiliary_core_up() */
return CMD_RET_FAILURE;
ulong stack, pc;
if (!boot_private_data)
return -EINVAL;
stack = *(ulong *)boot_private_data;
pc = *(ulong *)(boot_private_data + 4);
/* Set the stack and pc to M4 bootROM */
writel(stack, M4_BOOTROM_BASE_ADDR);
writel(pc, M4_BOOTROM_BASE_ADDR + 4);
/* Enable M4 */
clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
return 0;
}
/* Allow for arch specific config before we boot */
int __weak arch_auxiliary_core_check_up(u32 core_id)
int arch_auxiliary_core_check_up(u32 core_id)
{
/* please define platform specific arch_auxiliary_core_check_up() */
return 0;
unsigned int val;
val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET);
if (val & SRC_M4C_NON_SCLR_RST_MASK)
return 0; /* assert in reset */
return 1;
}
/*

38
arch/arm/mach-imx/mx6/soc.c
View file

@ -666,41 +666,3 @@ void gpr_init(void)
writel(0x007F007F, &iomux->gpr[7]);
}
}
#ifdef CONFIG_IMX_BOOTAUX
int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
{
struct src *src_reg;
u32 stack, pc;
if (!boot_private_data)
return -EINVAL;
stack = *(u32 *)boot_private_data;
pc = *(u32 *)(boot_private_data + 4);
/* Set the stack and pc to M4 bootROM */
writel(stack, M4_BOOTROM_BASE_ADDR);
writel(pc, M4_BOOTROM_BASE_ADDR + 4);
/* Enable M4 */
src_reg = (struct src *)SRC_BASE_ADDR;
clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK,
SRC_SCR_M4_ENABLE_MASK);
return 0;
}
int arch_auxiliary_core_check_up(u32 core_id)
{
struct src *src_reg = (struct src *)SRC_BASE_ADDR;
unsigned val;
val = readl(&src_reg->scr);
if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK)
return 0; /* assert in reset */
return 1;
}
#endif

36
arch/arm/mach-imx/mx7/soc.c
View file

@ -208,42 +208,6 @@ void get_board_serial(struct tag_serialnr *serialnr)
}
#endif
#ifdef CONFIG_IMX_BOOTAUX
int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
{
u32 stack, pc;
struct src *src_reg = (struct src *)SRC_BASE_ADDR;
if (!boot_private_data)
return 1;
stack = *(u32 *)boot_private_data;
pc = *(u32 *)(boot_private_data + 4);
/* Set the stack and pc to M4 bootROM */
writel(stack, M4_BOOTROM_BASE_ADDR);
writel(pc, M4_BOOTROM_BASE_ADDR + 4);
/* Enable M4 */
clrsetbits_le32(&src_reg->m4rcr, SRC_M4RCR_M4C_NON_SCLR_RST_MASK,
SRC_M4RCR_ENABLE_M4_MASK);
return 0;
}
int arch_auxiliary_core_check_up(u32 core_id)
{
uint32_t val;
struct src *src_reg = (struct src *)SRC_BASE_ADDR;
val = readl(&src_reg->m4rcr);
if (val & 0x00000001)
return 0; /* assert in reset */
return 1;
}
#endif
void set_wdog_reset(struct wdog_regs *wdog)
{
u32 reg = readw(&wdog->wcr);