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clk: imx: pllv3: add enable_bit
pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
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1 changed files with 9 additions and 0 deletions
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@ -25,6 +25,7 @@
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#define PLL_DENOM_OFFSET 0x20
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#define PLL_DENOM_OFFSET 0x20
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#define BM_PLL_POWER (0x1 << 12)
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#define BM_PLL_POWER (0x1 << 12)
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#define BM_PLL_ENABLE (0x1 << 13)
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#define BM_PLL_LOCK (0x1 << 31)
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#define BM_PLL_LOCK (0x1 << 31)
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struct clk_pllv3 {
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struct clk_pllv3 {
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@ -32,6 +33,7 @@ struct clk_pllv3 {
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void __iomem *base;
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void __iomem *base;
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u32 power_bit;
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u32 power_bit;
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bool powerup_set;
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bool powerup_set;
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u32 enable_bit;
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u32 div_mask;
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u32 div_mask;
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u32 div_shift;
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u32 div_shift;
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};
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};
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@ -83,6 +85,9 @@ static int clk_pllv3_generic_enable(struct clk *clk)
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val |= pll->power_bit;
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val |= pll->power_bit;
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else
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else
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val &= ~pll->power_bit;
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val &= ~pll->power_bit;
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val |= pll->enable_bit;
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writel(val, pll->base);
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writel(val, pll->base);
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return 0;
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return 0;
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@ -98,6 +103,9 @@ static int clk_pllv3_generic_disable(struct clk *clk)
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val &= ~pll->power_bit;
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val &= ~pll->power_bit;
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else
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else
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val |= pll->power_bit;
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val |= pll->power_bit;
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val &= ~pll->enable_bit;
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writel(val, pll->base);
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writel(val, pll->base);
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return 0;
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return 0;
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@ -238,6 +246,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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return ERR_PTR(-ENOMEM);
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return ERR_PTR(-ENOMEM);
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pll->power_bit = BM_PLL_POWER;
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pll->power_bit = BM_PLL_POWER;
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pll->enable_bit = BM_PLL_ENABLE;
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switch (type) {
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switch (type) {
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case IMX_PLLV3_GENERIC:
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case IMX_PLLV3_GENERIC:
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