Convert CONFIG_SPD_EEPROM to Kconfig

This converts the following to Kconfig:
   CONFIG_SPD_EEPROM

Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-11-19 18:45:34 -05:00
parent d91365203c
commit 8ce59b5932
9 changed files with 12 additions and 12 deletions

7
README
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@ -1683,13 +1683,6 @@ Low Level (hardware related) configuration options:
Sets the EBC0_CFG register for the NDFC. If not defined Sets the EBC0_CFG register for the NDFC. If not defined
a default value will be used. a default value will be used.
- CONFIG_SPD_EEPROM
Get DDR timing information from an I2C EEPROM. Common
with pluggable memory modules such as SODIMMs
SPD_EEPROM_ADDRESS
I2C address of the SPD EEPROM
- CONFIG_SYS_SPD_BUS_NUM - CONFIG_SYS_SPD_BUS_NUM
If SPD EEPROM is on an I2C bus other than the first If SPD EEPROM is on an I2C bus other than the first
one, specify here. Note that the value must resolve one, specify here. Note that the value must resolve

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@ -45,6 +45,7 @@ CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="8548cds/uImage.uboot" CONFIG_BOOTFILE="8548cds/uImage.uboot"
CONFIG_USE_ETHPRIME=y CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC0" CONFIG_ETHPRIME="eTSEC0"
CONFIG_SPD_EEPROM=y
CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_DDR_ECC=y CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

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@ -44,6 +44,7 @@ CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="8548cds/uImage.uboot" CONFIG_BOOTFILE="8548cds/uImage.uboot"
CONFIG_USE_ETHPRIME=y CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC0" CONFIG_ETHPRIME="eTSEC0"
CONFIG_SPD_EEPROM=y
CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_DDR_ECC=y CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

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@ -44,6 +44,7 @@ CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="8548cds/uImage.uboot" CONFIG_BOOTFILE="8548cds/uImage.uboot"
CONFIG_USE_ETHPRIME=y CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC0" CONFIG_ETHPRIME="eTSEC0"
CONFIG_SPD_EEPROM=y
CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_DDR_ECC=y CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

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@ -57,6 +57,7 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR_REDUND=0xFFF20000 CONFIG_ENV_ADDR_REDUND=0xFFF20000
CONFIG_USE_ETHPRIME=y CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="TSEC0" CONFIG_ETHPRIME="TSEC0"
CONFIG_SPD_EEPROM=y
CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFE001001 CONFIG_SYS_BR0_PRELIM=0xFE001001

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@ -37,3 +37,11 @@ config SYS_SPD_BUS_NUM
source "drivers/ddr/altera/Kconfig" source "drivers/ddr/altera/Kconfig"
source "drivers/ddr/imx/Kconfig" source "drivers/ddr/imx/Kconfig"
config SPD_EEPROM
bool "DDR controller makes use of an SPD EEPROM for JEDEC information"
depends on SYS_FSL_DDR || SYS_FSL_MMDC || CONFIG_ARMADA_XP
help
Get DDR timing information from an I2C EEPROM. Common with pluggable
memory modules such as SODIMMs. You must define SPD_EEPROM_ADDRESS
to the I2C address of the SPD EEPROM.

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@ -30,7 +30,6 @@
#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR #define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/* DDR Setup */ /* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_MEM_INIT_VALUE 0xDeadBeef

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@ -45,7 +45,4 @@
/* SPL */ /* SPL */
/* Defines for SPL */ /* Defines for SPL */
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SPD_EEPROM 0x4e
#endif /* _CONFIG_DB_MV7846MP_GP_H */ #endif /* _CONFIG_DB_MV7846MP_GP_H */

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@ -50,7 +50,6 @@
#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR #define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/* DDR Setup */ /* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_MEM_INIT_VALUE 0xDeadBeef