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ram: ast2600: Align the RL and WL setting

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Use macro to represent the RL and WL setting to ensure the PHY and
controller setting are aligned.

Review-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
This commit is contained in:
Dylan Hung 2022-11-11 15:30:08 +08:00 committed by Tom Rini
parent bd1e195421
commit 8c7b55724c
2 changed files with 13 additions and 0 deletions
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4
arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
View file

@ -104,6 +104,10 @@
#define SDRAM_FORCE_PRECHARGE_EN BIT(4) #define SDRAM_FORCE_PRECHARGE_EN BIT(4)
#define SDRAM_REFRESH_EN BIT(0) #define SDRAM_REFRESH_EN BIT(0)
/* MCR14 */
#define SDRAM_WL_SETTING GENMASK(23, 20)
#define SDRAM_CL_SETTING GENMASK(19, 16)
#define SDRAM_TEST_LEN_SHIFT 4 #define SDRAM_TEST_LEN_SHIFT 4
#define SDRAM_TEST_LEN_MASK 0xfffff #define SDRAM_TEST_LEN_MASK 0xfffff
#define SDRAM_TEST_START_ADDR_SHIFT 24 #define SDRAM_TEST_START_ADDR_SHIFT 24

9
drivers/ram/aspeed/sdram_ast2600.c
View file

@ -15,6 +15,7 @@
#include <asm/global_data.h> #include <asm/global_data.h>
#include <linux/err.h> #include <linux/err.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/bitfield.h>
#include <dt-bindings/clock/ast2600-clock.h> #include <dt-bindings/clock/ast2600-clock.h>
#define DDR_PHY_TBL_CHG_ADDR 0xaeeddeea #define DDR_PHY_TBL_CHG_ADDR 0xaeeddeea
@ -935,6 +936,7 @@ static void ast2600_sdrammc_lock(struct dram_info *info)
static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs)
{ {
int i; int i;
u32 reg;
writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, &regs->power_ctrl); writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, &regs->power_ctrl);
writel(SDRAM_VIDEO_UNLOCK_KEY, &regs->gm_protection_key); writel(SDRAM_VIDEO_UNLOCK_KEY, &regs->gm_protection_key);
@ -969,6 +971,13 @@ static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs)
for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
writel(ddr4_ac_timing[i], &regs->ac_timing[i]); writel(ddr4_ac_timing[i], &regs->ac_timing[i]);
/* update CL and WL */
reg = readl(&regs->ac_timing[1]);
reg &= ~(SDRAM_WL_SETTING | SDRAM_CL_SETTING);
reg |= FIELD_PREP(SDRAM_WL_SETTING, CONFIG_WL - 5) |
FIELD_PREP(SDRAM_CL_SETTING, CONFIG_RL - 5);
writel(reg, &regs->ac_timing[1]);
writel(DDR4_MR01_MODE, &regs->mr01_mode_setting); writel(DDR4_MR01_MODE, &regs->mr01_mode_setting);
writel(DDR4_MR23_MODE, &regs->mr23_mode_setting); writel(DDR4_MR23_MODE, &regs->mr23_mode_setting);
writel(DDR4_MR45_MODE, &regs->mr45_mode_setting); writel(DDR4_MR45_MODE, &regs->mr45_mode_setting);