mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-01 00:49:43 +00:00
AT91 rework: fix at91sam(9260/9g20/9xe)ek board port to build again:
Make ATMEL's at91sam9260/9g20/9xe-ek boards build again Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
This commit is contained in:
Reinhard Meyer
Albert ARIBAUD
parent
b8d41dda22
commit
8c6407fce3
6 changed files with 151 additions and 146 deletions
37
Makefile
37
Makefile
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@ -766,43 +766,6 @@ M5485HFE_config : unconfig
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## ARM926EJ-S Systems
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#########################################################################
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at91sam9260ek_nandflash_config \
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at91sam9260ek_dataflash_cs0_config \
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at91sam9260ek_dataflash_cs1_config \
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at91sam9260ek_config \
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at91sam9g20ek_nandflash_config \
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at91sam9g20ek_dataflash_cs0_config \
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at91sam9g20ek_dataflash_cs1_config \
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at91sam9g20ek_config : unconfig
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@mkdir -p $(obj)include
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@if [ "$(findstring 9g20,$@)" ] ; then \
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echo "#define CONFIG_AT91SAM9G20EK 1" >>$(obj)include/config.h ; \
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else \
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echo "#define CONFIG_AT91SAM9260EK 1" >>$(obj)include/config.h ; \
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fi;
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@if [ "$(findstring _nandflash,$@)" ] ; then \
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echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
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elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
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echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1" >>$(obj)include/config.h ; \
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else \
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echo "#define CONFIG_SYS_USE_DATAFLASH_CS1 1" >>$(obj)include/config.h ; \
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fi;
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@$(MKCONFIG) -n $@ -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91
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at91sam9xeek_nandflash_config \
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at91sam9xeek_dataflash_cs0_config \
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at91sam9xeek_dataflash_cs1_config \
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at91sam9xeek_config : unconfig
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@mkdir -p $(obj)include
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@if [ "$(findstring _nandflash,$@)" ] ; then \
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echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
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elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
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echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1" >>$(obj)include/config.h ; \
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else \
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echo "#define CONFIG_SYS_USE_DATAFLASH_CS1 1" >>$(obj)include/config.h ; \
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fi;
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@$(MKCONFIG) -n $@ -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91
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at91sam9261ek_nandflash_config \
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at91sam9261ek_dataflash_cs0_config \
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at91sam9261ek_dataflash_cs3_config \
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@ -23,17 +23,16 @@
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*/
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#include <common.h>
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#include <asm/arch/at91sam9260.h>
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#include <asm/io.h>
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#include <asm/arch/at91sam9260_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <asm/arch/hardware.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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#include <net.h>
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# include <net.h>
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#endif
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#include <netdev.h>
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@ -47,49 +46,53 @@ DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_CMD_NAND
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static void at91sam9260ek_nand_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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unsigned long csa;
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBICSA);
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at91_sys_write(AT91_MATRIX_EBICSA,
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csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
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/* Assign CS3 to NAND/SmartMedia Interface */
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csa = readl(&matrix->ebicsa);
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csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
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writel(csa, &matrix->ebicsa);
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/* Configure SMC CS3 for NAND/SmartMedia */
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_DBW_16 |
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AT91_SMC_MODE_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_DBW_8 |
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AT91_SMC_MODE_DBW_8 |
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#endif
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AT91_SMC_TDF_(2));
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
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AT91_SMC_MODE_TDF_CYCLE(2),
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&smc->cs[3].mode);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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/* Enable NandFlash */
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at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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}
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#endif
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#ifdef CONFIG_MACB
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static void at91sam9260ek_macb_hw_init(void)
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{
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unsigned long rstc;
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
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struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
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unsigned long erstl;
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
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/* Enable EMAC clock */
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writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
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/*
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* Disable pull-up on:
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@ -108,24 +111,23 @@ static void at91sam9260ek_macb_hw_init(void)
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pin_to_mask(AT91_PIN_PA25) |
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pin_to_mask(AT91_PIN_PA26) |
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pin_to_mask(AT91_PIN_PA28),
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pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
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&pioa->pudr);
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rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
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erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
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/* Need to reset PHY -> 500ms reset */
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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(AT91_RSTC_ERSTL & (0x0D << 8)) |
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AT91_RSTC_URSTEN);
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writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
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AT91_RSTC_MR_URSTEN, &rstc->mr);
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at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
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writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
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/* Wait for end hardware reset */
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while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
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while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
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;
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/* Restore NRST value */
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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(rstc) |
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AT91_RSTC_URSTEN);
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writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
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&rstc->mr);
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/* Re-enable pull-up */
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writel(pin_to_mask(AT91_PIN_PA14) |
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@ -134,17 +136,27 @@ static void at91sam9260ek_macb_hw_init(void)
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pin_to_mask(AT91_PIN_PA25) |
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pin_to_mask(AT91_PIN_PA26) |
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pin_to_mask(AT91_PIN_PA28),
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pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
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&pioa->puer);
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/* Initialize EMAC=MACB hardware */
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at91_macb_hw_init();
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}
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#endif
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int board_early_init_f(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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/* Enable clocks for all PIOs */
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writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
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(1 << ATMEL_ID_PIOC),
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&pmc->pcer);
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return 0;
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}
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int board_init(void)
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{
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/* Enable Ctrlc */
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console_init_f();
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#ifdef CONFIG_AT91SAM9G20EK
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/* arch number of AT91SAM9260EK-Board */
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gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK;
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@ -153,9 +165,9 @@ int board_init(void)
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gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK;
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#endif
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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at91_serial_hw_init();
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at91_seriald_hw_init();
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#ifdef CONFIG_CMD_NAND
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at91sam9260ek_nand_hw_init();
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#endif
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@ -171,8 +183,9 @@ int board_init(void)
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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gd->ram_size = get_ram_size(
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(void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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@ -186,7 +199,7 @@ int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
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rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
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#endif
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return rc;
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}
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@ -1 +0,0 @@
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CONFIG_SYS_TEXT_BASE = 0x23f00000
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@ -23,16 +23,12 @@
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*/
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#include <common.h>
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#include <asm/arch/at91sam9260.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/io.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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void coloured_LED_init(void)
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{
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA);
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/* Clock is enabled in board_early_init_f() */
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at91_set_gpio_output(CONFIG_RED_LED, 1);
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at91_set_gpio_output(CONFIG_GREEN_LED, 1);
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@ -74,6 +74,15 @@ omap1510inn arm arm925t - ti
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aspenite arm arm926ejs - Marvell armada100
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afeb9260 arm arm926ejs - - at91
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at91cap9adk arm arm926ejs - atmel at91
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at91sam9260ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH
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at91sam9260ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0
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at91sam9260ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1
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at91sam9g20ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH
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at91sam9g20ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0
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at91sam9g20ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1
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at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH
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at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0
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at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1
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snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260
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snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20
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cpu9260 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260
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@ -27,38 +27,53 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
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#ifdef CONFIG_AT91SAM9G20EK
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#define CONFIG_AT91SAM9G20 1 /* It's an Atmel AT91SAM9G20 SoC*/
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#else
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#define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/
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#endif
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#define CONFIG_ARCH_CPU_INIT
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/*
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* SoC must be defined first, before hardware.h is included.
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* In this case SoC is defined in boards.cfg.
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*/
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#include <asm/hardware.h>
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/*
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* Hardware drivers
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* Warning: changing CONFIG_SYS_TEXT_BASE requires
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* adapting the initial boot program.
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* Since the linker has to swallow that define, we must use a pure
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* hex number here!
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*/
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#define CONFIG_AT91_GPIO 1
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#define CONFIG_ATMEL_USART 1
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#undef CONFIG_USART0
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#undef CONFIG_USART1
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#undef CONFIG_USART2
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#define CONFIG_USART3 1 /* USART 3 is DBGU */
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#define CONFIG_SYS_TEXT_BASE 0x21f00000
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
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#define CONFIG_SYS_HZ 1000
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/* Define actual evaluation board type from used processor type */
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#ifdef CONFIG_AT91SAM9G20
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# define CONFIG_AT91SAM9G20EK /* It's an Atmel AT91SAM9G20 EK */
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#else
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# define CONFIG_AT91SAM9260EK /* It's an Atmel AT91SAM9260 EK */
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#endif
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/* Misc CPU related */
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#define CONFIG_ARCH_CPU_INIT
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_DISPLAY_CPUINFO
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/* general purpose I/O */
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#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
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#define CONFIG_AT91_GPIO
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#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
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/* serial console */
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART_BASE ATMEL_BASE_DBGU
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#define CONFIG_USART_ID ATMEL_ID_SYS
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
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/* LED */
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#define CONFIG_AT91_LED
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@ -91,10 +106,26 @@
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#define CONFIG_CMD_NAND 1
|
||||
#define CONFIG_CMD_USB 1
|
||||
|
||||
/* SDRAM */
|
||||
/*
|
||||
* SDRAM: 1 bank, min 32, max 128 MB
|
||||
* Initialized before u-boot gets started.
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM 0x20000000
|
||||
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
|
||||
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
|
||||
#define CONFIG_SYS_SDRAM_SIZE 0x04000000
|
||||
|
||||
/*
|
||||
* Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
|
||||
* leaving the correct space for initial global data structure above
|
||||
* that address while providing maximum stack area below.
|
||||
*/
|
||||
#ifdef CONFIG_AT91SAM9XE
|
||||
# define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE)
|
||||
#else
|
||||
# define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
|
||||
#endif
|
||||
|
||||
/* DataFlash */
|
||||
#define CONFIG_ATMEL_DATAFLASH_SPI
|
||||
|
|
@ -116,15 +147,12 @@
|
|||
#ifdef CONFIG_CMD_NAND
|
||||
#define CONFIG_NAND_ATMEL
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
#define CONFIG_SYS_NAND_DBW_8 1
|
||||
/* our ALE is AD21 */
|
||||
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
|
||||
#define CONFIG_SYS_NAND_DBW_8
|
||||
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
|
||||
/* our CLE is AD22 */
|
||||
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
|
||||
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
|
||||
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
|
||||
|
||||
#endif
|
||||
|
||||
/* NOR flash - no real flash on this board */
|
||||
|
|
@ -150,7 +178,7 @@
|
|||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
|
||||
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_MEMTEST_END 0x23e00000
|
||||
|
||||
#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
|
||||
|
|
@ -198,9 +226,6 @@
|
|||
|
||||
#endif
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
|
||||
|
||||
#define CONFIG_SYS_PROMPT "U-Boot> "
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
|
|
|
|||
Loading…
Reference in a new issue