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[MIPS] Rename Alchemy processor configs into CONFIG_SOC_*

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CONFIG_SOC_AU1X00

  Common Alchemy Au1x00 stuff. All Alchemy processor based machines
  need to have this config as a system type specifier.

CONFIG_SOC_AU1000, CONFIG_SOC_AU1100, CONFIG_SOC_AU1200,
CONFIG_SOC_AU1500, CONFIG_SOC_AU1550

  Machine type specifiers. Each port should have one of aboves.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
This commit is contained in:
Shinya Kuribayashi 2008-06-07 20:51:56 +09:00 committed by Shinya Kuribayashi
parent 7daf2ebe91
commit 8bde63eb3f
8 changed files with 26 additions and 26 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
cpu/mips/au1x00_eth.c
View file

@ -23,7 +23,7 @@
*/
#include <config.h>
#ifdef CONFIG_AU1X00
#ifdef CONFIG_SOC_AU1X00
#if defined(CFG_DISCOVER_PHY)
#error "PHY not supported yet"
@ -33,20 +33,20 @@
/* I assume ethernet behaves like au1000 */
#ifdef CONFIG_AU1000
#ifdef CONFIG_SOC_AU1000
/* Base address differ between cpu:s */
#define ETH0_BASE AU1000_ETH0_BASE
#define MAC0_ENABLE AU1000_MAC0_ENABLE
#else
#ifdef CONFIG_AU1100
#ifdef CONFIG_SOC_AU1100
#define ETH0_BASE AU1100_ETH0_BASE
#define MAC0_ENABLE AU1100_MAC0_ENABLE
#else
#ifdef CONFIG_AU1500
#ifdef CONFIG_SOC_AU1500
#define ETH0_BASE AU1500_ETH0_BASE
#define MAC0_ENABLE AU1500_MAC0_ENABLE
#else
#ifdef CONFIG_AU1550
#ifdef CONFIG_SOC_AU1550
#define ETH0_BASE AU1550_ETH0_BASE
#define MAC0_ENABLE AU1550_MAC0_ENABLE
#else
@ -308,4 +308,4 @@ int au1x00_enet_initialize(bd_t *bis){
return 1;
}
#endif /* CONFIG_AU1X00 */
#endif /* CONFIG_SOC_AU1X00 */

4
cpu/mips/au1x00_serial.c
View file

@ -27,7 +27,7 @@
#include <config.h>
#ifdef CONFIG_AU1X00
#ifdef CONFIG_SOC_AU1X00
#include <common.h>
#include <asm/au1x00.h>
@ -132,4 +132,4 @@ int serial_tstc (void)
}
return 0;
}
#endif /* CONFIG_SERIAL_AU1X00 */
#endif /* CONFIG_SOC_AU1X00 */

2
cpu/mips/au1x00_usb_ohci.c
View file

@ -35,7 +35,7 @@
#include <config.h>
#if defined(CONFIG_AU1X00) && defined(CONFIG_USB_OHCI)
#if defined(CONFIG_SOC_AU1X00) && defined(CONFIG_USB_OHCI)
/* #include <pci.h> no PCI on the AU1x00 */

6
include/asm-mips/addrspace.h
View file

@ -131,13 +131,13 @@
* Returns the uncached address of a sdram address
*/
#ifndef __ASSEMBLY__
#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229)
#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229)
/* We use a 36 bit physical address map here and
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
#else /* !CONFIG_AU1X00 */
#else /* !CONFIG_SOC_AU1X00 */
#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
#endif /* CONFIG_AU1X00 */
#endif /* CONFIG_SOC_AU1X00 */
#endif /* __ASSEMBLY__ */
/*

6
include/asm-mips/au1x00.h
View file

@ -137,7 +137,7 @@ static __inline__ int au_ffs(int x)
#define CP0_DEBUG $23
/* SDRAM Controller */
#ifdef CONFIG_AU1550
#ifdef CONFIG_SOC_AU1550
#define MEM_SDMODE0 0xB4000800
#define MEM_SDMODE1 0xB4000808
@ -156,7 +156,7 @@ static __inline__ int au_ffs(int x)
#define MEM_SDWRMD1 0xB4000888
#define MEM_SDWRMD2 0xB4000890
#else /* CONFIG_AU1550 */
#else /* CONFIG_SOC_AU1550 */
#define MEM_SDMODE0 0xB4000000
#define MEM_SDMODE1 0xB4000004
@ -174,7 +174,7 @@ static __inline__ int au_ffs(int x)
#define MEM_SDWRMD1 0xB4000028
#define MEM_SDWRMD2 0xB400002C
#endif /* CONFIG_AU1550 */
#endif /* CONFIG_SOC_AU1550 */
#define MEM_SDSLEEP 0xB4000030
#define MEM_SDSMCKE 0xB4000034

10
include/configs/dbau1x00.h
View file

@ -30,21 +30,21 @@
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_DBAU1X00 1
#define CONFIG_AU1X00 1 /* alchemy series cpu */
#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
#ifdef CONFIG_DBAU1000
/* Also known as Merlot */
#define CONFIG_AU1000 1
#define CONFIG_SOC_AU1000 1
#else
#ifdef CONFIG_DBAU1100
#define CONFIG_AU1100 1
#define CONFIG_SOC_AU1100 1
#else
#ifdef CONFIG_DBAU1500
#define CONFIG_AU1500 1
#define CONFIG_SOC_AU1500 1
#else
#ifdef CONFIG_DBAU1550
/* Cabernet */
#define CONFIG_AU1550 1
#define CONFIG_SOC_AU1550 1
#else
#error "No valid board set"
#endif

4
include/configs/gth2.h
View file

@ -30,9 +30,9 @@
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_GTH2 1
#define CONFIG_AU1X00 1 /* alchemy series cpu */
#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
#define CONFIG_AU1000 1
#define CONFIG_SOC_AU1000 1
#define CONFIG_MISC_INIT_R 1

8
include/configs/pb1x00.h
View file

@ -30,16 +30,16 @@
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_PB1X00 1
#define CONFIG_AU1X00 1 /* alchemy series cpu */
#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
#ifdef CONFIG_PB1000
#define CONFIG_AU1000 1
#define CONFIG_SOC_AU1000 1
#else
#ifdef CONFIG_PB1100
#define CONFIG_AU1100 1
#define CONFIG_SOC_AU1100 1
#else
#ifdef CONFIG_PB1500
#define CONFIG_AU1500 1
#define CONFIG_SOC_AU1500 1
#else
#error "No valid board set"
#endif