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Merge branch '2022-06-06-finish-SPL-Kconfig-migration' into next

Browse source 
- Bring in a number of series of patches that migrate all remaining
  CONFIG_SPL symbols to Kconfig, remove some dead code that this
  uncovered and then start to tighten the dependencies in Kconfig now
  that everything is migrated and these relationships can be clearly
  expressed.
This commit is contained in:
Tom Rini 2022-06-06 12:09:41 -04:00
commit 8bbbd63373
1740 changed files with 7693 additions and 8110 deletions
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26
Kconfig
View file

@ -228,12 +228,38 @@ config SYS_BOOT_GET_CMDLINE
Enables allocating and saving kernel cmdline in space between
"bootm_low" and "bootm_low" + BOOTMAPSZ.
config SYS_BARGSIZE
int "Size of kernel command line buffer in bytes"
depends on SYS_BOOT_GET_CMDLINE
default 512
help
Buffer size for Boot Arguments which are passed to the application
(usually a Linux kernel) when it is booted
config SYS_BOOT_GET_KBD
bool "Enable kernel board information setup"
help
Enables allocating and saving a kernel copy of the bd_info in
space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
config HAS_CUSTOM_SYS_INIT_SP_ADDR
bool "Use a custom location for the initial stack pointer address"
depends on ARC || (ARM && !INIT_SP_RELATIVE) || MIPS || PPC || RISCV
default y if TFABOOT
help
Typically, we use an initial stack pointer address that is calculated
by taking the statically defined CONFIG_SYS_INIT_RAM_ADDR, adding the
statically defined CONFIG_SYS_INIT_RAM_SIZE and then subtracting the
build-time constant of GENERATED_GBL_DATA_SIZE. On MIPS a different
but statica calculation is performed. However, some platforms will
take a different approach. Say Y here to define the address statically
instead.
config CUSTOM_SYS_INIT_SP_ADDR
hex "Static location for the initial stack pointer"
depends on HAS_CUSTOM_SYS_INIT_SP_ADDR
default SYS_TEXT_BASE if TFABOOT
config SYS_MALLOC_F
bool "Enable malloc() pool before relocation"
default y if DM

165
README
View file

@ -293,33 +293,6 @@ board_init_r():
SPL-specific notes:
- stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and
CONFIG_SPL_STACK_R_ADDR points into SDRAM
- preloader_console_init() can be called here - typically this is
done by selecting CONFIG_SPL_BOARD_INIT and then supplying a
spl_board_init() function containing this call
- loads U-Boot or (in falcon mode) Linux
Configuration Options:
----------------------
Configuration depends on the combination of board and CPU type; all
such information is kept in a configuration file
"include/configs/<board_name>.h".
Example: For a TQM823L module, all configuration settings are in
"include/configs/TQM823L.h".
Many of the options are named exactly as the corresponding Linux
kernel configuration options. The intention is to make it easier to
build a config tool - later.
- ARM Platform Bus Type(CCI):
CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
provides full cache coherency between two clusters of multi-core
CPUs and I/O coherency for devices and I/O masters
CONFIG_SYS_FSL_HAS_CCI400
Defined For SoC that has cache coherent interconnect
@ -493,12 +466,6 @@ The following options need to be configured:
Defines the SEC controller register space as Little Endian
- MIPS CPU options:
CONFIG_SYS_INIT_SP_OFFSET
Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack
pointer. This is needed for the temporary stack before
relocation.
CONFIG_XWAY_SWAP_BYTES
Enable compilation of tools/xway-swap-bytes needed for Lantiq
@ -1658,36 +1625,6 @@ The following options need to be configured:
CONFIG_SPL
Enable building of SPL globally.
CONFIG_SPL_MAX_FOOTPRINT
Maximum size in memory allocated to the SPL, BSS included.
When defined, the linker checks that the actual memory
used by SPL from _start to __bss_end does not exceed it.
CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
must not be both defined at the same time.
CONFIG_SPL_MAX_SIZE
Maximum size of the SPL image (text, data, rodata, and
linker lists sections), BSS excluded.
When defined, the linker checks that the actual size does
not exceed it.
CONFIG_SPL_RELOC_TEXT_BASE
Address to relocate to. If unspecified, this is equal to
CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
CONFIG_SPL_BSS_START_ADDR
Link address for the BSS within the SPL binary.
CONFIG_SPL_BSS_MAX_SIZE
Maximum size in memory allocated to the SPL BSS.
When defined, the linker checks that the actual memory used
by SPL from __bss_start to __bss_end does not exceed it.
CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
must not be both defined at the same time.
CONFIG_SPL_STACK
Adress of the start of the stack SPL will use
CONFIG_SPL_PANIC_ON_RAW_IMAGE
When defined, SPL will panic() if the image it has
loaded does not have a signature.
@ -1698,65 +1635,20 @@ The following options need to be configured:
consider that a completely unreadable NAND block is bad,
and thus should be skipped silently.
CONFIG_SPL_RELOC_STACK
Adress of the start of the stack SPL will use after
relocation. If unspecified, this is equal to
CONFIG_SPL_STACK.
CONFIG_SYS_SPL_MALLOC_START
Starting address of the malloc pool used in SPL.
When this option is set the full malloc is used in SPL and
it is set up by spl_init() and before that, the simple malloc()
can be used if CONFIG_SYS_MALLOC_F is defined.
CONFIG_SYS_SPL_MALLOC_SIZE
The size of the malloc pool used in SPL.
CONFIG_SPL_DISPLAY_PRINT
For ARM, enable an optional function to print more information
about the running system.
CONFIG_SPL_INIT_MINIMAL
Arch init code should be built for a very small image
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
Sector and number of sectors to load kernel argument
parameters from when MMC is being used in raw mode
(for falcon mode)
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
Filename to read to load U-Boot when reading from filesystem
CONFIG_SPL_FS_LOAD_KERNEL_NAME
Filename to read to load kernel uImage when reading
from filesystem (for Falcon mode)
CONFIG_SPL_FS_LOAD_ARGS_NAME
Filename to read to load kernel argument parameters
when reading from filesystem (for Falcon mode)
CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
Set this for NAND SPL on PPC mpc83xx targets, so that
start.S waits for the rest of the SPL to load before
continuing (the hardware starts execution after just
loading the first page rather than the full 4K).
CONFIG_SPL_SKIP_RELOCATE
Avoid SPL relocation
CONFIG_SPL_UBI
Support for a lightweight UBI (fastmap) scanner and
loader
CONFIG_SPL_NAND_RAW_ONLY
Support to boot only raw u-boot.bin images. Use this only
if you need to save space.
CONFIG_SPL_COMMON_INIT_DDR
Set for common ddr init with serial presence detect in
SPL binary.
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
@ -1781,35 +1673,12 @@ The following options need to be configured:
CONFIG_SPL_RAM_DEVICE
Support for running image already present in ram, in SPL binary
CONFIG_SPL_PAD_TO
Image offset to which the SPL should be padded before appending
the SPL payload. By default, this is defined as
CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
CONFIG_SPL_TARGET
Final target image containing SPL and payload. Some SPLs
use an arch-specific makefile fragment instead, for
example if more than one image needs to be produced.
CONFIG_SPL_FIT_PRINT
Printing information about a FIT image adds quite a bit of
code to SPL. So this is normally disabled in SPL. Use this
option to re-enable it. This will affect the output of the
bootm command when booting a FIT image.
- TPL framework
CONFIG_TPL
Enable building of TPL globally.
CONFIG_TPL_PAD_TO
Image offset to which the TPL should be padded before appending
the TPL payload. By default, this is defined as
CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
- Interrupt support (PPC):
There are common interrupt_init() and timer_interrupt()
@ -1853,16 +1722,6 @@ Configuration Settings:
- CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to
prompt for user input.
- CONFIG_SYS_CBSIZE: Buffer size for input from the Console
- CONFIG_SYS_PBSIZE: Buffer size for Console output
- CONFIG_SYS_MAXARGS: max. Number of arguments accepted for monitor commands
- CONFIG_SYS_BARGSIZE: Buffer size for Boot Arguments which are passed to
the application (usually a Linux kernel) when it is
booted
- CONFIG_SYS_BAUDRATE_TABLE:
List of legal baudrate settings for this board.
@ -1909,7 +1768,7 @@ Configuration Settings:
- CONFIG_SYS_MALLOC_SIMPLE
Provides a simple and small malloc() and calloc() for those
boards which do not use the full malloc in SPL (which is
enabled with CONFIG_SYS_SPL_MALLOC_START).
enabled with CONFIG_SYS_SPL_MALLOC).
- CONFIG_SYS_NONCACHED_MEMORY:
Size of non-cached memory area. This area of memory will be
@ -2186,10 +2045,6 @@ Low Level (hardware related) configuration options:
used in assembly code, so it must not contain typecasts or
integer size suffixes (e.g. "ULL").
- CONFIG_SYS_CCSR_DO_NOT_RELOCATE:
If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be
forced to a value that ensures that CCSR is not relocated.
- CONFIG_SYS_IMMR: Physical address of the Internal Memory.
DO NOT CHANGE unless you know exactly what you're
doing! (11-4) [MPC8xx systems only]
@ -2207,24 +2062,6 @@ Low Level (hardware related) configuration options:
U-Boot uses the following memory types:
- MPC8xx: IMMR (internal memory of the CPU)
- CONFIG_SYS_GBL_DATA_OFFSET:
Offset of the initial data structure in the memory
area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
data is located at the end of the available space
(sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
GENERATED_GBL_DATA_SIZE), and the initial stack is just
below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
CONFIG_SYS_GBL_DATA_OFFSET) downward.
Note:
On the MPC824X (or other systems that use the data
cache for initial memory) the address chosen for
CONFIG_SYS_INIT_RAM_ADDR is basically arbitrary - it must
point to an otherwise UNUSED address space between
the top of RAM and the start of the PCI space.
- CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)
- CONFIG_SYS_OR_TIMING_SDRAM:

3
arch/arc/lib/start.S
View file

@ -7,6 +7,7 @@
#include <config.h>
#include <linux/linkage.h>
#include <asm/arcregs.h>
#include <system-constants.h>
ENTRY(_start)
/* Setup interrupt vector base that matches "__text_start" */
@ -86,7 +87,7 @@ ENTRY(_start)
#endif
/* Establish C runtime stack and frame */
mov %sp, CONFIG_SYS_INIT_SP_ADDR
mov %sp, SYS_INIT_SP_ADDR
mov %fp, %sp
/* Allocate reserved area from current top of stack */

4
arch/arm/Makefile
View file

@ -103,8 +103,8 @@ libs-y += $(machdirs)
head-y := arch/arm/cpu/$(CPU)/start.o
ifeq ($(CONFIG_SPL_BUILD),y)
ifneq ($(CONFIG_SPL_START_S_PATH),)
head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o
ifeq ($(CONFIG_SYS_SOC)$(CONFIG_SPL_FRAMEWORK),"mxs")
head-y := arch/arm/cpu/arm926ejs/mxs/start.o
endif
endif

3
arch/arm/cpu/arm926ejs/mxs/start.S
View file

@ -21,6 +21,7 @@
#include <asm-offsets.h>
#include <config.h>
#include <common.h>
#include <system-constants.h>
/*
*************************************************************************
@ -44,7 +45,7 @@ reset:
* it point to the end of OCRAM if the SP is zero.
*/
cmp sp, #0x00000000
ldreq sp, =CONFIG_SYS_INIT_SP_ADDR
ldreq sp, =SYS_INIT_SP_ADDR
/*
* Store all registers on old stack pointer, this will allow us later to

3
arch/arm/cpu/armv7/lowlevel_init.S
View file

@ -13,6 +13,7 @@
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
#include <system-constants.h>
.pushsection .text.s_init, "ax"
WEAK(s_init)
@ -28,7 +29,7 @@ WEAK(lowlevel_init)
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr sp, =CONFIG_SPL_STACK
#else
ldr sp, =CONFIG_SYS_INIT_SP_ADDR
ldr sp, =SYS_INIT_SP_ADDR
#endif
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
#ifdef CONFIG_SPL_DM

3
arch/arm/cpu/armv7/start.S
View file

@ -17,6 +17,7 @@
#include <asm/system.h>
#include <linux/linkage.h>
#include <asm/armv7.h>
#include <system-constants.h>
/*************************************************************************
*
@ -254,7 +255,7 @@ ENTRY(cpu_init_cp15)
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr r0, =(CONFIG_SPL_STACK)
#else
ldr r0, =(CONFIG_SYS_INIT_SP_ADDR)
ldr r0, =(SYS_INIT_SP_ADDR)
#endif
bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
mov sp, r0

1
arch/arm/cpu/pxa/Makefile
View file

@ -5,7 +5,6 @@
extra-y = start.o
obj-$(CONFIG_CPU_PXA25X) += pxa2xx.o
obj-$(CONFIG_CPU_PXA27X) += pxa2xx.o
obj-y += cpuinfo.o

6
arch/arm/cpu/pxa/cpuinfo.c
View file

@ -11,12 +11,6 @@
#include <errno.h>
#include <linux/compiler.h>
#ifdef CONFIG_CPU_PXA25X
#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
#error "Init SP address must be set to 0xfffff800 for PXA250"
#endif
#endif
#define CPU_MASK_PXA_PRODID 0x000003f0
#define CPU_MASK_PXA_REVID 0x0000000f

111
arch/arm/cpu/pxa/start.S
View file

@ -49,9 +49,6 @@ reset:
bl cpu_init_crit
#endif
#ifdef CONFIG_CPU_PXA25X
bl lock_cache_for_stack
#endif
#ifdef CONFIG_CPU_PXA27X
/*
* enable clock for SRAM
@ -67,20 +64,7 @@ reset:
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
#ifdef CONFIG_CPU_PXA25X
/*
* Unlock (actually, disable) the cache now that board_init_f
* is done. We could do this earlier but we would need to add
* a new C runtime hook, whereas c_runtime_cpu_setup already
* exists.
* As this routine is just a call to cpu_init_crit, let us
* tail-optimize and do a simple branch here.
*/
b cpu_init_crit
#else
bx lr
#endif
/*
*************************************************************************
@ -92,7 +76,7 @@ c_runtime_cpu_setup:
*
*************************************************************************
*/
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
cpu_init_crit:
/*
* flush v4 I/D caches
@ -111,95 +95,4 @@ cpu_init_crit:
mcr p15, 0, r0, c1, c0, 0
mov pc, lr /* back to my caller */
#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || CONFIG_CPU_PXA25X */
/*
* Enable MMU to use DCache as DRAM.
*
* This is useful on PXA25x and PXA26x in early bootstages, where there is no
* other possible memory available to hold stack.
*/
#ifdef CONFIG_CPU_PXA25X
.macro CPWAIT reg
mrc p15, 0, \reg, c2, c0, 0
mov \reg, \reg
sub pc, pc, #4
.endm
lock_cache_for_stack:
/* Domain access -- enable for all CPs */
ldr r0, =0x0000ffff
mcr p15, 0, r0, c3, c0, 0
/* Point TTBR to MMU table */
ldr r0, =mmutable
mcr p15, 0, r0, c2, c0, 0
/* Kick in MMU, ICache, DCache, BTB */
mrc p15, 0, r0, c1, c0, 0
bic r0, #0x1b00
bic r0, #0x0087
orr r0, #0x1800
orr r0, #0x0005
mcr p15, 0, r0, c1, c0, 0
CPWAIT r0
/* Unlock Icache, Dcache */
mcr p15, 0, r0, c9, c1, 1
mcr p15, 0, r0, c9, c2, 1
/* Flush Icache, Dcache, BTB */
mcr p15, 0, r0, c7, c7, 0
/* Unlock I-TLB, D-TLB */
mcr p15, 0, r0, c10, c4, 1
mcr p15, 0, r0, c10, c8, 1
/* Flush TLB */
mcr p15, 0, r0, c8, c7, 0
/* Allocate 4096 bytes of Dcache as RAM */
/* Drain pending loads and stores */
mcr p15, 0, r0, c7, c10, 4
mov r4, #0x00
mov r5, #0x00
mov r2, #0x01
mcr p15, 0, r0, c9, c2, 0
CPWAIT r0
/* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
mov r0, #128
ldr r1, =0xfffff000
alloc:
mcr p15, 0, r1, c7, c2, 5
/* Drain pending loads and stores */
mcr p15, 0, r0, c7, c10, 4
strd r4, [r1], #8
strd r4, [r1], #8
strd r4, [r1], #8
strd r4, [r1], #8
subs r0, #0x01
bne alloc
/* Drain pending loads and stores */
mcr p15, 0, r0, c7, c10, 4
mov r2, #0x00
mcr p15, 0, r2, c9, c2, 0
CPWAIT r0
mov pc, lr
.section .mmutable, "a"
mmutable:
.align 14
/* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
.set __base, 0
.rept 0xfff
.word (__base << 20) | 0xc12
.set __base, __base + 1
.endr
/* 0xfff00000 : 1:1, cached mapping */
.word (0xfff << 20) | 0x1c1e
#endif /* CONFIG_CPU_PXA25X */
#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

19
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View file

@ -142,25 +142,6 @@
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
#define TP_INIT_PER_CLUSTER 4
/*
* Define default values for some CCSR macros to make header files cleaner*
*
* To completely disable CCSR relocation in a board header file, define
* CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
* to a value that is the same as CONFIG_SYS_CCSRBAR.
*/
#ifdef CONFIG_SYS_CCSRBAR_PHYS
#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \
CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
#endif
#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
#endif
#ifndef CONFIG_SYS_CCSRBAR
#define CONFIG_SYS_CCSRBAR 0x01000000
#endif

18
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
View file

@ -42,24 +42,6 @@
#define DCFG_DCSR_PORCR1 0
/*
* Define default values for some CCSR macros to make header files cleaner
*
* To completely disable CCSR relocation in a board header file, define
* CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
* to a value that is the same as CONFIG_SYS_CCSRBAR.
*/
#ifdef CONFIG_SYS_CCSRBAR_PHYS
#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly."
#endif
#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
#endif
#ifndef CONFIG_SYS_CCSRBAR
#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR
#endif

1
arch/arm/include/asm/arch-omap4/clock.h
View file

@ -7,7 +7,6 @@
*/
#ifndef _CLOCKS_OMAP4_H_
#define _CLOCKS_OMAP4_H_
#include <asm/omap_common.h>
/*
* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per

1
arch/arm/include/asm/arch-omap5/clock.h
View file

@ -8,7 +8,6 @@
*/
#ifndef _CLOCKS_OMAP5_H_
#define _CLOCKS_OMAP5_H_
#include <asm/omap_common.h>
/*
* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per

2
arch/arm/include/asm/arch-pxa/config.h
View file

@ -13,8 +13,6 @@
*/
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define CONFIG_SYS_TIMER_RATE 3250000
#elif defined(CONFIG_CPU_PXA25X)
#define CONFIG_SYS_TIMER_RATE 3686400
#else
#error "Timer frequency unknown - please config PXA CPU type"
#endif

1
arch/arm/include/asm/config.h
View file

@ -11,7 +11,6 @@
#if defined(CONFIG_ARCH_LS1021A) || \
defined(CONFIG_CPU_PXA27X) || \
defined(CONFIG_CPU_MONAHANS) || \
defined(CONFIG_CPU_PXA25X) || \
defined(CONFIG_FSL_LAYERSCAPE)
#include <asm/arch/config.h>
#endif

1
arch/arm/include/asm/omap_common.h
View file

@ -13,6 +13,7 @@
#include <linux/types.h>
#define NUM_SYS_CLKS 7
#define SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
struct bd_info;

3
arch/arm/lib/crt0.S
View file

@ -9,6 +9,7 @@
#include <asm-offsets.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <system-constants.h>
/*
* This file handles the target-independent stages of the U-Boot
@ -104,7 +105,7 @@ ENTRY(_main)
#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr r0, =(CONFIG_SPL_STACK)
#else
ldr r0, =(CONFIG_SYS_INIT_SP_ADDR)
ldr r0, =(SYS_INIT_SP_ADDR)
#endif
bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
mov sp, r0

3
arch/arm/lib/crt0_64.S
View file

@ -13,6 +13,7 @@
#include <asm-offsets.h>
#include <asm/macro.h>
#include <linux/linkage.h>
#include <system-constants.h>
/*
* This file handles the target-independent stages of the U-Boot
@ -81,7 +82,7 @@ ENTRY(_main)
#endif
add x0, x0, #CONFIG_SYS_INIT_SP_BSS_OFFSET
#else
ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
ldr x0, =(SYS_INIT_SP_ADDR)
#endif
bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
mov x0, sp

3
arch/arm/lib/vectors_m.S
View file

@ -7,6 +7,7 @@
#include <config.h>
#include <asm/assembler.h>
#include <linux/linkage.h>
#include <system-constants.h>
.type __hard_fault_entry, %function
__hard_fault_entry:
@ -35,7 +36,7 @@ __invalid_entry:
.section .vectors
ENTRY(_start)
.long CONFIG_SYS_INIT_SP_ADDR @ 0 - Reset stack pointer
.long SYS_INIT_SP_ADDR @ 0 - Reset stack pointer
.long reset @ 1 - Reset
.long __invalid_entry @ 2 - NMI
.long __hard_fault_entry @ 3 - HardFault

3
arch/arm/mach-kirkwood/include/mach/config.h
View file

@ -27,9 +27,6 @@
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
/* Kirkwood has 2k of Security SRAM, use it for SP */
#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
#define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE
#define MV_UART_CONSOLE_BASE KW_UART0_BASE
#define MV_SATA_BASE KW_SATA_BASE

10
arch/arm/mach-mvebu/Makefile
View file

@ -65,10 +65,12 @@ KWB_REPLACE += CSK_INDEX
KWB_CFG_CSK_INDEX = $(CONFIG_SECURED_MODE_CSK_INDEX)
KWB_REPLACE += SEC_BOOT_DEV
KWB_CFG_SEC_BOOT_DEV=$(patsubst "%",%, \
$(if $(findstring BOOT_SPI_NOR_FLASH,$(CONFIG_SPL_BOOT_DEVICE)),0x34) \
$(if $(findstring BOOT_SDIO_MMC_CARD,$(CONFIG_SPL_BOOT_DEVICE)),0x31) \
)
ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI),)
KWB_CFG_SEC_BOOT_DEV=0x34
endif
ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC),)
KWB_CFG_SEC_BOOT_DEV=0x31
endif
KWB_REPLACE += SEC_FUSE_DUMP
KWB_CFG_SEC_FUSE_DUMP = a38x

3
arch/arm/mach-mvebu/include/mach/config.h
View file

@ -27,9 +27,6 @@
#define CONFIG_SYS_L2_PL310
/* end of 16M scrubbed by training in bootrom */
#define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000
#define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE
/* Needed for SPI NOR booting in SPL */

8
arch/arm/mach-mvebu/lowlevel_spl.S
View file

@ -8,19 +8,19 @@
* contains U-Boot SPL, optionally it can also contain additional arguments.
* The number of these arguments is in r0, pointer to the argument array in r1.
* BootROM expects executable BIN header code to return to address stored in lr.
* Other registers (r2 - r12) must be preserved. We save all registers to
* CONFIG_SPL_BOOTROM_SAVE address. BIN header arguments (passed via r0 and r1)
* Other registers (r2 - r12) must be preserved. We save all registers to the
* address of CONFIG_SPL_STACK + 4. BIN header arguments (passed via r0 and r1)
* are currently not used by U-Boot SPL binary.
*/
ENTRY(save_boot_params)
stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */
ldr r12, =CONFIG_SPL_BOOTROM_SAVE
ldr r12, =(CONFIG_SPL_STACK + 4)
str sp, [r12]
b save_boot_params_ret
ENDPROC(save_boot_params)
ENTRY(return_to_bootrom)
ldr r12, =CONFIG_SPL_BOOTROM_SAVE
ldr r12, =(CONFIG_SPL_STACK + 4)
ldr sp, [r12]
ldmfd sp!, {r0 - r12, lr} /* @ restore registers from stack */
mov r0, #0x0 /* @ return value: 0x0 NO_ERR */

2
arch/arm/mach-mvebu/spl.c
View file

@ -283,7 +283,7 @@ u32 spl_boot_device(void)
int board_return_to_bootrom(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
u32 *regs = *(u32 **)CONFIG_SPL_BOOTROM_SAVE;
u32 *regs = *(u32 **)(CONFIG_SPL_STACK + 4);
printf("Returning to BootROM (return address 0x%08x)...\n", regs[13]);
return_to_bootrom();

1
arch/arm/mach-omap2/sata.c
View file

@ -13,6 +13,7 @@
#include <asm/arch/sata.h>
#include <sata.h>
#include <asm/io.h>
#include <asm/omap_common.h>
#include "pipe3-phy.h"
static struct pipe3_dpll_map dpll_map_sata[] = {

5
arch/arm/mach-omap2/timer.c
View file

@ -22,6 +22,7 @@
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <asm/omap_common.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
@ -33,7 +34,7 @@ static ulong get_timer_masked(void);
* Nothing really to do with interrupts, just starts up a counter.
*/
#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV))
#define TIMER_CLOCK (V_SCLK / (2 << SYS_PTV))
#define TIMER_OVERFLOW_VAL 0xffffffff
#define TIMER_LOAD_VAL 0
@ -42,7 +43,7 @@ int timer_init(void)
/* start the counter ticking up, reload value on overflow */
writel(TIMER_LOAD_VAL, &timer_base->tldr);
/* enable timer */
writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
writel((SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
&timer_base->tclr);
return 0;

1
arch/arm/mach-rmobile/lowlevel_init.S
View file

@ -6,6 +6,7 @@
#include <config.h>
#include <linux/linkage.h>
#include <system-constants.h>
ENTRY(lowlevel_init)
ldr r0, =MERAM_BASE

3
arch/arm/mach-rmobile/lowlevel_init_ca15.S
View file

@ -8,6 +8,7 @@
#include <config.h>
#include <linux/linkage.h>
#include <system-constants.h>
ENTRY(lowlevel_init)
#ifndef CONFIG_SPL_BUILD
@ -75,7 +76,7 @@ _enable_actlr_smp: /* R8A7794 only (CA7) */
#endif
_exit_init_l2_a15:
ldr r3, =(CONFIG_SYS_INIT_SP_ADDR)
ldr r3, =(SYS_INIT_SP_ADDR)
sub sp, r3, #4
str lr, [sp]

3
arch/arm/mach-rockchip/px30/Kconfig
View file

@ -56,9 +56,6 @@ config TPL_LDSCRIPT
config TPL_TEXT_BASE
default 0xff0e1000
config TPL_MAX_SIZE
default 10240
config TPL_STACK
default 0xff0e4fff

3
arch/arm/mach-rockchip/rk322x/Kconfig
View file

@ -26,9 +26,6 @@ config SPL_LIBGENERIC_SUPPORT
config SPL_SERIAL
default y
config TPL_MAX_SIZE
default 28672
config TPL_STACK
default 0x10088000

3
arch/arm/mach-rockchip/rk3288/Kconfig
View file

@ -172,9 +172,6 @@ config SPL_SERIAL
config TPL_LDSCRIPT
default "arch/arm/mach-rockchip/u-boot-tpl.lds"
config TPL_MAX_SIZE
default 32768
config TPL_STACK
default 0xff718000

3
arch/arm/mach-rockchip/rk3328/Kconfig
View file

@ -36,9 +36,6 @@ config TPL_LDSCRIPT
config TPL_TEXT_BASE
default 0xff091000
config TPL_MAX_SIZE
default 28672
config TPL_STACK
default 0xff098000

3
arch/arm/mach-rockchip/rk3368/Kconfig
View file

@ -71,9 +71,6 @@ config SPL_LDSCRIPT
config SPL_STACK_R_ADDR
default 0x04000000
config TPL_MAX_SIZE
default 28672
config TPL_STACK
default 0xff8cffff

3
arch/arm/mach-rockchip/rk3399/Kconfig
View file

@ -143,9 +143,6 @@ config SPL_LIBGENERIC_SUPPORT
config TPL_LDSCRIPT
default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
config TPL_MAX_SIZE
default 188416
config TPL_STACK
default 0xff8effff

3
arch/arm/mach-uniphier/arm32/late_lowlevel_init.S
View file

@ -6,8 +6,9 @@
#include <config.h>
#include <linux/linkage.h>
#include <system-constants.h>
ENTRY(lowlevel_init)
ldr sp, = CONFIG_SYS_INIT_SP_ADDR
ldr sp, = SYS_INIT_SP_ADDR
b uniphier_cache_disable
ENDPROC(lowlevel_init)

6
arch/m68k/Kconfig
View file

@ -53,12 +53,6 @@ config MCF5441x
select DM_SERIAL
bool
config MCF5227x
select OF_CONTROL
select DM
select DM_SERIAL
bool
# processor type
config M5208
bool

9
arch/m68k/cpu/mcf5227x/Makefile
View file

@ -1,9 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# ccflags-y += -DET_DEBUG
extra-y = start.o
obj-y = cpu.o speed.o cpu_init.o interrupts.o dspi.o

67
arch/m68k/cpu/mcf5227x/cpu.c
View file

@ -1,67 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#include <common.h>
#include <init.h>
#include <vsprintf.h>
#include <watchdog.h>
#include <command.h>
#include <asm/global_data.h>
#include <linux/delay.h>
#include <asm/immap.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);
setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
/* we don't return! */
return 0;
};
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
u16 id = 0;
u8 ver;
puts("CPU: ");
msk = (in_be16(&ccm->cir) >> 6);
ver = (in_be16(&ccm->cir) & 0x003f);
switch (msk) {
case 0x6c:
id = 52277;
break;
}
if (id) {
char buf1[32], buf2[32], buf3[32];
printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
ver);
printf(" CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
strmhz(buf1, gd->cpu_clk),
strmhz(buf2, gd->bus_clk),
strmhz(buf3, gd->arch.flb_clk));
printf(" INP CLK %s MHz VCO CLK %s MHz\n",
strmhz(buf1, gd->arch.inp_clk),
strmhz(buf2, gd->arch.vco_clk));
}
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */

152
arch/m68k/cpu/mcf5227x/cpu_init.c
View file

@ -1,152 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <watchdog.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <asm/rtc.h>
#include <linux/compiler.h>
void cfspi_port_conf(void)
{
gpio_t *gpio = (gpio_t *)MMAP_GPIO;
out_8(&gpio->par_dspi,
GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
GPIO_PAR_DSPI_SCK_SCK);
}
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f(void)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
#if !defined(CONFIG_CF_SBF)
scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
pll_t *pll = (pll_t *)MMAP_PLL;
/* Workaround, must place before fbcs */
out_be32(&pll->psr, 0x12);
out_be32(&scm1->mpr, 0x77777777);
out_be32(&scm1->pacra, 0);
out_be32(&scm1->pacrb, 0);
out_be32(&scm1->pacrc, 0);
out_be32(&scm1->pacrd, 0);
out_be32(&scm1->pacre, 0);
out_be32(&scm1->pacrf, 0);
out_be32(&scm1->pacrg, 0);
out_be32(&scm1->pacri, 0);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
&& defined(CONFIG_SYS_CS0_CTRL))
out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif
#endif /* CONFIG_CF_SBF */
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
&& defined(CONFIG_SYS_CS1_CTRL))
out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
&& defined(CONFIG_SYS_CS2_CTRL))
out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
&& defined(CONFIG_SYS_CS3_CTRL))
out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
&& defined(CONFIG_SYS_CS5_CTRL))
out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
#ifdef CONFIG_SYS_I2C_FSL
out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA);
#endif
icache_enable();
cfspi_port_conf();
}
/*
* initialize higher level parts of CPU like timers
*/
int cpu_init_r(void)
{
#ifdef CONFIG_MCFRTC
rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
#endif
return (0);
}
void uart_port_conf(int port)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (port) {
case 0:
clrbits_be16(&gpio->par_uart,
~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK));
setbits_be16(&gpio->par_uart,
GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
break;
case 1:
clrbits_be16(&gpio->par_uart,
~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK));
setbits_be16(&gpio->par_uart,
GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
break;
case 2:
clrbits_8(&gpio->par_dspi,
~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK));
out_8(&gpio->par_dspi,
GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
break;
}
}

43
arch/m68k/cpu/mcf5227x/dspi.c
View file

@ -1,43 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019
* Angelo Dureghello <angleo@sysam.it>
*
* CPU specific dspi routines
*/
#include <common.h>
#include <asm/immap.h>
#include <asm/io.h>
#ifdef CONFIG_CF_DSPI
void dspi_chip_select(int cs)
{
struct gpio *gpio = (struct gpio *)MMAP_GPIO;
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 2:
clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
break;
}
}
void dspi_chip_unselect(int cs)
{
struct gpio *gpio = (struct gpio *)MMAP_GPIO;
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 2:
clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
break;
}
}
#endif /* CONFIG_CF_DSPI */

37
arch/m68k/cpu/mcf5227x/interrupts.c
View file

@ -1,37 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
/* CPU specific interrupt routine */
#include <common.h>
#include <irq_func.h>
#include <asm/immap.h>
#include <asm/io.h>
int interrupt_init(void)
{
int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
setbits_be32(&intp->imrh0, 0xffffffff);
setbits_be32(&intp->imrl0, 0xffffffff);
enable_interrupts();
return 0;
}
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
}
#endif

127
arch/m68k/cpu/mcf5227x/speed.c
View file

@ -1,127 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
*
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#include <common.h>
#include <clock_legacy.h>
#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/immap.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Low Power Divider specifications
*/
#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
#define CLOCK_PLL_FVCO_MAX 540000000
#define CLOCK_PLL_FVCO_MIN 300000000
#define CLOCK_PLL_FSYS_MAX 266666666
#define CLOCK_PLL_FSYS_MIN 100000000
#define MHZ 1000000
void clock_enter_limp(int lpdiv)
{
ccm_t *ccm = (ccm_t *)MMAP_CCM;
int i, j;
/* Check bounds of divider */
if (lpdiv < CLOCK_LPD_MIN)
lpdiv = CLOCK_LPD_MIN;
if (lpdiv > CLOCK_LPD_MAX)
lpdiv = CLOCK_LPD_MAX;
/* Round divider down to nearest power of two */
for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
/* Apply the divider to the system clock */
clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
/* Enable Limp Mode */
setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
}
/*
* brief Exit Limp mode
* warning The PLL should be set and locked prior to exiting Limp mode
*/
void clock_exit_limp(void)
{
ccm_t *ccm = (ccm_t *)MMAP_CCM;
pll_t *pll = (pll_t *)MMAP_PLL;
/* Exit Limp mode */
clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
/* Wait for the PLL to lock */
while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
;
}
/*
* get_clocks() fills in gd->cpu_clock and gd->bus_clk
*/
int get_clocks(void)
{
ccm_t *ccm = (ccm_t *)MMAP_CCM;
pll_t *pll = (pll_t *)MMAP_PLL;
int vco, temp, pcrvalue, pfdr;
u8 bootmode;
pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF;
pfdr = pcrvalue >> 24;
if (pfdr == 0x1E)
bootmode = 0; /* Normal Mode */
#ifdef CONFIG_CF_SBF
bootmode = 3; /* Serial Mode */
#endif
if (bootmode == 0) {
/* Normal mode */
vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
/* Default value */
pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
pcrvalue |= 0x1E << 24;
out_be32(&pll->pcr, pcrvalue);
vco =
((in_be32(&pll->pcr) & 0xFF000000) >> 24) *
CONFIG_SYS_INPUT_CLKSRC;
}
gd->arch.vco_clk = vco; /* Vco clock */
} else if (bootmode == 3) {
/* serial mode */
vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
gd->arch.vco_clk = vco; /* Vco clock */
}
if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
/* Limp mode */
} else {
gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
gd->cpu_clk = vco / temp; /* cpu clock */
temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
gd->arch.flb_clk = vco / temp; /* flexbus clock */
gd->bus_clk = gd->arch.flb_clk;
}
#ifdef CONFIG_SYS_I2C_FSL
gd->arch.i2c1_clk = gd->bus_clk;
#endif
return (0);
}

491
arch/m68k/cpu/mcf5227x/start.S
View file

@ -1,491 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
*/
#include <asm-offsets.h>
#include <config.h>
#include <asm/cache.h>
#define _START _start
#define _FAULT _fault
#define SAVE_ALL \
move.w #0x2700,%sr; /* disable intrs */ \
subl #60,%sp; /* space for 15 regs */ \
moveml %d0-%d7/%a0-%a6,%sp@;
#define RESTORE_ALL \
moveml %sp@,%d0-%d7/%a0-%a6; \
addl #60,%sp; /* space for 15 regs */ \
rte;
#if defined(CONFIG_CF_SBF)
#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + \
CONFIG_SYS_INIT_RAM_ADDR)
#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + \
CONFIG_SYS_INIT_RAM_ADDR)
#endif
.text
/*
* Vector table. This is used for initial platform startup.
* These vectors are to catch any un-intended traps.
*/
_vectors:
#if defined(CONFIG_CF_SBF)
INITSP: .long 0 /* Initial SP */
INITPC: .long ASM_DRAMINIT /* Initial PC */
#else
INITSP: .long 0 /* Initial SP */
INITPC: .long _START /* Initial PC */
#endif
vector02_0F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
/* Reserved */
vector10_17:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector18_1F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
#if !defined(CONFIG_CF_SBF)
/* TRAP #0 - #15 */
vector20_2F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
/* Reserved */
vector30_3F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector64_127:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector128_191:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector192_255:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
#endif
#if defined(CONFIG_CF_SBF)
/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
asm_sbf_img_hdr:
.long 0x00000000 /* checksum, not yet implemented */
.long 0x00020000 /* image length */
.long CONFIG_SYS_TEXT_BASE /* image to be relocated at */
asm_dram_init:
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1 /* init Rambar */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
/* Must disable global address */
move.l #0xFC008000, %a1
move.l #(CONFIG_SYS_CS0_BASE), (%a1)
move.l #0xFC008008, %a1
move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
move.l #0xFC008004, %a1
move.l #(CONFIG_SYS_CS0_MASK), (%a1)
/*
* Dram Initialization
* a1, a2, and d0
*/
move.l #0xFC0A4074, %a1
move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
nop
/* SDRAM Chip 0 and 1 */
move.l #0xFC0B8110, %a1
move.l #0xFC0B8114, %a2
/* calculate the size */
move.l #0x13, %d1
move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
#ifdef CONFIG_SYS_SDRAM_BASE1
lsr.l #1, %d2
#endif
dramsz_loop:
lsr.l #1, %d2
add.l #1, %d1
cmp.l #1, %d2
bne dramsz_loop
/* SDRAM Chip 0 and 1 */
move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
or.l %d1, (%a1)
#ifdef CONFIG_SYS_SDRAM_BASE1
move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
or.l %d1, (%a2)
#endif
nop
/* dram cfg1 and cfg2 */
move.l #0xFC0B8008, %a1
move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
nop
move.l #0xFC0B800C, %a2
move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
nop
move.l #0xFC0B8000, %a1 /* Mode */
move.l #0xFC0B8004, %a2 /* Ctrl */
/* Issue PALL */
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
nop
/* Issue LEMR */
move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
nop
move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
nop
move.l #1000, %d0
wait1000:
nop
subq.l #1, %d0
bne wait1000
/* Issue PALL */
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
nop
/* Perform two refresh cycles */
move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
nop
move.l %d0, (%a2)
move.l %d0, (%a2)
nop
move.l #(CONFIG_SYS_SDRAM_CTRL), %d0
and.l #0x7FFFFFFF, %d0
or.l #0x10000c00, %d0
move.l %d0, (%a2)
nop
/*
* DSPI Initialization
* a0 - general, sram - 0x80008000 - 32, see M52277EVB.h
* a1 - dspi status
* a2 - dtfr
* a3 - drfr
* a4 - Dst addr
*/
/* Enable pins for DSPI mode - chip-selects are enabled later */
move.l #0xFC0A4036, %a0
move.b #0x3F, %d0
move.b %d0, (%a0)
/* DSPI CS */
#ifdef CONFIG_SYS_DSPI_CS0
move.b (%a0), %d0
or.l #0xC0, %d0
move.b %d0, (%a0)
#endif
#ifdef CONFIG_SYS_DSPI_CS2
move.l #0xFC0A4037, %a0
move.b (%a0), %d0
or.l #0x10, %d0
move.b %d0, (%a0)
#endif
nop
/* Configure DSPI module */
move.l #0xFC05C000, %a0
move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
move.l #0xFC05C00C, %a0
move.l #0x3E000011, (%a0)
move.l #0xFC05C034, %a2 /* dtfr */
move.l #0xFC05C03B, %a3 /* drfr */
move.l #(ASM_SBF_IMG_HDR + 4), %a1
move.l (%a1)+, %d5
move.l (%a1), %a4
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
move.l #0xFC05C02C, %a1 /* dspi status */
/* Issue commands and address */
move.l #0x8004000B, %d2 /* Fast Read Cmd */
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
move.l #0x80040000, %d2 /* Address byte 2 */
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
move.l #0x80040000, %d2 /* Address byte 1 */
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
move.l #0x80040000, %d2 /* Address byte 0 */
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
move.l #0x80040000, %d2 /* Dummy Wr and Rd */
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
/* Transfer serial boot header to sram */
asm_dspi_rd_loop1:
move.l #0x80040000, %d2
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
move.b %d1, (%a0) /* read, copy to dst */
add.l #1, %a0 /* inc dst by 1 */
sub.l #1, %d4 /* dec cnt by 1 */
bne asm_dspi_rd_loop1
/* Transfer u-boot from serial flash to memory */
asm_dspi_rd_loop2:
move.l #0x80040000, %d2
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
move.b %d1, (%a4) /* read, copy to dst */
add.l #1, %a4 /* inc dst by 1 */
sub.l #1, %d5 /* dec cnt by 1 */
bne asm_dspi_rd_loop2
move.l #0x00040000, %d2 /* Terminate */
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
/* jump to memory and execute */
move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
move.l %a0, (%a1)
jmp (%a0)
asm_dspi_wr_status:
move.l (%a1), %d0 /* status */
and.l #0x0000F000, %d0
cmp.l #0x00003000, %d0
bgt asm_dspi_wr_status
move.l %d2, (%a2)
rts
asm_dspi_rd_status:
move.l (%a1), %d0 /* status */
and.l #0x000000F0, %d0
lsr.l #4, %d0
cmp.l #0, %d0
beq asm_dspi_rd_status
move.b (%a3), %d1
rts
#endif /* CONFIG_CF_SBF */
.text
. = 0x400
.globl _start
_start:
nop
nop
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
#if defined(CONFIG_CF_SBF)
move.l #CONFIG_SYS_TEXT_BASE, %d0
movec %d0, %VBR
#else
move.l #CONFIG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
#endif
/* invalidate and disable cache */
move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #0, %d0
movec %d0, %ACR0
movec %d0, %ACR1
/* initialize general use internal ram */
move.l #0, %d0
move.l #(ICACHE_STATUS), %a1 /* icache */
move.l #(DCACHE_STATUS), %a2 /* icache */
move.l %d0, (%a1)
move.l %d0, (%a2)
/* put relocation table address to a5 */
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
* then (and always) gd struct space will be reserved
*/
move.l %sp, -(%sp)
bsr board_init_f_alloc_reserve
/* update stack and frame-pointers */
move.l %d0, %sp
move.l %sp, %fp
/* initialize reserved area */
move.l %d0, -(%sp)
bsr board_init_f_init_reserve
/* run low-level CPU init code (from flash) */
bsr cpu_init_f
clr.l %sp@-
/* run low-level board init code (from flash) */
move.l #board_init_f, %a1
jsr (%a1)
/* board_init_f() does not return */
/******************************************************************************/
/*
* void relocate_code(addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r3 = dest
* r4 = src
* r5 = length in bytes
* r6 = cachelinesize
*/
.globl relocate_code
relocate_code:
link.w %a6,#0
move.l 8(%a6), %sp /* set new stack pointer */
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
move.l 16(%a6), %a0 /* Save copy of Destination Address */
move.l #CONFIG_SYS_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
/* copy the code to RAM */
1:
move.l (%a1)+, (%a3)+
cmp.l %a1,%a2
bgt.s 1b
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
move.l %a0, %a1
add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
clear_bss:
/*
* Now clear BSS segment
*/
move.l %a0, %a1
add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a0, %d1
add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
bgt.s 6b
/*
* fix got table in RAM
*/
move.l %a0, %a1
add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a1,%a5 /* fix got pointer register a5 */
move.l %a0, %a2
add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
7:
move.l (%a1),%d1
sub.l #_start,%d1
add.l %a0,%d1
move.l %d1,(%a1)+
cmp.l %a2, %a1
bne 7b
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
jsr (%a1)
/******************************************************************************/
/* exception code */
.globl _fault
_fault:
bra _fault
.globl _exc_handler
_exc_handler:
SAVE_ALL
movel %sp,%sp@-
bsr exc_handler
addql #4,%sp
RESTORE_ALL
.globl _int_handler
_int_handler:
SAVE_ALL
movel %sp,%sp@-
bsr int_handler
addql #4,%sp
RESTORE_ALL
/******************************************************************************/
.align 4

2
arch/microblaze/cpu/start.S
View file

@ -19,7 +19,7 @@ _start:
mts rslr, r8
#if defined(CONFIG_SPL_BUILD)
addi r1, r0, CONFIG_SPL_STACK_ADDR
addi r1, r0, CONFIG_SPL_STACK
#else
addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
#endif

4
arch/mips/Makefile
View file

@ -3,9 +3,7 @@
head-y := arch/mips/cpu/start.o
ifeq ($(CONFIG_SPL_BUILD),y)
ifneq ($(CONFIG_SPL_START_S_PATH),)
head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o
endif
head-$(CONFIG_ARCH_JZ47XX) := arch/mips/mach-jz47xx/start.o
endif
libs-y += arch/mips/cpu/

8
arch/mips/cpu/start.S
View file

@ -10,11 +10,7 @@
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#ifndef CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_SP_OFFSET)
#endif
#include <system-constants.h>
#ifdef CONFIG_32BIT
# define STATUS_SET 0
@ -44,7 +40,7 @@
.macro setup_stack_gd
li t0, -16
PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
PTR_LI t1, SYS_INIT_SP_ADDR
and sp, t1, t0 # force 16 byte alignment
PTR_SUBU \
sp, sp, GD_SIZE # reserve space for gd

11
arch/mips/mach-mtmips/mt7628/lowlevel_init.S
View file

@ -12,16 +12,11 @@
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/asm.h>
#include <system-constants.h>
#include "mt7628.h"
/* Set temporary stack address range */
#ifndef CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_SP_OFFSET)
#endif
#define CACHE_STACK_SIZE 0x4000
#define CACHE_STACK_BASE (CONFIG_SYS_INIT_SP_ADDR - CACHE_STACK_SIZE)
#define CACHE_STACK_BASE (SYS_INIT_SP_ADDR - CACHE_STACK_SIZE)
#define DELAY_USEC(us) ((58 * (us)) / 3)
@ -134,7 +129,7 @@ NESTED(lowlevel_init, 0, ra)
#if CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
/* Set malloc base */
li t0, (CONFIG_SYS_INIT_SP_ADDR + 15) & (~15)
li t0, (SYS_INIT_SP_ADDR + 15) & (~15)
PTR_S t0, GD_MALLOC_BASE(k0) # gd->malloc_base offset
#endif

2
arch/powerpc/cpu/mpc83xx/Makefile
View file

@ -8,10 +8,12 @@
MINIMAL=
ifdef CONFIG_SPL_BUILD
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
endif
extra-y = start.o

3
arch/powerpc/cpu/mpc83xx/cpu_init.c
View file

@ -6,6 +6,7 @@
#include <common.h>
#include <asm-offsets.h>
#include <mpc83xx.h>
#include <system-constants.h>
#include <ioports.h>
#include <asm/global_data.h>
#include <asm/io.h>
@ -138,7 +139,7 @@ void cpu_init_f (volatile immap_t * im)
0;
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
gd = (gd_t *)SYS_INIT_SP_ADDR;
/* global data region was cleared in start.S */

3
arch/powerpc/cpu/mpc83xx/spl_minimal.c
View file

@ -7,6 +7,7 @@
#include <asm-offsets.h>
#include <clock_legacy.h>
#include <mpc83xx.h>
#include <system-constants.h>
#include <time.h>
#include <asm/global_data.h>
@ -25,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;
void cpu_init_f (volatile immap_t * im)
{
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
gd = (gd_t *)SYS_INIT_SP_ADDR;
/* global data region was cleared in start.S */

7
arch/powerpc/cpu/mpc83xx/start.S
View file

@ -13,6 +13,7 @@
#include <asm-offsets.h>
#include <config.h>
#include <mpc83xx.h>
#include <system-constants.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
@ -39,7 +40,7 @@
#endif
#if defined(CONFIG_NAND_SPL) || \
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
(defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL))
#define MINIMAL_SPL
#endif
@ -229,8 +230,8 @@ in_flash:
/* set up the stack pointer in our newly created
* cache-ram; use r3 to keep the new SP for now to
* avoid overiding the SP it uselessly */
lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
lis r3, SYS_INIT_SP_ADDR@h
ori r3, r3, SYS_INIT_SP_ADDR@l
/* r4 = end of GD area */
addi r4, r3, GENERATED_GBL_DATA_SIZE

2
arch/powerpc/cpu/mpc85xx/Makefile
View file

@ -9,10 +9,12 @@
MINIMAL=
ifdef CONFIG_SPL_BUILD
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
endif
extra-y = start.o resetvec.o

5
arch/powerpc/cpu/mpc85xx/cpu_init_early.c
View file

@ -4,6 +4,7 @@
*/
#include <common.h>
#include <system-constants.h>
#include <asm-offsets.h>
#include <asm/global_data.h>
#include <asm/processor.h>
@ -94,7 +95,7 @@ void cpu_init_early_f(void *fdt)
#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
gd = (gd_t *)SYS_INIT_SP_ADDR;
/* gd area was zeroed during startup */
@ -177,7 +178,7 @@ void cpu_init_early_f(void *fdt)
invalidate_tlb(1);
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \
!(defined(CONFIG_SPL_INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \
!(CONFIG_IS_ENABLED(INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \
!defined(CONFIG_NAND_SPL)
disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB);
#endif

7
arch/powerpc/cpu/mpc85xx/start.S
View file

@ -14,6 +14,7 @@
#include <asm-offsets.h>
#include <config.h>
#include <mpc85xx.h>
#include <system-constants.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
@ -27,7 +28,7 @@
#define LAW_EN 0x80000000
#if defined(CONFIG_NAND_SPL) || \
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
(defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL))
#define MINIMAL_SPL
#endif
@ -1160,8 +1161,8 @@ _start_cont:
bne 1b
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
lis r4,SYS_INIT_SP_ADDR@h
ori r4,r4,SYS_INIT_SP_ADDR@l
addi r3,r3,16 /* Pre-relocation malloc area */
stw r3,GD_MALLOC_BASE(r4)

2
arch/powerpc/cpu/mpc85xx/tlb.c
View file

@ -44,7 +44,7 @@ __weak void init_tlbs(void)
}
#if !defined(CONFIG_NAND_SPL) && \
(!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
(!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL))
void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
phys_addr_t *rpn)
{

2
arch/powerpc/cpu/mpc8xxx/Makefile
View file

@ -5,10 +5,12 @@
MINIMAL=
ifdef CONFIG_SPL_BUILD
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
endif
ifdef MINIMAL

4
arch/powerpc/cpu/mpc8xxx/law.c
View file

@ -79,7 +79,7 @@ void disable_law(u8 idx)
}
#if !defined(CONFIG_NAND_SPL) && \
(!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
(!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL))
static int get_law_entry(u8 i, struct law_entry *e)
{
u32 lawar;
@ -110,7 +110,7 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
}
#if !defined(CONFIG_NAND_SPL) && \
(!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
(!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL))
int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
u32 idx;

2
arch/powerpc/lib/Makefile
View file

@ -10,10 +10,12 @@ lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _lshrdi3.o
MINIMAL=
ifdef CONFIG_SPL_BUILD
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
endif
obj-y += bdinfo.o

3
arch/riscv/cpu/start.S
View file

@ -13,6 +13,7 @@
#include <config.h>
#include <common.h>
#include <elf.h>
#include <system-constants.h>
#include <asm/encoding.h>
#include <generated/asm-offsets.h>
@ -94,7 +95,7 @@ call_board_init_f:
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
li t1, CONFIG_SPL_STACK
#else
li t1, CONFIG_SYS_INIT_SP_ADDR
li t1, SYS_INIT_SP_ADDR
#endif
and sp, t1, t0 /* force 16 byte alignment */

2
arch/sandbox/include/asm/spl.h
View file

@ -6,8 +6,6 @@
#ifndef __asm_spl_h
#define __asm_spl_h
#define CONFIG_SPL_BOARD_LOAD_IMAGE
enum {
BOOT_DEVICE_BOARD,
};

2
arch/x86/include/asm/spl.h
View file

@ -7,8 +7,6 @@
#ifndef __asm_spl_h
#define __asm_spl_h
#define CONFIG_SPL_BOARD_LOAD_IMAGE
enum {
BOOT_DEVICE_SPI_MMAP = 10,
BOOT_DEVICE_FAST_SPI,

4
board/AndesTech/ax25-ae350/Kconfig
View file

@ -27,6 +27,10 @@ config SPL_TEXT_BASE
config SPL_OPENSBI_LOAD_ADDR
default 0x01000000
config SYS_FDT_BASE
hex
default 0x800f0000 if OF_SEPARATE
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select RISCV_NDS

2
board/congatec/common/Makefile
View file

@ -8,10 +8,12 @@
MINIMAL=
ifdef CONFIG_SPL_BUILD
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
endif
ifdef MINIMAL
# necessary to create built-in.o

2
board/davinci/da8xxevm/u-boot-spl-da850evm.lds
View file

@ -11,7 +11,7 @@ MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
LENGTH = 0x1080000 }
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)

2
board/freescale/common/Makefile
View file

@ -6,10 +6,12 @@
MINIMAL=
ifdef CONFIG_SPL_BUILD
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
endif
ifdef MINIMAL
# necessary to create built-in.o

2
board/freescale/p1010rdb/Makefile
View file

@ -5,10 +5,12 @@
MINIMAL=
ifdef CONFIG_SPL_BUILD
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
endif
ifdef MINIMAL
obj-y += spl_minimal.o

10
board/freescale/p1010rdb/spl.c
View file

@ -57,24 +57,24 @@ void board_init_f(ulong bootflag)
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
*/
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
relocate_code(CONFIG_VAL(RELOC_STACK), 0, CONFIG_SPL_RELOC_TEXT_BASE);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *)CONFIG_SPL_GD_ADDR;
gd = (gd_t *)CONFIG_VAL(GD_ADDR);
struct bd_info *bd;
memset(gd, 0, sizeof(gd_t));
bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
bd = (struct bd_info *)(CONFIG_VAL(GD_ADDR) + sizeof(gd_t));
memset(bd, 0, sizeof(struct bd_info));
gd->bd = bd;
arch_cpu_init();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
mem_malloc_init(CONFIG_VAL(RELOC_MALLOC_ADDR),
CONFIG_VAL(RELOC_MALLOC_SIZE));
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifndef CONFIG_SPL_NAND_BOOT

3
board/freescale/p1010rdb/tlb.c
View file

@ -72,8 +72,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),
#if defined(CONFIG_SYS_RAMBOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),

2
board/freescale/p1_p2_rdb_pc/Makefile
View file

@ -5,10 +5,12 @@
MINIMAL=
ifdef CONFIG_SPL_BUILD
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
endif
ifdef MINIMAL
obj-y += spl_minimal.o

10
board/freescale/p1_p2_rdb_pc/spl.c
View file

@ -63,24 +63,24 @@ void board_init_f(ulong bootflag)
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
*/
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
relocate_code(CONFIG_VAL(RELOC_STACK), 0, CONFIG_SPL_RELOC_TEXT_BASE);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *)CONFIG_SPL_GD_ADDR;
gd = (gd_t *)CONFIG_VAL(GD_ADDR);
struct bd_info *bd;
memset(gd, 0, sizeof(gd_t));
bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
bd = (struct bd_info *)(CONFIG_VAL(GD_ADDR) + sizeof(gd_t));
memset(bd, 0, sizeof(struct bd_info));
gd->bd = bd;
arch_cpu_init();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
mem_malloc_init(CONFIG_VAL(RELOC_MALLOC_ADDR),
CONFIG_VAL(RELOC_MALLOC_SIZE));
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifdef CONFIG_SPL_ENV_SUPPORT

3
board/freescale/p1_p2_rdb_pc/tlb.c
View file

@ -77,8 +77,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 7, BOOKE_PAGESZ_1M, 1),
#endif
#if defined(CONFIG_SYS_RAMBOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
/* **M** - 1G DDR for eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,

3
board/keymile/Kconfig
View file

@ -11,6 +11,9 @@ if VENDOR_KM
menu "KM Board Setup"
config HUSH_INIT_VAR
def_bool y
config KM_PNVRAM
hex "Pseudo RAM"
default 0x80000

1
board/synopsys/iot_devkit/u-boot.lds
View file

@ -5,6 +5,7 @@
*/
#include <config.h>
#include <system-constants.h>
MEMORY {
ROM : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE

6
boot/image-board.c
View file

@ -21,10 +21,6 @@
#include <asm/cache.h>
#include <asm/global_data.h>
#ifndef CONFIG_SYS_BARGSIZE
#define CONFIG_SYS_BARGSIZE 512
#endif
DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
@ -827,6 +823,7 @@ int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images,
return 0;
}
#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
/**
* boot_get_cmdline - allocate and initialize kernel cmdline
* @lmb: pointer to lmb handle, will be used for memory mgmt
@ -900,6 +897,7 @@ int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd)
return 0;
}
#endif
int image_setup_linux(bootm_headers_t *images)
{

17
cmd/Kconfig
View file

@ -71,6 +71,23 @@ config SYS_PROMPT_HUSH_PS2
printed when the command interpreter needs more input
to complete a command. Usually "> ".
config SYS_MAXARGS
int "Maximum number arguments accepted by commands"
default 16
config SYS_CBSIZE
int "Console input buffer size"
default 2048 if ARCH_TEGRA || ARCH_VERSAL || ARCH_ZYNQ || ARCH_ZYNQMP || \
RCAR_GEN3 || TARGET_SOCFPGA_SOC64
default 512 if ARCH_MX5 || ARCH_MX6 || ARCH_MX7 || FSL_LSCH2 || \
FSL_LSCH3 || X86
default 256 if M68K || PPC
default 1024
config SYS_PBSIZE
int "Buffer size for console output"
default 1044
config SYS_XTRACE
bool "Command execution tracer"
depends on CMDLINE

12
common/Kconfig
View file

@ -659,6 +659,18 @@ config MISC_INIT_R
help
Enabling this option calls 'misc_init_r' function
config SYS_MALLOC_BOOTPARAMS
bool "Malloc a buffer to use for bootparams"
help
In some cases rather than using a known location to store the
bi_boot_params portion of gd we need to allocate it from our malloc pool.
config SYS_BOOTPARAMS_LEN
hex "Size of the bootparam buffer to malloc in bytes"
depends on SYS_MALLOC_BOOTPARAMS
default 0x20000 if MIPS || RCAR_GEN3
default 0x10000
config ID_EEPROM
bool "Enable I2C connected system identifier EEPROM"
help

4
common/board_r.c
View file

@ -457,7 +457,7 @@ static int initr_env(void)
return 0;
}
#ifdef CONFIG_SYS_BOOTPARAMS_LEN
#ifdef CONFIG_SYS_MALLOC_BOOTPARAMS
static int initr_malloc_bootparams(void)
{
gd->bd->bi_boot_params = (ulong)malloc(CONFIG_SYS_BOOTPARAMS_LEN);
@ -713,7 +713,7 @@ static init_fnc_t init_sequence_r[] = {
initr_pvblock,
#endif
initr_env,
#ifdef CONFIG_SYS_BOOTPARAMS_LEN
#ifdef CONFIG_SYS_MALLOC_BOOTPARAMS
initr_malloc_bootparams,
#endif
INIT_FUNC_WATCHDOG_RESET

851
common/spl/Kconfig
View file

File diff suppressed because it is too large Load diff

124
common/spl/Kconfig.nxp Normal file
View file

@ -0,0 +1,124 @@
menu "PowerPC and LayerScape SPL Boot options"
depends on (PPC && SUPPORT_SPL && !SPL_FRAMEWORK) || \
((ARCH_LS1021A || ARCH_LS1043A || ARCH_LS1046A) && SUPPORT_SPL)
config SPL_NAND_BOOT
bool "Load SPL from NAND flash"
depends on PPC && (SUPPORT_SPL && !SPL_FRAMEWORK)
config SPL_MMC_BOOT
bool "Load SPL from SD Card / eMMC"
depends on PPC && (SUPPORT_SPL && !SPL_FRAMEWORK)
config SPL_SPI_BOOT
bool "Load SPL from SPI flash"
depends on PPC && (SUPPORT_SPL && !SPL_FRAMEWORK)
config SPL_FSL_PBL
bool "Create SPL in Freescale PBI format"
depends on (PPC || ARCH_LS1021A || ARCH_LS1043A || ARCH_LS1046A) && \
SUPPORT_SPL
help
Create boot binary having SPL binary in PBI format concatenated with
u-boot binary.
config SPL_SYS_CCSR_DO_NOT_RELOCATE
bool "Ensures that CCSR is not relocated"
depends on PPC
help
If this is defined, then CONFIG_SYS_CCSRBAR_PHYS will be forced to a
value that ensures that CCSR is not relocated.
config TPL_SYS_CCSR_DO_NOT_RELOCATE
def_bool y
depends on SPL_SYS_CCSR_DO_NOT_RELOCATE
menu "PowerPC SPL / TPL specific options"
depends on PPC && (SPL && !SPL_FRAMEWORK)
config SPL_INIT_MINIMAL
bool "Arch init code will be built for a very small image"
config SPL_FLUSH_IMAGE
bool "Clean dcache and invalidate icache after loading the image"
config SPL_SKIP_RELOCATE
bool "Skip relocating SPL"
config SPL_GD_ADDR
hex "Address to use for global data (gd) in SPL"
depends on !SPL_INIT_MINIMAL
config SPL_RELOC_TEXT_BASE
hex "Address to relocate SPL to"
default SPL_TEXT_BASE
help
If unspecified, this is equal to CONFIG_SPL_TEXT_BASE (i.e. no
relocation is done).
config SPL_RELOC_STACK
hex "Address of the start of the stack SPL will use after relocation."
help
If unspecified, this is equal to CONFIG_SYS_SPL_MALLOC_START. Starting
address of the malloc pool used in SPL. When this option is set the full
malloc is used in SPL and it is set up by spl_init() and before that, the
simple malloc() can be used if CONFIG_SYS_MALLOC_F is defined.
config SPL_RELOC_MALLOC
bool "SPL has malloc pool after relocation"
config SPL_RELOC_MALLOC_ADDR
hex "Address of malloc pool in SPL"
depends on SPL_RELOC_MALLOC
config SPL_RELOC_MALLOC_SIZE
hex "Size of malloc pool in SPL"
depends on SPL_RELOC_MALLOC
config TPL_GD_ADDR
hex "Address to use for global data (gd) in TPL"
depends on TPL
config TPL_RELOC_TEXT_BASE
hex "Address to relocate TPL to"
depends on TPL
default TPL_TEXT_BASE
help
If unspecified, this is equal to CONFIG_TPL_TEXT_BASE (i.e. no
relocation is done).
config TPL_RELOC_STACK
hex "Address of the start of the stack TPL will use after relocation."
depends on TPL
help
If unspecified, this is equal to CONFIG_SYS_TPL_MALLOC_START. Starting
address of the malloc pool used in TPL. When this option is set the full
malloc is used in TPL and it is set up by spl_init() and before that, the
simple malloc() can be used if CONFIG_SYS_MALLOC_F is defined.
config TPL_RELOC_MALLOC
bool "TPL has malloc pool after relocation"
depends on TPL
config TPL_RELOC_MALLOC_ADDR
hex "Address of malloc pool in TPL"
depends on TPL_RELOC_MALLOC
config TPL_RELOC_MALLOC_SIZE
hex "Size of malloc pool in TPL"
depends on TPL_RELOC_MALLOC
config TPL_PAD_TO
hex "Offset to which the TPL should be padded before appending the TPL payload"
depends on TPL && !TPL_FRAMEWORK
default TPL_MAX_SIZE
help
Image offset to which the TPL should be padded before appending the
TPL payload. By default, this is defined as CONFIG_TPL_MAX_SIZE, or 0 if
CONFIG_TPL_MAX_SIZE is undefined. CONFIG_TPL_PAD_TO must be either
0, meaning to append the TPL payload without any padding, or >=
CONFIG_TPL_MAX_SIZE.
endmenu
endmenu

322
common/spl/Kconfig.tpl Normal file
View file

@ -0,0 +1,322 @@
menu "TPL configuration options"
depends on TPL
config TPL_SIZE_LIMIT
hex "Maximum size of TPL image"
default 0x0
help
Specifies the maximum length of the U-Boot TPL image.
If this value is zero, it is ignored.
config TPL_BINMAN_SYMBOLS
bool "Declare binman symbols in TPL"
depends on SPL_FRAMEWORK && BINMAN
default y
help
This enables use of symbols in TPL which refer to U-Boot, enabling TPL
to obtain the location of U-Boot simply by calling spl_get_image_pos()
and spl_get_image_size().
For this to work, you must have a U-Boot image in the binman image, so
binman can update TPL with the location of it.
config TPL_FRAMEWORK
bool "Support TPL based upon the common SPL framework"
default y if SPL_FRAMEWORK
help
Enable the SPL framework under common/spl/ for TPL builds.
This framework supports MMC, NAND and YMODEM and other methods
loading of U-Boot's SPL stage. If unsure, say Y.
config TPL_BANNER_PRINT
bool "Enable output of the TPL banner 'U-Boot TPL ...'"
default y
help
If this option is enabled, TPL will print the banner with version
info. Disabling this option could be useful to reduce TPL boot time
(e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud).
config TPL_HANDOFF
bool "Pass hand-off information from TPL to SPL and U-Boot proper"
depends on HANDOFF && TPL_BLOBLIST
default y
help
This option enables TPL to write handoff information. This can be
used to pass information like the size of SDRAM from TPL to U-Boot
proper. The information is also available to SPL if it is useful
there.
config TPL_BOARD_INIT
bool "Call board-specific initialization in TPL"
help
If this option is enabled, U-Boot will call the function
spl_board_init() from board_init_r(). This function should be
provided by the board.
config TPL_BOOTCOUNT_LIMIT
bool "Support bootcount in TPL"
depends on TPL_ENV_SUPPORT
help
If this option is enabled, the TPL will support bootcount.
For example, it may be useful to choose the device to boot.
config TPL_SYS_MALLOC_SIMPLE
bool
prompt "Only use malloc_simple functions in the TPL"
help
Say Y here to only use the *_simple malloc functions from
malloc_simple.c, rather then using the versions from dlmalloc.c;
this will make the TPL binary smaller at the cost of more heap
usage as the *_simple malloc functions do not re-use free-ed mem.
config TPL_SEPARATE_BSS
bool "BSS section is in a different memory region from text"
default y if SPL_SEPARATE_BSS
help
Some platforms need a large BSS region in TPL and can provide this
because RAM is already set up. In this case BSS can be moved to RAM.
This option should then be enabled so that the correct device tree
location is used. Normally we put the device tree at the end of BSS
but with this option enabled, it goes at _image_binary_end.
config TPL_LDSCRIPT
string "Linker script for the TPL stage"
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64
default "arch/\$(ARCH)/cpu/u-boot-spl.lds"
help
The TPL stage will usually require a different linker-script
(as it runs from a different memory region) than the regular
U-Boot stage. Set this to the path of the linker-script to
be used for TPL.
May be left empty to trigger the Makefile infrastructure to
fall back to the linker-script used for the SPL stage.
config TPL_NEEDS_SEPARATE_STACK
bool "TPL needs a separate initial stack-pointer"
help
Enable, if the TPL stage should not inherit its initial
stack-pointer from the settings for the SPL stage.
config TPL_POWER
bool "Support power drivers"
help
Enable support for power control in TPL. This includes support
for PMICs (Power-management Integrated Circuits) and some of the
features provided by PMICs. In particular, voltage regulators can
be used to enable/disable power and vary its voltage. That can be
useful in TPL to turn on boot peripherals and adjust CPU voltage
so that the clock speed can be increased. This enables the drivers
in drivers/power, drivers/power/pmic and drivers/power/regulator
as part of an TPL build.
config TPL_TEXT_BASE
hex "Base address for the .text section of the TPL stage"
default 0
help
The base address for the .text section of the TPL stage.
config TPL_MAX_SIZE
hex "Maximum size (in bytes) for the TPL stage"
default 0x2e000 if ROCKCHIP_RK3399
default 0x8000 if ROCKCHIP_RK3288
default 0x7000 if ROCKCHIP_RK322X || ROCKCHIP_RK3328 || ROCKCHIP_RK3368
default 0x2800 if ROCKCHIP_PX30
default 0x0
help
The maximum size (in bytes) of the TPL stage.
config TPL_STACK
hex "Address of the initial stack-pointer for the TPL stage"
depends on TPL_NEEDS_SEPARATE_STACK
help
The address of the initial stack-pointer for the TPL stage.
Usually this will be the (aligned) top-of-stack.
config TPL_READ_ONLY
bool
depends on TPL_OF_PLATDATA
select TPL_OF_PLATDATA_NO_BIND
select TPL_OF_PLATDATA_RT
help
Some platforms (e.g. x86 Apollo Lake) load SPL into a read-only
section of memory. This means that of-platdata must make a copy (in
writeable memory) of anything it wants to modify, such as
device-private data.
config TPL_BOOTROM_SUPPORT
bool "Support returning to the BOOTROM (from TPL)"
help
Some platforms (e.g. the Rockchip RK3368) provide support in their
ROM for loading the next boot-stage after performing basic setup
from the TPL stage.
Enable this option, to return to the BOOTROM through the
BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the
boot device list, if not implemented for a given board)
config TPL_CRC32
bool "Support CRC32 in TPL"
default y if TPL_ENV_SUPPORT || TPL_BLOBLIST
help
Enable this to support CRC32 in uImages or FIT images within SPL.
This is a 32-bit checksum value that can be used to verify images.
For FIT images, this is the least secure type of checksum, suitable
for detected accidental image corruption. For secure applications you
should consider SHA1 or SHA256.
config TPL_DRIVERS_MISC
bool "Support misc drivers in TPL"
help
Enable miscellaneous drivers in TPL. These drivers perform various
tasks that don't fall nicely into other categories, Enable this
option to build the drivers in drivers/misc as part of an TPL
build, for those that support building in TPL (not all drivers do).
config TPL_ENV_SUPPORT
bool "Support an environment"
help
Enable environment support in TPL. See SPL_ENV_SUPPORT for details.
config TPL_GPIO
bool "Support GPIO in TPL"
help
Enable support for GPIOs (General-purpose Input/Output) in TPL.
GPIOs allow U-Boot to read the state of an input line (high or
low) and set the state of an output line. This can be used to
drive LEDs, control power to various system parts and read user
input. GPIOs can be useful in TPL to enable a 'sign-of-life' LED,
for example. Enable this option to build the drivers in
drivers/gpio as part of an TPL build.
config TPL_I2C
bool "Support I2C"
help
Enable support for the I2C bus in TPL. See SPL_I2C for
details.
config TPL_LIBCOMMON_SUPPORT
bool "Support common libraries"
help
Enable support for common U-Boot libraries within TPL. See
SPL_LIBCOMMON_SUPPORT for details.
config TPL_LIBGENERIC_SUPPORT
bool "Support generic libraries"
help
Enable support for generic U-Boot libraries within TPL. See
SPL_LIBGENERIC_SUPPORT for details.
config TPL_MPC8XXX_INIT_DDR
bool "Support MPC8XXX DDR init"
help
Enable support for DDR-SDRAM on the MPC8XXX family within TPL. See
SPL_MPC8XXX_INIT_DDR for details.
config TPL_MMC
bool "Support MMC"
depends on MMC
help
Enable support for MMC within TPL. See SPL_MMC for details.
config TPL_NAND_SUPPORT
bool "Support NAND flash"
help
Enable support for NAND in TPL. See SPL_NAND_SUPPORT for details.
config TPL_PCI
bool "Support PCI drivers"
help
Enable support for PCI in TPL. For platforms that need PCI to boot,
or must perform some init using PCI in SPL, this provides the
necessary driver support. This enables the drivers in drivers/pci
as part of a TPL build.
config TPL_PCH
bool "Support PCH drivers"
help
Enable support for PCH (Platform Controller Hub) devices in TPL.
These are used to set up GPIOs and the SPI peripheral early in
boot. This enables the drivers in drivers/pch as part of a TPL
build.
config TPL_RAM_SUPPORT
bool "Support booting from RAM"
help
Enable booting of an image in RAM. The image can be preloaded or
it can be loaded by TPL directly into RAM (e.g. using USB).
config TPL_RAM_DEVICE
bool "Support booting from preloaded image in RAM"
depends on TPL_RAM_SUPPORT
help
Enable booting of an image already loaded in RAM. The image has to
be already in memory when TPL takes over, e.g. loaded by the boot
ROM.
config TPL_RTC
bool "Support RTC drivers"
help
Enable RTC (Real-time Clock) support in TPL. This includes support
for reading and setting the time. Some RTC devices also have some
non-volatile (battery-backed) memory which is accessible if
needed. This enables the drivers in drivers/rtc as part of an TPL
build.
config TPL_SERIAL
bool "Support serial"
select TPL_PRINTF
select TPL_STRTO
help
Enable support for serial in TPL. See SPL_SERIAL for
details.
config TPL_SPI_FLASH_SUPPORT
bool "Support SPI flash drivers"
help
Enable support for using SPI flash in TPL. See SPL_SPI_FLASH_SUPPORT
for details.
config TPL_SPI_FLASH_TINY
bool "Enable low footprint TPL SPI Flash support"
depends on TPL_SPI_FLASH_SUPPORT && !SPI_FLASH_BAR
default y if SPI_FLASH
help
Enable lightweight TPL SPI Flash support that supports just reading
data/images from flash. No support to write/erase flash. Enable
this if you have TPL size limitations and don't need full-fledged
SPI flash support.
config TPL_SPI_LOAD
bool "Support loading from SPI flash"
depends on TPL_SPI_FLASH_SUPPORT
help
Enable support for loading next stage, U-Boot or otherwise, from
SPI NOR in U-Boot TPL.
config TPL_SPI
bool "Support SPI drivers"
help
Enable support for using SPI in TPL. See SPL_SPI for
details.
config TPL_DM_SPI
bool "Support SPI DM drivers in TPL"
help
Enable support for SPI DM drivers in TPL.
config TPL_DM_SPI_FLASH
bool "Support SPI DM FLASH drivers in TPL"
help
Enable support for SPI DM flash drivers in TPL.
config TPL_YMODEM_SUPPORT
bool "Support loading using Ymodem"
depends on TPL_SERIAL
help
While loading from serial is slow it can be a useful backup when
there is no other option. The Ymodem protocol provides a reliable
means of transmitting U-Boot over a serial line for using in TPL,
with a checksum to ensure correctness.
endmenu

201
common/spl/Kconfig.vpl Normal file
View file

@ -0,0 +1,201 @@
menu "VPL options"
depends on VPL
config VPL_BANNER_PRINT
bool "Enable output of the VPL banner 'U-Boot VPL ...'"
default y
help
If this option is enabled, VPL will print the banner with version
info. Disabling this option could be useful to reduce VPL boot time
(e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud).
config VPL_BOARD_INIT
bool "Call board-specific initialization in VPL"
help
If this option is enabled, U-Boot will call the function
spl_board_init() from board_init_r(). This function should be
provided by the board.
config VPL_CACHE
depends on CACHE
bool "Support cache drivers in VPL"
help
Enable support for cache drivers in VPL.
config VPL_CRC32
bool "Support CRC32 in VPL"
default y if VPL_ENV_SUPPORT || VPL_BLOBLIST
help
Enable this to support CRC32 in uImages or FIT images within VPL.
This is a 32-bit checksum value that can be used to verify images.
For FIT images, this is the least secure type of checksum, suitable
for detected accidental image corruption. For secure applications you
should consider SHA1 or SHA256.
config VPL_DM_SPI
bool "Support SPI DM drivers in VPL"
help
Enable support for SPI DM drivers in VPL.
config VPL_DM_SPI_FLASH
bool "Support SPI DM FLASH drivers in VPL"
help
Enable support for SPI DM flash drivers in VPL.
config VPL_FRAMEWORK
bool "Support VPL based upon the common SPL framework"
default y
help
Enable the SPL framework under common/spl/ for VPL builds.
This framework supports MMC, NAND and YMODEM and other methods
loading of U-Boot's next stage. If unsure, say Y.
config VPL_HANDOFF
bool "Pass hand-off information from VPL to SPL"
depends on HANDOFF && VPL_BLOBLIST
default y
help
This option enables VPL to write handoff information. This can be
used to pass information like the size of SDRAM from VPL to SPL. Also
VPL can receive information from TPL in the same place if that is
enabled.
config VPL_LIBCOMMON_SUPPORT
bool "Support common libraries"
default y if SPL_LIBCOMMON_SUPPORT
help
Enable support for common U-Boot libraries within VPL. See
SPL_LIBCOMMON_SUPPORT for details.
config VPL_LIBGENERIC_SUPPORT
bool "Support generic libraries"
default y if SPL_LIBGENERIC_SUPPORT
help
Enable support for generic U-Boot libraries within VPL. These
libraries include generic code to deal with device tree, hashing,
printf(), compression and the like. This option is enabled on many
boards. Enable this option to build the code in lib/ as part of a
VPL build.
config VPL_DRIVERS_MISC
bool "Support misc drivers"
default y if TPL_DRIVERS_MISC
help
Enable miscellaneous drivers in VPL. These drivers perform various
tasks that don't fall nicely into other categories, Enable this
option to build the drivers in drivers/misc as part of a VPL
build, for those that support building in VPL (not all drivers do).
config VPL_ENV_SUPPORT
bool "Support an environment"
help
Enable environment support in VPL. The U-Boot environment provides
a number of settings (essentially name/value pairs) which can
control many aspects of U-Boot's operation. Enabling this option will
make env_get() and env_set() available in VSPL.
config VPL_GPIO
bool "Support GPIO in VPL"
default y if SPL_GPIO
help
Enable support for GPIOs (General-purpose Input/Output) in VPL.
GPIOs allow U-Boot to read the state of an input line (high or
low) and set the state of an output line. This can be used to
drive LEDs, control power to various system parts and read user
input. GPIOs can be useful in VPL to enable a 'sign-of-life' LED,
for example. Enable this option to build the drivers in
drivers/gpio as part of a VPL build.
config VPL_HANDOFF
bool "Pass hand-off information from VPL to SPL and U-Boot proper"
depends on HANDOFF && VPL_BLOBLIST
default y
help
This option enables VPL to write handoff information. This can be
used to pass information like the size of SDRAM from VPL to U-Boot
proper. The information is also available to VPL if it is useful
there.
config VPL_HASH
bool "Support hashing drivers in VPL"
select SHA1
select SHA256
help
Enable hashing drivers in VPL. These drivers can be used to
accelerate secure boot processing in secure applications. Enable
this option to build system-specific drivers for hash acceleration
as part of a VPL build.
config VPL_I2C_SUPPORT
bool "Support I2C in VPL"
default y if SPL_I2C_SUPPORT
help
Enable support for the I2C bus in VPL. Vee SPL_I2C_SUPPORT for
details.
config VPL_PCH_SUPPORT
bool "Support PCH drivers"
default y if TPL_PCH_SUPPORT
help
Enable support for PCH (Platform Controller Hub) devices in VPL.
These are used to set up GPIOs and the SPI peripheral early in
boot. This enables the drivers in drivers/pch as part of a VPL
build.
config VPL_PCI
bool "Support PCI drivers"
default y if SPL_PCI
help
Enable support for PCI in VPL. For platforms that need PCI to boot,
or must perform some init using PCI in VPL, this provides the
necessary driver support. This enables the drivers in drivers/pci
as part of a VPL build.
config VPL_RTC
bool "Support RTC drivers"
help
Enable RTC (Real-time Clock) support in VPL. This includes support
for reading and setting the time. Some RTC devices also have some
non-volatile (battery-backed) memory which is accessible if
needed. This enables the drivers in drivers/rtc as part of a VPL
build.
config VPL_SERIAL
bool "Support serial"
default y if TPL_SERIAL
select VPL_PRINTF
select VPL_STRTO
help
Enable support for serial in VPL. See SPL_SERIAL_SUPPORT for
details.
config VPL_SIZE_LIMIT
hex "Maximum size of VPL image"
default 0x0
help
Specifies the maximum length of the U-Boot VPL image.
If this value is zero, it is ignored.
config VPL_SPI
bool "Support SPI drivers"
help
Enable support for using SPI in VPL. See SPL_SPI_SUPPORT for
details.
config VPL_SPI_FLASH_SUPPORT
bool "Support SPI flash drivers"
help
Enable support for using SPI flash in VPL, and loading U-Boot from
SPI flash. SPI flash (Serial Peripheral Bus flash) is named after
the SPI bus that is used to connect it to a system. It is a simple
but fast bidirectional 4-wire bus (clock, chip select and two data
lines). This enables the drivers in drivers/mtd/spi as part of a
VPL build. This normally requires VPL_SPI_SUPPORT.
config VPL_TEXT_BASE
hex "VPL Text Base"
default 0x0
help
The address in memory that VPL will be running from.
endmenu

6
common/spl/spl.c
View file

@ -19,6 +19,7 @@
#include <mapmem.h>
#include <serial.h>
#include <spl.h>
#include <system-constants.h>
#include <asm/global_data.h>
#include <asm-generic/gpio.h>
#include <asm/u-boot.h>
@ -728,9 +729,8 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
spl_set_bd();
#if defined(CONFIG_SYS_SPL_MALLOC_START)
mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
CONFIG_SYS_SPL_MALLOC_SIZE);
#if defined(CONFIG_SYS_SPL_MALLOC)
mem_malloc_init(SYS_SPL_MALLOC_START, CONFIG_SYS_SPL_MALLOC_SIZE);
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#endif
if (!(gd->flags & GD_FLG_SPL_INIT)) {

2
common/spl/spl_mmc.c
View file

@ -229,7 +229,7 @@ static int mmc_load_image_raw_os(struct spl_image_info *spl_image,
{
int ret;
#if defined(CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR)
#if CONFIG_VAL(SYS_MMCSD_RAW_MODE_ARGS_SECTOR)
unsigned long count;
count = blk_dread(mmc_get_blk_desc(mmc),

4
common/spl/spl_nor.c
View file

@ -74,8 +74,8 @@ static int spl_nor_load_image(struct spl_image_info *spl_image,
(void *)(CONFIG_SYS_OS_BASE +
sizeof(struct image_header)),
spl_image->size);
#ifdef CONFIG_SYS_FDT_BASE
spl_image->arg = (void *)CONFIG_SYS_FDT_BASE;
#ifdef CONFIG_SYS_SPL_ARGS_ADDR
spl_image->arg = (void *)CONFIG_SYS_SPL_ARGS_ADDR;
#endif
return 0;

24
common/spl/spl_sata.c
View file

@ -21,10 +21,6 @@
#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1
#endif
#ifndef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
#ifndef CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR
/* Dummy value to make the compiler happy */
#define CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR 0x100
@ -73,21 +69,11 @@ static int spl_sata_load_image(struct spl_image_info *spl_image,
int err = 0;
struct blk_desc *stor_dev;
#if !defined(CONFIG_DM_SCSI) && !defined(CONFIG_AHCI)
err = init_sata(CONFIG_SPL_SATA_BOOT_DEVICE);
#endif
if (err) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("spl: sata init failed: err - %d\n", err);
#endif
return err;
} else {
/* try to recognize storage devices immediately */
scsi_scan(false);
stor_dev = blk_get_devnum_by_type(IF_TYPE_SCSI, 0);
if (!stor_dev)
return -ENODEV;
}
/* try to recognize storage devices immediately */
scsi_scan(false);
stor_dev = blk_get_devnum_by_type(IF_TYPE_SCSI, 0);
if (!stor_dev)
return -ENODEV;
#if CONFIG_IS_ENABLED(OS_BOOT)
if (spl_start_uboot() ||

2
common/spl/spl_xip.c
View file

@ -14,7 +14,7 @@ static int spl_xip(struct spl_image_info *spl_image,
{
#if CONFIG_IS_ENABLED(OS_BOOT)
if (!spl_start_uboot()) {
spl_image->arg = (void *)CONFIG_SYS_FDT_BASE;
spl_image->arg = (void *)CONFIG_SYS_SPL_ARGS_ADDR;
spl_image->name = "Linux";
spl_image->os = IH_OS_LINUX;
spl_image->load_addr = CONFIG_SYS_LOAD_ADDR;

2
configs/10m50_defconfig
View file

@ -15,6 +15,8 @@ CONFIG_SYS_MONITOR_BASE=0xCFF80000
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
CONFIG_CMD_CPU=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_XIMG is not set

3
configs/3c120_defconfig
View file

@ -15,6 +15,8 @@ CONFIG_SYS_MONITOR_BASE=0xD7F80000
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
CONFIG_CMD_CPU=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_XIMG is not set
@ -37,6 +39,7 @@ CONFIG_ALTERA_SYSID=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CFI_FLASH=y
CONFIG_SYS_CFI_FLASH_STATUS_POLL=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y

2
configs/A10-OLinuXino-Lime_defconfig
View file

@ -11,7 +11,9 @@ CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

2
configs/A10s-OLinuXino-M_defconfig
View file

@ -9,7 +9,9 @@ CONFIG_MMC1_CD_PIN="PG13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_USB1_VBUS_PIN="PB10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

2
configs/A13-OLinuXinoM_defconfig
View file

@ -13,6 +13,8 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y
CONFIG_VIDEO_LCD_POWER="PB10"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

2
configs/A13-OLinuXino_defconfig
View file

@ -15,7 +15,9 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_DFU_RAM=y

2
configs/A20-OLinuXino-Lime2-eMMC_defconfig
View file

@ -13,7 +13,9 @@ CONFIG_SATAPWR="PC3"
CONFIG_SPL_SPI_SUNXI=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SCSI_AHCI=y

2
configs/A20-OLinuXino-Lime2_defconfig
View file

@ -11,7 +11,9 @@ CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SCSI_AHCI=y

2
configs/A20-OLinuXino-Lime_defconfig
View file

@ -9,7 +9,9 @@ CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

2
configs/A20-OLinuXino_MICRO-eMMC_defconfig
View file

@ -11,7 +11,9 @@ CONFIG_VIDEO_VGA=y
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

2
configs/A20-OLinuXino_MICRO_defconfig
View file

@ -12,7 +12,9 @@ CONFIG_VIDEO_VGA=y
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

2
configs/A20-Olimex-SOM-EVB_defconfig
View file

@ -12,7 +12,9 @@ CONFIG_USB0_VBUS_DET="PH5"
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

2
configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
View file

@ -13,7 +13,9 @@ CONFIG_SATAPWR="PC3"
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_SYS_I2C_MVTWSI=y

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