mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
usb: r8a66597: Checkpatch cleanup
Fix remaining checkpatch complaints in the driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
a3d65651d9
commit
8b54830154
2 changed files with 268 additions and 268 deletions
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@ -58,7 +58,7 @@ static void get_hub_data(struct usb_device *dev, u16 *hub_devnum, u16 *hubport)
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/* check a device connected to root_hub */
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if ((parent && parent->devnum == 1) ||
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(dev->devnum == 1))
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dev->devnum == 1)
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return;
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*hub_devnum = (u8)parent->devnum;
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@ -66,7 +66,7 @@ static void get_hub_data(struct usb_device *dev, u16 *hub_devnum, u16 *hubport)
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}
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static void set_devadd(struct r8a66597 *r8a66597, u8 r8a66597_address,
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struct usb_device *dev, int port)
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struct usb_device *dev, int port)
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{
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u16 val, usbspd, upphub, hubport;
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unsigned long devadd_reg = get_devadd_addr(r8a66597_address);
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@ -321,7 +321,7 @@ static int send_bulk_packet(struct r8a66597 *r8a66597, struct usb_device *dev,
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R8A66597_DPRINT("%s\n", __func__);
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r8a66597_mdfy(r8a66597, MBW | BULK_OUT_PIPENUM,
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MBW | CURPIPE, CFIFOSEL);
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MBW | CURPIPE, CFIFOSEL);
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r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, BULK_OUT_PIPENUM);
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tmp = r8a66597_read(r8a66597, CFIFOCTR);
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if ((tmp & FRDY) == 0) {
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@ -345,7 +345,7 @@ static int send_bulk_packet(struct r8a66597 *r8a66597, struct usb_device *dev,
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dev->act_len += size;
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r8a66597_mdfy(r8a66597, PID_BUF, PID,
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get_pipectr_addr(BULK_OUT_PIPENUM));
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get_pipectr_addr(BULK_OUT_PIPENUM));
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while (!(r8a66597_read(r8a66597, BEMPSTS) & (1 << BULK_OUT_PIPENUM)))
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if (ctrlc())
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@ -354,7 +354,7 @@ static int send_bulk_packet(struct r8a66597 *r8a66597, struct usb_device *dev,
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if (dev->act_len >= transfer_len)
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r8a66597_mdfy(r8a66597, PID_NAK, PID,
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get_pipectr_addr(BULK_OUT_PIPENUM));
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get_pipectr_addr(BULK_OUT_PIPENUM));
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return 0;
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}
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@ -375,17 +375,17 @@ static int receive_bulk_packet(struct r8a66597 *r8a66597,
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/* prepare */
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if (dev->act_len == 0) {
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r8a66597_mdfy(r8a66597, PID_NAK, PID,
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get_pipectr_addr(pipenum));
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get_pipectr_addr(pipenum));
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r8a66597_write(r8a66597, ~(1 << pipenum), BRDYSTS);
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r8a66597_write(r8a66597, TRCLR, get_pipetre_addr(pipenum));
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r8a66597_write(r8a66597,
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(transfer_len + maxpacket - 1) / maxpacket,
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(transfer_len + maxpacket - 1) / maxpacket,
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get_pipetrn_addr(pipenum));
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r8a66597_bset(r8a66597, TRENB, get_pipetre_addr(pipenum));
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r8a66597_mdfy(r8a66597, PID_BUF, PID,
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get_pipectr_addr(pipenum));
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get_pipectr_addr(pipenum));
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}
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r8a66597_mdfy(r8a66597, MBW | pipenum, MBW | CURPIPE, CFIFOSEL);
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@ -462,7 +462,7 @@ static int receive_control_packet(struct r8a66597 *r8a66597,
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}
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static int send_status_packet(struct r8a66597 *r8a66597,
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unsigned long pipe)
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unsigned long pipe)
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{
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r8a66597_bset(r8a66597, SQSET, DCPCTR);
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r8a66597_mdfy(r8a66597, PID_NAK, PID, DCPCTR);
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@ -553,9 +553,7 @@ static int check_usb_device_connecting(struct r8a66597 *r8a66597)
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return -1; /* fail */
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}
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/*-------------------------------------------------------------------------*
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* Virtual Root Hub
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*-------------------------------------------------------------------------*/
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/* Virtual Root Hub */
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#include <usbroothubdes.h>
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@ -637,34 +635,34 @@ static int r8a66597_submit_rh_msg(struct udevice *udev, struct usb_device *dev,
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switch ((wValue & 0xff00) >> 8) {
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case (0x01): /* device descriptor */
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len = min_t(unsigned int,
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leni,
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leni,
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min_t(unsigned int,
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sizeof(root_hub_dev_des),
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sizeof(root_hub_dev_des),
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wLength));
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memcpy(buffer, root_hub_dev_des, len);
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break;
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case (0x02): /* configuration descriptor */
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len = min_t(unsigned int,
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leni,
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leni,
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min_t(unsigned int,
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sizeof(root_hub_config_des),
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sizeof(root_hub_config_des),
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wLength));
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memcpy(buffer, root_hub_config_des, len);
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break;
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case (0x03): /* string descriptors */
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if (wValue == 0x0300) {
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len = min_t(unsigned int,
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leni,
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leni,
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min_t(unsigned int,
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sizeof(root_hub_str_index0),
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sizeof(root_hub_str_index0),
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wLength));
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memcpy(buffer, root_hub_str_index0, len);
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}
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if (wValue == 0x0301) {
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len = min_t(unsigned int,
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leni,
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leni,
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min_t(unsigned int,
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sizeof(root_hub_str_index1),
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sizeof(root_hub_str_index1),
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wLength));
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memcpy(buffer, root_hub_str_index1, len);
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}
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@ -697,7 +695,8 @@ static int r8a66597_submit_rh_msg(struct udevice *udev, struct usb_device *dev,
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} else {
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data[0] += 2;
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data[8] = (temp & RH_B_DR) >> 8;
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data[10] = data[9] = 0xff;
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data[9] = 0xff;
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data[10] = 0xff;
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}
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len = min_t(unsigned int, leni,
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@ -707,7 +706,7 @@ static int r8a66597_submit_rh_msg(struct udevice *udev, struct usb_device *dev,
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}
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case RH_GET_CONFIGURATION:
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*(__u8 *) buffer = 0x01;
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*(__u8 *)buffer = 0x01;
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len = 1;
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break;
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case RH_SET_CONFIGURATION:
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@ -727,9 +726,10 @@ static int r8a66597_submit_rh_msg(struct udevice *udev, struct usb_device *dev,
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return stat;
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}
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static int r8a66597_submit_control_msg(struct udevice *udev, struct usb_device *dev,
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unsigned long pipe, void *buffer, int length,
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struct devrequest *setup)
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static int r8a66597_submit_control_msg(struct udevice *udev,
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struct usb_device *dev,
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unsigned long pipe, void *buffer,
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int length, struct devrequest *setup)
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{
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struct r8a66597 *r8a66597 = dev_get_priv(udev);
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u16 r8a66597_address = setup->request == USB_REQ_SET_ADDRESS ?
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@ -754,7 +754,7 @@ static int r8a66597_submit_control_msg(struct udevice *udev, struct usb_device *
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dev->act_len = 0;
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if (usb_pipein(pipe))
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if (receive_control_packet(r8a66597, dev, buffer,
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length) < 0)
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length) < 0)
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return -1;
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if (send_status_packet(r8a66597, pipe) < 0)
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@ -765,8 +765,9 @@ static int r8a66597_submit_control_msg(struct udevice *udev, struct usb_device *
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return 0;
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}
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static int r8a66597_submit_bulk_msg(struct udevice *udev, struct usb_device *dev,
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unsigned long pipe, void *buffer, int length)
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static int r8a66597_submit_bulk_msg(struct udevice *udev,
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struct usb_device *dev, unsigned long pipe,
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void *buffer, int length)
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{
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struct r8a66597 *r8a66597 = dev_get_priv(udev);
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int ret = 0;
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@ -788,10 +789,10 @@ static int r8a66597_submit_bulk_msg(struct udevice *udev, struct usb_device *dev
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if (usb_pipein(pipe))
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ret = receive_bulk_packet(r8a66597, dev, pipe, buffer,
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length);
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length);
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else
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ret = send_bulk_packet(r8a66597, dev, pipe, buffer,
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length);
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length);
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}
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if (ret == 0)
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@ -824,7 +825,7 @@ static int r8a66597_usb_probe(struct udevice *dev)
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mdelay(100);
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enable_controller(priv);
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r8a66597_port_power(priv, 0 , 1);
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r8a66597_port_power(priv, 0, 1);
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/* check usb device */
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check_usb_device_connecting(priv);
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@ -72,9 +72,9 @@
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#define PIPE3TRE 0x98
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#define PIPE3TRN 0x9A
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#define PIPE4TRE 0x9C
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#define PIPE4TRN 0x9E
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#define PIPE5TRE 0xA0
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#define PIPE5TRN 0xA2
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#define PIPE4TRN 0x9E
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#define PIPE5TRE 0xA0
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#define PIPE5TRN 0xA2
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#define DEVADD0 0xD0
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#define DEVADD1 0xD2
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#define DEVADD2 0xD4
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@ -89,290 +89,290 @@
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#define SUSPMODE0 0x102 /* RZ/A only */
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/* System Configuration Control Register */
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#define HSE 0x0080 /* b7: Hi-speed enable */
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#define DCFM 0x0040 /* b6: Controller function select */
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#define DRPD 0x0020 /* b5: D+/- pull down control */
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#define DPRPU 0x0010 /* b4: D+ pull up control */
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#define XTAL 0x0004 /* b2: Crystal selection */
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#define XTAL12 0x0004 /* 12MHz */
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#define XTAL48 0x0000 /* 48MHz */
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#define UPLLE 0x0002 /* b1: internal PLL control */
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#define USBE 0x0001 /* b0: USB module operation enable */
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#define HSE 0x0080 /* b7: Hi-speed enable */
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#define DCFM 0x0040 /* b6: Controller function select */
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#define DRPD 0x0020 /* b5: D+/- pull down control */
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#define DPRPU 0x0010 /* b4: D+ pull up control */
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#define XTAL 0x0004 /* b2: Crystal selection */
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#define XTAL12 0x0004 /* 12MHz */
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#define XTAL48 0x0000 /* 48MHz */
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#define UPLLE 0x0002 /* b1: internal PLL control */
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#define USBE 0x0001 /* b0: USB module operation enable */
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/* System Configuration Status Register */
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#define OVCBIT 0x8000 /* b15-14: Over-current bit */
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#define OVCMON 0xC000 /* b15-14: Over-current monitor */
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#define SOFEA 0x0020 /* b5: SOF monitor */
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#define IDMON 0x0004 /* b3: ID-pin monitor */
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#define LNST 0x0003 /* b1-0: D+, D- line status */
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#define SE1 0x0003 /* SE1 */
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#define FS_KSTS 0x0002 /* Full-Speed K State */
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#define FS_JSTS 0x0001 /* Full-Speed J State */
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#define LS_JSTS 0x0002 /* Low-Speed J State */
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#define LS_KSTS 0x0001 /* Low-Speed K State */
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#define SE0 0x0000 /* SE0 */
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#define OVCBIT 0x8000 /* b15-14: Over-current bit */
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#define OVCMON 0xC000 /* b15-14: Over-current monitor */
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#define SOFEA 0x0020 /* b5: SOF monitor */
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#define IDMON 0x0004 /* b3: ID-pin monitor */
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#define LNST 0x0003 /* b1-0: D+, D- line status */
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#define SE1 0x0003 /* SE1 */
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#define FS_KSTS 0x0002 /* Full-Speed K State */
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#define FS_JSTS 0x0001 /* Full-Speed J State */
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#define LS_JSTS 0x0002 /* Low-Speed J State */
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#define LS_KSTS 0x0001 /* Low-Speed K State */
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#define SE0 0x0000 /* SE0 */
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/* Device State Control Register */
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#define EXTLP0 0x0400 /* b10: External port */
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#define VBOUT 0x0200 /* b9: VBUS output */
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#define WKUP 0x0100 /* b8: Remote wakeup */
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#define RWUPE 0x0080 /* b7: Remote wakeup sense */
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#define USBRST 0x0040 /* b6: USB reset enable */
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#define RESUME 0x0020 /* b5: Resume enable */
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#define UACT 0x0010 /* b4: USB bus enable */
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#define RHST 0x0007 /* b1-0: Reset handshake status */
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#define HSPROC 0x0004 /* HS handshake is processing */
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#define HSMODE 0x0003 /* Hi-Speed mode */
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#define FSMODE 0x0002 /* Full-Speed mode */
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#define LSMODE 0x0001 /* Low-Speed mode */
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#define UNDECID 0x0000 /* Undecided */
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#define EXTLP0 0x0400 /* b10: External port */
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#define VBOUT 0x0200 /* b9: VBUS output */
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#define WKUP 0x0100 /* b8: Remote wakeup */
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#define RWUPE 0x0080 /* b7: Remote wakeup sense */
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#define USBRST 0x0040 /* b6: USB reset enable */
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#define RESUME 0x0020 /* b5: Resume enable */
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#define UACT 0x0010 /* b4: USB bus enable */
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#define RHST 0x0007 /* b1-0: Reset handshake status */
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#define HSPROC 0x0004 /* HS handshake is processing */
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#define HSMODE 0x0003 /* Hi-Speed mode */
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#define FSMODE 0x0002 /* Full-Speed mode */
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#define LSMODE 0x0001 /* Low-Speed mode */
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#define UNDECID 0x0000 /* Undecided */
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/* Test Mode Register */
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#define UTST 0x000F /* b3-0: Test select */
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#define H_TST_PACKET 0x000C /* HOST TEST Packet */
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#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
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#define H_TST_K 0x000A /* HOST TEST K */
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#define H_TST_J 0x0009 /* HOST TEST J */
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#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
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#define P_TST_PACKET 0x0004 /* PERI TEST Packet */
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#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
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#define P_TST_K 0x0002 /* PERI TEST K */
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#define P_TST_J 0x0001 /* PERI TEST J */
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#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
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#define UTST 0x000F /* b3-0: Test select */
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#define H_TST_PACKET 0x000C /* HOST TEST Packet */
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#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
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#define H_TST_K 0x000A /* HOST TEST K */
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#define H_TST_J 0x0009 /* HOST TEST J */
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#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
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#define P_TST_PACKET 0x0004 /* PERI TEST Packet */
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#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
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#define P_TST_K 0x0002 /* PERI TEST K */
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#define P_TST_J 0x0001 /* PERI TEST J */
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#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
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/* Data Pin Configuration Register */
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#define LDRV 0x8000 /* b15: Drive Current Adjust */
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#define VIF1 0x0000 /* VIF = 1.8V */
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#define VIF3 0x8000 /* VIF = 3.3V */
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#define INTA 0x0001 /* b1: USB INT-pin active */
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#define LDRV 0x8000 /* b15: Drive Current Adjust */
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#define VIF1 0x0000 /* VIF = 1.8V */
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#define VIF3 0x8000 /* VIF = 3.3V */
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#define INTA 0x0001 /* b1: USB INT-pin active */
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/* DMAx Pin Configuration Register */
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#define DREQA 0x4000 /* b14: Dreq active select */
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#define BURST 0x2000 /* b13: Burst mode */
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#define DACKA 0x0400 /* b10: Dack active select */
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#define DFORM 0x0380 /* b9-7: DMA mode select */
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#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
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#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
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#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
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#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
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#define DENDA 0x0040 /* b6: Dend active select */
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#define PKTM 0x0020 /* b5: Packet mode */
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#define DENDE 0x0010 /* b4: Dend enable */
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#define OBUS 0x0004 /* b2: OUTbus mode */
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#define DREQA 0x4000 /* b14: Dreq active select */
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#define BURST 0x2000 /* b13: Burst mode */
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#define DACKA 0x0400 /* b10: Dack active select */
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#define DFORM 0x0380 /* b9-7: DMA mode select */
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#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
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#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
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#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
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#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
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#define DENDA 0x0040 /* b6: Dend active select */
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#define PKTM 0x0020 /* b5: Packet mode */
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#define DENDE 0x0010 /* b4: Dend enable */
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#define OBUS 0x0004 /* b2: OUTbus mode */
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/* CFIFO/DxFIFO Port Select Register */
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#define RCNT 0x8000 /* b15: Read count mode */
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#define REW 0x4000 /* b14: Buffer rewind */
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#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
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#define DREQE 0x1000 /* b12: DREQ output enable */
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#define MBW 0x0800 /* b10: Maximum bit width for FIFO access */
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#define MBW_8 0x0000 /* 8bit */
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#define MBW_16 0x0400 /* 16bit */
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#define MBW_32 0x0800 /* 32bit */
|
||||
#define BIGEND 0x0100 /* b8: Big endian mode */
|
||||
#define BYTE_LITTLE 0x0000 /* little dendian */
|
||||
#define BYTE_BIG 0x0100 /* big endifan */
|
||||
#define ISEL 0x0020 /* b5: DCP FIFO port direction select */
|
||||
#define CURPIPE 0x000F /* b2-0: PIPE select */
|
||||
#define RCNT 0x8000 /* b15: Read count mode */
|
||||
#define REW 0x4000 /* b14: Buffer rewind */
|
||||
#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
|
||||
#define DREQE 0x1000 /* b12: DREQ output enable */
|
||||
#define MBW 0x0800 /* b10: Maximum bit width for FIFO access */
|
||||
#define MBW_8 0x0000 /* 8bit */
|
||||
#define MBW_16 0x0400 /* 16bit */
|
||||
#define MBW_32 0x0800 /* 32bit */
|
||||
#define BIGEND 0x0100 /* b8: Big endian mode */
|
||||
#define BYTE_LITTLE 0x0000 /* little dendian */
|
||||
#define BYTE_BIG 0x0100 /* big endifan */
|
||||
#define ISEL 0x0020 /* b5: DCP FIFO port direction select */
|
||||
#define CURPIPE 0x000F /* b2-0: PIPE select */
|
||||
|
||||
/* CFIFO/DxFIFO Port Control Register */
|
||||
#define BVAL 0x8000 /* b15: Buffer valid flag */
|
||||
#define BCLR 0x4000 /* b14: Buffer clear */
|
||||
#define FRDY 0x2000 /* b13: FIFO ready */
|
||||
#define DTLN 0x0FFF /* b11-0: FIFO received data length */
|
||||
#define BVAL 0x8000 /* b15: Buffer valid flag */
|
||||
#define BCLR 0x4000 /* b14: Buffer clear */
|
||||
#define FRDY 0x2000 /* b13: FIFO ready */
|
||||
#define DTLN 0x0FFF /* b11-0: FIFO received data length */
|
||||
|
||||
/* Interrupt Enable Register 0 */
|
||||
#define VBSE 0x8000 /* b15: VBUS interrupt */
|
||||
#define RSME 0x4000 /* b14: Resume interrupt */
|
||||
#define SOFE 0x2000 /* b13: Frame update interrupt */
|
||||
#define DVSE 0x1000 /* b12: Device state transition interrupt */
|
||||
#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
|
||||
#define BEMPE 0x0400 /* b10: Buffer empty interrupt */
|
||||
#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
|
||||
#define BRDYE 0x0100 /* b8: Buffer ready interrupt */
|
||||
#define VBSE 0x8000 /* b15: VBUS interrupt */
|
||||
#define RSME 0x4000 /* b14: Resume interrupt */
|
||||
#define SOFE 0x2000 /* b13: Frame update interrupt */
|
||||
#define DVSE 0x1000 /* b12: Device state transition interrupt */
|
||||
#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
|
||||
#define BEMPE 0x0400 /* b10: Buffer empty interrupt */
|
||||
#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
|
||||
#define BRDYE 0x0100 /* b8: Buffer ready interrupt */
|
||||
|
||||
/* Interrupt Enable Register 1 */
|
||||
#define OVRCRE 0x8000 /* b15: Over-current interrupt */
|
||||
#define BCHGE 0x4000 /* b14: USB us chenge interrupt */
|
||||
#define DTCHE 0x1000 /* b12: Detach sense interrupt */
|
||||
#define ATTCHE 0x0800 /* b11: Attach sense interrupt */
|
||||
#define EOFERRE 0x0040 /* b6: EOF error interrupt */
|
||||
#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
|
||||
#define SACKE 0x0010 /* b4: SETUP ACK interrupt */
|
||||
#define OVRCRE 0x8000 /* b15: Over-current interrupt */
|
||||
#define BCHGE 0x4000 /* b14: USB us chenge interrupt */
|
||||
#define DTCHE 0x1000 /* b12: Detach sense interrupt */
|
||||
#define ATTCHE 0x0800 /* b11: Attach sense interrupt */
|
||||
#define EOFERRE 0x0040 /* b6: EOF error interrupt */
|
||||
#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
|
||||
#define SACKE 0x0010 /* b4: SETUP ACK interrupt */
|
||||
|
||||
/* BRDY Interrupt Enable/Status Register */
|
||||
#define BRDY9 0x0200 /* b9: PIPE9 */
|
||||
#define BRDY8 0x0100 /* b8: PIPE8 */
|
||||
#define BRDY7 0x0080 /* b7: PIPE7 */
|
||||
#define BRDY6 0x0040 /* b6: PIPE6 */
|
||||
#define BRDY5 0x0020 /* b5: PIPE5 */
|
||||
#define BRDY4 0x0010 /* b4: PIPE4 */
|
||||
#define BRDY3 0x0008 /* b3: PIPE3 */
|
||||
#define BRDY2 0x0004 /* b2: PIPE2 */
|
||||
#define BRDY1 0x0002 /* b1: PIPE1 */
|
||||
#define BRDY0 0x0001 /* b1: PIPE0 */
|
||||
#define BRDY9 0x0200 /* b9: PIPE9 */
|
||||
#define BRDY8 0x0100 /* b8: PIPE8 */
|
||||
#define BRDY7 0x0080 /* b7: PIPE7 */
|
||||
#define BRDY6 0x0040 /* b6: PIPE6 */
|
||||
#define BRDY5 0x0020 /* b5: PIPE5 */
|
||||
#define BRDY4 0x0010 /* b4: PIPE4 */
|
||||
#define BRDY3 0x0008 /* b3: PIPE3 */
|
||||
#define BRDY2 0x0004 /* b2: PIPE2 */
|
||||
#define BRDY1 0x0002 /* b1: PIPE1 */
|
||||
#define BRDY0 0x0001 /* b1: PIPE0 */
|
||||
|
||||
/* NRDY Interrupt Enable/Status Register */
|
||||
#define NRDY9 0x0200 /* b9: PIPE9 */
|
||||
#define NRDY8 0x0100 /* b8: PIPE8 */
|
||||
#define NRDY7 0x0080 /* b7: PIPE7 */
|
||||
#define NRDY6 0x0040 /* b6: PIPE6 */
|
||||
#define NRDY5 0x0020 /* b5: PIPE5 */
|
||||
#define NRDY4 0x0010 /* b4: PIPE4 */
|
||||
#define NRDY3 0x0008 /* b3: PIPE3 */
|
||||
#define NRDY2 0x0004 /* b2: PIPE2 */
|
||||
#define NRDY1 0x0002 /* b1: PIPE1 */
|
||||
#define NRDY0 0x0001 /* b1: PIPE0 */
|
||||
#define NRDY9 0x0200 /* b9: PIPE9 */
|
||||
#define NRDY8 0x0100 /* b8: PIPE8 */
|
||||
#define NRDY7 0x0080 /* b7: PIPE7 */
|
||||
#define NRDY6 0x0040 /* b6: PIPE6 */
|
||||
#define NRDY5 0x0020 /* b5: PIPE5 */
|
||||
#define NRDY4 0x0010 /* b4: PIPE4 */
|
||||
#define NRDY3 0x0008 /* b3: PIPE3 */
|
||||
#define NRDY2 0x0004 /* b2: PIPE2 */
|
||||
#define NRDY1 0x0002 /* b1: PIPE1 */
|
||||
#define NRDY0 0x0001 /* b1: PIPE0 */
|
||||
|
||||
/* BEMP Interrupt Enable/Status Register */
|
||||
#define BEMP9 0x0200 /* b9: PIPE9 */
|
||||
#define BEMP8 0x0100 /* b8: PIPE8 */
|
||||
#define BEMP7 0x0080 /* b7: PIPE7 */
|
||||
#define BEMP6 0x0040 /* b6: PIPE6 */
|
||||
#define BEMP5 0x0020 /* b5: PIPE5 */
|
||||
#define BEMP4 0x0010 /* b4: PIPE4 */
|
||||
#define BEMP3 0x0008 /* b3: PIPE3 */
|
||||
#define BEMP2 0x0004 /* b2: PIPE2 */
|
||||
#define BEMP1 0x0002 /* b1: PIPE1 */
|
||||
#define BEMP0 0x0001 /* b0: PIPE0 */
|
||||
#define BEMP9 0x0200 /* b9: PIPE9 */
|
||||
#define BEMP8 0x0100 /* b8: PIPE8 */
|
||||
#define BEMP7 0x0080 /* b7: PIPE7 */
|
||||
#define BEMP6 0x0040 /* b6: PIPE6 */
|
||||
#define BEMP5 0x0020 /* b5: PIPE5 */
|
||||
#define BEMP4 0x0010 /* b4: PIPE4 */
|
||||
#define BEMP3 0x0008 /* b3: PIPE3 */
|
||||
#define BEMP2 0x0004 /* b2: PIPE2 */
|
||||
#define BEMP1 0x0002 /* b1: PIPE1 */
|
||||
#define BEMP0 0x0001 /* b0: PIPE0 */
|
||||
|
||||
/* SOF Pin Configuration Register */
|
||||
#define TRNENSEL 0x0100 /* b8: Select transaction enable period */
|
||||
#define BRDYM 0x0040 /* b6: BRDY clear timing */
|
||||
#define INTL 0x0020 /* b5: Interrupt sense select */
|
||||
#define EDGESTS 0x0010 /* b4: */
|
||||
#define SOFMODE 0x000C /* b3-2: SOF pin select */
|
||||
#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
|
||||
#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
|
||||
#define SOF_DISABLE 0x0000 /* SOF OUT Disable */
|
||||
#define TRNENSEL 0x0100 /* b8: Select transaction enable period */
|
||||
#define BRDYM 0x0040 /* b6: BRDY clear timing */
|
||||
#define INTL 0x0020 /* b5: Interrupt sense select */
|
||||
#define EDGESTS 0x0010 /* b4: */
|
||||
#define SOFMODE 0x000C /* b3-2: SOF pin select */
|
||||
#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
|
||||
#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
|
||||
#define SOF_DISABLE 0x0000 /* SOF OUT Disable */
|
||||
|
||||
/* Interrupt Status Register 0 */
|
||||
#define VBINT 0x8000 /* b15: VBUS interrupt */
|
||||
#define RESM 0x4000 /* b14: Resume interrupt */
|
||||
#define SOFR 0x2000 /* b13: SOF frame update interrupt */
|
||||
#define DVST 0x1000 /* b12: Device state transition interrupt */
|
||||
#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
|
||||
#define BEMP 0x0400 /* b10: Buffer empty interrupt */
|
||||
#define NRDY 0x0200 /* b9: Buffer not ready interrupt */
|
||||
#define BRDY 0x0100 /* b8: Buffer ready interrupt */
|
||||
#define VBSTS 0x0080 /* b7: VBUS input port */
|
||||
#define DVSQ 0x0070 /* b6-4: Device state */
|
||||
#define DS_SPD_CNFG 0x0070 /* Suspend Configured */
|
||||
#define DS_SPD_ADDR 0x0060 /* Suspend Address */
|
||||
#define DS_SPD_DFLT 0x0050 /* Suspend Default */
|
||||
#define DS_SPD_POWR 0x0040 /* Suspend Powered */
|
||||
#define DS_SUSP 0x0040 /* Suspend */
|
||||
#define DS_CNFG 0x0030 /* Configured */
|
||||
#define DS_ADDS 0x0020 /* Address */
|
||||
#define DS_DFLT 0x0010 /* Default */
|
||||
#define DS_POWR 0x0000 /* Powered */
|
||||
#define DVSQS 0x0030 /* b5-4: Device state */
|
||||
#define VALID 0x0008 /* b3: Setup packet detected flag */
|
||||
#define CTSQ 0x0007 /* b2-0: Control transfer stage */
|
||||
#define CS_SQER 0x0006 /* Sequence error */
|
||||
#define CS_WRND 0x0005 /* Control write nodata status stage */
|
||||
#define CS_WRSS 0x0004 /* Control write status stage */
|
||||
#define CS_WRDS 0x0003 /* Control write data stage */
|
||||
#define CS_RDSS 0x0002 /* Control read status stage */
|
||||
#define CS_RDDS 0x0001 /* Control read data stage */
|
||||
#define CS_IDST 0x0000 /* Idle or setup stage */
|
||||
#define VBINT 0x8000 /* b15: VBUS interrupt */
|
||||
#define RESM 0x4000 /* b14: Resume interrupt */
|
||||
#define SOFR 0x2000 /* b13: SOF frame update interrupt */
|
||||
#define DVST 0x1000 /* b12: Device state transition interrupt */
|
||||
#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
|
||||
#define BEMP 0x0400 /* b10: Buffer empty interrupt */
|
||||
#define NRDY 0x0200 /* b9: Buffer not ready interrupt */
|
||||
#define BRDY 0x0100 /* b8: Buffer ready interrupt */
|
||||
#define VBSTS 0x0080 /* b7: VBUS input port */
|
||||
#define DVSQ 0x0070 /* b6-4: Device state */
|
||||
#define DS_SPD_CNFG 0x0070 /* Suspend Configured */
|
||||
#define DS_SPD_ADDR 0x0060 /* Suspend Address */
|
||||
#define DS_SPD_DFLT 0x0050 /* Suspend Default */
|
||||
#define DS_SPD_POWR 0x0040 /* Suspend Powered */
|
||||
#define DS_SUSP 0x0040 /* Suspend */
|
||||
#define DS_CNFG 0x0030 /* Configured */
|
||||
#define DS_ADDS 0x0020 /* Address */
|
||||
#define DS_DFLT 0x0010 /* Default */
|
||||
#define DS_POWR 0x0000 /* Powered */
|
||||
#define DVSQS 0x0030 /* b5-4: Device state */
|
||||
#define VALID 0x0008 /* b3: Setup packet detected flag */
|
||||
#define CTSQ 0x0007 /* b2-0: Control transfer stage */
|
||||
#define CS_SQER 0x0006 /* Sequence error */
|
||||
#define CS_WRND 0x0005 /* Control write nodata status stage */
|
||||
#define CS_WRSS 0x0004 /* Control write status stage */
|
||||
#define CS_WRDS 0x0003 /* Control write data stage */
|
||||
#define CS_RDSS 0x0002 /* Control read status stage */
|
||||
#define CS_RDDS 0x0001 /* Control read data stage */
|
||||
#define CS_IDST 0x0000 /* Idle or setup stage */
|
||||
|
||||
/* Interrupt Status Register 1 */
|
||||
#define OVRCR 0x8000 /* b15: Over-current interrupt */
|
||||
#define BCHG 0x4000 /* b14: USB bus chenge interrupt */
|
||||
#define DTCH 0x1000 /* b12: Detach sense interrupt */
|
||||
#define ATTCH 0x0800 /* b11: Attach sense interrupt */
|
||||
#define EOFERR 0x0040 /* b6: EOF-error interrupt */
|
||||
#define SIGN 0x0020 /* b5: Setup ignore interrupt */
|
||||
#define SACK 0x0010 /* b4: Setup acknowledge interrupt */
|
||||
#define OVRCR 0x8000 /* b15: Over-current interrupt */
|
||||
#define BCHG 0x4000 /* b14: USB bus chenge interrupt */
|
||||
#define DTCH 0x1000 /* b12: Detach sense interrupt */
|
||||
#define ATTCH 0x0800 /* b11: Attach sense interrupt */
|
||||
#define EOFERR 0x0040 /* b6: EOF-error interrupt */
|
||||
#define SIGN 0x0020 /* b5: Setup ignore interrupt */
|
||||
#define SACK 0x0010 /* b4: Setup acknowledge interrupt */
|
||||
|
||||
/* Frame Number Register */
|
||||
#define OVRN 0x8000 /* b15: Overrun error */
|
||||
#define CRCE 0x4000 /* b14: Received data error */
|
||||
#define FRNM 0x07FF /* b10-0: Frame number */
|
||||
#define OVRN 0x8000 /* b15: Overrun error */
|
||||
#define CRCE 0x4000 /* b14: Received data error */
|
||||
#define FRNM 0x07FF /* b10-0: Frame number */
|
||||
|
||||
/* Micro Frame Number Register */
|
||||
#define UFRNM 0x0007 /* b2-0: Micro frame number */
|
||||
#define UFRNM 0x0007 /* b2-0: Micro frame number */
|
||||
|
||||
/* Default Control Pipe Maxpacket Size Register */
|
||||
/* Pipe Maxpacket Size Register */
|
||||
#define DEVSEL 0xF000 /* b15-14: Device address select */
|
||||
#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
|
||||
#define DEVSEL 0xF000 /* b15-14: Device address select */
|
||||
#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
|
||||
|
||||
/* Default Control Pipe Control Register */
|
||||
#define BSTS 0x8000 /* b15: Buffer status */
|
||||
#define SUREQ 0x4000 /* b14: Send USB request */
|
||||
#define CSCLR 0x2000 /* b13: complete-split status clear */
|
||||
#define CSSTS 0x1000 /* b12: complete-split status */
|
||||
#define SUREQCLR 0x0800 /* b11: stop setup request */
|
||||
#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
|
||||
#define SQSET 0x0080 /* b7: Sequence toggle bit set */
|
||||
#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
|
||||
#define PBUSY 0x0020 /* b5: pipe busy */
|
||||
#define PINGE 0x0010 /* b4: ping enable */
|
||||
#define CCPL 0x0004 /* b2: Enable control transfer complete */
|
||||
#define PID 0x0003 /* b1-0: Response PID */
|
||||
#define PID_STALL11 0x0003 /* STALL */
|
||||
#define PID_STALL 0x0002 /* STALL */
|
||||
#define PID_BUF 0x0001 /* BUF */
|
||||
#define PID_NAK 0x0000 /* NAK */
|
||||
#define BSTS 0x8000 /* b15: Buffer status */
|
||||
#define SUREQ 0x4000 /* b14: Send USB request */
|
||||
#define CSCLR 0x2000 /* b13: complete-split status clear */
|
||||
#define CSSTS 0x1000 /* b12: complete-split status */
|
||||
#define SUREQCLR 0x0800 /* b11: stop setup request */
|
||||
#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
|
||||
#define SQSET 0x0080 /* b7: Sequence toggle bit set */
|
||||
#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
|
||||
#define PBUSY 0x0020 /* b5: pipe busy */
|
||||
#define PINGE 0x0010 /* b4: ping enable */
|
||||
#define CCPL 0x0004 /* b2: Enable control transfer complete */
|
||||
#define PID 0x0003 /* b1-0: Response PID */
|
||||
#define PID_STALL11 0x0003 /* STALL */
|
||||
#define PID_STALL 0x0002 /* STALL */
|
||||
#define PID_BUF 0x0001 /* BUF */
|
||||
#define PID_NAK 0x0000 /* NAK */
|
||||
|
||||
/* Pipe Window Select Register */
|
||||
#define PIPENM 0x0007 /* b2-0: Pipe select */
|
||||
#define PIPENM 0x0007 /* b2-0: Pipe select */
|
||||
|
||||
/* Pipe Configuration Register */
|
||||
#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
|
||||
#define R8A66597_ISO 0xC000 /* Isochronous */
|
||||
#define R8A66597_INT 0x8000 /* Interrupt */
|
||||
#define R8A66597_BULK 0x4000 /* Bulk */
|
||||
#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
|
||||
#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
|
||||
#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
|
||||
#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
|
||||
#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
|
||||
#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
|
||||
#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
|
||||
#define R8A66597_ISO 0xC000 /* Isochronous */
|
||||
#define R8A66597_INT 0x8000 /* Interrupt */
|
||||
#define R8A66597_BULK 0x4000 /* Bulk */
|
||||
#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
|
||||
#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
|
||||
#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
|
||||
#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
|
||||
#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
|
||||
#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
|
||||
|
||||
/* Pipe Buffer Configuration Register */
|
||||
#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
|
||||
#define BUFNMB 0x007F /* b6-0: Pipe buffer number */
|
||||
#define PIPE0BUF 256
|
||||
#define PIPExBUF 64
|
||||
#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
|
||||
#define BUFNMB 0x007F /* b6-0: Pipe buffer number */
|
||||
#define PIPE0BUF 256
|
||||
#define PIPExBUF 64
|
||||
|
||||
/* Pipe Maxpacket Size Register */
|
||||
#define MXPS 0x07FF /* b10-0: Maxpacket size */
|
||||
#define MXPS 0x07FF /* b10-0: Maxpacket size */
|
||||
|
||||
/* Pipe Cycle Configuration Register */
|
||||
#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
|
||||
#define IITV 0x0007 /* b2-0: Isochronous interval */
|
||||
#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
|
||||
#define IITV 0x0007 /* b2-0: Isochronous interval */
|
||||
|
||||
/* Pipex Control Register */
|
||||
#define BSTS 0x8000 /* b15: Buffer status */
|
||||
#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
|
||||
#define CSCLR 0x2000 /* b13: complete-split status clear */
|
||||
#define CSSTS 0x1000 /* b12: complete-split status */
|
||||
#define ATREPM 0x0400 /* b10: Auto repeat mode */
|
||||
#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
|
||||
#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
|
||||
#define SQSET 0x0080 /* b7: Sequence toggle bit set */
|
||||
#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
|
||||
#define PBUSY 0x0020 /* b5: pipe busy */
|
||||
#define PID 0x0003 /* b1-0: Response PID */
|
||||
#define BSTS 0x8000 /* b15: Buffer status */
|
||||
#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
|
||||
#define CSCLR 0x2000 /* b13: complete-split status clear */
|
||||
#define CSSTS 0x1000 /* b12: complete-split status */
|
||||
#define ATREPM 0x0400 /* b10: Auto repeat mode */
|
||||
#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
|
||||
#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
|
||||
#define SQSET 0x0080 /* b7: Sequence toggle bit set */
|
||||
#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
|
||||
#define PBUSY 0x0020 /* b5: pipe busy */
|
||||
#define PID 0x0003 /* b1-0: Response PID */
|
||||
|
||||
/* PIPExTRE */
|
||||
#define TRENB 0x0200 /* b9: Transaction counter enable */
|
||||
#define TRCLR 0x0100 /* b8: Transaction counter clear */
|
||||
#define TRENB 0x0200 /* b9: Transaction counter enable */
|
||||
#define TRCLR 0x0100 /* b8: Transaction counter clear */
|
||||
|
||||
/* PIPExTRN */
|
||||
#define TRNCNT 0xFFFF /* b15-0: Transaction counter */
|
||||
#define TRNCNT 0xFFFF /* b15-0: Transaction counter */
|
||||
|
||||
/* DEVADDx */
|
||||
#define UPPHUB 0x7800
|
||||
#define HUBPORT 0x0700
|
||||
#define USBSPD 0x00C0
|
||||
#define RTPORT 0x0001
|
||||
#define UPPHUB 0x7800
|
||||
#define HUBPORT 0x0700
|
||||
#define USBSPD 0x00C0
|
||||
#define RTPORT 0x0001
|
||||
|
||||
/* Suspend Mode Register */
|
||||
#define SUSPM 0x4000 /* b14: Suspend */
|
||||
#define SUSPM 0x4000 /* b14: Suspend */
|
||||
|
||||
#define R8A66597_MAX_NUM_PIPE 10
|
||||
#define R8A66597_BUF_BSIZE 8
|
||||
|
|
@ -387,9 +387,7 @@
|
|||
#define BULK_OUT_PIPENUM 4
|
||||
#define BULK_OUT_BUFNUM 40
|
||||
|
||||
#define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
|
||||
#define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
|
||||
#define make_devsel(addr) (addr << 12)
|
||||
#define make_devsel(addr) ((addr) << 12)
|
||||
|
||||
struct r8a66597 {
|
||||
unsigned long reg;
|
||||
|
|
@ -420,6 +418,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
|
|||
|
||||
if (len & 0x00000003) {
|
||||
unsigned long tmp = readl(fifoaddr);
|
||||
|
||||
memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03);
|
||||
}
|
||||
}
|
||||
|
|
@ -459,6 +458,7 @@ static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
|
|||
u16 val, u16 pat, unsigned long offset)
|
||||
{
|
||||
u16 tmp;
|
||||
|
||||
tmp = r8a66597_read(r8a66597, offset);
|
||||
tmp = tmp & (~pat);
|
||||
tmp = tmp | val;
|
||||
|
|
@ -523,7 +523,6 @@ static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
|
|||
#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
|
||||
#define get_devadd_addr(address) (DEVADD0 + address * 2)
|
||||
|
||||
|
||||
/* USB HUB CONSTANTS (not OHCI-specific; see hub.h, based on usb_ohci.h) */
|
||||
|
||||
/* destination of request */
|
||||
|
|
@ -606,11 +605,11 @@ static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
|
|||
|
||||
/* roothub.a masks */
|
||||
#define RH_A_NDP (0xff << 0) /* number of downstream ports */
|
||||
#define RH_A_PSM (1 << 8) /* power switching mode */
|
||||
#define RH_A_NPS (1 << 9) /* no power switching */
|
||||
#define RH_A_DT (1 << 10) /* device type (mbz) */
|
||||
#define RH_A_OCPM (1 << 11) /* over current protection mode */
|
||||
#define RH_A_NOCP (1 << 12) /* no over current protection */
|
||||
#define RH_A_PSM BIT(8) /* power switching mode */
|
||||
#define RH_A_NPS BIT(9) /* no power switching */
|
||||
#define RH_A_DT BIT(10) /* device type (mbz) */
|
||||
#define RH_A_OCPM BIT(11) /* over current protection mode */
|
||||
#define RH_A_NOCP BIT(12) /* no over current protection */
|
||||
#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
|
||||
|
||||
#endif /* __R8A66597_H__ */
|
||||
|
|
|
|||
Loading…
Reference in a new issue