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armv7: adapt omap4 to the new cache maintenance framework

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adapt omap4 to the new layered cache maintenance framework

Signed-off-by: Aneesh V <aneesh@ti.com>
This commit is contained in:
Aneesh V 2011-06-16 23:30:52 +00:00 committed by Albert ARIBAUD
parent 93bc21930a
commit 8b457fa828
5 changed files with 32 additions and 7 deletions
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12
arch/arm/cpu/armv7/omap4/board.c
View file

@ -127,3 +127,15 @@ int arch_cpu_init(void)
set_muxconf_regs();
return 0;
}
#ifndef CONFIG_SYS_L2CACHE_OFF
void v7_outer_cache_enable(void)
{
set_pl310_ctrl_reg(1);
}
void v7_outer_cache_disable(void)
{
set_pl310_ctrl_reg(0);
}
#endif

9
arch/arm/cpu/armv7/omap4/lowlevel_init.S
View file

@ -45,3 +45,12 @@ lowlevel_init:
*/
bl s_init
pop {ip, pc}
.globl set_pl310_ctrl_reg
set_pl310_ctrl_reg:
PUSH {r4-r11, lr} @ save registers - ROM code may pollute
@ our registers
LDR r12, =0x102 @ Set PL310 control register - value in R0
.word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5
@ call ROM Code API to set control register
POP {r4-r11, pc}

2
arch/arm/include/asm/arch-omap4/sys_proto.h
View file

@ -31,11 +31,11 @@ struct omap_sysinfo {
void gpmc_init(void);
void watchdog_init(void);
u32 get_device_type(void);
void invalidate_dcache(u32);
void set_muxconf_regs(void);
void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void set_pl310_ctrl_reg(u32 val);
extern const struct omap_sysinfo sysinfo;

8
include/configs/omap4_panda.h
View file

@ -45,9 +45,6 @@
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
/* Keep L2 Cache Disabled */
#define CONFIG_SYS_L2CACHE_OFF 1
/* Clock Defines */
#define V_OSCK 38400000 /* Clock output from T2 */
#define V_SCLK V_OSCK
@ -235,4 +232,9 @@
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310 1
#define CONFIG_SYS_PL310_BASE 0x48242000
#endif
#endif /* __CONFIG_H */

8
include/configs/omap4_sdp4430.h
View file

@ -46,9 +46,6 @@
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
/* Keep L2 Cache Disabled */
#define CONFIG_SYS_L2CACHE_OFF 1
/* Clock Defines */
#define V_OSCK 38400000 /* Clock output from T2 */
#define V_SCLK V_OSCK
@ -241,4 +238,9 @@
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310 1
#define CONFIG_SYS_PL310_BASE 0x48242000
#endif
#endif /* __CONFIG_H */