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u-boot-imx-20211022

Browse source 
-------------------
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/10887
 
 - imx8 : Toradex Verdin MX8M Plus
 	 Kontron pitx-imx8m
 - imx8ulp: several fixes and improvements
 - imx6ull fixes
 - switching to binman
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Merge tag 'u-boot-imx-20220207' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20211022
-------------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/10887

- imx8 : Toradex Verdin MX8M Plus
	 Kontron pitx-imx8m
- imx8ulp: several fixes and improvements
- imx6ull fixes
- switching to binman
This commit is contained in:
Tom Rini 2022-02-07 12:13:53 -05:00
commit 8b139f4e1c
154 changed files with 16023 additions and 541 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
Makefile
View file

@ -1535,7 +1535,6 @@ else
ifeq ($(CONFIG_BINMAN),y)
flash.bin: spl/u-boot-spl.bin $(INPUTS-y) FORCE
$(call if_changed,binman)
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
else
flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@

4
arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx28.cfg
View file

@ -2,5 +2,5 @@ DISPLAYPROGRESS
SECTION 0x0 BOOTABLE
TAG LAST
LOAD 0x1000 spl/u-boot-spl.bin
LOAD IVT 0x8000 0x1000
CALL HAB 0x8000 0x0
LOAD IVT 0xE000 0x1000
CALL HAB 0xE000 0x0

8
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
View file

@ -2,8 +2,8 @@ DISPLAYPROGRESS
SECTION 0x0 BOOTABLE
TAG LAST
LOAD 0x1000 spl/u-boot-spl.bin
LOAD IVT 0x8000 0x1000
CALL HAB 0x8000 0x0
LOAD IVT 0xE000 0x1000
CALL HAB 0xE000 0x0
LOAD 0x40002000 u-boot.bin
LOAD IVT 0x8000 0x40002000
CALL HAB 0x8000 0x0
LOAD IVT 0xE000 0x40002000
CALL HAB 0xE000 0x0

4
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
View file

@ -627,11 +627,11 @@ static void mxs_power_enable_4p2(void)
mxs_power_init_dcdc_4p2_source();
writel(vdddctrl, &power_regs->hw_power_vdddctrl);
writel(vddioctrl, &power_regs->hw_power_vddioctrl);
early_delay(20);
writel(vddactrl, &power_regs->hw_power_vddactrl);
early_delay(20);
writel(vddioctrl, &power_regs->hw_power_vddioctrl);
writel(vdddctrl, &power_regs->hw_power_vdddctrl);
/*
* Check if FET is enabled on either powerout and if so,

23
arch/arm/dts/Makefile
View file

@ -914,13 +914,16 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mn-ddr4-evk.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \
imx8mn-var-som-symphony.dtb \
imx8mq-evk.dtb \
imx8mm-beacon-kit.dtb \
imx8mn-beacon-kit.dtb \
imx8mq-phanbell.dtb \
imx8mp-evk.dtb \
imx8mp-phyboard-pollux-rdk.dtb \
imx8mq-pico-pi.dtb
imx8mp-verdin.dtb \
imx8mq-pico-pi.dtb \
imx8mq-kontron-pitx-imx8m.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb
@ -1178,9 +1181,23 @@ dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb
dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb \
imx8mm-cl-iot-gate-ied.dtbo \
imx8mm-cl-iot-gate-ied-adc0.dtbo \
imx8mm-cl-iot-gate-ied-adc1.dtbo \
imx8mm-cl-iot-gate-ied-can0.dtbo \
imx8mm-cl-iot-gate-ied-can1.dtbo \
imx8mm-cl-iot-gate-ied-tpm0.dtbo \
imx8mm-cl-iot-gate-ied-tpm1.dtbo
dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb
dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb \
imx8mm-cl-iot-gate-ied.dtbo \
imx8mm-cl-iot-gate-ied-adc0.dtbo \
imx8mm-cl-iot-gate-ied-adc1.dtbo \
imx8mm-cl-iot-gate-ied-can0.dtbo \
imx8mm-cl-iot-gate-ied-can1.dtbo \
imx8mm-cl-iot-gate-ied-tpm0.dtbo \
imx8mm-cl-iot-gate-ied-tpm1.dtbo
dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb

27
arch/arm/dts/fsl-imx8qxp-colibri.dts
View file

@ -129,6 +129,14 @@
>;
};
/* On Module I2C */
pinctrl_i2c0: i2c0grp {
fsl,pins = <
SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021
SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021
>;
};
/* Off Module I2C */
pinctrl_i2c1: i2c1grp {
fsl,pins = <
@ -298,6 +306,25 @@
};
};
&i2c0 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
status = "okay";
/* GPIO expander */
gpio_expander_43: gpio-expander@43 {
compatible = "fcs,fxl6408";
gpio-controller;
#gpio-cells = <2>;
reg = <0x43>;
initial_io_dir = <0xff>;
initial_output = <0x05>;
};
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;

73
arch/arm/dts/imx28-xea.dts
View file

@ -41,6 +41,15 @@
enable-active-high;
regulator-boot-on;
};
reg_usb_5v: regulator-usb-5v {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&mac0 {
@ -86,27 +95,49 @@
spi-max-frequency = <40000000>;
reg = <0>;
partition@0 {
label = "SPL (spi)";
reg = <0x0 0x10000>;
read-only;
};
partition@1 {
label = "u-boot (spi)";
reg = <0x10000 0x70000>;
read-only;
};
partition@2 {
label = "uboot-env (spi)";
reg = <0x80000 0x20000>;
};
partition@3 {
label = "kernel (spi)";
reg = <0x100000 0x400000>;
};
partition@4 {
label = "swupdate (spi)";
reg = <0x50000 0x800000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SPL";
reg = <0x0 0x10000>;
read-only;
};
partition@10000 {
label = "u-boot";
reg = <0x10000 0x70000>;
read-only;
};
partition@80000 {
label = "uboot-env1";
reg = <0x80000 0x10000>;
};
partition@90000 {
label = "uboot-env2";
reg = <0x90000 0x10000>;
};
partition@A0000 {
label = "rescue";
reg = <0xA0000 0xF40000>;
};
partition@FE0000 {
label = "spl-boot-data1";
reg = <0xFE0000 0x10000>;
};
partition@FF0000 {
label = "spl-boot-data2";
reg = <0xFF0000 0x10000>;
};
};
};
};
&usb0 {
vbus-supply = <&reg_usb_5v>;
status = "okay";
};
&usbphy0 {
status = "okay";
};

1
arch/arm/dts/imx6dl-dhcom-pdk2.dts
View file

@ -6,6 +6,7 @@
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-dhcom-som.dtsi"
#include "imx6qdl-dhcom-pdk2.dtsi"
/ {

17
arch/arm/dts/imx6q-dhcom-pdk2.dts
View file

@ -1,20 +1,25 @@
// SPDX-License-Identifier: (GPL-2.0+)
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015-2019 DH electronics GmbH
* Copyright (C) 2015-2021 DH electronics GmbH
* Copyright (C) 2018 Marek Vasut <marex@denx.de>
*
* DHCOM iMX6 variant:
* DHCM-iMX6Q-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2
* DHCOM PCB number: 493-300 or newer
* PDK2 PCB number: 516-400 or newer
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-dhcom-som.dtsi"
#include "imx6qdl-dhcom-pdk2.dtsi"
/ {
model = "Freescale i.MX6 Quad/Dual DHCOM Premium Developer Kit (2)";
compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom", "fsl,imx6q";
model = "DH electronics i.MX6Q DHCOM on Premium Developer Kit (2)";
compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som",
"fsl,imx6q";
};
&sata {
status = "okay";
};

2
arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi
View file

@ -15,7 +15,7 @@
};
&fec {
phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-post-delay = <10>;

396
arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi
View file

@ -1,43 +1,225 @@
// SPDX-License-Identifier: (GPL-2.0+)
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015-2019 DH electronics GmbH
* Copyright (C) 2015-2021 DH electronics GmbH
* Copyright (C) 2018 Marek Vasut <marex@denx.de>
*/
#include "imx6qdl-dhcom.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/input/input.h>
/ {
chosen {
stdout-path = &uart1;
stdout-path = "serial0:115200n8";
};
clk_ext_audio_codec: clock-codec {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
compatible = "fixed-clock";
};
display_bl: display-bl {
brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
compatible = "pwm-backlight";
default-brightness-level = <8>;
enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; /* GPIO G */
pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>;
status = "okay";
};
lcd_display: disp0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "rgb24";
pinctrl-0 = <&pinctrl_ipu1_lcdif &pinctrl_dhcom_g>;
pinctrl-names = "default";
status = "okay";
port@0 {
reg = <0>;
lcd_display_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
port@1 {
reg = <1>;
lcd_display_out: endpoint {
remote-endpoint = <&lcd_panel_in>;
};
};
};
gpio-keys {
#size-cells = <0>;
compatible = "gpio-keys";
button-0 {
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* GPIO A */
label = "TA1-GPIO-A";
linux,code = <KEY_A>;
pinctrl-0 = <&pinctrl_dhcom_a>;
pinctrl-names = "default";
wakeup-source;
};
button-1 {
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* GPIO B */
label = "TA2-GPIO-B";
linux,code = <KEY_B>;
pinctrl-0 = <&pinctrl_dhcom_b>;
pinctrl-names = "default";
wakeup-source;
};
button-2 {
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; /* GPIO C */
label = "TA3-GPIO-C";
linux,code = <KEY_C>;
pinctrl-0 = <&pinctrl_dhcom_c>;
pinctrl-names = "default";
wakeup-source;
};
button-3 {
gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; /* GPIO D */
label = "TA4-GPIO-D";
linux,code = <KEY_D>;
pinctrl-0 = <&pinctrl_dhcom_d>;
pinctrl-names = "default";
wakeup-source;
};
};
led {
compatible = "gpio-leds";
/*
* Disable led-5, because GPIO E is
* already used as touch interrupt.
*/
led-5 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */
pinctrl-0 = <&pinctrl_dhcom_e>;
pinctrl-names = "default";
status = "disabled";
};
led-6 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */
pinctrl-0 = <&pinctrl_dhcom_f>;
pinctrl-names = "default";
};
led-7 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */
pinctrl-0 = <&pinctrl_dhcom_h>;
pinctrl-names = "default";
};
led-8 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
pinctrl-0 = <&pinctrl_dhcom_i>;
pinctrl-names = "default";
};
};
panel {
backlight = <&display_bl>;
compatible = "edt,etm0700g0edh6";
port {
lcd_panel_in: endpoint {
remote-endpoint = <&lcd_display_out>;
};
};
};
sound {
compatible = "fsl,imx-audio-sgtl5000";
model = "imx-sgtl5000";
ssi-controller = <&ssi1>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"LINE_IN", "Line In Jack",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
compatible = "fsl,imx-audio-sgtl5000";
model = "imx-sgtl5000";
mux-ext-port = <3>;
mux-int-port = <1>;
ssi-controller = <&ssi1>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_ext>;
pinctrl-names = "default";
status = "okay";
};
&can1 {
status = "okay";
};
&can2 {
status = "disabled";
};
/* 1G ethernet */
/delete-node/ &ethphy0;
&fec {
phy-mode = "rgmii";
phy-handle = <&ethphy7>;
pinctrl-0 = <&pinctrl_enet_1G>;
pinctrl-names = "default";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy7: ethernet-phy@7 { /* KSZ 9021 */
compatible = "ethernet-phy-ieee802.3-c22";
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_ethphy7>;
pinctrl-names = "default";
reg = <7>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
rxc-skew-ps = <3000>;
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
rxdv-skew-ps = <0>;
txc-skew-ps = <3000>;
txd0-skew-ps = <0>;
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
txen-skew-ps = <0>;
};
};
};
&hdmi {
ddc-i2c-bus = <&i2c2>;
status = "okay";
@ -45,91 +227,35 @@
&i2c2 {
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
clocks = <&clk_ext_audio_codec>;
compatible = "fsl,sgtl5000";
reg = <0x0a>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
VDDIO-supply = <&sw2_reg>;
};
touchscreen@38 {
compatible = "edt,edt-ft5406";
interrupt-parent = <&gpio4>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
pinctrl-0 = <&pinctrl_dhcom_e>;
pinctrl-names = "default";
reg = <0x38>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_base &pinctrl_hog>;
pinctrl_hog: hog-grp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x400120b0
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0
MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x120b0
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0
MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x120b0
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x400120b0
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x400120b0
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x400120b0
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x400120b0
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x400120b0
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x400120b0
MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x400120b0
MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x400120b0
MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x400120b0
MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x400120b0
MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x400120b0
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x400120b0
MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x400120b0
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x400120b0
>;
};
pinctrl_audmux_ext: audmux-ext-grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
>;
};
pinctrl_enet_1G: enet-1G-grp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x000b0
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x000b1
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x000b1
>;
};
pinctrl_pcie: pcie-grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1
>;
};
&ipu1_di0_disp0 {
remote-endpoint = <&lcd_display_in>;
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>;
reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; /* GPIO J */
status = "okay";
};
&pwm1 {
status = "okay";
};
@ -137,6 +263,102 @@
status = "okay";
};
&usdhc3 {
&usdhc2 { /* SD card */
status = "okay";
};
&iomuxc {
pinctrl-0 = <
/*
* The following DHCOM GPIOs are used on this board.
* Therefore, they have been removed from the list below.
* A: key TA1
* B: key TA2
* C: key TA3
* D: key TA4
* E: touchscreen
* F: led6
* G: backlight enable
* H: led7
* I: led8
* J: PCIe reset
*/
&pinctrl_hog_base
&pinctrl_dhcom_k &pinctrl_dhcom_l
&pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
&pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
>;
pinctrl-names = "default";
pinctrl_audmux_ext: audmux-ext-grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
>;
};
pinctrl_enet_1G: enet-1G-grp {
fsl,pins = <
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
>;
};
pinctrl_ethphy7: ethphy7-grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0xb1 /* WOL */
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0xb0 /* Reset */
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0xb1 /* Int */
>;
};
pinctrl_ipu1_lcdif: ipu1-lcdif-grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38
>;
};
};

815
arch/arm/dts/imx6qdl-dhcom-som.dtsi Normal file
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@ -0,0 +1,815 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015-2021 DH electronics GmbH
* Copyright (C) 2018 Marek Vasut <marex@denx.de>
*/
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/input/input.h>
/ {
aliases {
i2c0 = &i2c2;
i2c1 = &i2c1;
i2c2 = &i2c3;
mmc0 = &usdhc2;
mmc1 = &usdhc3;
mmc2 = &usdhc4;
mmc3 = &usdhc1;
rtc0 = &rtc_i2c;
rtc1 = &snvs_rtc;
serial0 = &uart1;
serial1 = &uart5;
serial2 = &uart4;
serial3 = &uart2;
serial4 = &uart3;
};
memory@10000000 { /* Appropriate memory size will be filled by U-Boot */
device_type = "memory";
reg = <0x10000000 0x20000000>;
};
reg_3p3v: regulator-3P3V {
compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "3P3V";
};
reg_eth_vio: regulator-eth-vio {
compatible = "regulator-fixed";
gpio = <&gpio1 7 0>;
pinctrl-0 = <&pinctrl_enet_vio>;
pinctrl-names = "default";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "eth_vio";
vin-supply = <&sw2_reg>;
};
/* OE pin of the latch is low active */
reg_latch_oe_on: regulator-latch-oe-on {
compatible = "regulator-fixed";
gpio = <&gpio3 22 0>;
regulator-always-on;
regulator-name = "latch_oe_on";
};
reg_usb_h1_vbus: regulator-usb-h1-vbus {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 31 0>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "usb_h1_vbus";
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "usb_otg_vbus";
};
};
&can1 {
pinctrl-0 = <&pinctrl_flexcan1>;
pinctrl-names = "default";
status = "okay";
};
/*
* Special SoM hardware required which uses the pins from micro SD card. The
* pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
* Tx and Rx are routed to the DHCOM UART1 rts/cts pins. So to enable can2 on
* the board device tree file, the micro SD card must be disabled and the uart1
* rts/cts must be disabled or output on other DHCOM pins.
*/
&can2 {
pinctrl-0 = <&pinctrl_flexcan2>;
pinctrl-names = "default";
status = "disabled";
};
&ecspi1 {
cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_ecspi1>;
pinctrl-names = "default";
status = "okay";
flash@0 { /* S25FL116K */
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
m25p,fast-read;
reg = <0>;
spi-max-frequency = <50000000>;
};
};
&ecspi2 {
cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_ecspi2>;
pinctrl-names = "default";
status = "disabled";
};
&fec {
phy-mode = "rmii";
phy-handle = <&ethphy0>;
pinctrl-0 = <&pinctrl_enet_100M>;
pinctrl-names = "default";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */
compatible = "ethernet-phy-ieee802.3-c22";
interrupt-parent = <&gpio4>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_ethphy0>;
pinctrl-names = "default";
reg = <0>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
smsc,disable-energy-detect; /* Make plugin detection reliable */
};
};
};
&gpio1 {
gpio-line-names =
"", "", "DHCOM-A", "", "DHCOM-B", "DHCOM-C", "", "",
"", "", "", "", "", "", "", "",
"DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio2 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"SOM-HW2", "", "", "SOM-HW0", "", "SOM-MEM1", "SOM-MEM0", "",
"", "", "", "", "", "", "", "";
};
&gpio3 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "DHCOM-G", "", "", "", "";
};
&gpio4 {
gpio-line-names =
"", "", "", "", "", "DHCOM-E", "DHCOM-INT", "DHCOM-H",
"DHCOM-I", "DHCOM-L", "", "", "", "", "", "",
"", "", "", "", "DHCOM-F", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio5 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "DHCOM-V", "DHCOM-W", "", "DHCOM-O", "", "",
"", "", "", "", "", "", "", "";
};
&gpio6 {
gpio-line-names =
"", "", "", "DHCOM-D", "", "", "SOM-HW1", "",
"", "", "", "", "", "", "DHCOM-J", "DHCOM-K",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio7 {
gpio-line-names =
"DHCOM-M", "DHCOM-N", "", "", "", "", "", "",
"", "", "", "", "", "DHCOM-P", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&i2c1 {
/*
* Info: According to erratum ERR007805 clock frequency limit is 375000.
* The erratum for i.MX6S/DL is here [1] and for i.MX6Q/D is here [2].
* [1] https://www.nxp.com/docs/en/errata/IMX6SDLCE.pdf
* [2] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
*/
clock-frequency = <100000>;
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
pinctrl-names = "default", "gpio";
scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c2 {
/* Info: Clock frequency limit is 375000 (for details see i2c1) */
clock-frequency = <100000>;
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
pinctrl-names = "default", "gpio";
scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c3 {
/* Info: Clock frequency limit is 375000 (for details see i2c1) */
clock-frequency = <100000>;
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
pinctrl-names = "default", "gpio";
scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
ltc3676: pmic@3c {
compatible = "lltc,ltc3676";
interrupt-parent = <&gpio5>;
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&pinctrl_pmic>;
pinctrl-names = "default";
reg = <0x3c>;
regulators {
sw1_reg: sw1 {
lltc,fb-voltage-divider = <100000 110000>;
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1527272>;
regulator-min-microvolt = <787500>;
regulator-ramp-delay = <7000>;
regulator-suspend-mem-microvolt = <1040000>;
};
sw2_reg: sw2 {
lltc,fb-voltage-divider = <100000 28000>;
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3657142>;
regulator-min-microvolt = <1885714>;
regulator-ramp-delay = <7000>;
};
sw3_reg: sw3 {
lltc,fb-voltage-divider = <100000 110000>;
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1527272>;
regulator-min-microvolt = <787500>;
regulator-ramp-delay = <7000>;
regulator-suspend-mem-microvolt = <980000>;
};
sw4_reg: sw4 {
lltc,fb-voltage-divider = <100000 93100>;
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1659291>;
regulator-min-microvolt = <855571>;
regulator-ramp-delay = <7000>;
};
ldo1_reg: ldo1 {
lltc,fb-voltage-divider = <102000 29400>;
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3240306>;
regulator-min-microvolt = <3240306>;
};
ldo2_reg: ldo2 {
lltc,fb-voltage-divider = <100000 41200>;
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <2484708>;
regulator-min-microvolt = <2484708>;
};
};
};
touchscreen@49 { /* TSC2004 */
compatible = "ti,tsc2004";
interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&pinctrl_tsc2004>;
pinctrl-names = "default";
reg = <0x49>;
vio-supply = <&reg_3p3v>;
status = "disabled";
};
eeprom@50 {
compatible = "atmel,24c02";
pagesize = <16>;
reg = <0x50>;
};
rtc_i2c: rtc@56 {
compatible = "microcrystal,rv3029";
interrupt-parent = <&gpio7>;
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&pinctrl_rtc>;
pinctrl-names = "default";
reg = <0x56>;
};
};
&pcie {
pinctrl-0 = <&pinctrl_pcie>;
pinctrl-names = "default";
};
&pwm1 {
pinctrl-0 = <&pinctrl_pwm1>;
pinctrl-names = "default";
};
&reg_arm {
vin-supply = <&sw3_reg>;
};
&reg_pu {
vin-supply = <&sw1_reg>;
};
&reg_soc {
vin-supply = <&sw1_reg>;
};
&reg_vdd1p1 {
vin-supply = <&sw2_reg>;
};
&reg_vdd2p5 {
vin-supply = <&sw2_reg>;
};
&uart1 { /* DHCOM UART1 */
dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_uart1>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&uart4 { /* DHCOM UART3 */
pinctrl-0 = <&pinctrl_uart4>;
pinctrl-names = "default";
status = "okay";
};
&uart5 { /* DHCOM UART2 */
pinctrl-0 = <&pinctrl_uart5>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&usbh1 {
dr_mode = "host";
pinctrl-0 = <&pinctrl_usbh1>;
pinctrl-names = "default";
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usbotg {
disable-over-current;
dr_mode = "otg";
pinctrl-0 = <&pinctrl_usbotg>;
pinctrl-names = "default";
vbus-supply = <&reg_usb_otg_vbus>;
status = "okay";
};
&usdhc2 { /* External SD card via DHCOM */
cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
keep-power-in-suspend;
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-names = "default";
status = "disabled";
};
&usdhc3 { /* Micro SD card on module */
cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
fsl,wp-controller;
keep-power-in-suspend;
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-names = "default";
status = "okay";
};
&usdhc4 { /* eMMC on module */
bus-width = <8>;
keep-power-in-suspend;
no-1-8-v;
non-removable;
pinctrl-0 = <&pinctrl_usdhc4>;
pinctrl-names = "default";
status = "okay";
};
&weim {
#address-cells = <2>;
#size-cells = <1>;
fsl,weim-cs-gpr = <&gpr>;
pinctrl-0 = <&pinctrl_weim &pinctrl_weim_cs0 &pinctrl_weim_cs1>;
pinctrl-names = "default";
/* It is necessary to setup 2x 64MB otherwise setting gpr fails */
ranges = <0 0 0x08000000 0x04000000>, /* CS0 */
<1 0 0x0c000000 0x04000000>; /* CS1 */
status = "disabled";
};
&iomuxc {
pinctrl-0 = <
&pinctrl_hog_base
&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
&pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
&pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
&pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
&pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
&pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
>;
pinctrl-names = "default";
pinctrl_hog_base: hog-base-grp {
fsl,pins = <
/* GPIOs for memory coding */
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x120b0
MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x120b0
/* GPIOs for hardware coding */
MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x120b0
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x120b0
MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x120b0
>;
};
/* DHCOM GPIOs */
pinctrl_dhcom_a: dhcom-a-grp {
fsl,pins = <MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x400120b0>;
};
pinctrl_dhcom_b: dhcom-b-grp {
fsl,pins = <MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0>;
};
pinctrl_dhcom_c: dhcom-c-grp {
fsl,pins = <MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0>;
};
pinctrl_dhcom_d: dhcom-d-grp {
fsl,pins = <MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0>;
};
pinctrl_dhcom_e: dhcom-e-grp {
fsl,pins = <MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x400120b0>;
};
pinctrl_dhcom_f: dhcom-f-grp {
fsl,pins = <MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0>;
};
pinctrl_dhcom_g: dhcom-g-grp {
fsl,pins = <MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400120b0>;
};
pinctrl_dhcom_h: dhcom-h-grp {
fsl,pins = <MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x400120b0>;
};
pinctrl_dhcom_i: dhcom-i-grp {
fsl,pins = <MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0>;
};
pinctrl_dhcom_j: dhcom-j-grp {
fsl,pins = <MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0>;
};
pinctrl_dhcom_k: dhcom-k-grp {
fsl,pins = <MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x400120b0>;
};
pinctrl_dhcom_l: dhcom-l-grp {
fsl,pins = <MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x400120b0>;
};
pinctrl_dhcom_m: dhcom-m-grp {
fsl,pins = <MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x400120b0>;
};
pinctrl_dhcom_n: dhcom-n-grp {
fsl,pins = <MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x400120b0>;
};
pinctrl_dhcom_o: dhcom-o-grp {
fsl,pins = <MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x400120b0>;
};
pinctrl_dhcom_p: dhcom-p-grp {
fsl,pins = <MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x400120b0>;
};
pinctrl_dhcom_q: dhcom-q-grp {
fsl,pins = <MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x400120b0>;
};
pinctrl_dhcom_r: dhcom-r-grp {
fsl,pins = <MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x400120b0>;
};
pinctrl_dhcom_s: dhcom-s-grp {
fsl,pins = <MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x400120b0>;
};
pinctrl_dhcom_t: dhcom-t-grp {
fsl,pins = <MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x400120b0>;
};
pinctrl_dhcom_u: dhcom-u-grp {
fsl,pins = <MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x400120b0>;
};
pinctrl_dhcom_v: dhcom-v-grp {
fsl,pins = <MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x400120b0>;
};
pinctrl_dhcom_w: dhcom-w-grp {
fsl,pins = <MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x400120b0>;
};
pinctrl_dhcom_int: dhcom-int-grp {
fsl,pins = <MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x400120b0>;
};
pinctrl_ecspi1: ecspi1-grp {
fsl,pins = <
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
>;
};
pinctrl_ecspi2: ecspi2-grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0
>;
};
pinctrl_enet_100M: enet-100M-grp {
fsl,pins = <
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
pinctrl_enet_vio: enet-vio-grp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0
>;
};
pinctrl_ethphy0: ethphy0-grp {
fsl,pins = <
MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0xb0 /* Reset */
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0xb1 /* Int */
>;
};
pinctrl_flexcan1: flexcan1-grp {
fsl,pins = <
MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
>;
};
pinctrl_flexcan2: flexcan2-grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
>;
};
pinctrl_i2c1: i2c1-grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2-grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c2_gpio: i2c2-gpio-grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3-grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_i2c3_gpio: i2c3-gpio-grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
>;
};
pinctrl_pcie: pcie-grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* Wake */
>;
};
pinctrl_pmic: pmic-grp {
fsl,pins = <
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
>;
};
pinctrl_pwm1: pwm1-grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
>;
};
pinctrl_rtc: rtc-grp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x120b0
>;
};
pinctrl_tsc2004: tsc2004-grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x120b0
>;
};
pinctrl_uart1: uart1-grp {
fsl,pins = <
MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x4001b0b1
MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x4001b0b1
MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x4001b0b1
MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x4001b0b1
MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x4001b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
>;
};
pinctrl_uart4: uart4-grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
>;
};
pinctrl_uart5: uart5-grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x4001b0b1
>;
};
pinctrl_usbh1: usbh1-grp {
fsl,pins = <
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120b0
>;
};
pinctrl_usbotg: usbotg-grp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
>;
};
pinctrl_usdhc2: usdhc2-grp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x120b0
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
pinctrl_usdhc3: usdhc3-grp {
fsl,pins = <
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x120b0
>;
};
pinctrl_usdhc4: usdhc4-grp {
fsl,pins = <
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
pinctrl_weim: weim-grp {
fsl,pins = <
MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0a6
MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0a6
MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0a6
MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0a6
MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0a6
MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0a6
MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0a6
MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0a6
MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0a6
MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0a6
MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0a6
MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0a6
MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0a6
MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0a6
MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0a6
MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0a6
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0
MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb060 /* LE */
MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0a6
MX6QDL_PAD_EIM_RW__EIM_RW 0xb0a6 /* WE */
>;
};
pinctrl_weim_cs0: weim-cs0-grp {
fsl,pins = <
MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
>;
};
pinctrl_weim_cs1: weim-cs1-grp {
fsl,pins = <
MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
>;
};
};

6
arch/arm/dts/imx6qdl.dtsi
View file

@ -686,7 +686,7 @@
<0 54 IRQ_TYPE_LEVEL_HIGH>,
<0 127 IRQ_TYPE_LEVEL_HIGH>;
regulator-1p1 {
reg_vdd1p1: regulator-1p1 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <1000000>;
@ -701,7 +701,7 @@
anatop-enable-bit = <0>;
};
regulator-3p0 {
reg_vdd3p0: regulator-3p0 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
@ -716,7 +716,7 @@
anatop-enable-bit = <0>;
};
regulator-2p5 {
reg_vdd2p5: regulator-2p5 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2250000>;

2
arch/arm/dts/imx6ull-pinfunc.h
View file

@ -82,6 +82,6 @@
#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA07__ESAI_TX0 0x0200 0x048C 0x0000 0x9 0x0
#endif /* __DTS_IMX6ULL_PINFUNC_H */

37
arch/arm/dts/imx7ulp-com-u-boot.dtsi Normal file
View file

@ -0,0 +1,37 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright 2019 Foundries.io
*/
&iomuxc1 {
u-boot,dm-spl;
};
&ahbbridge0 {
u-boot,dm-spl;
};
&ahbbridge1 {
u-boot,dm-spl;
};
&lpuart4 {
u-boot,dm-spl;
};
&usbotg1 {
extcon = <&usbphy1>;
u-boot,dm-spl;
};
&usbphy1 {
u-boot,dm-spl;
};
&usdhc0 {
u-boot,dm-spl;
};
&gpio0 {
u-boot,dm-spl;
};

1
arch/arm/dts/imx7ulp-com.dts
View file

@ -6,6 +6,7 @@
/dts-v1/;
#include "imx7ulp.dtsi"
#include "imx7ulp-com-u-boot.dtsi"
/ {
model = "Embedded Artists i.MX7ULP COM";

36
arch/arm/dts/imx8mm-beacon-baseboard.dtsi
View file

@ -43,6 +43,17 @@
enable-active-high;
};
reg_usbotg1: regulator-usbotg1 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb_otg1>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
@ -102,7 +113,6 @@
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
clock-names = "xclk";
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
@ -170,6 +180,24 @@
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usbotg1>;
disable-over-current;
dr_mode="otg";
status = "okay";
};
&usbotg2 {
pinctrl-names = "default";
disable-over-current;
dr_mode="host";
status = "okay";
};
&usbphynop2 {
reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
@ -216,6 +244,12 @@
>;
};
pinctrl_reg_usb_otg1: usbotg1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6

4
arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
View file

@ -77,6 +77,10 @@
u-boot,dm-spl;
};
&usbotg1 {
dr_mode="host";
};
&usdhc2 {
u-boot,dm-spl;
};

7
arch/arm/dts/imx8mm-beacon-som.dtsi
View file

@ -91,7 +91,7 @@
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <80000000>;
spi-tx-bus-width = <4>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
};
};
@ -256,12 +256,13 @@
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <4>;
non-removable;
cap-power-off-card;
pm-ignore-notify;
keep-power-in-suspend;
mmc-pwrseq = <&usdhc1_pwrseq>;
status = "okay";

30
arch/arm/dts/imx8mm-cl-iot-gate-ied-adc0.dts Normal file
View file

@ -0,0 +1,30 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 Linaro
*/
/dts-v1/;
/plugin/;
&{/} {
vref_adc: regulator-vref-adc {
compatible = "regulator-fixed";
regulator-name = "vref_adc";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <2400000>;
regulator-always-on;
};
};
&ecspi2 {
#address-cells = <1>;
#size-cells = <0>;
adc0: adc@0 {
compatible = "maxim,max11108";
reg = <0>;
vref-supply = <&vref_adc>;
spi-max-frequency = <20000000>;
status = "okay";
};
};

30
arch/arm/dts/imx8mm-cl-iot-gate-ied-adc1.dts Normal file
View file

@ -0,0 +1,30 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 Linaro
*/
/dts-v1/;
/plugin/;
&{/} {
vref_adc: regulator-vref-adc {
compatible = "regulator-fixed";
regulator-name = "vref_adc";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <2400000>;
regulator-always-on;
};
};
&ecspi3 {
#address-cells = <1>;
#size-cells = <0>;
adc1: adc@0 {
compatible = "maxim,max11108";
reg = <0>;
vref-supply = <&vref_adc>;
spi-max-frequency = <20000000>;
status = "okay";
};
};

53
arch/arm/dts/imx8mm-cl-iot-gate-ied-can0.dts Normal file
View file

@ -0,0 +1,53 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 Linaro
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx8mm-pinfunc.h"
&{/} {
clocks {
#address-cells = <1>;
#size-cells = <0>;
clk40m: clk@1 {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-frequency = <40000000>;
clock-output-names = "clk40m";
};
};
};
&ecspi2 {
#address-cells = <1>;
#size-cells = <0>;
can0: can@0 {
compatible = "microchip,mcp2518fd";
reg = <0>;
microchip,rx-int = <&gpio4 31 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0>;
interrupt-parent = <&gpio5>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
spi-max-frequency = <20000000>;
clocks = <&clk40m>;
status = "okay";
};
};
&iomuxc {
pinctrl_can0: can0grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x00
MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00
>;
};
};

53
arch/arm/dts/imx8mm-cl-iot-gate-ied-can1.dts Normal file
View file

@ -0,0 +1,53 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 Linaro
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx8mm-pinfunc.h"
&{/} {
clocks {
#address-cells = <1>;
#size-cells = <0>;
clk40m: clk@1 {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-frequency = <40000000>;
clock-output-names = "clk40m";
};
};
};
&ecspi3 {
#address-cells = <1>;
#size-cells = <0>;
can1: can@0 {
compatible = "microchip,mcp2518fd";
reg = <0>;
microchip,rx-int = <&gpio5 28 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1>;
interrupt-parent = <&gpio5>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
spi-max-frequency = <20000000>;
clocks = <&clk40m>;
status = "okay";
};
};
&iomuxc {
pinctrl_can1: can1grp {
fsl,pins = <
MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x00
MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x00
>;
};
};

45
arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm0.dts Normal file
View file

@ -0,0 +1,45 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 Linaro
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include "imx8mm-pinfunc.h"
&{/} {
regulatot-tpm0-rst {
compatible = "regulator-fixed";
regulator-name = "tpm0-rst";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>;
regulator-always-on;
enable-active-high;
};
};
&ecspi2 {
#address-cells = <1>;
#size-cells = <0>;
tpm0: tpm@0 {
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm0>;
spi-max-frequency = <5000000>;
status = "okay";
};
};
&iomuxc {
pinctrl_tpm0: tpm0grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x0
>;
};
};

45
arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm1.dts Normal file
View file

@ -0,0 +1,45 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 Linaro
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include "imx8mm-pinfunc.h"
&{/} {
regulator-tpm1-rst {
compatible = "regulator-fixed";
regulator-name = "tpm1-rst";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>;
regulator-always-on;
enable-active-high;
};
};
&ecspi3 {
#address-cells = <1>;
#size-cells = <0>;
tpm1: tpm@0 {
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm1>;
spi-max-frequency = <5000000>;
status = "disabled";
};
};
&iomuxc {
pinctrl_tpm1: tpm1grp {
fsl,pins = <
MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x0
>;
};
};

85
arch/arm/dts/imx8mm-cl-iot-gate-ied.dts Normal file
View file

@ -0,0 +1,85 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 Linaro
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include "imx8mm-pinfunc.h"
&ecspi1 {
#address-cells = <1>;
#size-cells = <0>;
fsl,spi-num-chipselects = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
};
&ecspi2 {
#address-cells = <1>;
#size-cells = <0>;
fsl,spi-num-chipselects = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
};
&ecspi3 {
#address-cells = <1>;
#size-cells = <0>;
fsl,spi-num-chipselects = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
status = "okay";
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
>;
};
pinctrl_ecspi1_cs: ecspi1cs {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x02
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x02
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x102
>;
};
pinctrl_ecspi2_cs: ecspi2_csgrp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x02
MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x02
MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x102
>;
};
pinctrl_ecspi3_cs: ecspi3_csgrp {
fsl,pins = <
MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40000
>;
};
};

6
arch/arm/dts/imx8mm-kontron-n801x-s-lvds-u-boot.dtsi Normal file
View file

@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Kontron Electronics GmbH
*/
#include "imx8mm-kontron-n801x-u-boot.dtsi"

124
arch/arm/dts/imx8mm-kontron-n801x-s-u-boot.dtsi
View file

@ -3,126 +3,4 @@
* Copyright (C) 2019 Kontron Electronics GmbH
*/
#include "imx8mm-u-boot.dtsi"
/ {
aliases {
usb0 = &usbotg1;
usb1 = &usbotg2;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
&fec1 {
phy-mode = "rgmii-rxid";
};
&i2c1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&i2c2 {
status = "okay";
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&pinctrl_ecspi1 {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
/* Disable Pullup for SD_VSEL */
MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x41
>;
};
&pinctrl_uart3 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&pinctrl_usdhc1 {
u-boot,dm-spl;
};
&pinctrl_usdhc1_100mhz {
u-boot,dm-spl;
};
&pinctrl_usdhc1_200mhz {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&pca9450 {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
u-boot,dm-spl;
};
&ecspi1 {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&uart3 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&usdhc1 {
u-boot,dm-spl;
};
&usdhc2 {
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};
#include "imx8mm-kontron-n801x-u-boot.dtsi"

128
arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi Normal file
View file

@ -0,0 +1,128 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Kontron Electronics GmbH
*/
#include "imx8mm-u-boot.dtsi"
/ {
aliases {
usb0 = &usbotg1;
usb1 = &usbotg2;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
&fec1 {
phy-mode = "rgmii-rxid";
};
&i2c1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&i2c2 {
status = "okay";
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&pinctrl_ecspi1 {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
/* Disable Pullup for SD_VSEL */
MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x41
>;
};
&pinctrl_uart3 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&pinctrl_usdhc1 {
u-boot,dm-spl;
};
&pinctrl_usdhc1_100mhz {
u-boot,dm-spl;
};
&pinctrl_usdhc1_200mhz {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&pca9450 {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
u-boot,dm-spl;
};
&ecspi1 {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&uart3 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&usdhc1 {
u-boot,dm-spl;
};
&usdhc2 {
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};

3
arch/arm/dts/imx8mm-pinfunc.h
View file

@ -124,7 +124,7 @@
#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
@ -248,6 +248,7 @@
#define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x134 0x39C 0x000 0x2 0x0
#define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0

12
arch/arm/dts/imx8mm-u-boot.dtsi
View file

@ -45,19 +45,19 @@
type = "blob-ext";
};
1d_dmem {
1d-dmem {
filename = "lpddr4_pmu_train_1d_dmem.bin";
size = <0x4000>;
type = "blob-ext";
};
2d_imem {
2d-imem {
filename = "lpddr4_pmu_train_2d_imem.bin";
size = <0x8000>;
type = "blob-ext";
};
2d_dmem {
2d-dmem {
filename = "lpddr4_pmu_train_2d_dmem.bin";
size = <0x4000>;
type = "blob-ext";
@ -93,7 +93,7 @@
load = <CONFIG_SYS_TEXT_BASE>;
type = "standalone";
uboot_blob {
uboot-blob {
filename = "u-boot-nodtb.bin";
type = "blob-ext";
};
@ -107,7 +107,7 @@
load = <0x920000>;
type = "firmware";
atf_blob {
atf-blob {
filename = "bl31.bin";
type = "blob-ext";
};
@ -126,7 +126,7 @@
description = "NAME";
type = "flat_dt";
uboot_fdt_blob {
uboot-fdt-blob {
filename = "u-boot.dtb";
type = "blob-ext";
};

2
arch/arm/dts/imx8mm-venice-gw7902.dts
View file

@ -651,7 +651,7 @@
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* M2_RST# */
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */
MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */

46
arch/arm/dts/imx8mm.dtsi
View file

@ -510,7 +510,7 @@
};
gpr: iomuxc-gpr@30340000 {
compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
@ -1041,6 +1041,19 @@
reg = <0x32e50200 0x200>;
};
pcie_phy: pcie-phy@32f00000 {
compatible = "fsl,imx8mm-pcie-phy";
reg = <0x32f00000 0x10000>;
clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
clock-names = "ref";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
assigned-clock-rates = <100000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
resets = <&src IMX8MQ_RESET_PCIEPHY>;
reset-names = "pciephy";
#phy-cells = <0>;
status = "disabled";
};
};
dma_apbh: dma-controller@33000000 {
@ -1072,6 +1085,37 @@
status = "disabled";
};
pcie0: pcie@33800000 {
compatible = "fsl,imx8mm-pcie";
reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <2>;
linux,pci-domain = <0>;
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "apps", "turnoff";
phys = <&pcie_phy>;
phy-names = "pcie-phy";
status = "disabled";
};
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>, /* GIC Dist */

19
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
View file

@ -157,7 +157,9 @@
};
flash {
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
@ -224,4 +226,19 @@
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl: blob-ext@1 {
offset = <0x0>;
filename = "spl.bin";
};
uboot: blob-ext@2 {
offset = <0x58000>;
filename = "u-boot.itb";
};
};
};

256
arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi Normal file
View file

@ -0,0 +1,256 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Collabora Ltd.
*/
/ {
binman: binman {
multiple-images;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
};
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
u-boot,dm-spl;
};
&aips1 {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&aips3 {
u-boot,dm-spl;
};
&aips4 {
u-boot,dm-spl;
};
&clk {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&osc_24m {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
};
&pinctrl_reg_usdhc2_vmmc {
u-boot,dm-spl;
};
&pinctrl_uart4 {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&uart4 {
u-boot,dm-spl;
};
&usdhc2 {
u-boot,dm-spl;
};
&usdhc3 {
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};
&binman {
u-boot-spl-ddr {
align = <4>;
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
1d-imem {
filename = "ddr4_imem_1d.bin";
size = <0x8000>;
type = "blob-ext";
};
1d_dmem {
filename = "ddr4_dmem_1d.bin";
size = <0x4000>;
type = "blob-ext";
};
2d_imem {
filename = "ddr4_imem_2d.bin";
size = <0x8000>;
type = "blob-ext";
};
2d_dmem {
filename = "ddr4_dmem_2d.bin";
size = <0x4000>;
type = "blob-ext";
};
};
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
itb {
filename = "u-boot.itb";
fit {
description = "Configuration to load ATF before U-Boot";
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
fit,fdt-list = "of-list";
#address-cells = <1>;
images {
uboot {
arch = "arm64";
compression = "none";
description = "U-Boot (64-bit)";
load = <CONFIG_SYS_TEXT_BASE>;
type = "standalone";
uboot_blob {
filename = "u-boot-nodtb.bin";
type = "blob-ext";
};
};
atf {
arch = "arm64";
compression = "none";
description = "ARM Trusted Firmware";
entry = <0x960000>;
load = <0x960000>;
type = "firmware";
atf_blob {
filename = "bl31.bin";
type = "blob-ext";
};
};
binman_fip: fip {
arch = "arm64";
compression = "none";
description = "Trusted Firmware FIP";
load = <0x40310000>;
type = "firmware";
};
@fdt-SEQ {
compression = "none";
description = "NAME";
type = "flat_dt";
uboot_fdt_blob {
filename = "u-boot.dtb";
type = "blob-ext";
};
};
};
configurations {
default = "@config-DEFAULT-SEQ";
binman_configuration: @config-SEQ {
description = "NAME";
fdt = "fdt-SEQ";
firmware = "uboot";
loadables = "atf";
};
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl {
filename = "spl.bin";
offset = <0x0>;
type = "blob-ext";
};
binman_uboot: uboot {
filename = "u-boot.itb";
offset = <0x58000>;
type = "blob-ext";
};
};
};

240
arch/arm/dts/imx8mn-var-som-symphony.dts Normal file
View file

@ -0,0 +1,240 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019-2020 Variscite Ltd.
* Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
*/
/dts-v1/;
#include "imx8mn-var-som.dtsi"
/ {
model = "Variscite VAR-SOM-MX8MN Symphony evaluation board";
compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn";
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
gpio-keys {
compatible = "gpio-keys";
back {
label = "Back";
gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
home {
label = "Home";
gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
menu {
label = "Menu";
gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
};
};
leds {
compatible = "gpio-leds";
led {
label = "Heartbeat";
gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
};
&ethphy {
reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>;
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pca9534: gpio@20 {
compatible = "nxp,pca9534";
reg = <0x20>;
gpio-controller;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca9534>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
#gpio-cells = <2>;
wakeup-source;
/* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
usb3-sata-sel-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "usb3_sata_sel";
};
som-vselect-hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "som_vselect";
};
enet-sel-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "enet_sel";
};
};
extcon_usbotg1: typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
interrupt-parent = <&gpio1>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ptn5150>;
status = "okay";
};
};
&i2c3 {
/* Capacitive touch controller */
ft5x06_ts: touchscreen@38 {
compatible = "edt,edt-ft5406";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_captouch>;
interrupt-parent = <&gpio5>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
touchscreen-inverted-x;
touchscreen-inverted-y;
};
rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
};
};
/* Header */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* Header */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbotg1 {
disable-over-current;
extcon = <&extcon_usbotg1>, <&extcon_usbotg1>;
};
&pinctrl_fec1 {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
>;
};
&pinctrl_fec1_sleep {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
>;
};
&iomuxc {
pinctrl_captouch: captouchgrp {
fsl,pins = <
MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_pca9534: pca9534grp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16
>;
};
pinctrl_ptn5150: ptn5150grp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
};

547
arch/arm/dts/imx8mn-var-som.dtsi Normal file
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@ -0,0 +1,547 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
* Copyright 2019-2020 Variscite Ltd.
* Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include "imx8mn.dtsi"
/ {
model = "Variscite VAR-SOM-MX8MN module";
compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
chosen {
stdout-path = &uart4;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x40000000>;
};
reg_eth_phy: regulator-eth-phy {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_eth_phy>;
regulator-name = "eth_phy_pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&A53_0 {
cpu-supply = <&buck2_reg>;
};
&A53_1 {
cpu-supply = <&buck2_reg>;
};
&A53_2 {
cpu-supply = <&buck2_reg>;
};
&A53_3 {
cpu-supply = <&buck2_reg>;
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
<&gpio1 0 GPIO_ACTIVE_LOW>;
/delete-property/ dmas;
/delete-property/ dma-names;
status = "okay";
/* Resistive touch controller */
touchscreen@0 {
reg = <0>;
compatible = "ti,ads7846";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_restouch>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
spi-max-frequency = <1500000>;
pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
ti,x-min = /bits/ 16 <125>;
touchscreen-size-x = /bits/ 16 <4008>;
ti,y-min = /bits/ 16 <282>;
touchscreen-size-y = /bits/ 16 <3864>;
ti,x-plate-ohms = /bits/ 16 <180>;
touchscreen-max-pressure = /bits/ 16 <255>;
touchscreen-average-samples = /bits/ 16 <10>;
ti,debounce-tol = /bits/ 16 <3>;
ti,debounce-rep = /bits/ 16 <1>;
ti,settle-delay-usec = /bits/ 16 <150>;
ti,keep-vref-on;
wakeup-source;
};
};
&fec1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec1>;
pinctrl-1 = <&pinctrl_fec1_sleep>;
phy-mode = "rgmii";
phy-handle = <&ethphy>;
phy-supply = <&reg_eth_phy>;
phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@4b {
compatible = "rohm,bd71847";
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio2>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
rohm,reset-snvs-powered;
regulators {
buck1_reg: BUCK1 {
regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
};
buck2_reg: BUCK2 {
regulator-name = "buck2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
};
buck3_reg: BUCK3 {
regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
buck4_reg: BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <2600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck5_reg: BUCK5 {
regulator-name = "buck5";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
regulator-always-on;
};
buck6_reg: BUCK6 {
regulator-name = "buck6";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: LDO1 {
regulator-name = "ldo1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1900000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: LDO2 {
regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: LDO3 {
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: LDO4 {
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo5_reg: LDO5 {
regulator-compatible = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo6_reg: LDO6 {
regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
/* TODO: configure audio, as of now just put a placeholder */
wm8904: codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
status = "disabled";
};
};
&snvs_pwrkey {
status = "okay";
};
/* Bluetooth */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MN_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
/* Console */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
dr_mode = "peripheral";
status = "okay";
};
/* WIFI */
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <4>;
non-removable;
keep-power-in-suspend;
status = "okay";
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SD */
&usdhc2 {
assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
/* eMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13
MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_fec1_sleep: fec1sleepgrp {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141
>;
};
pinctrl_reg_eth_phy: regethphygrp {
fsl,pins = <
MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41
>;
};
pinctrl_restouch: restouchgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
>;
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
* Copyright 2022 Linaro
*/
#include "imx8mp-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
&iomuxc {
u-boot,dm-spl;
};
&reg_usdhc2_vmmc {
u-boot,dm-spl;
};
&pinctrl_uart2 {
u-boot,dm-spl;
};
&pinctrl_uart3 {
u-boot,dm-spl;
};
&pinctrl_usdhc2_gpio {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&uart2 {
u-boot,dm-spl;
};
&uart3 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
&i2c2 {
u-boot,dm-spl;
};
&i2c3 {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&pinctrl_i2c1_gpio {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
};
&usdhc2 {
u-boot,dm-spl;
sd-uhs-sdr104;
sd-uhs-ddr50;
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
assigned-clock-rates = <400000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
};
&usdhc3 {
u-boot,dm-spl;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
};
&binman {
itb {
fit {
images {
fip {
description = "Trusted Firmware FIP";
type = "firmware";
arch = "arm64";
compression = "none";
load = <0x40310000>;
fip_blob: blob-ext{
filename = "fip.bin";
};
};
};
configurations {
conf {
loadables = "atf", "fip";
};
};
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
* Copyright 2022 Linaro
*/
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx8mp.dtsi"
/ {
model = "Advantech i.MX8MPlus RSB3720A1 board";
compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
aliases {
rtc0 = &s35390a;
rtc1 = &snvs_rtc;
};
chosen {
stdout-path = &uart3;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0xc0000000>,
<0x1 0x00000000 0 0xc0000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
rpmsg_reserved: rpmsg@0x55800000 {
no-map;
reg = <0 0x55800000 0 0x800000>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
user {
label = "user";
gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
default-state = "off"; /* LED BLUE */
};
};
reg_usb1_host_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1_host_vbus";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_vbus>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_usdhc1_vmmc: regulator-usdhc1 {
compatible = "regulator-fixed";
regulator-name = "WLAN_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100>;
off-on-delay-us = <12000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
//gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100>;
off-on-delay-us = <12000>;
};
lvds_backlight0: lvds_backlight@0 {
compatible = "pwm-backlight";
pwms = <&pwm2 0 5000000>;
status = "disabled";
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <80>;
};
lvds_backlight1: lvds_backlight@1 {
compatible = "pwm-backlight";
pwms = <&pwm3 0 5000000>;
status = "disabled";
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <80>;
};
rtl8367 {
compatible = "realtek,rtl8367b";
pinctrl-names = "default";
gpio-sda = <&gpio5 10 GPIO_ACTIVE_HIGH>;
gpio-sck = <&gpio5 11 GPIO_ACTIVE_HIGH>;
realtek,extif0 = <1 0 1 1 1 1 1 1 2>;
};
};
&clk {
init-on-array = <IMX8MP_CLK_HSIO_ROOT>;
};
&A53_0 {
cpu-supply = <&buck2_reg>;
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
at803x,eee-disabled;
at803x,vddio-1p8v;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
status = "okay";
pmic: pca9450@25 {
reg = <0x25>;
compatible = "nxp,pca9450c", "nxp,pca9450b", "nxp,pca9450";
/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
pinctrl-0 = <&pinctrl_pmic>;
gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
regulators {
#address-cells = <1>;
#size-cells = <0>;
pca9450,pmic-buck2-uses-i2c-dvs;
/* Run/Standby voltage */
pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
buck1_reg: regulator@0 {
reg = <0>;
regulator-compatible = "buck1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2_reg: regulator@1 {
reg = <1>;
regulator-compatible = "buck2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck4_reg: regulator@3 {
reg = <3>;
regulator-compatible = "buck4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5_reg: regulator@4 {
reg = <4>;
regulator-compatible = "buck5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6_reg: regulator@5 {
reg = <5>;
regulator-compatible = "buck6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: regulator@6 {
reg = <6>;
regulator-compatible = "ldo1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: regulator@7 {
reg = <7>;
regulator-compatible = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: regulator@8 {
reg = <8>;
regulator-compatible = "ldo3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: regulator@9 {
reg = <9>;
regulator-compatible = "ldo4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5_reg: regulator@10 {
reg = <10>;
regulator-compatible = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
s35390a: s35390a@30 {
compatible = "sii,s35390a", "sii,s35392a";
reg = <0x30>;
status = "okay";
};
gpio_exp2: tca9538@71 {
compatible = "nxp,pca9538";
reg = <0x71>;
gpio-controller;
#gpio-cells = <2>;
};
gpio_exp1: tca9538@70 {
compatible = "nxp,pca9538";
reg = <0x70>;
gpio-controller;
#gpio-cells = <2>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
status = "okay";
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
status = "okay";
24c02@50 {
compatible = "fsl,24c02";
reg = <0x50>;
};
};
&snvs_pwrkey {
status = "okay";
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&uart1 { /* BT */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MP_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
/* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MP_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usb3_phy0 {
fsl,phy-tx-vref-tune = <6>;
fsl,phy-tx-rise-tune = <0>;
fsl,phy-tx-preemp-amp-tune = <3>;
fsl,phy-comp-dis-tune = <7>;
fsl,pcs-tx-deemph-3p5db = <0x21>;
fsl,phy-pcs-tx-swing-full = <0x7f>;
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "host";
status = "okay";
};
&usb3_phy1 {
fsl,phy-tx-preemp-amp-tune = <2>;
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
cqe-disabled;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "disabled";
};
&iomuxc {
pinctrl-names = "default";
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x116
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x400001c3
MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x400001c3
>;
};
pinctrl_i2c1_gpio: i2c1grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
>;
};
pinctrl_i2c2_gpio: i2c2grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3
>;
};
pinctrl_i2c3_gpio: i2c3grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3
>;
};
pinctrl_i2c4_gpio: i2c4_gpio_grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c3
MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c3
>;
};
pinctrl_pmic: pmicirq {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6
MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
>;
};
pinctrl_usb1_vbus: usb1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_gpio: usdhc1gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x19
MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x19
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_gpio: usdhc2grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>;
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
#include "imx8mp-u-boot.dtsi"
/ {
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
wdt-reboot {
compatible = "wdt-reboot";
u-boot,dm-spl;
wdt = <&wdog1>;
};
};
&clk {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&eqos {
compatible = "fsl,imx-eqos";
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
&i2c2 {
u-boot,dm-spl;
};
&i2c3 {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&pinctrl_reg_usdhc2_vmmc {
u-boot,dm-spl;
u-boot,off-on-delay-us = <20000>;
};
&pinctrl_uart3 {
u-boot,dm-spl;
};
&pinctrl_usdhc2_gpio {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&pmic {
u-boot,dm-spl;
};
&reg_usdhc2_vmmc {
u-boot,dm-spl;
};
&uart3 {
u-boot,dm-spl;
};
&usdhc2 {
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
assigned-clock-rates = <400000000>;
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
sd-uhs-ddr50;
sd-uhs-sdr104;
u-boot,dm-spl;
};
&usdhc3 {
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
assigned-clock-rates = <400000000>;
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx8mp.dtsi"
/ {
model = "Toradex Verdin iMX8M Plus";
compatible = "toradex,verdin-imx8mp", "fsl,imx8mp";
aliases {
eeprom0 = &eeprom_module;
eeprom1 = &eeprom_carrier;
eeprom2 = &eeprom_mipi_dsi;
/* Ethernet aliases to ensure correct MAC addresses */
ethernet0 = &eqos;
ethernet1 = &fec;
};
chosen {
bootargs = "console=ttymxc2,115200 earlycon";
stdout-path = &uart3;
};
reg_usb1_host_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; /* USB_2_EN */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_vbus>;
regulator-always-on;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "usb1_host_vbus";
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; /* SD_1_PWR_EN */
off-on-delay-us = <12000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "V3.3_SD";
startup-delay-us = <100>;
};
};
&eqos {
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <7>;
};
};
};
&fec {
fsl,magic-packet;
phy-handle = <&ethphy1>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <7>;
};
};
};
&gpio2 {
regulator-ethphy {
gpio-hog;
gpios = <20 GPIO_ACTIVE_HIGH>;
line-name = "reg_ethphy";
output-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_eth>;
};
ctrl_sleep_moci {
gpio-hog;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpios = <29 GPIO_ACTIVE_HIGH>;
line-name = "CTRL_SLEEP_MOCI#";
output-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
};
/* Verdin PMIC_I2C */
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
status = "okay";
pmic: pca9450@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
regulators {
#address-cells = <1>;
/* Run/Standby voltage */
pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
pca9450,pmic-buck2-uses-i2c-dvs;
#size-cells = <0>;
buck1_reg: regulator@0 {
reg = <0>;
regulator-always-on;
regulator-boot-on;
regulator-compatible = "buck1";
regulator-max-microvolt = <2187500>;
regulator-min-microvolt = <600000>;
regulator-ramp-delay = <3125>;
};
buck2_reg: regulator@1 {
reg = <1>;
regulator-always-on;
regulator-boot-on;
regulator-compatible = "buck2";
regulator-max-microvolt = <2187500>;
regulator-min-microvolt = <600000>;
regulator-ramp-delay = <3125>;
};
buck4_reg: regulator@3 {
reg = <3>;
regulator-always-on;
regulator-boot-on;
regulator-compatible = "buck4";
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
};
buck5_reg: regulator@4 {
reg = <4>;
regulator-always-on;
regulator-boot-on;
regulator-compatible = "buck5";
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
};
buck6_reg: regulator@5 {
reg = <5>;
regulator-always-on;
regulator-boot-on;
regulator-compatible = "buck6";
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
};
ldo1_reg: regulator@6 {
reg = <6>;
regulator-always-on;
regulator-boot-on;
regulator-compatible = "ldo1";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1600000>;
};
ldo2_reg: regulator@7 {
reg = <7>;
regulator-always-on;
regulator-boot-on;
regulator-compatible = "ldo2";
regulator-max-microvolt = <1150000>;
regulator-min-microvolt = <800000>;
};
ldo3_reg: regulator@8 {
reg = <8>;
regulator-always-on;
regulator-boot-on;
regulator-compatible = "ldo3";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <800000>;
};
ldo4_reg: regulator@9 {
reg = <9>;
regulator-always-on;
regulator-boot-on;
regulator-compatible = "ldo4";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <800000>;
};
ldo5_reg: regulator@10 { /* +V3.3_1.8_SD */
reg = <10>;
regulator-compatible = "ldo5";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
};
};
};
/* Epson RX8130 real time clock on carrier board */
rtc: rx8130@32 {
compatible = "epson,rx8130";
reg = <0x32>;
};
eeprom_module: eeprom@50 {
compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
pagesize = <16>;
reg = <0x50>;
};
};
/* Verdin I2C2 DSI */
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
status = "okay";
};
/* Verdin I2C4 CSI */
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
status = "okay";
pca6416: gpio@20 {
compatible = "ti,tca6416";
#gpio-cells = <2>;
gpio-controller;
reg = <0x20>;
};
};
/* Verdin I2C1 */
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
status = "okay";
/* EEPROM on MIPI-DSI to HDMI adapter */
eeprom_mipi_dsi: eeprom@50 {
compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
pagesize = <16>;
reg = <0x50>;
};
/* EEPROM on Verdin Development board */
eeprom_carrier: eeprom@57 {
compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
pagesize = <16>;
reg = <0x57>;
};
};
&snvs_pwrkey {
status = "okay";
};
/* Verdin UART3 */
&uart3 {
/* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb_dwc3_0 {
adp-disable;
dr_mode = "otg";
hnp-disable;
srp-disable;
usb-role-switch;
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
/* Verdin SDIO 1 */
&usdhc2 {
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
/* On-module eMMC */
&usdhc3 {
bus-width = <8>;
non-removable;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
status = "okay";
};
&wdog1 {
fsl,ext-reset-output;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, <&pinctrl_gpio3>,
<&pinctrl_gpio4>, <&pinctrl_gpio5>, <&pinctrl_gpio6>,
<&pinctrl_gpio7>, <&pinctrl_gpio8>;
pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c4 /* SODIMM 256 */
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
>;
};
/* (MEZ_)GPIO_1 shared with (MEZ_)DSI_1_INT# on Verdin Development Board */
pinctrl_gpio1: gpio1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184 /* SODIMM 206 */
>;
};
pinctrl_gpio2: gpio2grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x184 /* SODIMM 208 */
>;
};
pinctrl_gpio3: gpio3grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184 /* SODIMM 210 */
>;
};
pinctrl_gpio4: gpio4grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184 /* SODIMM 212 */
>;
};
pinctrl_gpio5: gpio5grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184 /* SODIMM 216 */
>;
};
pinctrl_gpio6: gpio6grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184 /* SODIMM 218 */
>;
};
pinctrl_gpio7: gpio7grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184 /* SODIMM 220 */
>;
};
pinctrl_gpio8: gpio8grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184 /* SODIMM 222 */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
>;
};
pinctrl_i2c1_gpio: i2c1grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
>;
};
pinctrl_i2c2_gpio: i2c2grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3
>;
};
pinctrl_i2c3_gpio: i2c3grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3
>;
};
pinctrl_i2c4_gpio: i2c4grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c3
MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c3
>;
};
pinctrl_reg_eth: regethgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x41
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49
MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49
>;
};
pinctrl_usb1_vbus: usb1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x1d1
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
fsl,pins = <
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x1d1
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
fsl,pins = <
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x1d1
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>;
};
};

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arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#include "imx8mq-u-boot.dtsi"
&usdhc1 {
mmc-hs400-1_8v;
};
&usdhc2 {
sd-uhs-sdr104;
sd-uhs-ddr50;
};

612
arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree File for the Kontron pitx-imx8m board.
*
* Copyright (C) 2021 Heiko Thiery <heiko.thiery@gmail.com>
*/
/dts-v1/;
#include "imx8mq.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
model = "Kontron pITX-imx8m";
compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
aliases {
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
spi0 = &qspi0;
spi1 = &ecspi2;
};
chosen {
stdout-path = "serial2:115200n8";
};
pcie0_refclk: pcie0-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pcie1_refclk: pcie1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2>;
regulator-name = "V_3V3_SD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&ecspi2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@0 {
compatible = "infineon,slb9670";
reg = <0>;
spi-max-frequency = <43000000>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
reset-assert-us = <10>;
reset-deassert-us = <280>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@8 {
compatible = "fsl,pfuze100";
fsl,pfuze-support-disable-sw;
reg = <0x8>;
regulators {
sw1a_reg: sw1ab {
regulator-name = "V_0V9_GPU";
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw1c_reg: sw1c {
regulator-name = "V_0V9_VPU";
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw2_reg: sw2 {
regulator-name = "V_1V1_NVCC_DRAM";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw3a_reg: sw3ab {
regulator-name = "V_1V0_DRAM";
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-name = "V_1V8_S0";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
swbst_reg: swbst {
regulator-name = "NC";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-name = "V_0V9_SNVS";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-name = "V_0V55_VREF_DDR";
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-name = "V_1V5_CSI";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-name = "V_0V9_PHY";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <975000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-name = "V_1V8_PHY";
regulator-min-microvolt = <1675000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-name = "V_1V8_VDDA";
regulator-min-microvolt = <1625000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-name = "V_3V3_PHY";
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3625000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-name = "V_2V8_CAM";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
fan-controller@1b {
compatible = "maxim,max6650";
reg = <0x1b>;
maxim,fan-microvolt = <5000000>;
};
rtc@32 {
compatible = "microcrystal,rv8803";
reg = <0x32>;
};
sensor@4b {
compatible = "national,lm75b";
reg = <0x4b>;
};
eeprom@51 {
compatible = "atmel,24c32";
reg = <0x51>;
pagesize = <32>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
/* M.2 B-key slot */
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&clk IMX8MQ_CLK_PCIE1_AUX>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
status = "okay";
};
/* Intel Ethernet Controller I210/I211 */
&pcie1 {
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_AUX>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie1_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
fsl,max-link-speed = <1>;
status = "okay";
};
&pgc_gpu {
power-supply = <&sw1a_reg>;
};
&pgc_vpu {
power-supply = <&sw1c_reg>;
};
&qspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
m25p,fast-read;
spi-max-frequency = <50000000>;
};
};
&snvs_pwrkey {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
maximum-speed = "high-speed";
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usdhc1 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vqmmc-supply = <&sw4_reg>;
bus-width = <8>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
&usdhc2 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* TPM Reset */
MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* USB2 Hub Reset */
>;
};
pinctrl_gpio: gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* GPIO0 */
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 /* GPIO1 */
MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* GPIO2 */
MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* GPIO3 */
MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* GPIO4 */
MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* GPIO5 */
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* GPIO6 */
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x19 /* GPIO7 */
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x16 /* PCIE_PERST */
MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 /* W_DISABLE */
>;
};
pinctrl_reg_usdhc2: regusdhc2gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19
MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19
MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19
>;
};
pinctrl_ecspi2_cs: ecspi2csgrp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49
MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x19
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usb0: usb0grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x19
MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

2
arch/arm/dts/imx8mq-pinfunc.h
View file

@ -130,7 +130,7 @@
#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0

59
arch/arm/dts/imx8mq-u-boot.dtsi
View file

@ -12,41 +12,47 @@
&binman {
u-boot-spl-ddr {
align = <4>;
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
align-size = <4>;
align = <4>;
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
blob_1: blob-ext@1 {
1d-imem {
filename = "lpddr4_pmu_train_1d_imem.bin";
size = <0x8000>;
type = "blob-ext";
};
blob_2: blob-ext@2 {
1d-dmem {
filename = "lpddr4_pmu_train_1d_dmem.bin";
size = <0x4000>;
type = "blob-ext";
};
blob_3: blob-ext@3 {
2d-imem {
filename = "lpddr4_pmu_train_2d_imem.bin";
size = <0x8000>;
type = "blob-ext";
};
blob_4: blob-ext@4 {
2d-dmem {
filename = "lpddr4_pmu_train_2d_dmem.bin";
size = <0x4000>;
type = "blob-ext";
};
};
signed_hdmi {
signed-hdmi {
filename = "signed_hdmi.bin";
blob_5: blob-ext@5 {
signed-hdmi-imx8m {
filename = "signed_hdmi_imx8m.bin";
type = "blob-ext";
};
};
@ -59,9 +65,7 @@
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
itb {
@ -69,42 +73,45 @@
fit {
description = "Configuration to load ATF before U-Boot";
#address-cells = <1>;
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
#address-cells = <1>;
images {
uboot {
description = "U-Boot (64-bit)";
type = "standalone";
arch = "arm64";
compression = "none";
description = "U-Boot (64-bit)";
load = <CONFIG_SYS_TEXT_BASE>;
type = "standalone";
uboot_blob: blob-ext {
uboot-blob {
filename = "u-boot-nodtb.bin";
type = "blob-ext";
};
};
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
load = <0x910000>;
description = "ARM Trusted Firmware";
entry = <0x910000>;
load = <0x910000>;
type = "firmware";
atf_blob: blob-ext {
atf-blob {
filename = "bl31.bin";
type = "blob-ext";
};
};
fdt {
compression = "none";
description = "NAME";
type = "flat_dt";
compression = "none";
uboot_fdt_blob: blob-ext {
uboot-fdt-blob {
filename = "u-boot.dtb";
type = "blob-ext";
};
};
};
@ -114,9 +121,9 @@
conf {
description = "NAME";
fdt = "fdt";
firmware = "uboot";
loadables = "atf";
fdt = "fdt";
};
};
};
@ -126,14 +133,16 @@
filename = "flash.bin";
pad-byte = <0x00>;
spl: blob-ext@1 {
offset = <0x0>;
spl {
filename = "spl.bin";
offset = <0x0>;
type = "blob-ext";
};
uboot: blob-ext@2 {
offset = <0x57c00>;
binman_uboot: uboot {
filename = "u-boot.itb";
offset = <0x57c00>;
type = "blob-ext";
};
};
};

203
arch/arm/dts/imx8mq.dtsi
View file

@ -11,6 +11,7 @@
#include "dt-bindings/input/input.h"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/interconnect/imx8mq.h>
#include "imx8mq-pinfunc.h"
/ {
@ -39,8 +40,6 @@
spi0 = &ecspi1;
spi1 = &ecspi2;
spi2 = &ecspi3;
usb0 = &usb_dwc3_0;
usb1 = &usb_dwc3_1;
};
ckil: clock-ckil {
@ -194,7 +193,6 @@
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
};
psci {
@ -288,11 +286,13 @@
};
soc@0 {
compatible = "simple-bus";
compatible = "fsl,imx8mq-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
nvmem-cells = <&imx8mq_uid>;
nvmem-cell-names = "soc_unique_id";
bus@30000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
@ -557,9 +557,17 @@
#address-cells = <1>;
#size-cells = <1>;
imx8mq_uid: soc-uid@410 {
reg = <0x4 0x8>;
};
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
fec_mac_address: mac-address@90 {
reg = <0x90 6>;
};
};
anatop: syscon@30360000 {
@ -828,6 +836,8 @@
clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
<&clk IMX8MQ_CLK_ECSPI1_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -840,6 +850,8 @@
clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
<&clk IMX8MQ_CLK_ECSPI2_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -852,6 +864,8 @@
clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
<&clk IMX8MQ_CLK_ECSPI3_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -1018,9 +1032,14 @@
reg = <0x30a00300 0x100>;
clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
clock-names = "phy_ref";
assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
assigned-clock-rates = <24000000>;
assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
<&clk IMX8MQ_CLK_DSI_PHY_REF>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
<&clk IMX8MQ_VIDEO_PLL1>,
<&clk IMX8MQ_VIDEO_PLL1_OUT>;
assigned-clock-rates = <0>, <0>, <24000000>, <594000000>;
#phy-cells = <0>;
power-domains = <&pgc_mipi>;
status = "disabled";
@ -1077,6 +1096,110 @@
status = "disabled";
};
mipi_csi1: csi@30a70000 {
compatible = "fsl,imx8mq-mipi-csi2";
reg = <0x30a70000 0x1000>;
clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
<&clk IMX8MQ_CLK_CSI1_ESC>,
<&clk IMX8MQ_CLK_CSI1_PHY_REF>;
clock-names = "core", "esc", "ui";
assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
<&clk IMX8MQ_CLK_CSI1_PHY_REF>,
<&clk IMX8MQ_CLK_CSI1_ESC>;
assigned-clock-rates = <266000000>, <333000000>, <66000000>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_SYS2_PLL_1000M>,
<&clk IMX8MQ_SYS1_PLL_800M>;
power-domains = <&pgc_mipi_csi1>;
resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>,
<&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>,
<&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>;
fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;
interconnect-names = "dram";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi1_mipi_ep: endpoint {
remote-endpoint = <&csi1_ep>;
};
};
};
};
csi1: csi@30a90000 {
compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
reg = <0x30a90000 0x10000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>;
clock-names = "mclk";
status = "disabled";
port {
csi1_ep: endpoint {
remote-endpoint = <&csi1_mipi_ep>;
};
};
};
mipi_csi2: csi@30b60000 {
compatible = "fsl,imx8mq-mipi-csi2";
reg = <0x30b60000 0x1000>;
clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
<&clk IMX8MQ_CLK_CSI2_ESC>,
<&clk IMX8MQ_CLK_CSI2_PHY_REF>;
clock-names = "core", "esc", "ui";
assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
<&clk IMX8MQ_CLK_CSI2_PHY_REF>,
<&clk IMX8MQ_CLK_CSI2_ESC>;
assigned-clock-rates = <266000000>, <333000000>, <66000000>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_SYS2_PLL_1000M>,
<&clk IMX8MQ_SYS1_PLL_800M>;
power-domains = <&pgc_mipi_csi2>;
resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>,
<&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>,
<&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>;
fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>;
interconnect-names = "dram";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi2_mipi_ep: endpoint {
remote-endpoint = <&csi2_ep>;
};
};
};
};
csi2: csi@30b80000 {
compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
reg = <0x30b80000 0x10000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>;
clock-names = "mclk";
status = "disabled";
port {
csi2_ep: endpoint {
remote-endpoint = <&csi2_mipi_ep>;
};
};
};
mu: mailbox@30aa0000 {
compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
reg = <0x30aa0000 0x10000>;
@ -1154,12 +1277,50 @@
<&clk IMX8MQ_CLK_ENET_PHY_REF>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>,
<&clk IMX8MQ_CLK_ENET_TIMER>,
<&clk IMX8MQ_CLK_ENET_REF>,
<&clk IMX8MQ_CLK_ENET_PHY_REF>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_SYS2_PLL_100M>,
<&clk IMX8MQ_SYS2_PLL_125M>,
<&clk IMX8MQ_SYS2_PLL_50M>;
assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
nvmem-cells = <&fec_mac_address>;
nvmem-cell-names = "mac-address";
nvmem_macaddr_swap;
fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
status = "disabled";
};
};
noc: interconnect@32700000 {
compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc";
reg = <0x32700000 0x100000>;
clocks = <&clk IMX8MQ_CLK_NOC>;
fsl,ddrc = <&ddrc>;
#interconnect-cells = <1>;
operating-points-v2 = <&noc_opp_table>;
noc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-133M {
opp-hz = /bits/ 64 <133333333>;
};
opp-400M {
opp-hz = /bits/ 64 <400000000>;
};
opp-800M {
opp-hz = /bits/ 64 <800000000>;
};
};
};
bus@32c00000 { /* AIPS4 */
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x32c00000 0x400000>;
@ -1304,10 +1465,9 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
<0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
@ -1317,11 +1477,20 @@
<0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <2>;
linux,pci-domain = <0>;
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIEPHY>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "turnoff";
assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&clk IMX8MQ_CLK_PCIE1_AUX>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
<&clk IMX8MQ_SYS2_PLL_100M>,
<&clk IMX8MQ_SYS1_PLL_80M>;
assigned-clock-rates = <250000000>, <100000000>,
<10000000>;
status = "disabled";
};
@ -1333,10 +1502,9 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */
<0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
@ -1346,11 +1514,20 @@
<0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <2>;
linux,pci-domain = <1>;
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIEPHY2>,
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "turnoff";
assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&clk IMX8MQ_CLK_PCIE2_AUX>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
<&clk IMX8MQ_SYS2_PLL_100M>,
<&clk IMX8MQ_SYS1_PLL_80M>;
assigned-clock-rates = <250000000>, <100000000>,
<10000000>;
status = "disabled";
};

6
arch/arm/include/asm/arch-imx8m/imx-regs.h
View file

@ -80,8 +80,10 @@
#include <linux/bitops.h>
#include <stdbool.h>
#define GPR_TZASC_EN BIT(0)
#define GPR_TZASC_EN_LOCK BIT(16)
#define GPR_TZASC_EN BIT(0)
#define GPR_TZASC_ID_SWAP_BYPASS BIT(1)
#define GPR_TZASC_EN_LOCK BIT(16)
#define GPR_TZASC_ID_SWAP_BYPASS_LOCK BIT(17)
#define SRC_SCR_M4_ENABLE_OFFSET 3
#define SRC_SCR_M4_ENABLE_MASK BIT(3)

37
arch/arm/include/asm/arch-imx8ulp/cgc.h
View file

@ -6,11 +6,15 @@
#ifndef _ASM_ARCH_CGC_H
#define _ASM_ARCH_CGC_H
enum cgc1_clk {
enum cgc_clk {
DUMMY0_CLK,
DUMMY1_CLK,
LPOSC,
NIC_APCLK,
NIC_PERCLK,
XBAR_APCLK,
XBAR_BUSCLK,
AD_SLOWCLK,
SOSC,
SOSC_DIV1,
SOSC_DIV2,
@ -34,6 +38,28 @@ enum cgc1_clk {
PLL3_PFD2_DIV2,
PLL3_PFD3_DIV1,
PLL3_PFD3_DIV2,
LVDS,
LPAV_AXICLK,
LPAV_AHBCLK,
LPAV_BUSCLK,
PLL4,
PLL4_VCODIV,
PLL4_PFD0,
PLL4_PFD1,
PLL4_PFD2,
PLL4_PFD3,
PLL4_PFD0_DIV1,
PLL4_PFD0_DIV2,
PLL4_PFD1_DIV1,
PLL4_PFD1_DIV2,
PLL4_PFD2_DIV1,
PLL4_PFD2_DIV2,
PLL4_PFD3_DIV1,
PLL4_PFD3_DIV2,
CM33_BUSCLK,
PLL1_VCO_DIV,
PLL0_PFD2_DIV,
PLL0_PFD1_DIV,
};
struct cgc1_regs {
@ -119,12 +145,17 @@ struct cgc2_regs {
u32 lvdscfg;
};
u32 cgc1_clk_get_rate(enum cgc1_clk clk);
u32 cgc_clk_get_rate(enum cgc_clk clk);
void cgc1_pll3_init(void);
void cgc1_pll2_init(void);
void cgc1_soscdiv_init(void);
void cgc1_init_core_clk(void);
void cgc2_pll4_init(void);
void cgc2_ddrclk_config(u32 src, u32 div);
u32 cgc1_sosc_div(enum cgc1_clk clk);
void cgc2_ddrclk_wait_unlock(void);
u32 cgc1_sosc_div(enum cgc_clk clk);
void cgc1_enet_stamp_sel(u32 clk_src);
void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd);
void cgc2_pll4_pfddiv_config(enum cgc_clk pllpfddiv, u32 div);
void cgc2_lpav_init(enum cgc_clk clk);
#endif

4
arch/arm/include/asm/arch-imx8ulp/clock.h
View file

@ -38,4 +38,8 @@ void init_clk_ddr(void);
int set_ddr_clk(u32 phy_freq_mhz);
void clock_init(void);
void cgc1_enet_stamp_sel(u32 clk_src);
void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz);
void reset_lcdclk(void);
void enable_mipi_dsi_clk(unsigned char enable);
void enable_adc1_clk(bool enable);
#endif

1
arch/arm/include/asm/arch-imx8ulp/imx-regs.h
View file

@ -30,6 +30,7 @@
#define PCC_XRDC_MGR_ADDR 0x292d00bc
#define PCC1_RBASE 0x28091000
#define PCC3_RBASE 0x292d0000
#define PCC4_RBASE 0x29800000
#define PCC5_RBASE 0x2da70000

4
arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h
View file

@ -9,6 +9,10 @@
#include <asm/arch/iomux.h>
enum {
IMX8ULP_PAD_PTA3__TPM0_CH2 = IOMUX_PAD(0x000c, 0x000c, IOMUX_CONFIG_MPORTS | 0x6, 0x0948, 0x1, 0),
IMX8ULP_PAD_PTA8__LPI2C0_SCL = IOMUX_PAD(0x0020, 0x0020, IOMUX_CONFIG_MPORTS | 0x5, 0x097c, 0x2, 0),
IMX8ULP_PAD_PTA9__LPI2C0_SDA = IOMUX_PAD(0x0024, 0x0024, IOMUX_CONFIG_MPORTS | 0x5, 0x0980, 0x2, 0),
IMX8ULP_PAD_PTB7__PMIC0_MODE2 = IOMUX_PAD(0x009C, 0x009C, IOMUX_CONFIG_MPORTS | 0xA, 0x0000, 0x0, 0),
IMX8ULP_PAD_PTB8__PMIC0_MODE1 = IOMUX_PAD(0x00A0, 0x00A0, IOMUX_CONFIG_MPORTS | 0xA, 0x0000, 0x0, 0),
IMX8ULP_PAD_PTB9__PMIC0_MODE0 = IOMUX_PAD(0x00A4, 0x00A4, IOMUX_CONFIG_MPORTS | 0xA, 0x0000, 0x0, 0),

70
arch/arm/include/asm/arch-imx8ulp/pcc.h
View file

@ -8,6 +8,10 @@
#include <asm/arch/cgc.h>
enum pcc1_entry {
ADC1_PCC1_SLOT = 34,
};
enum pcc3_entry {
DMA1_MP_PCC3_SLOT = 1,
DMA1_CH0_PCC3_SLOT = 2,
@ -90,6 +94,68 @@ enum pcc4_entry {
RGPIOF_PCC4_SLOT = 31,
};
enum pcc5_entry {
DMA2_MP_PCC5_SLOT = 0,
DMA2_CH0_PCC5_SLOT = 1,
DMA2_CH1_PCC5_SLOT = 2,
DMA2_CH2_PCC5_SLOT = 3,
DMA2_CH3_PCC5_SLOT = 4,
DMA2_CH4_PCC5_SLOT = 5,
DMA2_CH5_PCC5_SLOT = 6,
DMA2_CH6_PCC5_SLOT = 7,
DMA2_CH7_PCC5_SLOT = 8,
DMA2_CH8_PCC5_SLOT = 9,
DMA2_CH9_PCC5_SLOT = 10,
DMA2_CH10_PCC5_SLOT = 11,
DMA2_CH11_PCC5_SLOT = 12,
DMA2_CH12_PCC5_SLOT = 13,
DMA2_CH13_PCC5_SLOT = 14,
DMA2_CH14_PCC5_SLOT = 15,
DMA2_CH15_PCC5_SLOT = 16,
DMA2_CH16_PCC5_SLOT = 17,
DMA2_CH17_PCC5_SLOT = 18,
DMA2_CH18_PCC5_SLOT = 19,
DMA2_CH19_PCC5_SLOT = 20,
DMA2_CH20_PCC5_SLOT = 21,
DMA2_CH21_PCC5_SLOT = 22,
DMA2_CH22_PCC5_SLOT = 23,
DMA2_CH23_PCC5_SLOT = 24,
DMA2_CH24_PCC5_SLOT = 25,
DMA2_CH25_PCC5_SLOT = 26,
DMA2_CH26_PCC5_SLOT = 27,
DMA2_CH27_PCC5_SLOT = 28,
DMA2_CH28_PCC5_SLOT = 29,
DMA2_CH29_PCC5_SLOT = 30,
DMA2_CH30_PCC5_SLOT = 31,
DMA2_CH31_PCC5_SLOT = 32,
MU2_B_PCC5_SLOT = 33,
MU3_B_PCC5_SLOT = 34,
SEMA42_2_PCC5_SLOT = 35,
CMC2_PCC5_SLOT = 36,
AVD_SIM_PCC5_SLOT = 37,
LPAV_CGC_PCC5_SLOT = 38,
PCC5_PCC5_SLOT = 39,
TPM8_PCC5_SLOT = 40,
SAI6_PCC5_SLOT = 41,
SAI7_PCC5_SLOT = 42,
SPDIF_PCC5_SLOT = 43,
ISI_PCC5_SLOT = 44,
CSI_REGS_PCC5_SLOT = 45,
CSI_PCC5_SLOT = 47,
DSI_PCC5_SLOT = 48,
WDOG5_PCC5_SLOT = 50,
EPDC_PCC5_SLOT = 51,
PXP_PCC5_SLOT = 52,
SFA2_PCC5_SLOT = 53,
GPU2D_PCC5_SLOT = 60,
GPU3D_PCC5_SLOT = 61,
DCNANO_PCC5_SLOT = 62,
LPDDR4_PCC5_SLOT = 66,
CSI_CLK_UI_PCC5_SLOT = 67,
CSI_CLK_ESC_PCC5_SLOT = 68,
RGPIOD_PCC5_SLOT = 69,
};
/* PCC registers */
#define PCC_PR_OFFSET 31
#define PCC_PR_MASK (0x1 << PCC_PR_OFFSET)
@ -130,10 +196,10 @@ struct pcc_entry {
};
int pcc_clock_enable(int pcc_controller, int pcc_clk_slot, bool enable);
int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc1_clk src);
int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc_clk src);
int pcc_clock_div_config(int pcc_controller, int pcc_clk_slot, bool frac, u8 div);
bool pcc_clock_is_enable(int pcc_controller, int pcc_clk_slot);
int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc1_clk *src);
int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc_clk *src);
int pcc_reset_peripheral(int pcc_controller, int pcc_clk_slot, bool reset);
u32 pcc_clock_get_rate(int pcc_controller, int pcc_clk_slot);
#endif

2
arch/arm/include/asm/arch-imx8ulp/sys_proto.h
View file

@ -16,4 +16,6 @@ enum bt_mode get_boot_mode(void);
int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm);
int xrdc_config_pdac_openacc(u32 bridge, u32 index);
enum boot_device get_boot_device(void);
void set_lpav_qos(void);
void load_lposc_fuse(void);
#endif

1
arch/arm/include/asm/arch-mx6/crm_regs.h
View file

@ -1291,7 +1291,6 @@ struct mxc_ccm_reg {
(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x60
#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT 4
#define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23)

1
arch/arm/include/asm/mach-imx/iomux-v3.h
View file

@ -243,6 +243,7 @@ typedef u64 iomux_v3_cfg_t;
#endif
#define IMX_PAD_SION 0x40000000
#define IOMUX_CONFIG_SION 0x10
#define GPIO_PIN_MASK 0x1f

5
arch/arm/include/asm/mach-imx/sys_proto.h
View file

@ -236,4 +236,9 @@ unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
unsigned long reg3);
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
void enable_ca7_smp(void);
#endif
#endif

2
arch/arm/mach-imx/cache.c
View file

@ -11,7 +11,7 @@
#include <asm/io.h>
#include <asm/mach-imx/sys_proto.h>
static void enable_ca7_smp(void)
void enable_ca7_smp(void)
{
u32 val;

42
arch/arm/mach-imx/cmd_nandbcb.c
View file

@ -132,6 +132,7 @@ static struct platform_config imx8q_plat_config = {
/* boot search related variables and definitions */
static int g_boot_search_count = 4;
static int g_boot_secondary_offset;
static int g_boot_search_stride;
static int g_pages_per_stride;
@ -275,9 +276,9 @@ static int nandbcb_set_boot_config(int argc, char * const argv[],
boot_stream2_address = ((maxsize - boot_stream1_address) / 2 +
boot_stream1_address);
if (boot_cfg->secondary_boot_stream_off_in_MB)
if (g_boot_secondary_offset)
boot_stream2_address =
(loff_t)boot_cfg->secondary_boot_stream_off_in_MB * 1024 * 1024;
(loff_t)g_boot_secondary_offset * 1024 * 1024;
max_boot_stream_size = boot_stream2_address - boot_stream1_address;
@ -650,7 +651,7 @@ static int write_fcb(struct boot_config *boot_cfg, struct fcb_block *fcb)
};
ret = mtd_write_oob(mtd, off, &ops);
printf("NAND FCB write to 0x%llxx offset 0x%zx written: %s\n", off, ops.len, ret ? "ERROR" : "OK");
printf("NAND FCB write to 0x%llx offset 0x%zx written: %s\n", off, ops.len, ret ? "ERROR" : "OK");
}
if (ret)
@ -1269,6 +1270,36 @@ static bool check_fingerprint(void *data, int fingerprint)
return (*(int *)(data + off) == fingerprint);
}
static int fuse_secondary_boot(u32 bank, u32 word, u32 mask, u32 off)
{
int err;
u32 val;
int ret;
err = fuse_read(bank, word, &val);
if (err)
return 0;
val = (val & mask) >> off;
if (val > 10)
return 0;
switch (val) {
case 0:
ret = 4;
break;
case 1:
ret = 1;
break;
default:
ret = 2 << val;
break;
}
return ret;
};
static int fuse_to_search_count(u32 bank, u32 word, u32 mask, u32 off)
{
int err;
@ -1506,6 +1537,11 @@ static int do_nandbcb(struct cmd_tbl *cmdtp, int flag, int argc,
g_boot_search_count);
}
if (plat_config.misc_flags & FIRMWARE_SECONDARY_FIXED_ADDR) {
if (is_imx8mn())
g_boot_secondary_offset = fuse_secondary_boot(2, 1, 0xff0000, 16);
}
cmd = argv[1];
--argc;
++argv;

25
arch/arm/mach-imx/imx8m/Kconfig
View file

@ -112,6 +112,19 @@ config TARGET_PICO_IMX8MQ
select IMX8MQ
select IMX8M_LPDDR4
config TARGET_IMX8MN_VAR_SOM
bool "imx8mn_var_som"
select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR4
config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"
select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
config TARGET_VERDIN_IMX8MM
bool "Support Toradex Verdin iMX8M Mini module"
select BINMAN
@ -119,6 +132,13 @@ config TARGET_VERDIN_IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_VERDIN_IMX8MP
bool "Support Toradex Verdin iMX8M Plus module"
select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_BEACON
bool "imx8mm Beacon Embedded devkit"
select BINMAN
@ -153,6 +173,7 @@ config TARGET_IMX8MM_CL_IOT_GATE
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
select SUPPORT_EXTENSION_SCAN
config TARGET_IMX8MM_CL_IOT_GATE_OPTEE
bool "CompuLab iot-gate-imx8 with optee support"
@ -160,6 +181,7 @@ config TARGET_IMX8MM_CL_IOT_GATE_OPTEE
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
select SUPPORT_EXTENSION_SCAN
endchoice
source "board/beacon/imx8mm/Kconfig"
@ -172,11 +194,14 @@ source "board/freescale/imx8mn_evk/Kconfig"
source "board/freescale/imx8mp_evk/Kconfig"
source "board/gateworks/venice/Kconfig"
source "board/google/imx8mq_phanbell/Kconfig"
source "board/kontron/pitx_imx8m/Kconfig"
source "board/kontron/sl-mx8mm/Kconfig"
source "board/phytec/phycore_imx8mm/Kconfig"
source "board/phytec/phycore_imx8mp/Kconfig"
source "board/ronetix/imx8mq-cm/Kconfig"
source "board/technexion/pico-imx8mq/Kconfig"
source "board/variscite/imx8mn_var_som/Kconfig"
source "board/toradex/verdin-imx8mm/Kconfig"
source "board/toradex/verdin-imx8mp/Kconfig"
endif

24
arch/arm/mach-imx/imx8m/clock_imx8mm.c
View file

@ -244,9 +244,29 @@ int intpll_configure(enum pll_clocks pll, ulong freq)
INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
break;
case MHZ(1200):
/* 24 * 0xc8 / 2 / 2 ^ 1 */
/* 24 * 0x12c / 3 / 2 ^ 1 */
pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x12c) |
INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
break;
case MHZ(1400):
/* 24 * 0x15e / 3 / 2 ^ 1 */
pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x15e) |
INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
break;
case MHZ(1500):
/* 24 * 0x177 / 3 / 2 ^ 1 */
pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x177) |
INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
break;
case MHZ(1600):
/* 24 * 0xc8 / 3 / 2 ^ 0 */
pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) |
INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(1);
INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
break;
case MHZ(1800):
/* 24 * 0xe1 / 3 / 2 ^ 0 */
pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xe1) |
INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
break;
case MHZ(2000):
/* 24 * 0xfa / 3 / 2 ^ 0 */

8
arch/arm/mach-imx/imx8m/clock_imx8mq.c
View file

@ -359,10 +359,18 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
clock_get_target_val(IPG_CLK_ROOT, &val);
val = val & 0x3;
return get_root_clk(AHB_CLK_ROOT) / (val + 1);
case MXC_CSPI_CLK:
return get_root_clk(ECSPI1_CLK_ROOT);
case MXC_ESDHC_CLK:
return get_root_clk(USDHC1_CLK_ROOT);
case MXC_ESDHC2_CLK:
return get_root_clk(USDHC2_CLK_ROOT);
case MXC_I2C_CLK:
return get_root_clk(I2C1_CLK_ROOT);
case MXC_UART_CLK:
return get_root_clk(UART1_CLK_ROOT);
case MXC_QSPI_CLK:
return get_root_clk(QSPI_CLK_ROOT);
default:
return get_root_clk(clk);
}

50
arch/arm/mach-imx/imx8m/soc.c
View file

@ -66,8 +66,21 @@ void enable_tzc380(void)
/* Enable TZASC and lock setting */
setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
/*
* According to TRM, TZASC_ID_SWAP_BYPASS should be set in
* order to avoid AXI Bus errors when GPU is in use
*/
if (is_imx8mm() || is_imx8mn() || is_imx8mp())
setbits_le32(&gpr->gpr[10], BIT(1));
setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
/*
* imx8mn and imx8mp implements the lock bit for
* TZASC_ID_SWAP_BYPASS, enable it to lock settings
*/
if (is_imx8mn() || is_imx8mp())
setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
/*
* set Region 0 attribute to allow secure and non-secure
* read/write permission. Found some masters like usb dwc3
@ -1316,40 +1329,35 @@ void do_error(struct pt_regs *pt_regs, unsigned int esr)
enum env_location env_get_location(enum env_operation op, int prio)
{
enum boot_device dev = get_boot_device();
enum env_location env_loc = ENVL_UNKNOWN;
if (prio)
return env_loc;
return ENVL_UNKNOWN;
switch (dev) {
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
case QSPI_BOOT:
env_loc = ENVL_SPI_FLASH;
break;
#endif
#ifdef CONFIG_ENV_IS_IN_NAND
if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
return ENVL_SPI_FLASH;
return ENVL_NOWHERE;
case NAND_BOOT:
env_loc = ENVL_NAND;
break;
#endif
#ifdef CONFIG_ENV_IS_IN_MMC
if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
return ENVL_NAND;
return ENVL_NOWHERE;
case SD1_BOOT:
case SD2_BOOT:
case SD3_BOOT:
case MMC1_BOOT:
case MMC2_BOOT:
case MMC3_BOOT:
env_loc = ENVL_MMC;
break;
#endif
if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
return ENVL_MMC;
else if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
return ENVL_EXT4;
else if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
return ENVL_FAT;
return ENVL_NOWHERE;
default:
#if defined(CONFIG_ENV_IS_NOWHERE)
env_loc = ENVL_NOWHERE;
#endif
break;
return ENVL_NOWHERE;
}
return env_loc;
}
#ifndef ENV_IS_EMBEDDED

325
arch/arm/mach-imx/imx8ulp/cgc.c
View file

@ -189,8 +189,8 @@ void cgc2_pll4_init(void)
;
/* Enable all 4 PFDs */
setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 0); /* 316.8Mhz for NIC_LPAV */
setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 8);
setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0);
setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */
setbits_le32(&cgc2_regs->pll4pfdcfg, 12 << 16);
setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24);
@ -205,15 +205,144 @@ void cgc2_pll4_init(void)
clrbits_le32(&cgc2_regs->pll4div_pfd1, BIT(7) | BIT(15) | BIT(23) | BIT(31));
}
void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd)
{
void __iomem *reg = &cgc2_regs->pll4div_pfd0;
u32 halt_mask = BIT(7) | BIT(15);
u32 pfd_shift = (pllpfd - PLL4_PFD0) * 8;
u32 val;
if (pllpfd < PLL4_PFD0 || pllpfd > PLL4_PFD3)
return;
if ((pllpfd - PLL4_PFD0) >> 1)
reg = &cgc2_regs->pll4div_pfd1;
halt_mask = halt_mask << (((pllpfd - PLL4_PFD0) & 0x1) * 16);
/* halt pfd div */
setbits_le32(reg, halt_mask);
/* gate pfd */
setbits_le32(&cgc2_regs->pll4pfdcfg, BIT(7) << pfd_shift);
val = readl(&cgc2_regs->pll4pfdcfg);
val &= ~(0x3f << pfd_shift);
val |= (pfd << pfd_shift);
writel(val, &cgc2_regs->pll4pfdcfg);
/* ungate */
clrbits_le32(&cgc2_regs->pll4pfdcfg, BIT(7) << pfd_shift);
/* Wait stable */
while ((readl(&cgc2_regs->pll4pfdcfg) & (BIT(6) << pfd_shift))
!= (BIT(6) << pfd_shift))
;
/* enable pfd div */
clrbits_le32(reg, halt_mask);
}
void cgc2_pll4_pfddiv_config(enum cgc_clk pllpfddiv, u32 div)
{
void __iomem *reg = &cgc2_regs->pll4div_pfd0;
u32 shift = ((pllpfddiv - PLL4_PFD0_DIV1) & 0x3) * 8;
if (pllpfddiv < PLL4_PFD0_DIV1 || pllpfddiv > PLL4_PFD3_DIV2)
return;
if ((pllpfddiv - PLL4_PFD0_DIV1) >> 2)
reg = &cgc2_regs->pll4div_pfd1;
/* Halt pfd div */
setbits_le32(reg, BIT(7) << shift);
/* Clear div */
clrbits_le32(reg, 0x3f << shift);
/* Set div*/
setbits_le32(reg, div << shift);
/* Enable pfd div */
clrbits_le32(reg, BIT(7) << shift);
}
void cgc2_ddrclk_config(u32 src, u32 div)
{
/* If reg lock is set, wait until unlock by HW */
/* This lock is triggered by div updating and ddrclk halt status change, */
while ((readl(&cgc2_regs->ddrclk) & BIT(31)))
;
writel((src << 28) | (div << 21), &cgc2_regs->ddrclk);
/* wait for DDRCLK switching done */
while (!(readl(&cgc2_regs->ddrclk) & BIT(27)))
;
}
u32 decode_pll(enum cgc1_clk pll)
void cgc2_ddrclk_wait_unlock(void)
{
while ((readl(&cgc2_regs->ddrclk) & BIT(31)))
;
}
void cgc2_lpav_init(enum cgc_clk clk)
{
u32 i, scs, reg;
const enum cgc_clk src[] = {FRO, PLL4_PFD1, SOSC, LVDS};
reg = readl(&cgc2_regs->niclpavclk);
scs = (reg >> 28) & 0x3;
for (i = 0; i < 4; i++) {
if (clk == src[i]) {
if (scs == i)
return;
reg &= ~(0x3 << 28);
reg |= (i << 28);
writel(reg, &cgc2_regs->niclpavclk);
break;
}
}
if (i == 4)
printf("Invalid clock source [%u] for LPAV\n", clk);
}
u32 cgc2_nic_get_rate(enum cgc_clk clk)
{
u32 reg, rate;
u32 scs, lpav_axi_clk, lpav_ahb_clk, lpav_bus_clk;
const enum cgc_clk src[] = {FRO, PLL4_PFD1, SOSC, LVDS};
reg = readl(&cgc2_regs->niclpavclk);
scs = (reg >> 28) & 0x3;
lpav_axi_clk = ((reg >> 21) & 0x3f) + 1;
lpav_ahb_clk = ((reg >> 14) & 0x3f) + 1;
lpav_bus_clk = ((reg >> 7) & 0x3f) + 1;
rate = cgc_clk_get_rate(src[scs]);
switch (clk) {
case LPAV_AXICLK:
rate = rate / lpav_axi_clk;
break;
case LPAV_AHBCLK:
rate = rate / (lpav_axi_clk * lpav_ahb_clk);
break;
case LPAV_BUSCLK:
rate = rate / (lpav_axi_clk * lpav_bus_clk);
break;
default:
return 0;
}
return rate;
}
u32 decode_pll(enum cgc_clk pll)
{
u32 reg, infreq, mult;
u32 num, denom;
@ -246,6 +375,17 @@ u32 decode_pll(enum cgc1_clk pll)
denom = readl(&cgc1_regs->pll3denom) & 0x3FFFFFFF;
num = readl(&cgc1_regs->pll3num) & 0x3FFFFFFF;
return (u64)infreq * mult + (u64)infreq * num / denom;
case PLL4:
reg = readl(&cgc2_regs->pll4csr);
if (!(reg & BIT(24)))
return 0;
reg = readl(&cgc2_regs->pll4cfg);
mult = (reg >> 16) & 0x7F;
denom = readl(&cgc2_regs->pll4denom) & 0x3FFFFFFF;
num = readl(&cgc2_regs->pll4num) & 0x3FFFFFFF;
return (u64)infreq * mult + (u64)infreq * num / denom;
default:
printf("Unsupported pll clocks %d\n", pll);
@ -255,93 +395,117 @@ u32 decode_pll(enum cgc1_clk pll)
return 0;
}
u32 cgc1_pll3_vcodiv_rate(void)
u32 cgc_pll_vcodiv_rate(enum cgc_clk clk)
{
u32 reg, gate, div;
void __iomem *plldiv_vco;
enum cgc_clk pll;
reg = readl(&cgc1_regs->pll3div_vco);
if (clk == PLL3_VCODIV) {
plldiv_vco = &cgc1_regs->pll3div_vco;
pll = PLL3;
} else {
plldiv_vco = &cgc2_regs->pll4div_vco;
pll = PLL4;
}
reg = readl(plldiv_vco);
gate = BIT(7) & reg;
div = reg & 0x3F;
return gate ? 0 : decode_pll(PLL3) / (div + 1);
return gate ? 0 : decode_pll(pll) / (div + 1);
}
u32 cgc1_pll3_pfd_rate(enum cgc1_clk clk)
u32 cgc_pll_pfd_rate(enum cgc_clk clk)
{
u32 index, gate, vld, reg;
void __iomem *pllpfdcfg;
enum cgc_clk pll;
switch (clk) {
case PLL3_PFD0:
index = 0;
break;
case PLL3_PFD1:
index = 1;
break;
case PLL3_PFD2:
index = 2;
break;
case PLL3_PFD3:
index = 3;
index = clk - PLL3_PFD0;
pllpfdcfg = &cgc1_regs->pll3pfdcfg;
pll = PLL3;
break;
case PLL4_PFD0:
case PLL4_PFD1:
case PLL4_PFD2:
case PLL4_PFD3:
index = clk - PLL4_PFD0;
pllpfdcfg = &cgc2_regs->pll4pfdcfg;
pll = PLL4;
break;
default:
return 0;
}
reg = readl(&cgc1_regs->pll3pfdcfg);
reg = readl(pllpfdcfg);
gate = reg & (BIT(7) << (index * 8));
vld = reg & (BIT(6) << (index * 8));
if (gate || !vld)
return 0;
return (u64)decode_pll(PLL3) * 18 / ((reg >> (index * 8)) & 0x3F);
return (u64)decode_pll(pll) * 18 / ((reg >> (index * 8)) & 0x3F);
}
u32 cgc1_pll3_pfd_div(enum cgc1_clk clk)
u32 cgc_pll_pfd_div(enum cgc_clk clk)
{
void __iomem *base;
u32 pfd, index, gate, reg;
switch (clk) {
case PLL3_PFD0_DIV1:
base = &cgc1_regs->pll3div_pfd0;
pfd = PLL3_PFD0;
index = 0;
break;
case PLL3_PFD0_DIV2:
base = &cgc1_regs->pll3div_pfd0;
pfd = PLL3_PFD0;
index = 1;
index = clk - PLL3_PFD0_DIV1;
break;
case PLL3_PFD1_DIV1:
base = &cgc1_regs->pll3div_pfd0;
pfd = PLL3_PFD1;
index = 2;
break;
case PLL3_PFD1_DIV2:
base = &cgc1_regs->pll3div_pfd0;
pfd = PLL3_PFD1;
index = 3;
index = clk - PLL3_PFD0_DIV1;
break;
case PLL3_PFD2_DIV1:
base = &cgc1_regs->pll3div_pfd1;
pfd = PLL3_PFD2;
index = 0;
break;
case PLL3_PFD2_DIV2:
base = &cgc1_regs->pll3div_pfd1;
pfd = PLL3_PFD2;
index = 1;
index = clk - PLL3_PFD2_DIV1;
break;
case PLL3_PFD3_DIV1:
base = &cgc1_regs->pll3div_pfd1;
pfd = PLL3_PFD3;
index = 2;
break;
case PLL3_PFD3_DIV2:
base = &cgc1_regs->pll3div_pfd1;
pfd = PLL3_PFD3;
index = 3;
index = clk - PLL3_PFD2_DIV1;
break;
case PLL4_PFD0_DIV1:
case PLL4_PFD0_DIV2:
base = &cgc2_regs->pll4div_pfd0;
pfd = PLL4_PFD0;
index = clk - PLL4_PFD0_DIV1;
break;
case PLL4_PFD1_DIV1:
case PLL4_PFD1_DIV2:
base = &cgc2_regs->pll4div_pfd0;
pfd = PLL4_PFD1;
index = clk - PLL4_PFD0_DIV1;
break;
case PLL4_PFD2_DIV1:
case PLL4_PFD2_DIV2:
base = &cgc2_regs->pll4div_pfd1;
pfd = PLL4_PFD2;
index = clk - PLL4_PFD2_DIV1;
break;
case PLL4_PFD3_DIV1:
case PLL4_PFD3_DIV2:
base = &cgc2_regs->pll4div_pfd1;
pfd = PLL4_PFD3;
index = clk - PLL4_PFD2_DIV1;
break;
default:
return 0;
@ -353,10 +517,52 @@ u32 cgc1_pll3_pfd_div(enum cgc1_clk clk)
if (gate)
return 0;
return cgc1_pll3_pfd_rate(pfd) / (((reg >> (index * 8)) & 0x3F) + 1);
return cgc_pll_pfd_rate(pfd) / (((reg >> (index * 8)) & 0x3F) + 1);
}
u32 cgc1_sosc_div(enum cgc1_clk clk)
u32 cgc1_nic_get_rate(enum cgc_clk clk)
{
u32 reg, rate;
u32 scs, nic_ad_divplat, nic_per_divplat;
u32 xbar_ad_divplat, xbar_divbus, ad_slow;
const enum cgc_clk src[] = {FRO, PLL3_PFD0, SOSC, LVDS};
reg = readl(&cgc1_regs->nicclk);
scs = (reg >> 28) & 0x3;
nic_ad_divplat = ((reg >> 21) & 0x3f) + 1;
nic_per_divplat = ((reg >> 14) & 0x3f) + 1;
reg = readl(&cgc1_regs->xbarclk);
xbar_ad_divplat = ((reg >> 14) & 0x3f) + 1;
xbar_divbus = ((reg >> 7) & 0x3f) + 1;
ad_slow = (reg & 0x3f) + 1;
rate = cgc_clk_get_rate(src[scs]);
switch (clk) {
case NIC_APCLK:
rate = rate / nic_ad_divplat;
break;
case NIC_PERCLK:
rate = rate / (nic_ad_divplat * nic_per_divplat);
break;
case XBAR_APCLK:
rate = rate / (nic_ad_divplat * xbar_ad_divplat);
break;
case XBAR_BUSCLK:
rate = rate / (nic_ad_divplat * xbar_ad_divplat * xbar_divbus);
break;
case AD_SLOWCLK:
rate = rate / (nic_ad_divplat * xbar_ad_divplat * ad_slow);
break;
default:
return 0;
}
return rate;
}
u32 cgc1_sosc_div(enum cgc_clk clk)
{
u32 reg, gate, index;
@ -385,7 +591,7 @@ u32 cgc1_sosc_div(enum cgc1_clk clk)
return 24000000 / (((reg >> (index * 8)) & 0x3F) + 1);
}
u32 cgc1_fro_div(enum cgc1_clk clk)
u32 cgc1_fro_div(enum cgc_clk clk)
{
u32 reg, gate, vld, index;
@ -415,9 +621,11 @@ u32 cgc1_fro_div(enum cgc1_clk clk)
return 24000000 / (((reg >> (index * 8)) & 0x3F) + 1);
}
u32 cgc1_clk_get_rate(enum cgc1_clk clk)
u32 cgc_clk_get_rate(enum cgc_clk clk)
{
switch (clk) {
case LVDS:
return 0; /* No external LVDS clock used */
case SOSC:
case SOSC_DIV1:
case SOSC_DIV2:
@ -429,16 +637,21 @@ u32 cgc1_clk_get_rate(enum cgc1_clk clk)
case FRO_DIV3:
return cgc1_fro_div(clk);
case PLL2:
return decode_pll(PLL2);
case PLL3:
return decode_pll(PLL3);
case PLL4:
return decode_pll(clk);
case PLL3_VCODIV:
return cgc1_pll3_vcodiv_rate();
case PLL4_VCODIV:
return cgc_pll_vcodiv_rate(clk);
case PLL3_PFD0:
case PLL3_PFD1:
case PLL3_PFD2:
case PLL3_PFD3:
return cgc1_pll3_pfd_rate(clk);
case PLL4_PFD0:
case PLL4_PFD1:
case PLL4_PFD2:
case PLL4_PFD3:
return cgc_pll_pfd_rate(clk);
case PLL3_PFD0_DIV1:
case PLL3_PFD0_DIV2:
case PLL3_PFD1_DIV1:
@ -447,9 +660,27 @@ u32 cgc1_clk_get_rate(enum cgc1_clk clk)
case PLL3_PFD2_DIV2:
case PLL3_PFD3_DIV1:
case PLL3_PFD3_DIV2:
return cgc1_pll3_pfd_div(clk);
case PLL4_PFD0_DIV1:
case PLL4_PFD0_DIV2:
case PLL4_PFD1_DIV1:
case PLL4_PFD1_DIV2:
case PLL4_PFD2_DIV1:
case PLL4_PFD2_DIV2:
case PLL4_PFD3_DIV1:
case PLL4_PFD3_DIV2:
return cgc_pll_pfd_div(clk);
case NIC_APCLK:
case NIC_PERCLK:
case XBAR_APCLK:
case XBAR_BUSCLK:
case AD_SLOWCLK:
return cgc1_nic_get_rate(clk);
case LPAV_AXICLK:
case LPAV_AHBCLK:
case LPAV_BUSCLK:
return cgc2_nic_get_rate(clk);
default:
printf("Unsupported cgc1 clock: %d\n", clk);
printf("Unsupported cgc clock: %d\n", clk);
return 0;
}
}

154
arch/arm/mach-imx/imx8ulp/clock.c
View file

@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define PLL_USB_LOCK_MASK (0x01 << 31)
#define PCC5_LPDDR4_ADDR 0x2da70108
static void lpuart_set_clk(u32 index, enum cgc1_clk clk)
static void lpuart_set_clk(u32 index, enum cgc_clk clk)
{
const u32 lpuart_pcc_slots[] = {
LPUART4_PCC3_SLOT,
@ -97,6 +97,9 @@ void ddrphy_pll_lock(void)
void init_clk_ddr(void)
{
/* disable the ddr pcc */
writel(0xc0000000, PCC5_LPDDR4_ADDR);
/* enable pll4 and ddrclk*/
cgc2_pll4_init();
cgc2_ddrclk_config(1, 1);
@ -104,6 +107,9 @@ void init_clk_ddr(void)
/* enable ddr pcc */
writel(0xd0000000, PCC5_LPDDR4_ADDR);
/* Wait until ddrclk reg lock bit is cleared, so that the div update is finished */
cgc2_ddrclk_wait_unlock();
/* for debug */
/* setclkout_ddr(); */
}
@ -141,6 +147,9 @@ int set_ddr_clk(u32 phy_freq_mhz)
return -EINVAL;
}
/* Wait until ddrclk reg lock bit is cleared, so that the div update is finished */
cgc2_ddrclk_wait_unlock();
return 0;
}
@ -186,6 +195,9 @@ int enable_i2c_clk(unsigned char enable, u32 i2c_num)
LPI2C7_PCC4_SLOT << 8 | 4,
};
if (i2c_num == 0)
return 0;
if (i2c_num < 4 || i2c_num > 7)
return -EINVAL;
@ -214,6 +226,9 @@ u32 imx_get_i2cclk(u32 i2c_num)
LPI2C7_PCC4_SLOT << 8 | 4,
};
if (i2c_num == 0)
return 24000000;
if (i2c_num < 4 || i2c_num > 7)
return 0;
@ -317,6 +332,99 @@ int enable_usb_pll(ulong usb_phy_base)
return 0;
}
void enable_mipi_dsi_clk(unsigned char enable)
{
if (enable) {
pcc_clock_enable(5, DSI_PCC5_SLOT, false);
pcc_reset_peripheral(5, DSI_PCC5_SLOT, true);
pcc_clock_sel(5, DSI_PCC5_SLOT, PLL4_PFD3_DIV2);
pcc_clock_div_config(5, DSI_PCC5_SLOT, 0, 6);
pcc_clock_enable(5, DSI_PCC5_SLOT, true);
pcc_reset_peripheral(5, DSI_PCC5_SLOT, false);
} else {
pcc_clock_enable(5, DSI_PCC5_SLOT, false);
pcc_reset_peripheral(5, DSI_PCC5_SLOT, true);
}
}
void enable_adc1_clk(bool enable)
{
if (enable) {
pcc_clock_enable(1, ADC1_PCC1_SLOT, false);
pcc_clock_sel(1, ADC1_PCC1_SLOT, CM33_BUSCLK);
pcc_clock_enable(1, ADC1_PCC1_SLOT, true);
pcc_reset_peripheral(1, ADC1_PCC1_SLOT, false);
} else {
pcc_clock_enable(1, ADC1_PCC1_SLOT, false);
}
}
void reset_lcdclk(void)
{
/* Disable clock and reset dcnano*/
pcc_clock_enable(5, DCNANO_PCC5_SLOT, false);
pcc_reset_peripheral(5, DCNANO_PCC5_SLOT, true);
}
void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz)
{
u8 pcd, best_pcd = 0;
u32 frac, rate, parent_rate, pfd, div;
u32 best_pfd = 0, best_frac = 0, best = 0, best_div = 0;
u32 pll4_rate;
pcc_clock_enable(5, DCNANO_PCC5_SLOT, false);
pll4_rate = cgc_clk_get_rate(PLL4);
pll4_rate = pll4_rate / 1000; /* Change to khz*/
debug("PLL4 rate %ukhz\n", pll4_rate);
for (pfd = 12; pfd <= 35; pfd++) {
parent_rate = pll4_rate;
parent_rate = parent_rate * 18 / pfd;
for (div = 1; div <= 64; div++) {
parent_rate = parent_rate / div;
for (pcd = 0; pcd < 8; pcd++) {
for (frac = 0; frac < 2; frac++) {
if (pcd == 0 && frac == 1)
continue;
rate = parent_rate * (frac + 1) / (pcd + 1);
if (rate > freq_in_khz)
continue;
if (best == 0 || rate > best) {
best = rate;
best_pfd = pfd;
best_frac = frac;
best_pcd = pcd;
best_div = div;
}
}
}
}
}
if (best == 0) {
printf("Can't find parent clock for LCDIF, target freq: %u\n", freq_in_khz);
return;
}
debug("LCD target rate %ukhz, best rate %ukhz, frac %u, pcd %u, best_pfd %u, best_div %u\n",
freq_in_khz, best, best_frac, best_pcd, best_pfd, best_div);
cgc2_pll4_pfd_config(PLL4_PFD0, best_pfd);
cgc2_pll4_pfddiv_config(PLL4_PFD0_DIV1, best_div - 1);
pcc_clock_sel(5, DCNANO_PCC5_SLOT, PLL4_PFD0_DIV1);
pcc_clock_div_config(5, DCNANO_PCC5_SLOT, best_frac, best_pcd + 1);
pcc_clock_enable(5, DCNANO_PCC5_SLOT, true);
pcc_reset_peripheral(5, DCNANO_PCC5_SLOT, false);
}
u32 mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
@ -327,7 +435,7 @@ u32 mxc_get_clock(enum mxc_clock clk)
case MXC_ESDHC3_CLK:
return pcc_clock_get_rate(4, SDHC2_PCC4_SLOT);
case MXC_ARM_CLK:
return cgc1_clk_get_rate(PLL2);
return cgc_clk_get_rate(PLL2);
default:
return 0;
}
@ -376,16 +484,40 @@ int do_mx8ulp_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char * const
printf("SDHC1 %8d MHz\n", pcc_clock_get_rate(4, SDHC1_PCC4_SLOT) / 1000000);
printf("SDHC2 %8d MHz\n", pcc_clock_get_rate(4, SDHC2_PCC4_SLOT) / 1000000);
printf("SOSC %8d MHz\n", cgc1_clk_get_rate(SOSC) / 1000000);
printf("FRO %8d MHz\n", cgc1_clk_get_rate(FRO) / 1000000);
printf("PLL2 %8d MHz\n", cgc1_clk_get_rate(PLL2) / 1000000);
printf("PLL3 %8d MHz\n", cgc1_clk_get_rate(PLL3) / 1000000);
printf("PLL3_VCODIV %8d MHz\n", cgc1_clk_get_rate(PLL3_VCODIV) / 1000000);
printf("PLL3_PFD0 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD0) / 1000000);
printf("PLL3_PFD1 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD1) / 1000000);
printf("PLL3_PFD2 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD2) / 1000000);
printf("PLL3_PFD3 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD3) / 1000000);
printf("SOSC %8d MHz\n", cgc_clk_get_rate(SOSC) / 1000000);
printf("FRO %8d MHz\n", cgc_clk_get_rate(FRO) / 1000000);
printf("PLL2 %8d MHz\n", cgc_clk_get_rate(PLL2) / 1000000);
printf("PLL3 %8d MHz\n", cgc_clk_get_rate(PLL3) / 1000000);
printf("PLL3_VCODIV %8d MHz\n", cgc_clk_get_rate(PLL3_VCODIV) / 1000000);
printf("PLL3_PFD0 %8d MHz\n", cgc_clk_get_rate(PLL3_PFD0) / 1000000);
printf("PLL3_PFD1 %8d MHz\n", cgc_clk_get_rate(PLL3_PFD1) / 1000000);
printf("PLL3_PFD2 %8d MHz\n", cgc_clk_get_rate(PLL3_PFD2) / 1000000);
printf("PLL3_PFD3 %8d MHz\n", cgc_clk_get_rate(PLL3_PFD3) / 1000000);
printf("PLL4_PFD0 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD0) / 1000000);
printf("PLL4_PFD1 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD1) / 1000000);
printf("PLL4_PFD2 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD2) / 1000000);
printf("PLL4_PFD3 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD3) / 1000000);
printf("PLL4_PFD0_DIV1 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD0_DIV1) / 1000000);
printf("PLL4_PFD0_DIV2 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD0_DIV2) / 1000000);
printf("PLL4_PFD1_DIV1 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD1_DIV1) / 1000000);
printf("PLL4_PFD1_DIV2 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD1_DIV2) / 1000000);
printf("PLL4_PFD2_DIV1 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD2_DIV1) / 1000000);
printf("PLL4_PFD2_DIV2 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD2_DIV2) / 1000000);
printf("PLL4_PFD3_DIV1 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD3_DIV1) / 1000000);
printf("PLL4_PFD3_DIV2 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD3_DIV2) / 1000000);
printf("LPAV_AXICLK %8d MHz\n", cgc_clk_get_rate(LPAV_AXICLK) / 1000000);
printf("LPAV_AHBCLK %8d MHz\n", cgc_clk_get_rate(LPAV_AHBCLK) / 1000000);
printf("LPAV_BUSCLK %8d MHz\n", cgc_clk_get_rate(LPAV_BUSCLK) / 1000000);
printf("NIC_APCLK %8d MHz\n", cgc_clk_get_rate(NIC_APCLK) / 1000000);
printf("NIC_PERCLK %8d MHz\n", cgc_clk_get_rate(NIC_PERCLK) / 1000000);
printf("XBAR_APCLK %8d MHz\n", cgc_clk_get_rate(XBAR_APCLK) / 1000000);
printf("XBAR_BUSCLK %8d MHz\n", cgc_clk_get_rate(XBAR_BUSCLK) / 1000000);
printf("AD_SLOWCLK %8d MHz\n", cgc_clk_get_rate(AD_SLOWCLK) / 1000000);
return 0;
}

158
arch/arm/mach-imx/imx8ulp/pcc.c
View file

@ -12,10 +12,25 @@
#include <asm/arch/cgc.h>
#include <asm/arch/sys_proto.h>
#define cgc1_clk_TYPES 2
#define cgc1_clk_NUM 8
#define cgc_clk_TYPES 2
#define cgc_clk_NUM 8
static enum cgc1_clk pcc3_clksrc[][8] = {
static enum cgc_clk pcc1_clksrc[][8] = {
{
},
{
DUMMY0_CLK,
LPOSC,
SOSC_DIV2,
FRO_DIV2,
CM33_BUSCLK,
PLL1_VCO_DIV,
PLL0_PFD2_DIV,
PLL0_PFD1_DIV,
}
};
static enum cgc_clk pcc3_clksrc[][8] = {
{
},
{ DUMMY0_CLK,
@ -29,7 +44,7 @@ static enum cgc1_clk pcc3_clksrc[][8] = {
}
};
static enum cgc1_clk pcc4_clksrc[][8] = {
static enum cgc_clk pcc4_clksrc[][8] = {
{
DUMMY0_CLK,
SOSC_DIV1,
@ -52,6 +67,34 @@ static enum cgc1_clk pcc4_clksrc[][8] = {
}
};
static enum cgc_clk pcc5_clksrc[][8] = {
{
DUMMY0_CLK,
PLL4_PFD3_DIV2,
PLL4_PFD2_DIV2,
PLL4_PFD2_DIV1,
PLL4_PFD1_DIV2,
PLL4_PFD1_DIV1,
PLL4_PFD0_DIV2,
PLL4_PFD0_DIV1
},
{
DUMMY0_CLK,
DUMMY1_CLK,
LPOSC,
SOSC_DIV2,
FRO_DIV2,
LPAV_BUSCLK,
PLL4_VCODIV,
PLL4_PFD3_DIV1
}
};
static struct pcc_entry pcc1_arrays[] = {
{PCC1_RBASE, ADC1_PCC1_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV, PCC_HAS_RST_B},
{}
};
static struct pcc_entry pcc3_arrays[] = {
{PCC3_RBASE, DMA1_MP_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},
{PCC3_RBASE, DMA1_CH0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},
@ -136,12 +179,79 @@ static struct pcc_entry pcc4_arrays[] = {
{}
};
static struct pcc_entry pcc5_arrays[] = {
{PCC5_RBASE, DMA2_MP_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH0_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH1_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH2_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH3_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH4_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH5_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH6_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH7_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH8_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH9_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH10_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH11_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH12_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH13_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH14_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH15_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH16_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH17_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH18_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH19_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH20_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH21_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH22_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH23_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH24_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH25_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH26_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH27_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH28_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH29_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH30_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, DMA2_CH31_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, MU2_B_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, MU3_B_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, SEMA42_2_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, CMC2_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, AVD_SIM_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, LPAV_CGC_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, PCC5_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, TPM8_PCC5_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B },
{PCC5_RBASE, SAI6_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B },
{PCC5_RBASE, SAI7_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B },
{PCC5_RBASE, SPDIF_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B },
{PCC5_RBASE, ISI_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B },
{PCC5_RBASE, CSI_REGS_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B },
{PCC5_RBASE, CSI_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B },
{PCC5_RBASE, DSI_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B },
{PCC5_RBASE, WDOG5_PCC5_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B },
{PCC5_RBASE, EPDC_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B },
{PCC5_RBASE, PXP_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B },
{PCC5_RBASE, SFA2_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{PCC5_RBASE, GPU2D_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B },
{PCC5_RBASE, GPU3D_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B },
{PCC5_RBASE, DCNANO_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B },
{PCC5_RBASE, LPDDR4_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B },
{PCC5_RBASE, CSI_CLK_UI_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_NO_RST_B },
{PCC5_RBASE, CSI_CLK_ESC_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_NO_RST_B },
{PCC5_RBASE, RGPIOD_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
{}
};
static int find_pcc_entry(int pcc_controller, int pcc_clk_slot, struct pcc_entry **out)
{
struct pcc_entry *pcc_array;
int index = 0;
switch (pcc_controller) {
case 1:
pcc_array = pcc1_arrays;
*out = &pcc1_arrays[0];
break;
case 3:
pcc_array = pcc3_arrays;
*out = &pcc3_arrays[0];
@ -150,6 +260,10 @@ static int find_pcc_entry(int pcc_controller, int pcc_clk_slot, struct pcc_entry
pcc_array = pcc4_arrays;
*out = &pcc4_arrays[0];
break;
case 5:
pcc_array = pcc5_arrays;
*out = &pcc5_arrays[0];
break;
default:
printf("Not supported pcc_controller: %d\n", pcc_controller);
return -EINVAL;
@ -199,12 +313,12 @@ int pcc_clock_enable(int pcc_controller, int pcc_clk_slot, bool enable)
}
/* The clock source select needs clock is disabled */
int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc1_clk src)
int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc_clk src)
{
u32 val, i, clksrc_type;
void __iomem *reg;
struct pcc_entry *pcc_array;
enum cgc1_clk *cgc1_clk_array;
enum cgc_clk *cgc_clk_array;
int clk;
clk = find_pcc_entry(pcc_controller, pcc_clk_slot, &pcc_array);
@ -220,19 +334,23 @@ int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc1_clk src)
return -EPERM;
}
if (pcc_controller == 3)
cgc1_clk_array = pcc3_clksrc[clksrc_type];
if (pcc_controller == 1)
cgc_clk_array = pcc1_clksrc[clksrc_type];
else if (pcc_controller == 3)
cgc_clk_array = pcc3_clksrc[clksrc_type];
else if (pcc_controller == 4)
cgc_clk_array = pcc4_clksrc[clksrc_type];
else
cgc1_clk_array = pcc4_clksrc[clksrc_type];
cgc_clk_array = pcc5_clksrc[clksrc_type];
for (i = 0; i < cgc1_clk_NUM; i++) {
if (cgc1_clk_array[i] == src) {
for (i = 0; i < cgc_clk_NUM; i++) {
if (cgc_clk_array[i] == src) {
/* Find the clock src, then set it to PCS */
break;
}
}
if (i == cgc1_clk_NUM) {
if (i == cgc_clk_NUM) {
printf("No parent in PCS of PCC %d, invalid scg_clk %d\n", clk, src);
return -EINVAL;
}
@ -320,13 +438,13 @@ bool pcc_clock_is_enable(int pcc_controller, int pcc_clk_slot)
return false;
}
int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc1_clk *src)
int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc_clk *src)
{
u32 val, clksrc_type;
void __iomem *reg;
struct pcc_entry *pcc_array;
int clk;
enum cgc1_clk *cgc1_clk_array;
enum cgc_clk *cgc_clk_array;
clk = find_pcc_entry(pcc_controller, pcc_clk_slot, &pcc_array);
if (clk < 0)
@ -360,11 +478,13 @@ int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc1_clk *sr
}
if (pcc_controller == 3)
cgc1_clk_array = pcc3_clksrc[clksrc_type];
cgc_clk_array = pcc3_clksrc[clksrc_type];
else if (pcc_controller == 4)
cgc_clk_array = pcc4_clksrc[clksrc_type];
else
cgc1_clk_array = pcc4_clksrc[clksrc_type];
cgc_clk_array = pcc5_clksrc[clksrc_type];
*src = cgc1_clk_array[val];
*src = cgc_clk_array[val];
debug("%s: parent cgc1 clk %d\n", __func__, *src);
@ -412,7 +532,7 @@ u32 pcc_clock_get_rate(int pcc_controller, int pcc_clk_slot)
{
u32 val, rate, frac, div;
void __iomem *reg;
enum cgc1_clk parent;
enum cgc_clk parent;
int ret;
int clk;
struct pcc_entry *pcc_array;
@ -425,7 +545,7 @@ u32 pcc_clock_get_rate(int pcc_controller, int pcc_clk_slot)
if (ret)
return 0;
rate = cgc1_clk_get_rate(parent);
rate = cgc_clk_get_rate(parent);
debug("%s: parent rate %u\n", __func__, rate);

117
arch/arm/mach-imx/imx8ulp/soc.c
View file

@ -23,6 +23,8 @@
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
#include <fuse.h>
#include <thermal.h>
DECLARE_GLOBAL_DATA_PTR;
@ -210,11 +212,27 @@ int print_cpuinfo(void)
cpurev = get_cpu_rev();
printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
printf("CPU: i.MX%s rev%d.%d at %d MHz\n",
get_imx_type((cpurev & 0xFF000) >> 12),
(cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
#if defined(CONFIG_IMX_PMC_TEMPERATURE)
struct udevice *udev;
int ret, temp;
ret = uclass_get_device(UCLASS_THERMAL, 0, &udev);
if (!ret) {
ret = thermal_get_temp(udev, &temp);
if (!ret)
printf("CPU current temperature: %d\n", temp);
else
debug(" - failed to get CPU current temperature\n");
} else {
debug(" - failed to get CPU current temperature\n");
}
#endif
printf("Reset cause: %s\n", get_reset_cause(cause));
printf("Boot mode: ");
@ -462,28 +480,84 @@ static int trdc_set_access(void)
/* Iomuxc0: : PBridge1 slot 33 */
trdc_mbc_set_access(2, 7, 1, 33, false);
/* flexspi0 */
trdc_mrc_region_set_access(0, 7, 0x04000000, 0x0c000000, false);
/* tpm0: PBridge1 slot 21 */
trdc_mbc_set_access(2, 7, 1, 21, false);
/* lpi2c0: PBridge1 slot 24 */
trdc_mbc_set_access(2, 7, 1, 24, false);
return 0;
}
void lpav_configure(void)
{
/* LPAV to APD */
setbits_le32(SIM_SEC_BASE_ADDR + 0x44, BIT(7));
/* PXP/GPU 2D/3D/DCNANO/MIPI_DSI/EPDC/HIFI4 to APD */
setbits_le32(SIM_SEC_BASE_ADDR + 0x4c, 0x7F);
/* LPAV slave/dma2 ch allocation and request allocation to APD */
writel(0x1f, SIM_SEC_BASE_ADDR + 0x50);
writel(0xffffffff, SIM_SEC_BASE_ADDR + 0x54);
writel(0x003fffff, SIM_SEC_BASE_ADDR + 0x58);
}
void load_lposc_fuse(void)
{
int ret;
u32 val = 0, val2 = 0, reg;
ret = fuse_read(25, 0, &val);
if (ret)
return; /* failed */
ret = fuse_read(25, 1, &val2);
if (ret)
return; /* failed */
/* LPOSCCTRL */
reg = readl(0x2802f304);
reg &= ~0xff;
reg |= (val & 0xff);
writel(reg, 0x2802f304);
}
void set_lpav_qos(void)
{
/* Set read QoS of dcnano on LPAV NIC */
writel(0xf, 0x2e447100);
}
int arch_cpu_init(void)
{
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
u32 val = 0;
int ret;
bool rdc_en = true; /* Default assume DBD_EN is set */
/* Disable wdog */
init_wdog();
/* Read DBD_EN fuse */
ret = fuse_read(8, 1, &val);
if (!ret)
rdc_en = !!(val & 0x4000);
if (get_boot_mode() == SINGLE_BOOT) {
release_rdc(RDC_TRDC);
if (rdc_en)
release_rdc(RDC_TRDC);
trdc_set_access();
/* LPAV to APD */
setbits_le32(0x2802B044, BIT(7));
/* GPU 2D/3D to APD */
setbits_le32(0x2802B04C, BIT(1) | BIT(2));
/* DCNANO and MIPI_DSI to APD */
setbits_le32(0x2802B04C, BIT(1) | BIT(2) | BIT(3) | BIT(4));
lpav_configure();
}
/* release xrdc, then allow A35 to write SRAM2 */
release_rdc(RDC_XRDC);
/* Release xrdc, then allow A35 to write SRAM2 */
if (rdc_en)
release_rdc(RDC_XRDC);
xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00);
clock_init();
@ -531,7 +605,30 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
u32 val[2] = {};
int ret;
ret = fuse_read(5, 3, &val[0]);
if (ret)
goto err;
ret = fuse_read(5, 4, &val[1]);
if (ret)
goto err;
mac[0] = val[0];
mac[1] = val[0] >> 8;
mac[2] = val[0] >> 16;
mac[3] = val[0] >> 24;
mac[4] = val[1];
mac[5] = val[1] >> 8;
debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
__func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
return;
err:
memset(mac, 0, 6);
printf("%s: fuse read err: %d\n", __func__, ret);
}
int (*card_emmc_is_boot_part_en)(void) = (void *)0x67cc;

10
arch/arm/mach-imx/mx6/soc.c
View file

@ -366,11 +366,13 @@ static void init_bandgap(void)
* 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
*/
if (is_mx6ull()) {
static const u32 map[] = {6, 1, 2, 3, 4, 5, 0, 7};
val = readl(&fuse->mem0);
val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
val &= 0x7;
writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
writel(map[val] << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
&anatop->ana_misc0_set);
}
}
@ -487,6 +489,9 @@ int arch_cpu_init(void)
if (is_mx6dqp())
noc_setup();
#endif
enable_ca7_smp();
return 0;
}
@ -498,8 +503,7 @@ __weak int board_mmc_get_env_dev(int devno)
static int mmc_get_boot_dev(void)
{
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
u32 soc_sbmr = readl(&src_regs->sbmr1);
u32 soc_sbmr = imx6_src_get_boot_mode();
u32 bootsel;
int devno;

3
arch/arm/mach-imx/mx7/soc.c
View file

@ -14,6 +14,7 @@
#include <asm/mach-imx/rdc-sema.h>
#include <asm/arch/imx-rdc.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/bootm.h>
#include <dm.h>
@ -323,6 +324,8 @@ int arch_cpu_init(void)
imx_gpcv2_init();
enable_ca7_smp();
return 0;
}
#else

15
arch/arm/mach-imx/mx7ulp/Kconfig
View file

@ -9,6 +9,9 @@ config LDO_ENABLED_MODE
Select this option to enable the PMC1 LDO.
config MX7ULP
select ARCH_SUPPORT_PSCI
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select HAS_CAAM
bool
@ -20,6 +23,18 @@ config TARGET_MX7ULP_COM
bool "Support MX7ULP COM board"
select MX7ULP
select SYS_ARCH_TIMER
select SPL_DM if SPL
select SPL_GPIO_SUPPORT if SPL
select SPL_LIBCOMMON_SUPPORT if SPL
select SPL_LIBDISK_SUPPORT if SPL
select SPL_LIBGENERIC_SUPPORT if SPL
select SPL_MMC_SUPPORT if SPL
select SPL_OF_CONTROL if SPL
select SPL_OF_LIBFDT if SPL
select SPL_PINCTRL if SPL
select SPL_SEPARATE_BSS if SPL
select SPL_SERIAL_SUPPORT if SPL
select SUPPORT_SPL
config TARGET_MX7ULP_EVK
bool "Support mx7ulp EVK board"

2
arch/arm/mach-imx/mx7ulp/soc.c
View file

@ -13,6 +13,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/hab.h>
#include <asm/mach-imx/sys_proto.h>
#include <asm/setup.h>
#include <linux/bitops.h>
@ -77,6 +78,7 @@ enum bt_mode get_boot_mode(void)
int arch_cpu_init(void)
{
enable_ca7_smp();
return 0;
}

5
board/beacon/imx8mm/imx8mm_beacon.c
View file

@ -50,8 +50,3 @@ int board_init(void)
return 0;
}
int board_mmc_get_env_dev(int devno)
{
return devno;
}

5
board/beacon/imx8mn/imx8mn_beacon.c
View file

@ -50,8 +50,3 @@ int board_init(void)
return 0;
}
int board_mmc_get_env_dev(int devno)
{
return CONFIG_SYS_MMC_ENV_DEV;
}

2
board/beacon/imx8mn/spl.c
View file

@ -122,6 +122,8 @@ void board_init_f(ulong dummy)
hang();
}
enable_tzc380();
/* DDR initialization */
spl_dram_init();

333
board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
View file

@ -6,14 +6,21 @@
#include <common.h>
#include <env.h>
#include <extension_board.h>
#include <hang.h>
#include <i2c.h>
#include <init.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx8mm_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/sections.h>
#include "ddr/ddr.h"
@ -41,6 +48,25 @@ int board_phys_sdram_size(phys_size_t *size)
return 0;
}
/* IOT_GATE-iMX8 extension boards ID */
typedef enum {
IOT_GATE_EXT_EMPTY, /* No extension */
IOT_GATE_EXT_CAN, /* CAN bus */
IOT_GATE_EXT_IED, /* Bridge */
IOT_GATE_EXT_POE, /* POE */
IOT_GATE_EXT_POEV2, /* POEv2 */
} iot_gate_imx8_ext;
typedef enum {
IOT_GATE_IMX8_CARD_ID_EMPTY = 0, /* card id - uninhabited */
IOT_GATE_IMX8_CARD_ID_DI4O4 = 1, /* Card ID - IED-DI4O4 */
IOT_GATE_IMX8_CARD_ID_RS_485 = 2, /* Card ID - IED-RS485 */
IOT_GATE_IMX8_CARD_ID_TPM = 3, /* Card ID - IED-TPM */
IOT_GATE_IMX8_CARD_ID_CAN = 4, /* Card ID - IED-CAN */
IOT_GATE_IMX8_CARD_ID_CL420 = 5, /* Card ID - IED-CL420 */
IOT_GATE_IMX8_CARD_ID_RS_232 = 6, /* Card ID - IED-RS232 */
} iot_gate_imx8_ied_ext;
static int setup_fec(void)
{
if (IS_ENABLED(CONFIG_FEC_MXC)) {
@ -85,6 +111,313 @@ int board_mmc_get_env_dev(int devno)
return devno;
}
#define IOT_GATE_IMX8_EXT_I2C 3 /* I2C ID of the extension board */
#define IOT_GATE_IMX8_EXT_I2C_ADDR_EEPROM 0x54 /* I2C address of the EEPROM */
/* I2C address of the EEPROM in the POE extension */
#define IOT_GATE_IMX8_EXT_I2C_ADDR_EEPROM_POE 0x50
#define IOT_GATE_IMX8_EXT_I2C_ADDR_EEPROM_POEV2 0x51
#define IOT_GATE_IMX8_EXT_I2C_ADDR_GPIO 0x22 /* I2C address of the GPIO
extender */
static int iot_gate_imx8_ext_id = IOT_GATE_EXT_EMPTY; /* Extension board ID */
static int iot_gate_imx8_ext_ied_id [3] = {
IOT_GATE_IMX8_CARD_ID_EMPTY,
IOT_GATE_IMX8_CARD_ID_EMPTY,
IOT_GATE_IMX8_CARD_ID_EMPTY };
/*
* iot_gate_imx8_detect_ext() - extended board detection
* The detection is done according to the detected I2C devices.
*/
static void iot_gate_imx8_detect_ext(void)
{
int ret;
struct udevice *i2c_bus, *i2c_dev;
ret = uclass_get_device_by_seq(UCLASS_I2C, IOT_GATE_IMX8_EXT_I2C,
&i2c_bus);
if (ret) {
printf("%s: Failed getting i2c device\n", __func__);
return;
}
ret = dm_i2c_probe(i2c_bus, IOT_GATE_IMX8_EXT_I2C_ADDR_EEPROM_POE, 0,
&i2c_dev);
if (!ret) {
iot_gate_imx8_ext_id = IOT_GATE_EXT_POE;
return;
}
ret = dm_i2c_probe(i2c_bus, IOT_GATE_IMX8_EXT_I2C_ADDR_EEPROM_POEV2, 0,
&i2c_dev);
if (!ret) {
iot_gate_imx8_ext_id = IOT_GATE_EXT_POEV2;
return;
}
ret = dm_i2c_probe(i2c_bus, IOT_GATE_IMX8_EXT_I2C_ADDR_EEPROM, 0,
&i2c_dev);
if (ret){
iot_gate_imx8_ext_id = IOT_GATE_EXT_EMPTY;
return;
}
/* Only the bridge extension includes the GPIO extender */
ret = dm_i2c_probe(i2c_bus, IOT_GATE_IMX8_EXT_I2C_ADDR_GPIO, 0,
&i2c_dev);
if (ret) /* GPIO extender not detected */
iot_gate_imx8_ext_id = IOT_GATE_EXT_CAN;
else /* GPIO extender detected */
iot_gate_imx8_ext_id = IOT_GATE_EXT_IED;
}
static iomux_v3_cfg_t const iot_gate_imx8_ext_ied_pads[] = {
IMX8MM_PAD_NAND_ALE_GPIO3_IO0 | MUX_PAD_CTRL(PAD_CTL_PE),
IMX8MM_PAD_NAND_CE0_B_GPIO3_IO1 | MUX_PAD_CTRL(PAD_CTL_PE),
IMX8MM_PAD_NAND_DATA00_GPIO3_IO6 | MUX_PAD_CTRL(PAD_CTL_PE),
IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 | MUX_PAD_CTRL(PAD_CTL_PE),
IMX8MM_PAD_NAND_DATA02_GPIO3_IO8 | MUX_PAD_CTRL(PAD_CTL_PE),
IMX8MM_PAD_NAND_DATA03_GPIO3_IO9 | MUX_PAD_CTRL(PAD_CTL_PE),
};
static iomux_v3_cfg_t const iot_gate_imx8_ext_poev2_pads[] = {
IMX8MM_PAD_SAI3_TXD_GPIO5_IO1 | MUX_PAD_CTRL(PAD_CTL_PE |
PAD_CTL_PUE),
};
/* Extension board bridge GPIOs */
#define IOT_GATE_IMX8_GPIO_EXT_IED_I0 IMX_GPIO_NR(3, 0) /* IN 0 */
#define IOT_GATE_IMX8_GPIO_EXT_IED_I1 IMX_GPIO_NR(3, 1) /* IN 1 */
#define IOT_GATE_IMX8_GPIO_EXT_IED_I2 IMX_GPIO_NR(3, 6) /* IN 2 */
#define IOT_GATE_IMX8_GPIO_EXT_IED_I3 IMX_GPIO_NR(3, 7) /* IN 3 */
#define IOT_GATE_IMX8_GPIO_EXT_IED_O0 IMX_GPIO_NR(3, 8) /* OUT 0 */
#define IOT_GATE_IMX8_GPIO_EXT_IED_O1 IMX_GPIO_NR(3, 9) /* OUT 1 */
#define IOT_GATE_IMX8_GPIO_EXT_IED_O2 IMX_GPIO_NR(6, 9) /* OUT 2 */
#define IOT_GATE_IMX8_GPIO_EXT_IED_O3 IMX_GPIO_NR(6, 10)/* OUT 3 */
/* Extension board POE GPIOs */
#define IOT_GATE_IMX8_GPIO_EXT_POE_MUX IMX_GPIO_NR(5, 1)/* USB_MUX */
/*
* iot_gate_imx8_update_pinmux() - update the pinmux
* Update the pinmux according to the detected extended board.
*/
static void iot_gate_imx8_update_pinmux(void)
{
if (iot_gate_imx8_ext_id == IOT_GATE_EXT_POEV2) {
imx_iomux_v3_setup_multiple_pads(iot_gate_imx8_ext_poev2_pads,
ARRAY_SIZE(iot_gate_imx8_ext_poev2_pads));
gpio_request(IOT_GATE_IMX8_GPIO_EXT_POE_MUX, "poev2_usb-mux");
/* Update USB MUX state */
gpio_direction_output(IOT_GATE_IMX8_GPIO_EXT_POE_MUX, 1);
return;
}
if (iot_gate_imx8_ext_id != IOT_GATE_EXT_IED)
return;
imx_iomux_v3_setup_multiple_pads(iot_gate_imx8_ext_ied_pads,
ARRAY_SIZE(iot_gate_imx8_ext_ied_pads));
gpio_request(IOT_GATE_IMX8_GPIO_EXT_IED_I0, "ied-di4o4_i0");
gpio_direction_input(IOT_GATE_IMX8_GPIO_EXT_IED_I0);
gpio_request(IOT_GATE_IMX8_GPIO_EXT_IED_I1, "ied-di4o4_i1");
gpio_direction_input(IOT_GATE_IMX8_GPIO_EXT_IED_I1);
gpio_request(IOT_GATE_IMX8_GPIO_EXT_IED_I2, "ied-di4o4_i2");
gpio_direction_input(IOT_GATE_IMX8_GPIO_EXT_IED_I2);
gpio_request(IOT_GATE_IMX8_GPIO_EXT_IED_I3, "ied-di4o4_i3");
gpio_direction_input(IOT_GATE_IMX8_GPIO_EXT_IED_I3);
gpio_request(IOT_GATE_IMX8_GPIO_EXT_IED_O0, "ied-di4o4_o0");
gpio_direction_output(IOT_GATE_IMX8_GPIO_EXT_IED_O0, 0);
gpio_request(IOT_GATE_IMX8_GPIO_EXT_IED_O1, "ied-di4o4_o1");
gpio_direction_output(IOT_GATE_IMX8_GPIO_EXT_IED_O1, 0);
gpio_request(IOT_GATE_IMX8_GPIO_EXT_IED_O2, "ied-di4o4_o2");
gpio_direction_output(IOT_GATE_IMX8_GPIO_EXT_IED_O2, 0);
gpio_request(IOT_GATE_IMX8_GPIO_EXT_IED_O3, "ied-di4o4_o3");
gpio_direction_output(IOT_GATE_IMX8_GPIO_EXT_IED_O3, 0);
}
#define IOT_GATE_IMX8_GPIO_S0B0 IMX_GPIO_NR(6, 0) /* Slot ID slot 0 bit 0 */
#define IOT_GATE_IMX8_GPIO_S0B1 IMX_GPIO_NR(6, 1) /* Slot ID slot 0 bit 1 */
#define IOT_GATE_IMX8_GPIO_S0B2 IMX_GPIO_NR(6, 2) /* Slot ID slot 0 bit 2 */
#define IOT_GATE_IMX8_GPIO_S1B0 IMX_GPIO_NR(6, 3) /* Slot ID slot 1 bit 0 */
#define IOT_GATE_IMX8_GPIO_S1B1 IMX_GPIO_NR(6, 4) /* Slot ID slot 1 bit 1 */
#define IOT_GATE_IMX8_GPIO_S1B2 IMX_GPIO_NR(6, 5) /* Slot ID slot 1 bit 2 */
#define IOT_GATE_IMX8_GPIO_S2B0 IMX_GPIO_NR(6, 6) /* Slot ID slot 2 bit 0 */
#define IOT_GATE_IMX8_GPIO_S2B1 IMX_GPIO_NR(6, 7) /* Slot ID slot 2 bit 1 */
#define IOT_GATE_IMX8_GPIO_S2B2 IMX_GPIO_NR(6, 8) /* Slot ID slot 2 bit 2 */
/*
* iot_gate_imx8_update_ext_ied()
* Update device tree of the extended board IED-BASE.
* The device tree is updated according to the detected sub modules.
*
* Return 0 for success, 1 for failure.
*/
static int iot_gate_imx8_update_ext_ied(void)
{
int revision;
if (iot_gate_imx8_ext_id != IOT_GATE_EXT_IED)
return 0;
/* ID GPIO initializations */
if (gpio_request(IOT_GATE_IMX8_GPIO_S0B0, "id_s0b0") ||
gpio_request(IOT_GATE_IMX8_GPIO_S0B1, "id_s0b1") ||
gpio_request(IOT_GATE_IMX8_GPIO_S0B2, "id_s0b2") ||
gpio_request(IOT_GATE_IMX8_GPIO_S1B0, "id_s1b0") ||
gpio_request(IOT_GATE_IMX8_GPIO_S1B1, "id_s1b1") ||
gpio_request(IOT_GATE_IMX8_GPIO_S1B2, "id_s1b2") ||
gpio_request(IOT_GATE_IMX8_GPIO_S2B0, "id_s2b0") ||
gpio_request(IOT_GATE_IMX8_GPIO_S2B1, "id_s2b1") ||
gpio_request(IOT_GATE_IMX8_GPIO_S2B2, "id_s2b2")) {
printf("%s: ID GPIO request failure\n", __func__);
return 1;
}
gpio_direction_input(IOT_GATE_IMX8_GPIO_S0B0);
gpio_direction_input(IOT_GATE_IMX8_GPIO_S0B1);
gpio_direction_input(IOT_GATE_IMX8_GPIO_S0B2);
gpio_direction_input(IOT_GATE_IMX8_GPIO_S1B0);
gpio_direction_input(IOT_GATE_IMX8_GPIO_S1B1);
gpio_direction_input(IOT_GATE_IMX8_GPIO_S1B2);
gpio_direction_input(IOT_GATE_IMX8_GPIO_S2B0);
gpio_direction_input(IOT_GATE_IMX8_GPIO_S2B1);
gpio_direction_input(IOT_GATE_IMX8_GPIO_S2B2);
/* Get slot 0 card ID */
revision = gpio_get_value(IOT_GATE_IMX8_GPIO_S0B0) |
gpio_get_value(IOT_GATE_IMX8_GPIO_S0B1) << 1 |
gpio_get_value(IOT_GATE_IMX8_GPIO_S0B2) << 2;
iot_gate_imx8_ext_ied_id[0] = revision;
/* Get slot 1 card ID */
revision = gpio_get_value(IOT_GATE_IMX8_GPIO_S1B0) |
gpio_get_value(IOT_GATE_IMX8_GPIO_S1B1) << 1 |
gpio_get_value(IOT_GATE_IMX8_GPIO_S1B2) << 2;
iot_gate_imx8_ext_ied_id[1] = revision;
/* Get slot 2 card ID */
revision = gpio_get_value(IOT_GATE_IMX8_GPIO_S2B0) |
gpio_get_value(IOT_GATE_IMX8_GPIO_S2B1) << 1 |
gpio_get_value(IOT_GATE_IMX8_GPIO_S2B2) << 2;
iot_gate_imx8_ext_ied_id[2] = revision;
return 0;
}
int board_fix_fdt(void *rw_fdt_blob)
{
return 0;
}
int extension_board_scan(struct list_head *extension_list)
{
struct extension *extension = NULL;
int i;
int ret = 0;
iot_gate_imx8_detect_ext(); /* Extended board detection */
switch(iot_gate_imx8_ext_id) {
case IOT_GATE_EXT_EMPTY:
break;
case IOT_GATE_EXT_CAN:
extension = calloc(1, sizeof(struct extension));
snprintf(extension->name, sizeof(extension->name),
"IOT_GATE_EXT_CAN");
break;
case IOT_GATE_EXT_IED:
extension = calloc(1, sizeof(struct extension));
snprintf(extension->name, sizeof(extension->name),
"IOT_GATE_EXT_IED");
snprintf(extension->overlay, sizeof(extension->overlay),
"imx8mm-cl-iot-gate-ied.dtbo");
break;
case IOT_GATE_EXT_POE:
extension = calloc(1, sizeof(struct extension));
snprintf(extension->name, sizeof(extension->name),
"IOT_GATE_EXT_POE");
break;
case IOT_GATE_EXT_POEV2:
extension = calloc(1, sizeof(struct extension));
snprintf(extension->name, sizeof(extension->name),
"IOT_GATE_EXT_POEV2");
break;
default:
printf("IOT_GATE-iMX8 extension board: unknown\n");
break;
}
if (extension) {
snprintf(extension->owner, sizeof(extension->owner),
"Compulab");
list_add_tail(&extension->list, extension_list);
ret = 1;
} else
return ret;
iot_gate_imx8_update_pinmux();
iot_gate_imx8_update_ext_ied();
for (i=0; i<ARRAY_SIZE(iot_gate_imx8_ext_ied_id); i++) {
extension = NULL;
switch (iot_gate_imx8_ext_ied_id[i]) {
case IOT_GATE_IMX8_CARD_ID_EMPTY:
break;
case IOT_GATE_IMX8_CARD_ID_RS_485:
extension = calloc(1, sizeof(struct extension));
snprintf(extension->name, sizeof(extension->name),
"IOT_GATE_IMX8_CARD_ID_RS_485");
break;
case IOT_GATE_IMX8_CARD_ID_RS_232:
extension = calloc(1, sizeof(struct extension));
snprintf(extension->name, sizeof(extension->name),
"IOT_GATE_IMX8_CARD_ID_RS_232");
break;
case IOT_GATE_IMX8_CARD_ID_CAN:
extension = calloc(1, sizeof(struct extension));
snprintf(extension->name, sizeof(extension->name),
"IOT_GATE_IMX8_CARD_ID_CAN");
snprintf(extension->overlay, sizeof(extension->overlay),
"imx8mm-cl-iot-gate-ied-can%d.dtbo", i);
break;
case IOT_GATE_IMX8_CARD_ID_TPM:
extension = calloc(1, sizeof(struct extension));
snprintf(extension->name, sizeof(extension->name),
"IOT_GATE_IMX8_CARD_ID_TPM");
snprintf(extension->overlay, sizeof(extension->overlay),
"imx8mm-cl-iot-gate-ied-tpm%d.dtbo", i);
break;
case IOT_GATE_IMX8_CARD_ID_CL420:
extension = calloc(1, sizeof(struct extension));
snprintf(extension->name, sizeof(extension->name),
"IOT_GATE_IMX8_CARD_ID_CL420");
snprintf(extension->overlay, sizeof(extension->overlay),
"imx8mm-cl-iot-gate-ied-can%d.dtbo", i);
break;
case IOT_GATE_IMX8_CARD_ID_DI4O4:
extension = calloc(1, sizeof(struct extension));
snprintf(extension->name, sizeof(extension->name),
"IOT_GATE_IMX8_CARD_ID_DI4O4");
break;
default:
printf("%s: invalid slot %d card ID: %d\n",
__func__, i, iot_gate_imx8_ext_ied_id[i]);
break;
}
if (extension) {
snprintf(extension->owner, sizeof(extension->owner),
"Compulab");
snprintf(extension->other, sizeof(extension->other),
"On slot %d", i);
list_add_tail(&extension->list, extension_list);
ret = ret + 1;
}
}
return ret;
}
int board_late_init(void)
{
if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {

26
board/ea/mx7ulp_com/mx7ulp_com.c
View file

@ -52,3 +52,29 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
if (!strcmp(name, "imx7ulp-com"))
return 0;
return -1;
}
#endif
void spl_board_init(void)
{
preloader_console_init();
}
void board_init_f(ulong dummy)
{
arch_cpu_init();
board_early_init_f();
}
#endif

2
board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg
View file

@ -7,4 +7,4 @@
ROM_VERSION v2
BOOT_FROM sd
LOADER mkimage.flash.mkimage 0x912000
LOADER u-boot-spl-ddr.bin 0x912000

56
board/freescale/imx8ulp_evk/imx8ulp_evk.c
View file

@ -12,6 +12,7 @@
#include <asm/arch/sys_proto.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
@ -48,11 +49,66 @@ int board_phy_config(struct phy_device *phydev)
}
#endif
#define I2C_PAD_CTRL (PAD_CTL_ODE)
static const iomux_cfg_t lpi2c0_pads[] = {
IMX8ULP_PAD_PTA8__LPI2C0_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
IMX8ULP_PAD_PTA9__LPI2C0_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
};
#define TPM_PAD_CTRL (PAD_CTL_DSE)
static const iomux_cfg_t tpm0_pads[] = {
IMX8ULP_PAD_PTA3__TPM0_CH2 | MUX_PAD_CTRL(TPM_PAD_CTRL),
};
void mipi_dsi_mux_panel(void)
{
int ret;
struct gpio_desc desc;
/* It is temp solution to directly access i2c, need change to rpmsg later */
/* enable lpi2c0 clock and iomux */
imx8ulp_iomux_setup_multiple_pads(lpi2c0_pads, ARRAY_SIZE(lpi2c0_pads));
writel(0xD2000000, 0x28091060);
ret = dm_gpio_lookup_name("gpio@20_9", &desc);
if (ret) {
printf("%s lookup gpio@20_9 failed ret = %d\n", __func__, ret);
return;
}
ret = dm_gpio_request(&desc, "dsi_mux");
if (ret) {
printf("%s request dsi_mux failed ret = %d\n", __func__, ret);
return;
}
dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
}
void mipi_dsi_panel_backlight(void)
{
/* It is temp solution to directly access pwm, need change to rpmsg later */
imx8ulp_iomux_setup_multiple_pads(tpm0_pads, ARRAY_SIZE(tpm0_pads));
writel(0xD4000001, 0x28091054);
/* Use center-aligned PWM mode, CPWMS=1, MSnB:MSnA = 10, ELSnB:ELSnA = 00 */
writel(1000, 0x28095018);
writel(1000, 0x28095034); /* MOD = CV, full duty */
writel(0x28, 0x28095010);
writel(0x20, 0x28095030);
}
int board_init(void)
{
if (IS_ENABLED(CONFIG_FEC_MXC))
setup_fec();
if (IS_ENABLED(CONFIG_DM_VIDEO)) {
mipi_dsi_mux_panel();
mipi_dsi_panel_backlight();
}
return 0;
}

9
board/freescale/imx8ulp_evk/spl.c
View file

@ -77,6 +77,12 @@ void spl_board_init(void)
/* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */
/* Load the lposc fuse for single boot to work around ROM issue,
* The fuse depends on S400 to read.
*/
if (is_soc_rev(CHIP_REV_1_0) && get_boot_mode() == SINGLE_BOOT)
load_lposc_fuse();
upower_init();
power_init_board();
@ -90,6 +96,9 @@ void spl_board_init(void)
/* Init XRDC MRC for VIDEO, DSP domains */
xrdc_init_mrc();
/* Call it after PS16 power up */
set_lpav_qos();
}
void board_init_f(ulong dummy)

15
board/kontron/pitx_imx8m/Kconfig Normal file
View file

@ -0,0 +1,15 @@
if TARGET_KONTRON_PITX_IMX8M
config SYS_BOARD
default "pitx_imx8m"
config SYS_VENDOR
default "kontron"
config SYS_CONFIG_NAME
default "kontron_pitx_imx8m"
config IMX_CONFIG
default "arch/arm/mach-imx/imx8m/imximage.cfg"
endif

7
board/kontron/pitx_imx8m/MAINTAINERS Normal file
View file

@ -0,0 +1,7 @@
Kontron pITX-imx8m Board
M: Heiko Thiery <heiko.thiery@gmail.com>
S: Maintained
F: arch/arm/dts/imx8mq-kontron-pitx-imx8m*
F: board/kontron/pitx_imx8m/*
F: include/configs/kontron_pitx_imx8m.h
F: configs/kontron_pitx_imx8m_defconfig

8
board/kontron/pitx_imx8m/Makefile Normal file
View file

@ -0,0 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += pitx_imx8m.o pitx_misc.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o pitx_misc.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_2gb.o lpddr4_timing_4gb.o
endif

1853
board/kontron/pitx_imx8m/lpddr4_timing_2gb.c Normal file
View file

File diff suppressed because it is too large Load diff

1853
board/kontron/pitx_imx8m/lpddr4_timing_4gb.c Normal file
View file

File diff suppressed because it is too large Load diff

169
board/kontron/pitx_imx8m/pitx_imx8m.c Normal file
View file

@ -0,0 +1,169 @@
// SPDX-License-Identifier: GPL-2.0+
#include "pitx_misc.h"
#include <common.h>
#include <init.h>
#include <mmc.h>
#include <miiphy.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm-generic/gpio.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MQ_PAD_UART3_RXD__UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MQ_PAD_UART3_TXD__UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MQ_PAD_ECSPI1_SS0__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
}
int board_phys_sdram_size(phys_size_t *memsize)
{
int variant = 0;
variant = get_pitx_board_variant();
switch(variant) {
case 2:
*memsize = 0x80000000;
break;
case 3:
*memsize = 0x100000000;
break;
default:
printf("Unknown DDR type!!!\n");
*memsize = 0x40000000;
break;
}
debug("Memsize: %d MiB\n", (int)(*memsize >> 20));
return 0;
}
#ifdef CONFIG_FEC_MXC
#define FEC_RST_PAD IMX_GPIO_NR(1, 11)
static iomux_v3_cfg_t const fec1_rst_pads[] = {
IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_fec(void)
{
imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
ARRAY_SIZE(fec1_rst_pads));
}
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
setup_iomux_fec();
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
return set_clk_enet(ENET_125MHZ);
}
int board_phy_config(struct phy_device *phydev)
{
unsigned int val;
/*
* Set LED configuration register 1:
* LED2_SEL: 0b1011 (link established, blink on activity)
*/
val = phy_read(phydev, MDIO_DEVAD_NONE, 0x18);
val &= 0xf0ff;
phy_write(phydev, MDIO_DEVAD_NONE, 0x18, val | (0xb << 8));
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
int board_init(void)
{
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3)
init_usb_clk();
#endif
return 0;
}
#ifdef CONFIG_MISC_INIT_R
#define TPM_RESET IMX_GPIO_NR(3, 2)
#define USBHUB_RESET IMX_GPIO_NR(3, 4)
static void reset_device_by_gpio(const char *label, int pin, int delay_ms)
{
gpio_request(pin, label);
gpio_direction_output(pin, 0);
mdelay(delay_ms);
gpio_direction_output(pin, 1);
}
int misc_init_r(void)
{
/*
* reset TPM chip (Infineon SLB9670) as required by datasheet
* (60ms minimum Reset Inactive Time, 70ms implemented)
*/
reset_device_by_gpio("tpm_reset", TPM_RESET, 70);
/*
* reset USB hub as required by datasheet
* (3ms minimum reset duration, 10ms implemented)
*/
reset_device_by_gpio("usbhub_reset", USBHUB_RESET, 10);
return 0;
}
#endif
int board_mmc_get_env_dev(int devno)
{
return devno;
}
uint mmc_get_env_part(struct mmc *mmc)
{
/* part 1 for eMMC, part 1 for SD card */
return (mmc_get_env_dev() == 0) ? 1 : 0;
}
int board_late_init(void)
{
return 0;
}

38
board/kontron/pitx_imx8m/pitx_misc.c Normal file
View file

@ -0,0 +1,38 @@
// SPDX-License-Identifier: GPL-2.0+
#include <asm/arch/imx8mq_pins.h>
#include <asm-generic/gpio.h>
#include <asm/mach-imx/gpio.h>
/*
* BRD_REV1 BRD_REV0
* 0 0 n/a
* 0 1 n/a
* 1 0 2GB LPDDR4
* 1 1 4GB LPDDR4
*/
#define BRD_REV0 IMX_GPIO_NR(5, 0)
#define BRD_REV1 IMX_GPIO_NR(5, 1)
static iomux_v3_cfg_t const brdrev_pads[] = {
IMX8MQ_PAD_SAI3_TXC__GPIO5_IO0 | MUX_PAD_CTRL(PAD_CTL_PUE),
IMX8MQ_PAD_SAI3_TXD__GPIO5_IO1 | MUX_PAD_CTRL(PAD_CTL_PUE),
IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 | MUX_PAD_CTRL(PAD_CTL_PUE),
};
int get_pitx_board_variant(void)
{
int variant = 0;
imx_iomux_v3_setup_multiple_pads(brdrev_pads, ARRAY_SIZE(brdrev_pads));
gpio_request(BRD_REV0, "BRD_REV0");
gpio_direction_input(BRD_REV0);
gpio_request(BRD_REV1, "BRD_REV1");
gpio_direction_input(BRD_REV1);
variant |= !!gpio_get_value(BRD_REV0) << 0;
variant |= !!gpio_get_value(BRD_REV1) << 1;
return variant;
}

6
board/kontron/pitx_imx8m/pitx_misc.h Normal file
View file

@ -0,0 +1,6 @@
#ifndef __PITX_MISC_H
#define __PITX_MISC_H
int get_pitx_board_variant(void);
#endif

299
board/kontron/pitx_imx8m/spl.c Normal file
View file

@ -0,0 +1,299 @@
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
#include <errno.h>
#include <fsl_esdhc_imx.h>
#include <hang.h>
#include <init.h>
#include <log.h>
#include <spl.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <linux/delay.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "pitx_misc.h"
extern struct dram_timing_info dram_timing_2gb;
extern struct dram_timing_info dram_timing_4gb;
DECLARE_GLOBAL_DATA_PTR;
static void spl_dram_init(void)
{
struct dram_timing_info *dram_timing;
int variant = 0, size;
variant = get_pitx_board_variant();
switch(variant) {
case 2:
dram_timing = &dram_timing_2gb;
size = 2;
break;
case 3:
dram_timing = &dram_timing_4gb;
size = 4;
break;
default:
printf("Unknown DDR type (%d)\n", variant);
return;
};
/* ddr init */
ddr_init(dram_timing);
}
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
.gp = IMX_GPIO_NR(5, 14),
},
.sda = {
.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
.gp = IMX_GPIO_NR(5, 15),
},
};
#if CONFIG_IS_ENABLED(MMC)
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
/* the eMMC does not have a CD pin */
ret = 1;
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
}
return ret;
}
#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
PAD_CTL_FSEL2)
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
static iomux_v3_cfg_t const usdhc1_pads[] = {
IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
};
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC1_BASE_ADDR, 0, 8},
{USDHC2_BASE_ADDR, 0, 4},
};
int board_mmc_init(struct bd_info *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 USDHC1
* mmc1 USDHC2
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(0);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
ARRAY_SIZE(usdhc1_pads));
gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
gpio_direction_output(USDHC1_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC1_PWR_GPIO, 1);
break;
case 1:
init_clk_usdhc(1);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
ARRAY_SIZE(usdhc2_pads));
gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
gpio_direction_output(USDHC2_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC2_PWR_GPIO, 1);
break;
default:
printf("Warning: you configured more USDHC controllers "
"(%d) than supported by the board\n", i + 1);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
}
const char *spl_board_loader_name(u32 boot_device)
{
switch (boot_device) {
case BOOT_DEVICE_MMC1:
return "eMMC";
case BOOT_DEVICE_MMC2:
return "SD card";
default:
return NULL;
}
}
#endif
#if CONFIG_IS_ENABLED(POWER_LEGACY)
#define I2C_PMIC 0
static int pfuze_mode_init(struct pmic *p, u32 mode)
{
unsigned char offset, i, switch_num;
u32 id;
int ret;
pmic_reg_read(p, PFUZE100_DEVICEID, &id);
id = id & 0xf;
if (id == 0) {
switch_num = 6;
offset = PFUZE100_SW1CMODE;
} else if (id == 1) {
switch_num = 4;
offset = PFUZE100_SW2MODE;
} else {
printf("Not supported, id=%d\n", id);
return -EINVAL;
}
ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
if (ret < 0) {
printf("Set SW1AB mode error!\n");
return ret;
}
for (i = 0; i < switch_num - 1; i++) {
ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
if (ret < 0) {
printf("Set switch 0x%x mode error!\n",
offset + i * SWITCH_SIZE);
return ret;
}
}
return ret;
}
int power_init_board(void)
{
struct pmic *p;
int ret;
unsigned int reg;
ret = power_pfuze100_init(I2C_PMIC);
if (ret)
return -ENODEV;
p = pmic_get("PFUZE100");
ret = pmic_probe(p);
if (ret)
return -ENODEV;
pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
if ((reg & 0x3f) != 0x18) {
reg &= ~0x3f;
reg |= 0x18;
pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
}
ret = pfuze_mode_init(p, APS_PFM);
if (ret < 0)
return ret;
/* set SW3A standby mode to off */
pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
reg &= ~0xf;
reg |= APS_OFF;
pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
return 0;
}
#endif
void board_init_f(ulong dummy)
{
int ret;
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
arch_cpu_init();
init_uart_clk(2);
board_early_init_f();
timer_init();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
ret = spl_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
}
enable_tzc380();
setup_i2c(0, 100000, 0x7f, &i2c_pad_info1);
#if CONFIG_IS_ENABLED(POWER_LEGACY)
power_init_board();
#endif
spl_dram_init();
board_init_r(NULL, 0);
}

1
board/liebherr/xea/MAINTAINERS
View file

@ -4,3 +4,4 @@ S: Maintained
F: board/liebherr/xea/
F: include/configs/xea.h
F: configs/imx28_xea_defconfig
F: configs/imx28_xea_sb_defconfig

7
board/liebherr/xea/spl_xea.c
View file

@ -290,6 +290,12 @@ u32 mxs_dram_vals[] = {
0x00000000, 0xffffffff
};
#ifndef CONFIG_SPL_FRAMEWORK
void board_init_ll(const u32 arg, const uint32_t *resptr)
{
mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
}
#else
void lowlevel_init(void)
{
struct mxs_pinctrl_regs *pinctrl_regs =
@ -301,3 +307,4 @@ void lowlevel_init(void)
mxs_common_spl_init(0, NULL, iomux_setup, ARRAY_SIZE(iomux_setup));
}
#endif

2
board/liebherr/xea/xea.c
View file

@ -58,7 +58,7 @@ static void init_clocks(void)
mxs_set_sspclk(MXC_SSPCLK3, 96000, 0);
}
#ifdef CONFIG_SPL_BUILD
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK)
void board_init_f(ulong arg)
{
init_clocks();

71
board/storopack/smegw01/imximage.cfg
View file

@ -44,57 +44,80 @@ BOOT_FROM sd
/* DDR initialization came from Phytec */
DATA 4 0x30340004 0x4F400005
/* Clear then set bit30 to ensure exit from DDR retention */
DATA 4 0x30360388 0x40000000
DATA 4 0x30360384 0x40000000
/* deassert presetn */
DATA 4 0x30391000 0x00000002
/* DDR Controller Regs */
DATA 4 0x307a0000 0x01040001
DATA 4 0x307a0064 0x00400046
DATA 4 0x307a0490 0x00000001
DATA 4 0x307a00d4 0x00690000
DATA 4 0x307a00d0 0x00020083
DATA 4 0x307a00dc 0x09300004
DATA 4 0x307a00e0 0x04480000
DATA 4 0x307a00e4 0x00100004
DATA 4 0x307a00f4 0x0000033f
DATA 4 0x307a0100 0x090e110a
DATA 4 0x307a0104 0x0007020e
DATA 4 0x307a0108 0x03040407
DATA 4 0x307a010c 0x00002006
DATA 4 0x307a0110 0x04020304
DATA 4 0x307a0114 0x03030202
DATA 4 0x307a0120 0x00000803
DATA 4 0x307a0180 0x00800020
DATA 4 0x307a0190 0x02098204
DATA 4 0x307a0194 0x00030303
DATA 4 0x307a01a0 0x80400003
DATA 4 0x307a01a4 0x00100020
DATA 4 0x307a01a8 0x80100004
DATA 4 0x307a0064 0x0040002b
DATA 4 0x307a0490 0x00000001
DATA 4 0x307a00d0 0x00020083
DATA 4 0x307a00d4 0x00690000
DATA 4 0x307a00dc 0x09300004
DATA 4 0x307a00e0 0x04080000
DATA 4 0x307a00e4 0x00100004
DATA 4 0x307a00f4 0x0000033f
DATA 4 0x307a0100 0x090b1109
DATA 4 0x307a0104 0x0007020d
DATA 4 0x307a0108 0x03040407
DATA 4 0x307a010c 0x00002006
DATA 4 0x307a0110 0x04020205
DATA 4 0x307a0114 0x03030202
DATA 4 0x307a0120 0x00000802
DATA 4 0x307a0180 0x00800020
DATA 4 0x307a0184 0x02000100
DATA 4 0x307a0190 0x02098204
DATA 4 0x307a0194 0x00030303
DATA 4 0x307a0200 0x00001f15
DATA 4 0x307a0200 0x0000001f
DATA 4 0x307a0204 0x00080808
DATA 4 0x307a020c 0x00000000
DATA 4 0x307a0210 0x00000f0f
DATA 4 0x307a0214 0x07070707
DATA 4 0x307a0218 0x0f0f0707
DATA 4 0x307a0218 0x0f070707
DATA 4 0x307a0240 0x06000604
DATA 4 0x307a0244 0x00000001
/* deassert presetn */
DATA 4 0x30391000 0x00000000
/* PHY Controller Regs */
DATA 4 0x30790000 0x17420f40
DATA 4 0x30790004 0x10210100
DATA 4 0x30790010 0x00060807
DATA 4 0x307900b0 0x1010007e
DATA 4 0x3079009c 0x00000d6e
DATA 4 0x30790020 0x0a0a0a0a
DATA 4 0x30790030 0x06060606
/* write leveling values for each byte lane */
DATA 4 0x3079006c 0x06090108
/* write leveling resync cycle */
DATA 4 0x30790078 0x00000001
DATA 4 0x30790078 0x00000000
DATA 4 0x30790030 0x08080808
DATA 4 0x30790020 0x08080808
DATA 4 0x30790050 0x01000010
DATA 4 0x30790050 0x00000010
DATA 4 0x30790018 0x0000000f
/* start manual ZQ */
DATA 4 0x307900c0 0x0e407304
DATA 4 0x307900c0 0x0e447304
DATA 4 0x307900c0 0x0e447306
CHECK_BITS_SET 4 0x307900c4 0x1
DATA 4 0x307900c0 0x0e447304
CHECK_BITS_SET 4 0x307900c4 0x1
/* end manual ZQ */
DATA 4 0x307900c0 0x0e407304
/* final init sequence */
DATA 4 0x30384130 0x00000000
DATA 4 0x30340020 0x00000178
DATA 4 0x30384130 0x00000002
DATA 4 0x30790018 0x0000000f
CHECK_BITS_SET 4 0x307a0004 0x1

42
board/toradex/verdin-imx8mp/Kconfig Normal file
View file

@ -0,0 +1,42 @@
if TARGET_VERDIN_IMX8MP
config IMX_CONFIG
default "board/toradex/verdin-imx8mp/imximage.cfg"
config SYS_BOARD
default "verdin-imx8mp"
config SYS_CONFIG_NAME
default "verdin-imx8mp"
config SYS_VENDOR
default "toradex"
config TDX_CFG_BLOCK
default y
config TDX_CFG_BLOCK_2ND_ETHADDR
default y
config TDX_CFG_BLOCK_DEV
default "2"
config TDX_CFG_BLOCK_EXTRA
default y
# Toradex config block in eMMC, at the end of 1st "boot sector"
config TDX_CFG_BLOCK_OFFSET
default "-512"
config TDX_CFG_BLOCK_PART
default "1"
config TDX_HAVE_EEPROM_EXTRA
default y
config TDX_HAVE_MMC
default y
source "board/toradex/common/Kconfig"
endif

10
board/toradex/verdin-imx8mp/MAINTAINERS Normal file
View file

@ -0,0 +1,10 @@
Verdin iMX8M Plus
F: arch/arm/dts/imx8mp-verdin.dts
F: arch/arm/dts/imx8mp-verdin-u-boot.dtsi
F: board/toradex/verdin-imx8mp/
F: configs/verdin-imx8mp_defconfig
F: doc/board/toradex/verdin-imx8mp.rst
F: include/configs/verdin-imx8mp.h
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
S: Maintained
W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus

11
board/toradex/verdin-imx8mp/Makefile Normal file
View file

@ -0,0 +1,11 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Copyright 2022 Toradex
#
obj-y += verdin-imx8mp.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif

10
board/toradex/verdin-imx8mp/imximage.cfg Normal file
View file

@ -0,0 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2022 Toradex
*/
#define __ASSEMBLY__
ROM_VERSION v2
BOOT_FROM emmc_fastboot
LOADER u-boot-spl-ddr.bin 0x920000

2169
board/toradex/verdin-imx8mp/lpddr4_timing.c Normal file
View file

File diff suppressed because it is too large Load diff

158
board/toradex/verdin-imx8mp/spl.c Normal file
View file

@ -0,0 +1,158 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2022 Toradex
*/
#include <common.h>
#include <hang.h>
#include <init.h>
#include <log.h>
#include <spl.h>
#include <asm/global_data.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx8mp_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/ddr.h>
#include <power/pmic.h>
#include <power/pca9450.h>
extern struct dram_timing_info dram_timing2;
DECLARE_GLOBAL_DATA_PTR;
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
return BOOT_DEVICE_BOOTROM;
}
void spl_dram_init(void)
{
/*
* try configuring for quad die, dual rank aka 8 GB falling back to
* dual die, single rank aka 1 GB (untested), 2 GB or 4 GB if it fails
*/
if (ddr_init(&dram_timing)) {
printf("Quad die, dual rank failed, attempting dual die, single rank configuration.\n");
ddr_init(&dram_timing2);
}
}
void spl_board_init(void)
{
/*
* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
* not allow to change it. Should set the clock after PMIC
* setting done. Default is 400Mhz (system_pll1_800m with div = 2)
* set by ROM for ND VDD_SOC
*/
clock_enable(CCGR_GIC, 0);
clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
clock_enable(CCGR_GIC, 1);
puts("Normal Boot\n");
}
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
.gp = IMX_GPIO_NR(5, 14),
},
.sda = {
.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
.gp = IMX_GPIO_NR(5, 15),
},
};
#if CONFIG_IS_ENABLED(POWER_LEGACY)
#define I2C_PMIC 0
int power_init_board(void)
{
struct pmic *p;
int ret;
ret = power_pca9450_init(I2C_PMIC, 0x25);
if (ret)
printf("power init failed\n");
p = pmic_get("PCA9450");
pmic_probe(p);
/* BUCKxOUT_DVS0/1 control BUCK123 output */
pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
/*
* increase VDD_SOC to typical value 0.95V before first
* DRAM access, set DVS1 to 0.85v for suspend.
* Enable DVS control through PMIC_STBY_REQ and
* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
*/
if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
/* set DVS0 to 0.85v for special case */
pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
else
pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1c);
pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
/* Kernel uses OD/OD freq for SoC */
/* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95v */
pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1c);
/* set WDOG_B_CFG to cold reset */
pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
/* set LDO4 and CONFIG2 to enable the I2C level translator */
pmic_reg_write(p, PCA9450_LDO4CTRL, 0x59);
pmic_reg_write(p, PCA9450_CONFIG2, 0x1);
return 0;
}
#endif
#if IS_ENABLED(CONFIG_SPL_LOAD_FIT)
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
}
#endif
/* Do not use BSS area in this phase */
void board_init_f(ulong dummy)
{
int ret;
arch_cpu_init();
init_uart_clk(1);
board_early_init_f();
ret = spl_early_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
}
preloader_console_init();
enable_tzc380();
/* Adjust PMIC voltage to 1.0V for 800 MHz */
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
/* PMIC initialization */
power_init_board();
/* DDR initialization */
spl_dram_init();
}

140
board/toradex/verdin-imx8mp/verdin-imx8mp.c Normal file
View file

@ -0,0 +1,140 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2022 Toradex
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx8mp_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm-generic/gpio.h>
#include <asm/global_data.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <errno.h>
#include <env.h>
#include <init.h>
#include <linux/delay.h>
#include <micrel.h>
#include <miiphy.h>
#include <netdev.h>
#include "../common/tdx-cfg-block.h"
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/* Verdin UART_3, Console/Debug UART */
static const iomux_v3_cfg_t uart_pads[] = {
MX8MP_PAD_UART3_RXD__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX8MP_PAD_UART3_TXD__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static const iomux_v3_cfg_t wdog_pads[] = {
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
init_uart_clk(2);
return 0;
}
static void setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* Enable RGMII TX clk output */
setbits_le32(&gpr->gpr[1], BIT(22));
}
static int setup_eqos(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* set INTF as RGMII, enable RGMII TXC clock */
clrsetbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
return set_clk_eqos(ENET_125MHZ);
}
#if IS_ENABLED(CONFIG_NET)
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
int board_init(void)
{
int ret = 0;
if (IS_ENABLED(CONFIG_FEC_MXC))
setup_fec();
if (IS_ENABLED(CONFIG_DWC_ETH_QOS))
ret = setup_eqos();
return ret;
}
static void select_dt_from_module_version(void)
{
char variant[32];
char *env_variant = env_get("variant");
int is_wifi = 0;
if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) {
/*
* If we have a valid config block and it says we are a module with
* Wi-Fi/Bluetooth make sure we use the -wifi device tree.
*/
is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_WIFI_BT_IT) ||
(tdx_hw_tag.prodid == VERDIN_IMX8MPQ_2GB_WIFI_BT_IT) ||
(tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT);
}
if (is_wifi)
strlcpy(&variant[0], "wifi", sizeof(variant));
else
strlcpy(&variant[0], "nonwifi", sizeof(variant));
if (strcmp(variant, env_variant)) {
printf("Setting variant to %s\n", variant);
env_set("variant", variant);
if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
env_save();
}
}
int board_late_init(void)
{
select_dt_from_module_version();
return 0;
}
#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
return 0;
}
#endif

17
board/variscite/imx8mn_var_som/Kconfig Normal file
View file

@ -0,0 +1,17 @@
if TARGET_IMX8MN_VAR_SOM
config SYS_BOARD
default "imx8mn_var_som"
config SYS_VENDOR
default "variscite"
config SYS_CONFIG_NAME
default "imx8mn_var_som"
config IMX_CONFIG
default "board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg"
source "board/freescale/common/Kconfig"
endif

7
board/variscite/imx8mn_var_som/MAINTAINERS Normal file
View file

@ -0,0 +1,7 @@
ARM i.MX8MN VARISCITE VAR-SOM-MX8MN MODULE
M: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
S: Maintained
F: arch/arm/dts/imx8mn-var-som*
F: board/variscite/imx8mn_var_som/
F: configs/imx8mn_var_som_defconfig
F: include/configs/imx8mn_var_som.h

Some files were not shown because too many files have changed in this diff Show more