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riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode
The Andes PLMT driver directly accesses the mtime MMIO region, indicating its intended use in the M-mode boot stage. However, since U-Boot proper (S-mode) also uses the PLMT driver, we need to specifically mark the region as readable through PMPCFGx (or S/U-mode read-only shared data region for Smepmp) in OpenSBI. Granting permission for this case doesn't make sense. Instead, we should use the generic RISC-V timer driver to read the mtime through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER config, which ensures that the PLMT driver is linked exclusively against M-mode U-Boot or U-Boot SPL binaries. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
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3 changed files with 11 additions and 3 deletions
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@ -4,8 +4,9 @@ config RISCV_NDS
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imply CPU
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imply CPU_RISCV
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imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
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imply ANDES_PLMT_TIMER
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imply SPL_ANDES_PLMT_TIMER
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imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
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imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
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imply V5L2_CACHE
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imply SPL_CPU
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imply SPL_OPENSBI
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@ -59,7 +59,14 @@ config ALTERA_TIMER
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config ANDES_PLMT_TIMER
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bool
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depends on RISCV_MMODE || SPL_RISCV_MMODE
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depends on RISCV_MMODE
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help
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The Andes PLMT block holds memory-mapped mtime register
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associated with timer tick.
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config SPL_ANDES_PLMT_TIMER
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bool
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depends on SPL_RISCV_MMODE
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help
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The Andes PLMT block holds memory-mapped mtime register
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associated with timer tick.
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@ -4,7 +4,7 @@
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obj-y += timer-uclass.o
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obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
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obj-$(CONFIG_ANDES_PLMT_TIMER) += andes_plmt_timer.o
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obj-$(CONFIG_$(SPL_)ANDES_PLMT_TIMER) += andes_plmt_timer.o
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obj-$(CONFIG_ARC_TIMER) += arc_timer.o
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obj-$(CONFIG_ARM_TWD_TIMER) += arm_twd_timer.o
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obj-$(CONFIG_AST_TIMER) += ast_timer.o
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