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https://github.com/AsahiLinux/u-boot
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exynos: Update origen and smdkv310 to use common tzpc_init
Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Acked-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
parent
b5f9756f7f
commit
8a00061e20
5 changed files with 8 additions and 125 deletions
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@ -87,12 +87,14 @@ lowlevel_init:
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1:
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/* for UART */
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bl uart_asm_init
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bl arch_cpu_init
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bl tzpc_init
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pop {pc}
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wakeup_reset:
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bl system_clock_init
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bl mem_ctrl_asm_init
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bl arch_cpu_init
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bl tzpc_init
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exit_wakeup:
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@ -353,45 +355,3 @@ uart_asm_init:
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nop
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nop
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/* Setting TZPC[TrustZone Protection Controller] */
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tzpc_init:
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ldr r0, =TZPC0_BASE
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mov r1, #R0SIZE
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str r1, [r0]
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mov r1, #DECPROTXSET
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str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
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ldr r0, =TZPC1_BASE
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str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
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ldr r0, =TZPC2_BASE
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str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
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ldr r0, =TZPC3_BASE
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str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
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ldr r0, =TZPC4_BASE
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str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
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ldr r0, =TZPC5_BASE
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str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
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mov pc, lr
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@ -121,19 +121,6 @@
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#define UBRDIV_OFFSET 0x28
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#define UFRACVAL_OFFSET 0x2C
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/* TZPC : Register Offsets */
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#define TZPC0_BASE 0x10110000
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#define TZPC1_BASE 0x10120000
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#define TZPC2_BASE 0x10130000
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#define TZPC3_BASE 0x10140000
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#define TZPC4_BASE 0x10150000
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#define TZPC5_BASE 0x10160000
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#define TZPC_DECPROT0SET_OFFSET 0x804
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#define TZPC_DECPROT1SET_OFFSET 0x810
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#define TZPC_DECPROT2SET_OFFSET 0x81C
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#define TZPC_DECPROT3SET_OFFSET 0x828
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/* CLK_SRC_CPU */
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#define MUX_HPM_SEL_MOUTAPLL 0x0
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#define MUX_HPM_SEL_SCLKMPLL 0x1
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@ -617,16 +604,4 @@
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* UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
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*/
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#define UFRACVAL_VAL 0x4
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/*
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* TZPC Register Value :
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* R0SIZE: 0x0 : Size of secured ram
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*/
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#define R0SIZE 0x0
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/*
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* TZPC Decode Protection Register Value :
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* DECPROTXSET: 0xFF : Set Decode region to non-secure
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*/
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#define DECPROTXSET 0xFF
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#endif
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@ -85,12 +85,14 @@ lowlevel_init:
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1:
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/* for UART */
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bl uart_asm_init
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bl arch_cpu_init
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bl tzpc_init
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pop {pc}
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wakeup_reset:
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bl system_clock_init
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bl mem_ctrl_asm_init
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bl arch_cpu_init
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bl tzpc_init
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exit_wakeup:
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@ -410,61 +412,3 @@ uart_asm_init:
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nop
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nop
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nop
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/* Setting TZPC[TrustZone Protection Controller] */
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tzpc_init:
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ldr r0, =0x10110000
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mov r1, #0x0
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str r1, [r0]
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mov r1, #0xff
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str r1, [r0, #0x0804]
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str r1, [r0, #0x0810]
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str r1, [r0, #0x081C]
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str r1, [r0, #0x0828]
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ldr r0, =0x10120000
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mov r1, #0x0
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str r1, [r0]
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mov r1, #0xff
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str r1, [r0, #0x0804]
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str r1, [r0, #0x0810]
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str r1, [r0, #0x081C]
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str r1, [r0, #0x0828]
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ldr r0, =0x10130000
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mov r1, #0x0
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str r1, [r0]
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mov r1, #0xff
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str r1, [r0, #0x0804]
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str r1, [r0, #0x0810]
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str r1, [r0, #0x081C]
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str r1, [r0, #0x0828]
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ldr r0, =0x10140000
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mov r1, #0x0
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str r1, [r0]
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mov r1, #0xff
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str r1, [r0, #0x0804]
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str r1, [r0, #0x0810]
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str r1, [r0, #0x081C]
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str r1, [r0, #0x0828]
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ldr r0, =0x10150000
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mov r1, #0x0
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str r1, [r0]
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mov r1, #0xff
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str r1, [r0, #0x0804]
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str r1, [r0, #0x0810]
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str r1, [r0, #0x081C]
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str r1, [r0, #0x0828]
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ldr r0, =0x10160000
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mov r1, #0x0
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str r1, [r0]
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mov r1, #0xff
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str r1, [r0, #0x0804]
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str r1, [r0, #0x0810]
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str r1, [r0, #0x081C]
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str r1, [r0, #0x0828]
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mov pc, lr
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@ -96,6 +96,8 @@
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#define CONFIG_SPL
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#define COPY_BL2_FNPTR_ADDR 0x02020030
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#define CONFIG_SPL_TEXT_BASE 0x02021410
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#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
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/* Miscellaneous configurable options */
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@ -95,6 +95,8 @@
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#define CONFIG_SPL
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#define COPY_BL2_FNPTR_ADDR 0x00002488
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#define CONFIG_SPL_TEXT_BASE 0x02021410
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#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
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/* Miscellaneous configurable options */
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