mirror of
https://github.com/AsahiLinux/u-boot
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Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
This commit is contained in:
commit
89d56f5503
5 changed files with 25 additions and 21 deletions
5
Makefile
5
Makefile
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@ -1261,14 +1261,11 @@ CMS700_config: unconfig
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CPCI2DP_config: unconfig
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CPCI2DP_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd
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CPCI405_config: unconfig
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CPCI405_config \
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
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CPCI4052_config \
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CPCI4052_config \
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CPCI405DT_config \
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CPCI405DT_config \
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CPCI405AB_config: unconfig
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CPCI405AB_config: unconfig
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@mkdir -p $(obj)board/esd/cpci405
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@mkdir -p $(obj)board/esd/cpci405
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@echo "TEXT_BASE = 0xFFFC0000" > $(obj)board/esd/cpci405/config.tmp
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
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CPCIISER4_config: unconfig
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CPCIISER4_config: unconfig
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@ -21,8 +21,4 @@
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# MA 02111-1307 USA
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# MA 02111-1307 USA
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#
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#
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sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
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TEXT_BASE = 0xFFFC0000
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ifndef TEXT_BASE
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TEXT_BASE = 0xFFFD0000
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endif
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@ -107,7 +107,7 @@ int board_early_init_f(void)
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* Setup the GPIO pins
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* Setup the GPIO pins
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* TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
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* TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
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*/
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*/
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out32(GPIO0_OR, 0x40000002);
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out32(GPIO0_OR, 0x40000102);
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out32(GPIO0_TCR, 0x4c90011f);
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out32(GPIO0_TCR, 0x4c90011f);
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out32(GPIO0_OSRL, 0x28051400);
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out32(GPIO0_OSRL, 0x28051400);
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out32(GPIO0_OSRH, 0x55005000);
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out32(GPIO0_OSRH, 0x55005000);
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@ -755,17 +755,31 @@ int post_hotkeys_pressed(void)
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#ifdef CONFIG_RESET_PHY_R
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#ifdef CONFIG_RESET_PHY_R
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void reset_phy(void)
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void reset_phy(void)
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{
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{
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char *s;
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unsigned short val_method, val_behavior;
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/* special LED setup for NGCC/CANDES */
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if ((s = getenv("bd_type")) &&
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((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
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val_method = 0x0e0a;
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val_behavior = 0x0cf2;
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} else {
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/* PMC440 standard type */
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val_method = 0x0e10;
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val_behavior = 0x0cf0;
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}
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if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
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if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
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miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
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miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
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miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0df0);
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miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior);
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miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, 0x0e10);
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miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method);
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miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
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miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
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}
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}
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if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
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if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
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miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
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miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
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miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0df0);
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miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior);
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miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, 0x0e10);
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miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method);
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miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
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miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
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}
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}
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}
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}
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@ -196,9 +196,9 @@
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
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#define CONFIG_SYS_FLASH_BASE TEXT_BASE
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
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#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
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/*
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/*
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@ -235,18 +235,15 @@
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_FPGA
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#define CONFIG_CMD_FPGA
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#undef CONFIG_CMD_NFS
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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