Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-29 16:10:58 +00:00
Code Issues Projects Releases Packages Wiki Activity

Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

Browse source
This commit is contained in:
Wolfgang Denk 2008-12-13 00:36:25 +01:00
commit 89d56f5503
5 changed files with 25 additions and 21 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
Makefile
View file

@ -1261,14 +1261,11 @@ CMS700_config: unconfig
CPCI2DP_config: unconfig CPCI2DP_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd
CPCI405_config: unconfig CPCI405_config \
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
CPCI4052_config \ CPCI4052_config \
CPCI405DT_config \ CPCI405DT_config \
CPCI405AB_config: unconfig CPCI405AB_config: unconfig
@mkdir -p $(obj)board/esd/cpci405 @mkdir -p $(obj)board/esd/cpci405
@echo "TEXT_BASE = 0xFFFC0000" > $(obj)board/esd/cpci405/config.tmp
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
CPCIISER4_config: unconfig CPCIISER4_config: unconfig

6
board/esd/cpci405/config.mk
View file

@ -21,8 +21,4 @@
# MA 02111-1307 USA # MA 02111-1307 USA
# #
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp TEXT_BASE = 0xFFFC0000
ifndef TEXT_BASE
TEXT_BASE = 0xFFFD0000
endif

24
board/esd/pmc440/pmc440.c
View file

@ -107,7 +107,7 @@ int board_early_init_f(void)
* Setup the GPIO pins * Setup the GPIO pins
* TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
*/ */
out32(GPIO0_OR, 0x40000002); out32(GPIO0_OR, 0x40000102);
out32(GPIO0_TCR, 0x4c90011f); out32(GPIO0_TCR, 0x4c90011f);
out32(GPIO0_OSRL, 0x28051400); out32(GPIO0_OSRL, 0x28051400);
out32(GPIO0_OSRH, 0x55005000); out32(GPIO0_OSRH, 0x55005000);
@ -755,17 +755,31 @@ int post_hotkeys_pressed(void)
#ifdef CONFIG_RESET_PHY_R #ifdef CONFIG_RESET_PHY_R
void reset_phy(void) void reset_phy(void)
{ {
char *s;
unsigned short val_method, val_behavior;
/* special LED setup for NGCC/CANDES */
if ((s = getenv("bd_type")) &&
((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
val_method = 0x0e0a;
val_behavior = 0x0cf2;
} else {
/* PMC440 standard type */
val_method = 0x0e10;
val_behavior = 0x0cf0;
}
if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) { if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010); miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0df0); miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior);
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, 0x0e10); miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method);
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000); miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
} }
if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) { if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010); miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0df0); miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior);
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, 0x0e10); miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method);
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000); miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
} }
} }

6
include/configs/CPCI405.h
View file

@ -196,9 +196,9 @@
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/ */
#define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFFFD0000 #define CONFIG_SYS_FLASH_BASE TEXT_BASE
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ #define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
/* /*

5
include/configs/alpr.h
View file

@ -235,18 +235,15 @@
#define CONFIG_CMD_DHCP #define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG #define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM #define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FPGA #define CONFIG_CMD_FPGA
#define CONFIG_CMD_I2C #define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ #define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII #define CONFIG_CMD_MII
#define CONFIG_CMD_NAND #define CONFIG_CMD_NAND
#define CONFIG_CMD_NET #define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI #define CONFIG_CMD_PCI
#define CONFIG_CMD_PING #define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO #undef CONFIG_CMD_NFS
#undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_WATCHDOG /* watchdog disabled */